amdgpu_irq.c 11 KB

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  1. /*
  2. * Copyright 2008 Advanced Micro Devices, Inc.
  3. * Copyright 2008 Red Hat Inc.
  4. * Copyright 2009 Jerome Glisse.
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the "Software"),
  8. * to deal in the Software without restriction, including without limitation
  9. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10. * and/or sell copies of the Software, and to permit persons to whom the
  11. * Software is furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice shall be included in
  14. * all copies or substantial portions of the Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22. * OTHER DEALINGS IN THE SOFTWARE.
  23. *
  24. * Authors: Dave Airlie
  25. * Alex Deucher
  26. * Jerome Glisse
  27. */
  28. #include <drm/drmP.h>
  29. #include <drm/drm_crtc_helper.h>
  30. #include <drm/amdgpu_drm.h>
  31. #include "amdgpu.h"
  32. #include "amdgpu_ih.h"
  33. #include "atom.h"
  34. #include "amdgpu_connectors.h"
  35. #include <linux/pm_runtime.h>
  36. #define AMDGPU_WAIT_IDLE_TIMEOUT 200
  37. /*
  38. * Handle hotplug events outside the interrupt handler proper.
  39. */
  40. /**
  41. * amdgpu_hotplug_work_func - display hotplug work handler
  42. *
  43. * @work: work struct
  44. *
  45. * This is the hot plug event work handler (all asics).
  46. * The work gets scheduled from the irq handler if there
  47. * was a hot plug interrupt. It walks the connector table
  48. * and calls the hotplug handler for each one, then sends
  49. * a drm hotplug event to alert userspace.
  50. */
  51. static void amdgpu_hotplug_work_func(struct work_struct *work)
  52. {
  53. struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
  54. hotplug_work);
  55. struct drm_device *dev = adev->ddev;
  56. struct drm_mode_config *mode_config = &dev->mode_config;
  57. struct drm_connector *connector;
  58. if (mode_config->num_connector) {
  59. list_for_each_entry(connector, &mode_config->connector_list, head)
  60. amdgpu_connector_hotplug(connector);
  61. }
  62. /* Just fire off a uevent and let userspace tell us what to do */
  63. drm_helper_hpd_irq_event(dev);
  64. }
  65. /**
  66. * amdgpu_irq_reset_work_func - execute gpu reset
  67. *
  68. * @work: work struct
  69. *
  70. * Execute scheduled gpu reset (cayman+).
  71. * This function is called when the irq handler
  72. * thinks we need a gpu reset.
  73. */
  74. static void amdgpu_irq_reset_work_func(struct work_struct *work)
  75. {
  76. struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
  77. reset_work);
  78. amdgpu_gpu_reset(adev);
  79. }
  80. /* Disable *all* interrupts */
  81. static void amdgpu_irq_disable_all(struct amdgpu_device *adev)
  82. {
  83. unsigned long irqflags;
  84. unsigned i, j;
  85. int r;
  86. spin_lock_irqsave(&adev->irq.lock, irqflags);
  87. for (i = 0; i < AMDGPU_MAX_IRQ_SRC_ID; ++i) {
  88. struct amdgpu_irq_src *src = adev->irq.sources[i];
  89. if (!src || !src->funcs->set || !src->num_types)
  90. continue;
  91. for (j = 0; j < src->num_types; ++j) {
  92. atomic_set(&src->enabled_types[j], 0);
  93. r = src->funcs->set(adev, src, j,
  94. AMDGPU_IRQ_STATE_DISABLE);
  95. if (r)
  96. DRM_ERROR("error disabling interrupt (%d)\n",
  97. r);
  98. }
  99. }
  100. spin_unlock_irqrestore(&adev->irq.lock, irqflags);
  101. }
  102. /**
  103. * amdgpu_irq_preinstall - drm irq preinstall callback
  104. *
  105. * @dev: drm dev pointer
  106. *
  107. * Gets the hw ready to enable irqs (all asics).
  108. * This function disables all interrupt sources on the GPU.
  109. */
  110. void amdgpu_irq_preinstall(struct drm_device *dev)
  111. {
  112. struct amdgpu_device *adev = dev->dev_private;
  113. /* Disable *all* interrupts */
  114. amdgpu_irq_disable_all(adev);
  115. /* Clear bits */
  116. amdgpu_ih_process(adev);
  117. }
  118. /**
  119. * amdgpu_irq_postinstall - drm irq preinstall callback
  120. *
  121. * @dev: drm dev pointer
  122. *
  123. * Handles stuff to be done after enabling irqs (all asics).
  124. * Returns 0 on success.
  125. */
  126. int amdgpu_irq_postinstall(struct drm_device *dev)
  127. {
  128. dev->max_vblank_count = 0x001fffff;
  129. return 0;
  130. }
  131. /**
  132. * amdgpu_irq_uninstall - drm irq uninstall callback
  133. *
  134. * @dev: drm dev pointer
  135. *
  136. * This function disables all interrupt sources on the GPU (all asics).
  137. */
  138. void amdgpu_irq_uninstall(struct drm_device *dev)
  139. {
  140. struct amdgpu_device *adev = dev->dev_private;
  141. if (adev == NULL) {
  142. return;
  143. }
  144. amdgpu_irq_disable_all(adev);
  145. }
  146. /**
  147. * amdgpu_irq_handler - irq handler
  148. *
  149. * @int irq, void *arg: args
  150. *
  151. * This is the irq handler for the amdgpu driver (all asics).
  152. */
  153. irqreturn_t amdgpu_irq_handler(int irq, void *arg)
  154. {
  155. struct drm_device *dev = (struct drm_device *) arg;
  156. struct amdgpu_device *adev = dev->dev_private;
  157. irqreturn_t ret;
  158. ret = amdgpu_ih_process(adev);
  159. if (ret == IRQ_HANDLED)
  160. pm_runtime_mark_last_busy(dev->dev);
  161. return ret;
  162. }
  163. /**
  164. * amdgpu_msi_ok - asic specific msi checks
  165. *
  166. * @adev: amdgpu device pointer
  167. *
  168. * Handles asic specific MSI checks to determine if
  169. * MSIs should be enabled on a particular chip (all asics).
  170. * Returns true if MSIs should be enabled, false if MSIs
  171. * should not be enabled.
  172. */
  173. static bool amdgpu_msi_ok(struct amdgpu_device *adev)
  174. {
  175. /* force MSI on */
  176. if (amdgpu_msi == 1)
  177. return true;
  178. else if (amdgpu_msi == 0)
  179. return false;
  180. return true;
  181. }
  182. /**
  183. * amdgpu_irq_init - init driver interrupt info
  184. *
  185. * @adev: amdgpu device pointer
  186. *
  187. * Sets up the work irq handlers, vblank init, MSIs, etc. (all asics).
  188. * Returns 0 for success, error for failure.
  189. */
  190. int amdgpu_irq_init(struct amdgpu_device *adev)
  191. {
  192. int r = 0;
  193. spin_lock_init(&adev->irq.lock);
  194. r = drm_vblank_init(adev->ddev, adev->mode_info.num_crtc);
  195. if (r) {
  196. return r;
  197. }
  198. /* enable msi */
  199. adev->irq.msi_enabled = false;
  200. if (amdgpu_msi_ok(adev)) {
  201. int ret = pci_enable_msi(adev->pdev);
  202. if (!ret) {
  203. adev->irq.msi_enabled = true;
  204. dev_info(adev->dev, "amdgpu: using MSI.\n");
  205. }
  206. }
  207. INIT_WORK(&adev->hotplug_work, amdgpu_hotplug_work_func);
  208. INIT_WORK(&adev->reset_work, amdgpu_irq_reset_work_func);
  209. adev->irq.installed = true;
  210. r = drm_irq_install(adev->ddev, adev->ddev->pdev->irq);
  211. if (r) {
  212. adev->irq.installed = false;
  213. flush_work(&adev->hotplug_work);
  214. return r;
  215. }
  216. DRM_INFO("amdgpu: irq initialized.\n");
  217. return 0;
  218. }
  219. /**
  220. * amdgpu_irq_fini - tear down driver interrupt info
  221. *
  222. * @adev: amdgpu device pointer
  223. *
  224. * Tears down the work irq handlers, vblank handlers, MSIs, etc. (all asics).
  225. */
  226. void amdgpu_irq_fini(struct amdgpu_device *adev)
  227. {
  228. unsigned i;
  229. drm_vblank_cleanup(adev->ddev);
  230. if (adev->irq.installed) {
  231. drm_irq_uninstall(adev->ddev);
  232. adev->irq.installed = false;
  233. if (adev->irq.msi_enabled)
  234. pci_disable_msi(adev->pdev);
  235. flush_work(&adev->hotplug_work);
  236. }
  237. for (i = 0; i < AMDGPU_MAX_IRQ_SRC_ID; ++i) {
  238. struct amdgpu_irq_src *src = adev->irq.sources[i];
  239. if (!src)
  240. continue;
  241. kfree(src->enabled_types);
  242. src->enabled_types = NULL;
  243. }
  244. }
  245. /**
  246. * amdgpu_irq_add_id - register irq source
  247. *
  248. * @adev: amdgpu device pointer
  249. * @src_id: source id for this source
  250. * @source: irq source
  251. *
  252. */
  253. int amdgpu_irq_add_id(struct amdgpu_device *adev, unsigned src_id,
  254. struct amdgpu_irq_src *source)
  255. {
  256. if (src_id >= AMDGPU_MAX_IRQ_SRC_ID)
  257. return -EINVAL;
  258. if (adev->irq.sources[src_id] != NULL)
  259. return -EINVAL;
  260. if (!source->funcs)
  261. return -EINVAL;
  262. if (source->num_types && !source->enabled_types) {
  263. atomic_t *types;
  264. types = kcalloc(source->num_types, sizeof(atomic_t),
  265. GFP_KERNEL);
  266. if (!types)
  267. return -ENOMEM;
  268. source->enabled_types = types;
  269. }
  270. adev->irq.sources[src_id] = source;
  271. return 0;
  272. }
  273. /**
  274. * amdgpu_irq_dispatch - dispatch irq to IP blocks
  275. *
  276. * @adev: amdgpu device pointer
  277. * @entry: interrupt vector
  278. *
  279. * Dispatches the irq to the different IP blocks
  280. */
  281. void amdgpu_irq_dispatch(struct amdgpu_device *adev,
  282. struct amdgpu_iv_entry *entry)
  283. {
  284. unsigned src_id = entry->src_id;
  285. struct amdgpu_irq_src *src;
  286. int r;
  287. if (src_id >= AMDGPU_MAX_IRQ_SRC_ID) {
  288. DRM_DEBUG("Invalid src_id in IV: %d\n", src_id);
  289. return;
  290. }
  291. src = adev->irq.sources[src_id];
  292. if (!src) {
  293. DRM_DEBUG("Unhandled interrupt src_id: %d\n", src_id);
  294. return;
  295. }
  296. r = src->funcs->process(adev, src, entry);
  297. if (r)
  298. DRM_ERROR("error processing interrupt (%d)\n", r);
  299. }
  300. /**
  301. * amdgpu_irq_update - update hw interrupt state
  302. *
  303. * @adev: amdgpu device pointer
  304. * @src: interrupt src you want to enable
  305. * @type: type of interrupt you want to update
  306. *
  307. * Updates the interrupt state for a specific src (all asics).
  308. */
  309. int amdgpu_irq_update(struct amdgpu_device *adev,
  310. struct amdgpu_irq_src *src, unsigned type)
  311. {
  312. unsigned long irqflags;
  313. enum amdgpu_interrupt_state state;
  314. int r;
  315. spin_lock_irqsave(&adev->irq.lock, irqflags);
  316. /* we need to determine after taking the lock, otherwise
  317. we might disable just enabled interrupts again */
  318. if (amdgpu_irq_enabled(adev, src, type))
  319. state = AMDGPU_IRQ_STATE_ENABLE;
  320. else
  321. state = AMDGPU_IRQ_STATE_DISABLE;
  322. r = src->funcs->set(adev, src, type, state);
  323. spin_unlock_irqrestore(&adev->irq.lock, irqflags);
  324. return r;
  325. }
  326. /**
  327. * amdgpu_irq_get - enable interrupt
  328. *
  329. * @adev: amdgpu device pointer
  330. * @src: interrupt src you want to enable
  331. * @type: type of interrupt you want to enable
  332. *
  333. * Enables the interrupt type for a specific src (all asics).
  334. */
  335. int amdgpu_irq_get(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
  336. unsigned type)
  337. {
  338. if (!adev->ddev->irq_enabled)
  339. return -ENOENT;
  340. if (type >= src->num_types)
  341. return -EINVAL;
  342. if (!src->enabled_types || !src->funcs->set)
  343. return -EINVAL;
  344. if (atomic_inc_return(&src->enabled_types[type]) == 1)
  345. return amdgpu_irq_update(adev, src, type);
  346. return 0;
  347. }
  348. bool amdgpu_irq_get_delayed(struct amdgpu_device *adev,
  349. struct amdgpu_irq_src *src,
  350. unsigned type)
  351. {
  352. if ((type >= src->num_types) || !src->enabled_types)
  353. return false;
  354. return atomic_inc_return(&src->enabled_types[type]) == 1;
  355. }
  356. /**
  357. * amdgpu_irq_put - disable interrupt
  358. *
  359. * @adev: amdgpu device pointer
  360. * @src: interrupt src you want to disable
  361. * @type: type of interrupt you want to disable
  362. *
  363. * Disables the interrupt type for a specific src (all asics).
  364. */
  365. int amdgpu_irq_put(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
  366. unsigned type)
  367. {
  368. if (!adev->ddev->irq_enabled)
  369. return -ENOENT;
  370. if (type >= src->num_types)
  371. return -EINVAL;
  372. if (!src->enabled_types || !src->funcs->set)
  373. return -EINVAL;
  374. if (atomic_dec_and_test(&src->enabled_types[type]))
  375. return amdgpu_irq_update(adev, src, type);
  376. return 0;
  377. }
  378. /**
  379. * amdgpu_irq_enabled - test if irq is enabled or not
  380. *
  381. * @adev: amdgpu device pointer
  382. * @idx: interrupt src you want to test
  383. *
  384. * Tests if the given interrupt source is enabled or not
  385. */
  386. bool amdgpu_irq_enabled(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
  387. unsigned type)
  388. {
  389. if (!adev->ddev->irq_enabled)
  390. return false;
  391. if (type >= src->num_types)
  392. return false;
  393. if (!src->enabled_types || !src->funcs->set)
  394. return false;
  395. return !!atomic_read(&src->enabled_types[type]);
  396. }