pwm-imx.c 8.2 KB

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  1. /*
  2. * simple driver for PWM (Pulse Width Modulator) controller
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License version 2 as
  6. * published by the Free Software Foundation.
  7. *
  8. * Derived from pxa PWM driver by eric miao <eric.miao@marvell.com>
  9. */
  10. #include <linux/module.h>
  11. #include <linux/kernel.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/slab.h>
  14. #include <linux/err.h>
  15. #include <linux/clk.h>
  16. #include <linux/delay.h>
  17. #include <linux/io.h>
  18. #include <linux/pwm.h>
  19. #include <linux/of.h>
  20. #include <linux/of_device.h>
  21. /* i.MX1 and i.MX21 share the same PWM function block: */
  22. #define MX1_PWMC 0x00 /* PWM Control Register */
  23. #define MX1_PWMS 0x04 /* PWM Sample Register */
  24. #define MX1_PWMP 0x08 /* PWM Period Register */
  25. #define MX1_PWMC_EN (1 << 4)
  26. /* i.MX27, i.MX31, i.MX35 share the same PWM function block: */
  27. #define MX3_PWMCR 0x00 /* PWM Control Register */
  28. #define MX3_PWMSR 0x04 /* PWM Status Register */
  29. #define MX3_PWMSAR 0x0C /* PWM Sample Register */
  30. #define MX3_PWMPR 0x10 /* PWM Period Register */
  31. #define MX3_PWMCR_PRESCALER(x) ((((x) - 1) & 0xFFF) << 4)
  32. #define MX3_PWMCR_STOPEN (1 << 25)
  33. #define MX3_PWMCR_DOZEEN (1 << 24)
  34. #define MX3_PWMCR_WAITEN (1 << 23)
  35. #define MX3_PWMCR_DBGEN (1 << 22)
  36. #define MX3_PWMCR_POUTC (1 << 18)
  37. #define MX3_PWMCR_CLKSRC_IPG_HIGH (2 << 16)
  38. #define MX3_PWMCR_CLKSRC_IPG (1 << 16)
  39. #define MX3_PWMCR_SWR (1 << 3)
  40. #define MX3_PWMCR_EN (1 << 0)
  41. #define MX3_PWMSR_FIFOAV_4WORDS 0x4
  42. #define MX3_PWMSR_FIFOAV_MASK 0x7
  43. #define MX3_PWM_SWR_LOOP 5
  44. struct imx_chip {
  45. struct clk *clk_per;
  46. void __iomem *mmio_base;
  47. struct pwm_chip chip;
  48. };
  49. #define to_imx_chip(chip) container_of(chip, struct imx_chip, chip)
  50. static int imx_pwm_config_v1(struct pwm_chip *chip,
  51. struct pwm_device *pwm, int duty_ns, int period_ns)
  52. {
  53. struct imx_chip *imx = to_imx_chip(chip);
  54. /*
  55. * The PWM subsystem allows for exact frequencies. However,
  56. * I cannot connect a scope on my device to the PWM line and
  57. * thus cannot provide the program the PWM controller
  58. * exactly. Instead, I'm relying on the fact that the
  59. * Bootloader (u-boot or WinCE+haret) has programmed the PWM
  60. * function group already. So I'll just modify the PWM sample
  61. * register to follow the ratio of duty_ns vs. period_ns
  62. * accordingly.
  63. *
  64. * This is good enough for programming the brightness of
  65. * the LCD backlight.
  66. *
  67. * The real implementation would divide PERCLK[0] first by
  68. * both the prescaler (/1 .. /128) and then by CLKSEL
  69. * (/2 .. /16).
  70. */
  71. u32 max = readl(imx->mmio_base + MX1_PWMP);
  72. u32 p = max * duty_ns / period_ns;
  73. writel(max - p, imx->mmio_base + MX1_PWMS);
  74. return 0;
  75. }
  76. static int imx_pwm_enable_v1(struct pwm_chip *chip, struct pwm_device *pwm)
  77. {
  78. struct imx_chip *imx = to_imx_chip(chip);
  79. u32 val;
  80. int ret;
  81. ret = clk_prepare_enable(imx->clk_per);
  82. if (ret < 0)
  83. return ret;
  84. val = readl(imx->mmio_base + MX1_PWMC);
  85. val |= MX1_PWMC_EN;
  86. writel(val, imx->mmio_base + MX1_PWMC);
  87. return 0;
  88. }
  89. static void imx_pwm_disable_v1(struct pwm_chip *chip, struct pwm_device *pwm)
  90. {
  91. struct imx_chip *imx = to_imx_chip(chip);
  92. u32 val;
  93. val = readl(imx->mmio_base + MX1_PWMC);
  94. val &= ~MX1_PWMC_EN;
  95. writel(val, imx->mmio_base + MX1_PWMC);
  96. clk_disable_unprepare(imx->clk_per);
  97. }
  98. static void imx_pwm_sw_reset(struct pwm_chip *chip)
  99. {
  100. struct imx_chip *imx = to_imx_chip(chip);
  101. struct device *dev = chip->dev;
  102. int wait_count = 0;
  103. u32 cr;
  104. writel(MX3_PWMCR_SWR, imx->mmio_base + MX3_PWMCR);
  105. do {
  106. usleep_range(200, 1000);
  107. cr = readl(imx->mmio_base + MX3_PWMCR);
  108. } while ((cr & MX3_PWMCR_SWR) &&
  109. (wait_count++ < MX3_PWM_SWR_LOOP));
  110. if (cr & MX3_PWMCR_SWR)
  111. dev_warn(dev, "software reset timeout\n");
  112. }
  113. static void imx_pwm_wait_fifo_slot(struct pwm_chip *chip,
  114. struct pwm_device *pwm)
  115. {
  116. struct imx_chip *imx = to_imx_chip(chip);
  117. struct device *dev = chip->dev;
  118. unsigned int period_ms;
  119. int fifoav;
  120. u32 sr;
  121. sr = readl(imx->mmio_base + MX3_PWMSR);
  122. fifoav = sr & MX3_PWMSR_FIFOAV_MASK;
  123. if (fifoav == MX3_PWMSR_FIFOAV_4WORDS) {
  124. period_ms = DIV_ROUND_UP(pwm_get_period(pwm),
  125. NSEC_PER_MSEC);
  126. msleep(period_ms);
  127. sr = readl(imx->mmio_base + MX3_PWMSR);
  128. if (fifoav == (sr & MX3_PWMSR_FIFOAV_MASK))
  129. dev_warn(dev, "there is no free FIFO slot\n");
  130. }
  131. }
  132. static int imx_pwm_apply_v2(struct pwm_chip *chip, struct pwm_device *pwm,
  133. struct pwm_state *state)
  134. {
  135. unsigned long period_cycles, duty_cycles, prescale;
  136. struct imx_chip *imx = to_imx_chip(chip);
  137. struct pwm_state cstate;
  138. unsigned long long c;
  139. int ret;
  140. u32 cr;
  141. pwm_get_state(pwm, &cstate);
  142. if (state->enabled) {
  143. c = clk_get_rate(imx->clk_per);
  144. c *= state->period;
  145. do_div(c, 1000000000);
  146. period_cycles = c;
  147. prescale = period_cycles / 0x10000 + 1;
  148. period_cycles /= prescale;
  149. c = (unsigned long long)period_cycles * state->duty_cycle;
  150. do_div(c, state->period);
  151. duty_cycles = c;
  152. /*
  153. * according to imx pwm RM, the real period value should be
  154. * PERIOD value in PWMPR plus 2.
  155. */
  156. if (period_cycles > 2)
  157. period_cycles -= 2;
  158. else
  159. period_cycles = 0;
  160. /*
  161. * Wait for a free FIFO slot if the PWM is already enabled, and
  162. * flush the FIFO if the PWM was disabled and is about to be
  163. * enabled.
  164. */
  165. if (cstate.enabled) {
  166. imx_pwm_wait_fifo_slot(chip, pwm);
  167. } else {
  168. ret = clk_prepare_enable(imx->clk_per);
  169. if (ret)
  170. return ret;
  171. imx_pwm_sw_reset(chip);
  172. }
  173. writel(duty_cycles, imx->mmio_base + MX3_PWMSAR);
  174. writel(period_cycles, imx->mmio_base + MX3_PWMPR);
  175. cr = MX3_PWMCR_PRESCALER(prescale) |
  176. MX3_PWMCR_STOPEN | MX3_PWMCR_DOZEEN | MX3_PWMCR_WAITEN |
  177. MX3_PWMCR_DBGEN | MX3_PWMCR_CLKSRC_IPG_HIGH |
  178. MX3_PWMCR_EN;
  179. if (state->polarity == PWM_POLARITY_INVERSED)
  180. cr |= MX3_PWMCR_POUTC;
  181. writel(cr, imx->mmio_base + MX3_PWMCR);
  182. } else if (cstate.enabled) {
  183. writel(0, imx->mmio_base + MX3_PWMCR);
  184. clk_disable_unprepare(imx->clk_per);
  185. }
  186. return 0;
  187. }
  188. static const struct pwm_ops imx_pwm_ops_v1 = {
  189. .enable = imx_pwm_enable_v1,
  190. .disable = imx_pwm_disable_v1,
  191. .config = imx_pwm_config_v1,
  192. .owner = THIS_MODULE,
  193. };
  194. static const struct pwm_ops imx_pwm_ops_v2 = {
  195. .apply = imx_pwm_apply_v2,
  196. .owner = THIS_MODULE,
  197. };
  198. struct imx_pwm_data {
  199. bool polarity_supported;
  200. const struct pwm_ops *ops;
  201. };
  202. static struct imx_pwm_data imx_pwm_data_v1 = {
  203. .ops = &imx_pwm_ops_v1,
  204. };
  205. static struct imx_pwm_data imx_pwm_data_v2 = {
  206. .polarity_supported = true,
  207. .ops = &imx_pwm_ops_v2,
  208. };
  209. static const struct of_device_id imx_pwm_dt_ids[] = {
  210. { .compatible = "fsl,imx1-pwm", .data = &imx_pwm_data_v1, },
  211. { .compatible = "fsl,imx27-pwm", .data = &imx_pwm_data_v2, },
  212. { /* sentinel */ }
  213. };
  214. MODULE_DEVICE_TABLE(of, imx_pwm_dt_ids);
  215. static int imx_pwm_probe(struct platform_device *pdev)
  216. {
  217. const struct of_device_id *of_id =
  218. of_match_device(imx_pwm_dt_ids, &pdev->dev);
  219. const struct imx_pwm_data *data;
  220. struct imx_chip *imx;
  221. struct resource *r;
  222. int ret = 0;
  223. if (!of_id)
  224. return -ENODEV;
  225. data = of_id->data;
  226. imx = devm_kzalloc(&pdev->dev, sizeof(*imx), GFP_KERNEL);
  227. if (imx == NULL)
  228. return -ENOMEM;
  229. imx->clk_per = devm_clk_get(&pdev->dev, "per");
  230. if (IS_ERR(imx->clk_per)) {
  231. dev_err(&pdev->dev, "getting per clock failed with %ld\n",
  232. PTR_ERR(imx->clk_per));
  233. return PTR_ERR(imx->clk_per);
  234. }
  235. imx->chip.ops = data->ops;
  236. imx->chip.dev = &pdev->dev;
  237. imx->chip.base = -1;
  238. imx->chip.npwm = 1;
  239. if (data->polarity_supported) {
  240. dev_dbg(&pdev->dev, "PWM supports output inversion\n");
  241. imx->chip.of_xlate = of_pwm_xlate_with_flags;
  242. imx->chip.of_pwm_n_cells = 3;
  243. }
  244. r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  245. imx->mmio_base = devm_ioremap_resource(&pdev->dev, r);
  246. if (IS_ERR(imx->mmio_base))
  247. return PTR_ERR(imx->mmio_base);
  248. ret = pwmchip_add(&imx->chip);
  249. if (ret < 0)
  250. return ret;
  251. platform_set_drvdata(pdev, imx);
  252. return 0;
  253. }
  254. static int imx_pwm_remove(struct platform_device *pdev)
  255. {
  256. struct imx_chip *imx;
  257. imx = platform_get_drvdata(pdev);
  258. if (imx == NULL)
  259. return -ENODEV;
  260. return pwmchip_remove(&imx->chip);
  261. }
  262. static struct platform_driver imx_pwm_driver = {
  263. .driver = {
  264. .name = "imx-pwm",
  265. .of_match_table = imx_pwm_dt_ids,
  266. },
  267. .probe = imx_pwm_probe,
  268. .remove = imx_pwm_remove,
  269. };
  270. module_platform_driver(imx_pwm_driver);
  271. MODULE_LICENSE("GPL v2");
  272. MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");