intel-pt.c 64 KB

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  1. /*
  2. * intel_pt.c: Intel Processor Trace support
  3. * Copyright (c) 2013-2015, Intel Corporation.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms and conditions of the GNU General Public License,
  7. * version 2, as published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. */
  15. #include <inttypes.h>
  16. #include <stdio.h>
  17. #include <stdbool.h>
  18. #include <errno.h>
  19. #include <linux/kernel.h>
  20. #include <linux/types.h>
  21. #include "../perf.h"
  22. #include "session.h"
  23. #include "machine.h"
  24. #include "memswap.h"
  25. #include "sort.h"
  26. #include "tool.h"
  27. #include "event.h"
  28. #include "evlist.h"
  29. #include "evsel.h"
  30. #include "map.h"
  31. #include "color.h"
  32. #include "util.h"
  33. #include "thread.h"
  34. #include "thread-stack.h"
  35. #include "symbol.h"
  36. #include "callchain.h"
  37. #include "dso.h"
  38. #include "debug.h"
  39. #include "auxtrace.h"
  40. #include "tsc.h"
  41. #include "intel-pt.h"
  42. #include "config.h"
  43. #include "intel-pt-decoder/intel-pt-log.h"
  44. #include "intel-pt-decoder/intel-pt-decoder.h"
  45. #include "intel-pt-decoder/intel-pt-insn-decoder.h"
  46. #include "intel-pt-decoder/intel-pt-pkt-decoder.h"
  47. #define MAX_TIMESTAMP (~0ULL)
  48. struct intel_pt {
  49. struct auxtrace auxtrace;
  50. struct auxtrace_queues queues;
  51. struct auxtrace_heap heap;
  52. u32 auxtrace_type;
  53. struct perf_session *session;
  54. struct machine *machine;
  55. struct perf_evsel *switch_evsel;
  56. struct thread *unknown_thread;
  57. bool timeless_decoding;
  58. bool sampling_mode;
  59. bool snapshot_mode;
  60. bool per_cpu_mmaps;
  61. bool have_tsc;
  62. bool data_queued;
  63. bool est_tsc;
  64. bool sync_switch;
  65. bool mispred_all;
  66. int have_sched_switch;
  67. u32 pmu_type;
  68. u64 kernel_start;
  69. u64 switch_ip;
  70. u64 ptss_ip;
  71. struct perf_tsc_conversion tc;
  72. bool cap_user_time_zero;
  73. struct itrace_synth_opts synth_opts;
  74. bool sample_instructions;
  75. u64 instructions_sample_type;
  76. u64 instructions_id;
  77. bool sample_branches;
  78. u32 branches_filter;
  79. u64 branches_sample_type;
  80. u64 branches_id;
  81. bool sample_transactions;
  82. u64 transactions_sample_type;
  83. u64 transactions_id;
  84. bool sample_ptwrites;
  85. u64 ptwrites_sample_type;
  86. u64 ptwrites_id;
  87. bool sample_pwr_events;
  88. u64 pwr_events_sample_type;
  89. u64 mwait_id;
  90. u64 pwre_id;
  91. u64 exstop_id;
  92. u64 pwrx_id;
  93. u64 cbr_id;
  94. u64 tsc_bit;
  95. u64 mtc_bit;
  96. u64 mtc_freq_bits;
  97. u32 tsc_ctc_ratio_n;
  98. u32 tsc_ctc_ratio_d;
  99. u64 cyc_bit;
  100. u64 noretcomp_bit;
  101. unsigned max_non_turbo_ratio;
  102. unsigned cbr2khz;
  103. unsigned long num_events;
  104. char *filter;
  105. struct addr_filters filts;
  106. };
  107. enum switch_state {
  108. INTEL_PT_SS_NOT_TRACING,
  109. INTEL_PT_SS_UNKNOWN,
  110. INTEL_PT_SS_TRACING,
  111. INTEL_PT_SS_EXPECTING_SWITCH_EVENT,
  112. INTEL_PT_SS_EXPECTING_SWITCH_IP,
  113. };
  114. struct intel_pt_queue {
  115. struct intel_pt *pt;
  116. unsigned int queue_nr;
  117. struct auxtrace_buffer *buffer;
  118. struct auxtrace_buffer *old_buffer;
  119. void *decoder;
  120. const struct intel_pt_state *state;
  121. struct ip_callchain *chain;
  122. struct branch_stack *last_branch;
  123. struct branch_stack *last_branch_rb;
  124. size_t last_branch_pos;
  125. union perf_event *event_buf;
  126. bool on_heap;
  127. bool stop;
  128. bool step_through_buffers;
  129. bool use_buffer_pid_tid;
  130. bool sync_switch;
  131. pid_t pid, tid;
  132. int cpu;
  133. int switch_state;
  134. pid_t next_tid;
  135. struct thread *thread;
  136. bool exclude_kernel;
  137. bool have_sample;
  138. u64 time;
  139. u64 timestamp;
  140. u32 flags;
  141. u16 insn_len;
  142. u64 last_insn_cnt;
  143. char insn[INTEL_PT_INSN_BUF_SZ];
  144. };
  145. static void intel_pt_dump(struct intel_pt *pt __maybe_unused,
  146. unsigned char *buf, size_t len)
  147. {
  148. struct intel_pt_pkt packet;
  149. size_t pos = 0;
  150. int ret, pkt_len, i;
  151. char desc[INTEL_PT_PKT_DESC_MAX];
  152. const char *color = PERF_COLOR_BLUE;
  153. color_fprintf(stdout, color,
  154. ". ... Intel Processor Trace data: size %zu bytes\n",
  155. len);
  156. while (len) {
  157. ret = intel_pt_get_packet(buf, len, &packet);
  158. if (ret > 0)
  159. pkt_len = ret;
  160. else
  161. pkt_len = 1;
  162. printf(".");
  163. color_fprintf(stdout, color, " %08x: ", pos);
  164. for (i = 0; i < pkt_len; i++)
  165. color_fprintf(stdout, color, " %02x", buf[i]);
  166. for (; i < 16; i++)
  167. color_fprintf(stdout, color, " ");
  168. if (ret > 0) {
  169. ret = intel_pt_pkt_desc(&packet, desc,
  170. INTEL_PT_PKT_DESC_MAX);
  171. if (ret > 0)
  172. color_fprintf(stdout, color, " %s\n", desc);
  173. } else {
  174. color_fprintf(stdout, color, " Bad packet!\n");
  175. }
  176. pos += pkt_len;
  177. buf += pkt_len;
  178. len -= pkt_len;
  179. }
  180. }
  181. static void intel_pt_dump_event(struct intel_pt *pt, unsigned char *buf,
  182. size_t len)
  183. {
  184. printf(".\n");
  185. intel_pt_dump(pt, buf, len);
  186. }
  187. static int intel_pt_do_fix_overlap(struct intel_pt *pt, struct auxtrace_buffer *a,
  188. struct auxtrace_buffer *b)
  189. {
  190. bool consecutive = false;
  191. void *start;
  192. start = intel_pt_find_overlap(a->data, a->size, b->data, b->size,
  193. pt->have_tsc, &consecutive);
  194. if (!start)
  195. return -EINVAL;
  196. b->use_size = b->data + b->size - start;
  197. b->use_data = start;
  198. if (b->use_size && consecutive)
  199. b->consecutive = true;
  200. return 0;
  201. }
  202. /* This function assumes data is processed sequentially only */
  203. static int intel_pt_get_trace(struct intel_pt_buffer *b, void *data)
  204. {
  205. struct intel_pt_queue *ptq = data;
  206. struct auxtrace_buffer *buffer = ptq->buffer;
  207. struct auxtrace_buffer *old_buffer = ptq->old_buffer;
  208. struct auxtrace_queue *queue;
  209. bool might_overlap;
  210. if (ptq->stop) {
  211. b->len = 0;
  212. return 0;
  213. }
  214. queue = &ptq->pt->queues.queue_array[ptq->queue_nr];
  215. buffer = auxtrace_buffer__next(queue, buffer);
  216. if (!buffer) {
  217. if (old_buffer)
  218. auxtrace_buffer__drop_data(old_buffer);
  219. b->len = 0;
  220. return 0;
  221. }
  222. ptq->buffer = buffer;
  223. if (!buffer->data) {
  224. int fd = perf_data__fd(ptq->pt->session->data);
  225. buffer->data = auxtrace_buffer__get_data(buffer, fd);
  226. if (!buffer->data)
  227. return -ENOMEM;
  228. }
  229. might_overlap = ptq->pt->snapshot_mode || ptq->pt->sampling_mode;
  230. if (might_overlap && !buffer->consecutive && old_buffer &&
  231. intel_pt_do_fix_overlap(ptq->pt, old_buffer, buffer))
  232. return -ENOMEM;
  233. if (buffer->use_data) {
  234. b->len = buffer->use_size;
  235. b->buf = buffer->use_data;
  236. } else {
  237. b->len = buffer->size;
  238. b->buf = buffer->data;
  239. }
  240. b->ref_timestamp = buffer->reference;
  241. if (!old_buffer || (might_overlap && !buffer->consecutive)) {
  242. b->consecutive = false;
  243. b->trace_nr = buffer->buffer_nr + 1;
  244. } else {
  245. b->consecutive = true;
  246. }
  247. if (ptq->step_through_buffers)
  248. ptq->stop = true;
  249. if (b->len) {
  250. if (old_buffer)
  251. auxtrace_buffer__drop_data(old_buffer);
  252. ptq->old_buffer = buffer;
  253. } else {
  254. auxtrace_buffer__drop_data(buffer);
  255. return intel_pt_get_trace(b, data);
  256. }
  257. return 0;
  258. }
  259. struct intel_pt_cache_entry {
  260. struct auxtrace_cache_entry entry;
  261. u64 insn_cnt;
  262. u64 byte_cnt;
  263. enum intel_pt_insn_op op;
  264. enum intel_pt_insn_branch branch;
  265. int length;
  266. int32_t rel;
  267. char insn[INTEL_PT_INSN_BUF_SZ];
  268. };
  269. static int intel_pt_config_div(const char *var, const char *value, void *data)
  270. {
  271. int *d = data;
  272. long val;
  273. if (!strcmp(var, "intel-pt.cache-divisor")) {
  274. val = strtol(value, NULL, 0);
  275. if (val > 0 && val <= INT_MAX)
  276. *d = val;
  277. }
  278. return 0;
  279. }
  280. static int intel_pt_cache_divisor(void)
  281. {
  282. static int d;
  283. if (d)
  284. return d;
  285. perf_config(intel_pt_config_div, &d);
  286. if (!d)
  287. d = 64;
  288. return d;
  289. }
  290. static unsigned int intel_pt_cache_size(struct dso *dso,
  291. struct machine *machine)
  292. {
  293. off_t size;
  294. size = dso__data_size(dso, machine);
  295. size /= intel_pt_cache_divisor();
  296. if (size < 1000)
  297. return 10;
  298. if (size > (1 << 21))
  299. return 21;
  300. return 32 - __builtin_clz(size);
  301. }
  302. static struct auxtrace_cache *intel_pt_cache(struct dso *dso,
  303. struct machine *machine)
  304. {
  305. struct auxtrace_cache *c;
  306. unsigned int bits;
  307. if (dso->auxtrace_cache)
  308. return dso->auxtrace_cache;
  309. bits = intel_pt_cache_size(dso, machine);
  310. /* Ignoring cache creation failure */
  311. c = auxtrace_cache__new(bits, sizeof(struct intel_pt_cache_entry), 200);
  312. dso->auxtrace_cache = c;
  313. return c;
  314. }
  315. static int intel_pt_cache_add(struct dso *dso, struct machine *machine,
  316. u64 offset, u64 insn_cnt, u64 byte_cnt,
  317. struct intel_pt_insn *intel_pt_insn)
  318. {
  319. struct auxtrace_cache *c = intel_pt_cache(dso, machine);
  320. struct intel_pt_cache_entry *e;
  321. int err;
  322. if (!c)
  323. return -ENOMEM;
  324. e = auxtrace_cache__alloc_entry(c);
  325. if (!e)
  326. return -ENOMEM;
  327. e->insn_cnt = insn_cnt;
  328. e->byte_cnt = byte_cnt;
  329. e->op = intel_pt_insn->op;
  330. e->branch = intel_pt_insn->branch;
  331. e->length = intel_pt_insn->length;
  332. e->rel = intel_pt_insn->rel;
  333. memcpy(e->insn, intel_pt_insn->buf, INTEL_PT_INSN_BUF_SZ);
  334. err = auxtrace_cache__add(c, offset, &e->entry);
  335. if (err)
  336. auxtrace_cache__free_entry(c, e);
  337. return err;
  338. }
  339. static struct intel_pt_cache_entry *
  340. intel_pt_cache_lookup(struct dso *dso, struct machine *machine, u64 offset)
  341. {
  342. struct auxtrace_cache *c = intel_pt_cache(dso, machine);
  343. if (!c)
  344. return NULL;
  345. return auxtrace_cache__lookup(dso->auxtrace_cache, offset);
  346. }
  347. static int intel_pt_walk_next_insn(struct intel_pt_insn *intel_pt_insn,
  348. uint64_t *insn_cnt_ptr, uint64_t *ip,
  349. uint64_t to_ip, uint64_t max_insn_cnt,
  350. void *data)
  351. {
  352. struct intel_pt_queue *ptq = data;
  353. struct machine *machine = ptq->pt->machine;
  354. struct thread *thread;
  355. struct addr_location al;
  356. unsigned char buf[INTEL_PT_INSN_BUF_SZ];
  357. ssize_t len;
  358. int x86_64;
  359. u8 cpumode;
  360. u64 offset, start_offset, start_ip;
  361. u64 insn_cnt = 0;
  362. bool one_map = true;
  363. intel_pt_insn->length = 0;
  364. if (to_ip && *ip == to_ip)
  365. goto out_no_cache;
  366. if (*ip >= ptq->pt->kernel_start)
  367. cpumode = PERF_RECORD_MISC_KERNEL;
  368. else
  369. cpumode = PERF_RECORD_MISC_USER;
  370. thread = ptq->thread;
  371. if (!thread) {
  372. if (cpumode != PERF_RECORD_MISC_KERNEL)
  373. return -EINVAL;
  374. thread = ptq->pt->unknown_thread;
  375. }
  376. while (1) {
  377. thread__find_addr_map(thread, cpumode, MAP__FUNCTION, *ip, &al);
  378. if (!al.map || !al.map->dso)
  379. return -EINVAL;
  380. if (al.map->dso->data.status == DSO_DATA_STATUS_ERROR &&
  381. dso__data_status_seen(al.map->dso,
  382. DSO_DATA_STATUS_SEEN_ITRACE))
  383. return -ENOENT;
  384. offset = al.map->map_ip(al.map, *ip);
  385. if (!to_ip && one_map) {
  386. struct intel_pt_cache_entry *e;
  387. e = intel_pt_cache_lookup(al.map->dso, machine, offset);
  388. if (e &&
  389. (!max_insn_cnt || e->insn_cnt <= max_insn_cnt)) {
  390. *insn_cnt_ptr = e->insn_cnt;
  391. *ip += e->byte_cnt;
  392. intel_pt_insn->op = e->op;
  393. intel_pt_insn->branch = e->branch;
  394. intel_pt_insn->length = e->length;
  395. intel_pt_insn->rel = e->rel;
  396. memcpy(intel_pt_insn->buf, e->insn,
  397. INTEL_PT_INSN_BUF_SZ);
  398. intel_pt_log_insn_no_data(intel_pt_insn, *ip);
  399. return 0;
  400. }
  401. }
  402. start_offset = offset;
  403. start_ip = *ip;
  404. /* Load maps to ensure dso->is_64_bit has been updated */
  405. map__load(al.map);
  406. x86_64 = al.map->dso->is_64_bit;
  407. while (1) {
  408. len = dso__data_read_offset(al.map->dso, machine,
  409. offset, buf,
  410. INTEL_PT_INSN_BUF_SZ);
  411. if (len <= 0)
  412. return -EINVAL;
  413. if (intel_pt_get_insn(buf, len, x86_64, intel_pt_insn))
  414. return -EINVAL;
  415. intel_pt_log_insn(intel_pt_insn, *ip);
  416. insn_cnt += 1;
  417. if (intel_pt_insn->branch != INTEL_PT_BR_NO_BRANCH)
  418. goto out;
  419. if (max_insn_cnt && insn_cnt >= max_insn_cnt)
  420. goto out_no_cache;
  421. *ip += intel_pt_insn->length;
  422. if (to_ip && *ip == to_ip)
  423. goto out_no_cache;
  424. if (*ip >= al.map->end)
  425. break;
  426. offset += intel_pt_insn->length;
  427. }
  428. one_map = false;
  429. }
  430. out:
  431. *insn_cnt_ptr = insn_cnt;
  432. if (!one_map)
  433. goto out_no_cache;
  434. /*
  435. * Didn't lookup in the 'to_ip' case, so do it now to prevent duplicate
  436. * entries.
  437. */
  438. if (to_ip) {
  439. struct intel_pt_cache_entry *e;
  440. e = intel_pt_cache_lookup(al.map->dso, machine, start_offset);
  441. if (e)
  442. return 0;
  443. }
  444. /* Ignore cache errors */
  445. intel_pt_cache_add(al.map->dso, machine, start_offset, insn_cnt,
  446. *ip - start_ip, intel_pt_insn);
  447. return 0;
  448. out_no_cache:
  449. *insn_cnt_ptr = insn_cnt;
  450. return 0;
  451. }
  452. static bool intel_pt_match_pgd_ip(struct intel_pt *pt, uint64_t ip,
  453. uint64_t offset, const char *filename)
  454. {
  455. struct addr_filter *filt;
  456. bool have_filter = false;
  457. bool hit_tracestop = false;
  458. bool hit_filter = false;
  459. list_for_each_entry(filt, &pt->filts.head, list) {
  460. if (filt->start)
  461. have_filter = true;
  462. if ((filename && !filt->filename) ||
  463. (!filename && filt->filename) ||
  464. (filename && strcmp(filename, filt->filename)))
  465. continue;
  466. if (!(offset >= filt->addr && offset < filt->addr + filt->size))
  467. continue;
  468. intel_pt_log("TIP.PGD ip %#"PRIx64" offset %#"PRIx64" in %s hit filter: %s offset %#"PRIx64" size %#"PRIx64"\n",
  469. ip, offset, filename ? filename : "[kernel]",
  470. filt->start ? "filter" : "stop",
  471. filt->addr, filt->size);
  472. if (filt->start)
  473. hit_filter = true;
  474. else
  475. hit_tracestop = true;
  476. }
  477. if (!hit_tracestop && !hit_filter)
  478. intel_pt_log("TIP.PGD ip %#"PRIx64" offset %#"PRIx64" in %s is not in a filter region\n",
  479. ip, offset, filename ? filename : "[kernel]");
  480. return hit_tracestop || (have_filter && !hit_filter);
  481. }
  482. static int __intel_pt_pgd_ip(uint64_t ip, void *data)
  483. {
  484. struct intel_pt_queue *ptq = data;
  485. struct thread *thread;
  486. struct addr_location al;
  487. u8 cpumode;
  488. u64 offset;
  489. if (ip >= ptq->pt->kernel_start)
  490. return intel_pt_match_pgd_ip(ptq->pt, ip, ip, NULL);
  491. cpumode = PERF_RECORD_MISC_USER;
  492. thread = ptq->thread;
  493. if (!thread)
  494. return -EINVAL;
  495. thread__find_addr_map(thread, cpumode, MAP__FUNCTION, ip, &al);
  496. if (!al.map || !al.map->dso)
  497. return -EINVAL;
  498. offset = al.map->map_ip(al.map, ip);
  499. return intel_pt_match_pgd_ip(ptq->pt, ip, offset,
  500. al.map->dso->long_name);
  501. }
  502. static bool intel_pt_pgd_ip(uint64_t ip, void *data)
  503. {
  504. return __intel_pt_pgd_ip(ip, data) > 0;
  505. }
  506. static bool intel_pt_get_config(struct intel_pt *pt,
  507. struct perf_event_attr *attr, u64 *config)
  508. {
  509. if (attr->type == pt->pmu_type) {
  510. if (config)
  511. *config = attr->config;
  512. return true;
  513. }
  514. return false;
  515. }
  516. static bool intel_pt_exclude_kernel(struct intel_pt *pt)
  517. {
  518. struct perf_evsel *evsel;
  519. evlist__for_each_entry(pt->session->evlist, evsel) {
  520. if (intel_pt_get_config(pt, &evsel->attr, NULL) &&
  521. !evsel->attr.exclude_kernel)
  522. return false;
  523. }
  524. return true;
  525. }
  526. static bool intel_pt_return_compression(struct intel_pt *pt)
  527. {
  528. struct perf_evsel *evsel;
  529. u64 config;
  530. if (!pt->noretcomp_bit)
  531. return true;
  532. evlist__for_each_entry(pt->session->evlist, evsel) {
  533. if (intel_pt_get_config(pt, &evsel->attr, &config) &&
  534. (config & pt->noretcomp_bit))
  535. return false;
  536. }
  537. return true;
  538. }
  539. static bool intel_pt_branch_enable(struct intel_pt *pt)
  540. {
  541. struct perf_evsel *evsel;
  542. u64 config;
  543. evlist__for_each_entry(pt->session->evlist, evsel) {
  544. if (intel_pt_get_config(pt, &evsel->attr, &config) &&
  545. (config & 1) && !(config & 0x2000))
  546. return false;
  547. }
  548. return true;
  549. }
  550. static unsigned int intel_pt_mtc_period(struct intel_pt *pt)
  551. {
  552. struct perf_evsel *evsel;
  553. unsigned int shift;
  554. u64 config;
  555. if (!pt->mtc_freq_bits)
  556. return 0;
  557. for (shift = 0, config = pt->mtc_freq_bits; !(config & 1); shift++)
  558. config >>= 1;
  559. evlist__for_each_entry(pt->session->evlist, evsel) {
  560. if (intel_pt_get_config(pt, &evsel->attr, &config))
  561. return (config & pt->mtc_freq_bits) >> shift;
  562. }
  563. return 0;
  564. }
  565. static bool intel_pt_timeless_decoding(struct intel_pt *pt)
  566. {
  567. struct perf_evsel *evsel;
  568. bool timeless_decoding = true;
  569. u64 config;
  570. if (!pt->tsc_bit || !pt->cap_user_time_zero)
  571. return true;
  572. evlist__for_each_entry(pt->session->evlist, evsel) {
  573. if (!(evsel->attr.sample_type & PERF_SAMPLE_TIME))
  574. return true;
  575. if (intel_pt_get_config(pt, &evsel->attr, &config)) {
  576. if (config & pt->tsc_bit)
  577. timeless_decoding = false;
  578. else
  579. return true;
  580. }
  581. }
  582. return timeless_decoding;
  583. }
  584. static bool intel_pt_tracing_kernel(struct intel_pt *pt)
  585. {
  586. struct perf_evsel *evsel;
  587. evlist__for_each_entry(pt->session->evlist, evsel) {
  588. if (intel_pt_get_config(pt, &evsel->attr, NULL) &&
  589. !evsel->attr.exclude_kernel)
  590. return true;
  591. }
  592. return false;
  593. }
  594. static bool intel_pt_have_tsc(struct intel_pt *pt)
  595. {
  596. struct perf_evsel *evsel;
  597. bool have_tsc = false;
  598. u64 config;
  599. if (!pt->tsc_bit)
  600. return false;
  601. evlist__for_each_entry(pt->session->evlist, evsel) {
  602. if (intel_pt_get_config(pt, &evsel->attr, &config)) {
  603. if (config & pt->tsc_bit)
  604. have_tsc = true;
  605. else
  606. return false;
  607. }
  608. }
  609. return have_tsc;
  610. }
  611. static u64 intel_pt_ns_to_ticks(const struct intel_pt *pt, u64 ns)
  612. {
  613. u64 quot, rem;
  614. quot = ns / pt->tc.time_mult;
  615. rem = ns % pt->tc.time_mult;
  616. return (quot << pt->tc.time_shift) + (rem << pt->tc.time_shift) /
  617. pt->tc.time_mult;
  618. }
  619. static struct intel_pt_queue *intel_pt_alloc_queue(struct intel_pt *pt,
  620. unsigned int queue_nr)
  621. {
  622. struct intel_pt_params params = { .get_trace = 0, };
  623. struct intel_pt_queue *ptq;
  624. ptq = zalloc(sizeof(struct intel_pt_queue));
  625. if (!ptq)
  626. return NULL;
  627. if (pt->synth_opts.callchain) {
  628. size_t sz = sizeof(struct ip_callchain);
  629. sz += pt->synth_opts.callchain_sz * sizeof(u64);
  630. ptq->chain = zalloc(sz);
  631. if (!ptq->chain)
  632. goto out_free;
  633. }
  634. if (pt->synth_opts.last_branch) {
  635. size_t sz = sizeof(struct branch_stack);
  636. sz += pt->synth_opts.last_branch_sz *
  637. sizeof(struct branch_entry);
  638. ptq->last_branch = zalloc(sz);
  639. if (!ptq->last_branch)
  640. goto out_free;
  641. ptq->last_branch_rb = zalloc(sz);
  642. if (!ptq->last_branch_rb)
  643. goto out_free;
  644. }
  645. ptq->event_buf = malloc(PERF_SAMPLE_MAX_SIZE);
  646. if (!ptq->event_buf)
  647. goto out_free;
  648. ptq->pt = pt;
  649. ptq->queue_nr = queue_nr;
  650. ptq->exclude_kernel = intel_pt_exclude_kernel(pt);
  651. ptq->pid = -1;
  652. ptq->tid = -1;
  653. ptq->cpu = -1;
  654. ptq->next_tid = -1;
  655. params.get_trace = intel_pt_get_trace;
  656. params.walk_insn = intel_pt_walk_next_insn;
  657. params.data = ptq;
  658. params.return_compression = intel_pt_return_compression(pt);
  659. params.branch_enable = intel_pt_branch_enable(pt);
  660. params.max_non_turbo_ratio = pt->max_non_turbo_ratio;
  661. params.mtc_period = intel_pt_mtc_period(pt);
  662. params.tsc_ctc_ratio_n = pt->tsc_ctc_ratio_n;
  663. params.tsc_ctc_ratio_d = pt->tsc_ctc_ratio_d;
  664. if (pt->filts.cnt > 0)
  665. params.pgd_ip = intel_pt_pgd_ip;
  666. if (pt->synth_opts.instructions) {
  667. if (pt->synth_opts.period) {
  668. switch (pt->synth_opts.period_type) {
  669. case PERF_ITRACE_PERIOD_INSTRUCTIONS:
  670. params.period_type =
  671. INTEL_PT_PERIOD_INSTRUCTIONS;
  672. params.period = pt->synth_opts.period;
  673. break;
  674. case PERF_ITRACE_PERIOD_TICKS:
  675. params.period_type = INTEL_PT_PERIOD_TICKS;
  676. params.period = pt->synth_opts.period;
  677. break;
  678. case PERF_ITRACE_PERIOD_NANOSECS:
  679. params.period_type = INTEL_PT_PERIOD_TICKS;
  680. params.period = intel_pt_ns_to_ticks(pt,
  681. pt->synth_opts.period);
  682. break;
  683. default:
  684. break;
  685. }
  686. }
  687. if (!params.period) {
  688. params.period_type = INTEL_PT_PERIOD_INSTRUCTIONS;
  689. params.period = 1;
  690. }
  691. }
  692. ptq->decoder = intel_pt_decoder_new(&params);
  693. if (!ptq->decoder)
  694. goto out_free;
  695. return ptq;
  696. out_free:
  697. zfree(&ptq->event_buf);
  698. zfree(&ptq->last_branch);
  699. zfree(&ptq->last_branch_rb);
  700. zfree(&ptq->chain);
  701. free(ptq);
  702. return NULL;
  703. }
  704. static void intel_pt_free_queue(void *priv)
  705. {
  706. struct intel_pt_queue *ptq = priv;
  707. if (!ptq)
  708. return;
  709. thread__zput(ptq->thread);
  710. intel_pt_decoder_free(ptq->decoder);
  711. zfree(&ptq->event_buf);
  712. zfree(&ptq->last_branch);
  713. zfree(&ptq->last_branch_rb);
  714. zfree(&ptq->chain);
  715. free(ptq);
  716. }
  717. static void intel_pt_set_pid_tid_cpu(struct intel_pt *pt,
  718. struct auxtrace_queue *queue)
  719. {
  720. struct intel_pt_queue *ptq = queue->priv;
  721. if (queue->tid == -1 || pt->have_sched_switch) {
  722. ptq->tid = machine__get_current_tid(pt->machine, ptq->cpu);
  723. thread__zput(ptq->thread);
  724. }
  725. if (!ptq->thread && ptq->tid != -1)
  726. ptq->thread = machine__find_thread(pt->machine, -1, ptq->tid);
  727. if (ptq->thread) {
  728. ptq->pid = ptq->thread->pid_;
  729. if (queue->cpu == -1)
  730. ptq->cpu = ptq->thread->cpu;
  731. }
  732. }
  733. static void intel_pt_sample_flags(struct intel_pt_queue *ptq)
  734. {
  735. if (ptq->state->flags & INTEL_PT_ABORT_TX) {
  736. ptq->flags = PERF_IP_FLAG_BRANCH | PERF_IP_FLAG_TX_ABORT;
  737. } else if (ptq->state->flags & INTEL_PT_ASYNC) {
  738. if (ptq->state->to_ip)
  739. ptq->flags = PERF_IP_FLAG_BRANCH | PERF_IP_FLAG_CALL |
  740. PERF_IP_FLAG_ASYNC |
  741. PERF_IP_FLAG_INTERRUPT;
  742. else
  743. ptq->flags = PERF_IP_FLAG_BRANCH |
  744. PERF_IP_FLAG_TRACE_END;
  745. ptq->insn_len = 0;
  746. } else {
  747. if (ptq->state->from_ip)
  748. ptq->flags = intel_pt_insn_type(ptq->state->insn_op);
  749. else
  750. ptq->flags = PERF_IP_FLAG_BRANCH |
  751. PERF_IP_FLAG_TRACE_BEGIN;
  752. if (ptq->state->flags & INTEL_PT_IN_TX)
  753. ptq->flags |= PERF_IP_FLAG_IN_TX;
  754. ptq->insn_len = ptq->state->insn_len;
  755. memcpy(ptq->insn, ptq->state->insn, INTEL_PT_INSN_BUF_SZ);
  756. }
  757. }
  758. static int intel_pt_setup_queue(struct intel_pt *pt,
  759. struct auxtrace_queue *queue,
  760. unsigned int queue_nr)
  761. {
  762. struct intel_pt_queue *ptq = queue->priv;
  763. if (list_empty(&queue->head))
  764. return 0;
  765. if (!ptq) {
  766. ptq = intel_pt_alloc_queue(pt, queue_nr);
  767. if (!ptq)
  768. return -ENOMEM;
  769. queue->priv = ptq;
  770. if (queue->cpu != -1)
  771. ptq->cpu = queue->cpu;
  772. ptq->tid = queue->tid;
  773. if (pt->sampling_mode && !pt->snapshot_mode &&
  774. pt->timeless_decoding)
  775. ptq->step_through_buffers = true;
  776. ptq->sync_switch = pt->sync_switch;
  777. }
  778. if (!ptq->on_heap &&
  779. (!ptq->sync_switch ||
  780. ptq->switch_state != INTEL_PT_SS_EXPECTING_SWITCH_EVENT)) {
  781. const struct intel_pt_state *state;
  782. int ret;
  783. if (pt->timeless_decoding)
  784. return 0;
  785. intel_pt_log("queue %u getting timestamp\n", queue_nr);
  786. intel_pt_log("queue %u decoding cpu %d pid %d tid %d\n",
  787. queue_nr, ptq->cpu, ptq->pid, ptq->tid);
  788. while (1) {
  789. state = intel_pt_decode(ptq->decoder);
  790. if (state->err) {
  791. if (state->err == INTEL_PT_ERR_NODATA) {
  792. intel_pt_log("queue %u has no timestamp\n",
  793. queue_nr);
  794. return 0;
  795. }
  796. continue;
  797. }
  798. if (state->timestamp)
  799. break;
  800. }
  801. ptq->timestamp = state->timestamp;
  802. intel_pt_log("queue %u timestamp 0x%" PRIx64 "\n",
  803. queue_nr, ptq->timestamp);
  804. ptq->state = state;
  805. ptq->have_sample = true;
  806. intel_pt_sample_flags(ptq);
  807. ret = auxtrace_heap__add(&pt->heap, queue_nr, ptq->timestamp);
  808. if (ret)
  809. return ret;
  810. ptq->on_heap = true;
  811. }
  812. return 0;
  813. }
  814. static int intel_pt_setup_queues(struct intel_pt *pt)
  815. {
  816. unsigned int i;
  817. int ret;
  818. for (i = 0; i < pt->queues.nr_queues; i++) {
  819. ret = intel_pt_setup_queue(pt, &pt->queues.queue_array[i], i);
  820. if (ret)
  821. return ret;
  822. }
  823. return 0;
  824. }
  825. static inline void intel_pt_copy_last_branch_rb(struct intel_pt_queue *ptq)
  826. {
  827. struct branch_stack *bs_src = ptq->last_branch_rb;
  828. struct branch_stack *bs_dst = ptq->last_branch;
  829. size_t nr = 0;
  830. bs_dst->nr = bs_src->nr;
  831. if (!bs_src->nr)
  832. return;
  833. nr = ptq->pt->synth_opts.last_branch_sz - ptq->last_branch_pos;
  834. memcpy(&bs_dst->entries[0],
  835. &bs_src->entries[ptq->last_branch_pos],
  836. sizeof(struct branch_entry) * nr);
  837. if (bs_src->nr >= ptq->pt->synth_opts.last_branch_sz) {
  838. memcpy(&bs_dst->entries[nr],
  839. &bs_src->entries[0],
  840. sizeof(struct branch_entry) * ptq->last_branch_pos);
  841. }
  842. }
  843. static inline void intel_pt_reset_last_branch_rb(struct intel_pt_queue *ptq)
  844. {
  845. ptq->last_branch_pos = 0;
  846. ptq->last_branch_rb->nr = 0;
  847. }
  848. static void intel_pt_update_last_branch_rb(struct intel_pt_queue *ptq)
  849. {
  850. const struct intel_pt_state *state = ptq->state;
  851. struct branch_stack *bs = ptq->last_branch_rb;
  852. struct branch_entry *be;
  853. if (!ptq->last_branch_pos)
  854. ptq->last_branch_pos = ptq->pt->synth_opts.last_branch_sz;
  855. ptq->last_branch_pos -= 1;
  856. be = &bs->entries[ptq->last_branch_pos];
  857. be->from = state->from_ip;
  858. be->to = state->to_ip;
  859. be->flags.abort = !!(state->flags & INTEL_PT_ABORT_TX);
  860. be->flags.in_tx = !!(state->flags & INTEL_PT_IN_TX);
  861. /* No support for mispredict */
  862. be->flags.mispred = ptq->pt->mispred_all;
  863. if (bs->nr < ptq->pt->synth_opts.last_branch_sz)
  864. bs->nr += 1;
  865. }
  866. static inline bool intel_pt_skip_event(struct intel_pt *pt)
  867. {
  868. return pt->synth_opts.initial_skip &&
  869. pt->num_events++ < pt->synth_opts.initial_skip;
  870. }
  871. static void intel_pt_prep_b_sample(struct intel_pt *pt,
  872. struct intel_pt_queue *ptq,
  873. union perf_event *event,
  874. struct perf_sample *sample)
  875. {
  876. event->sample.header.type = PERF_RECORD_SAMPLE;
  877. event->sample.header.misc = PERF_RECORD_MISC_USER;
  878. event->sample.header.size = sizeof(struct perf_event_header);
  879. if (!pt->timeless_decoding)
  880. sample->time = tsc_to_perf_time(ptq->timestamp, &pt->tc);
  881. sample->cpumode = PERF_RECORD_MISC_USER;
  882. sample->ip = ptq->state->from_ip;
  883. sample->pid = ptq->pid;
  884. sample->tid = ptq->tid;
  885. sample->addr = ptq->state->to_ip;
  886. sample->period = 1;
  887. sample->cpu = ptq->cpu;
  888. sample->flags = ptq->flags;
  889. sample->insn_len = ptq->insn_len;
  890. memcpy(sample->insn, ptq->insn, INTEL_PT_INSN_BUF_SZ);
  891. }
  892. static int intel_pt_inject_event(union perf_event *event,
  893. struct perf_sample *sample, u64 type)
  894. {
  895. event->header.size = perf_event__sample_event_size(sample, type, 0);
  896. return perf_event__synthesize_sample(event, type, 0, sample);
  897. }
  898. static inline int intel_pt_opt_inject(struct intel_pt *pt,
  899. union perf_event *event,
  900. struct perf_sample *sample, u64 type)
  901. {
  902. if (!pt->synth_opts.inject)
  903. return 0;
  904. return intel_pt_inject_event(event, sample, type);
  905. }
  906. static int intel_pt_deliver_synth_b_event(struct intel_pt *pt,
  907. union perf_event *event,
  908. struct perf_sample *sample, u64 type)
  909. {
  910. int ret;
  911. ret = intel_pt_opt_inject(pt, event, sample, type);
  912. if (ret)
  913. return ret;
  914. ret = perf_session__deliver_synth_event(pt->session, event, sample);
  915. if (ret)
  916. pr_err("Intel PT: failed to deliver event, error %d\n", ret);
  917. return ret;
  918. }
  919. static int intel_pt_synth_branch_sample(struct intel_pt_queue *ptq)
  920. {
  921. struct intel_pt *pt = ptq->pt;
  922. union perf_event *event = ptq->event_buf;
  923. struct perf_sample sample = { .ip = 0, };
  924. struct dummy_branch_stack {
  925. u64 nr;
  926. struct branch_entry entries;
  927. } dummy_bs;
  928. if (pt->branches_filter && !(pt->branches_filter & ptq->flags))
  929. return 0;
  930. if (intel_pt_skip_event(pt))
  931. return 0;
  932. intel_pt_prep_b_sample(pt, ptq, event, &sample);
  933. sample.id = ptq->pt->branches_id;
  934. sample.stream_id = ptq->pt->branches_id;
  935. /*
  936. * perf report cannot handle events without a branch stack when using
  937. * SORT_MODE__BRANCH so make a dummy one.
  938. */
  939. if (pt->synth_opts.last_branch && sort__mode == SORT_MODE__BRANCH) {
  940. dummy_bs = (struct dummy_branch_stack){
  941. .nr = 1,
  942. .entries = {
  943. .from = sample.ip,
  944. .to = sample.addr,
  945. },
  946. };
  947. sample.branch_stack = (struct branch_stack *)&dummy_bs;
  948. }
  949. return intel_pt_deliver_synth_b_event(pt, event, &sample,
  950. pt->branches_sample_type);
  951. }
  952. static void intel_pt_prep_sample(struct intel_pt *pt,
  953. struct intel_pt_queue *ptq,
  954. union perf_event *event,
  955. struct perf_sample *sample)
  956. {
  957. intel_pt_prep_b_sample(pt, ptq, event, sample);
  958. if (pt->synth_opts.callchain) {
  959. thread_stack__sample(ptq->thread, ptq->chain,
  960. pt->synth_opts.callchain_sz, sample->ip);
  961. sample->callchain = ptq->chain;
  962. }
  963. if (pt->synth_opts.last_branch) {
  964. intel_pt_copy_last_branch_rb(ptq);
  965. sample->branch_stack = ptq->last_branch;
  966. }
  967. }
  968. static inline int intel_pt_deliver_synth_event(struct intel_pt *pt,
  969. struct intel_pt_queue *ptq,
  970. union perf_event *event,
  971. struct perf_sample *sample,
  972. u64 type)
  973. {
  974. int ret;
  975. ret = intel_pt_deliver_synth_b_event(pt, event, sample, type);
  976. if (pt->synth_opts.last_branch)
  977. intel_pt_reset_last_branch_rb(ptq);
  978. return ret;
  979. }
  980. static int intel_pt_synth_instruction_sample(struct intel_pt_queue *ptq)
  981. {
  982. struct intel_pt *pt = ptq->pt;
  983. union perf_event *event = ptq->event_buf;
  984. struct perf_sample sample = { .ip = 0, };
  985. if (intel_pt_skip_event(pt))
  986. return 0;
  987. intel_pt_prep_sample(pt, ptq, event, &sample);
  988. sample.id = ptq->pt->instructions_id;
  989. sample.stream_id = ptq->pt->instructions_id;
  990. sample.period = ptq->state->tot_insn_cnt - ptq->last_insn_cnt;
  991. ptq->last_insn_cnt = ptq->state->tot_insn_cnt;
  992. return intel_pt_deliver_synth_event(pt, ptq, event, &sample,
  993. pt->instructions_sample_type);
  994. }
  995. static int intel_pt_synth_transaction_sample(struct intel_pt_queue *ptq)
  996. {
  997. struct intel_pt *pt = ptq->pt;
  998. union perf_event *event = ptq->event_buf;
  999. struct perf_sample sample = { .ip = 0, };
  1000. if (intel_pt_skip_event(pt))
  1001. return 0;
  1002. intel_pt_prep_sample(pt, ptq, event, &sample);
  1003. sample.id = ptq->pt->transactions_id;
  1004. sample.stream_id = ptq->pt->transactions_id;
  1005. return intel_pt_deliver_synth_event(pt, ptq, event, &sample,
  1006. pt->transactions_sample_type);
  1007. }
  1008. static void intel_pt_prep_p_sample(struct intel_pt *pt,
  1009. struct intel_pt_queue *ptq,
  1010. union perf_event *event,
  1011. struct perf_sample *sample)
  1012. {
  1013. intel_pt_prep_sample(pt, ptq, event, sample);
  1014. /*
  1015. * Zero IP is used to mean "trace start" but that is not the case for
  1016. * power or PTWRITE events with no IP, so clear the flags.
  1017. */
  1018. if (!sample->ip)
  1019. sample->flags = 0;
  1020. }
  1021. static int intel_pt_synth_ptwrite_sample(struct intel_pt_queue *ptq)
  1022. {
  1023. struct intel_pt *pt = ptq->pt;
  1024. union perf_event *event = ptq->event_buf;
  1025. struct perf_sample sample = { .ip = 0, };
  1026. struct perf_synth_intel_ptwrite raw;
  1027. if (intel_pt_skip_event(pt))
  1028. return 0;
  1029. intel_pt_prep_p_sample(pt, ptq, event, &sample);
  1030. sample.id = ptq->pt->ptwrites_id;
  1031. sample.stream_id = ptq->pt->ptwrites_id;
  1032. raw.flags = 0;
  1033. raw.ip = !!(ptq->state->flags & INTEL_PT_FUP_IP);
  1034. raw.payload = cpu_to_le64(ptq->state->ptw_payload);
  1035. sample.raw_size = perf_synth__raw_size(raw);
  1036. sample.raw_data = perf_synth__raw_data(&raw);
  1037. return intel_pt_deliver_synth_event(pt, ptq, event, &sample,
  1038. pt->ptwrites_sample_type);
  1039. }
  1040. static int intel_pt_synth_cbr_sample(struct intel_pt_queue *ptq)
  1041. {
  1042. struct intel_pt *pt = ptq->pt;
  1043. union perf_event *event = ptq->event_buf;
  1044. struct perf_sample sample = { .ip = 0, };
  1045. struct perf_synth_intel_cbr raw;
  1046. u32 flags;
  1047. if (intel_pt_skip_event(pt))
  1048. return 0;
  1049. intel_pt_prep_p_sample(pt, ptq, event, &sample);
  1050. sample.id = ptq->pt->cbr_id;
  1051. sample.stream_id = ptq->pt->cbr_id;
  1052. flags = (u16)ptq->state->cbr_payload | (pt->max_non_turbo_ratio << 16);
  1053. raw.flags = cpu_to_le32(flags);
  1054. raw.freq = cpu_to_le32(raw.cbr * pt->cbr2khz);
  1055. raw.reserved3 = 0;
  1056. sample.raw_size = perf_synth__raw_size(raw);
  1057. sample.raw_data = perf_synth__raw_data(&raw);
  1058. return intel_pt_deliver_synth_event(pt, ptq, event, &sample,
  1059. pt->pwr_events_sample_type);
  1060. }
  1061. static int intel_pt_synth_mwait_sample(struct intel_pt_queue *ptq)
  1062. {
  1063. struct intel_pt *pt = ptq->pt;
  1064. union perf_event *event = ptq->event_buf;
  1065. struct perf_sample sample = { .ip = 0, };
  1066. struct perf_synth_intel_mwait raw;
  1067. if (intel_pt_skip_event(pt))
  1068. return 0;
  1069. intel_pt_prep_p_sample(pt, ptq, event, &sample);
  1070. sample.id = ptq->pt->mwait_id;
  1071. sample.stream_id = ptq->pt->mwait_id;
  1072. raw.reserved = 0;
  1073. raw.payload = cpu_to_le64(ptq->state->mwait_payload);
  1074. sample.raw_size = perf_synth__raw_size(raw);
  1075. sample.raw_data = perf_synth__raw_data(&raw);
  1076. return intel_pt_deliver_synth_event(pt, ptq, event, &sample,
  1077. pt->pwr_events_sample_type);
  1078. }
  1079. static int intel_pt_synth_pwre_sample(struct intel_pt_queue *ptq)
  1080. {
  1081. struct intel_pt *pt = ptq->pt;
  1082. union perf_event *event = ptq->event_buf;
  1083. struct perf_sample sample = { .ip = 0, };
  1084. struct perf_synth_intel_pwre raw;
  1085. if (intel_pt_skip_event(pt))
  1086. return 0;
  1087. intel_pt_prep_p_sample(pt, ptq, event, &sample);
  1088. sample.id = ptq->pt->pwre_id;
  1089. sample.stream_id = ptq->pt->pwre_id;
  1090. raw.reserved = 0;
  1091. raw.payload = cpu_to_le64(ptq->state->pwre_payload);
  1092. sample.raw_size = perf_synth__raw_size(raw);
  1093. sample.raw_data = perf_synth__raw_data(&raw);
  1094. return intel_pt_deliver_synth_event(pt, ptq, event, &sample,
  1095. pt->pwr_events_sample_type);
  1096. }
  1097. static int intel_pt_synth_exstop_sample(struct intel_pt_queue *ptq)
  1098. {
  1099. struct intel_pt *pt = ptq->pt;
  1100. union perf_event *event = ptq->event_buf;
  1101. struct perf_sample sample = { .ip = 0, };
  1102. struct perf_synth_intel_exstop raw;
  1103. if (intel_pt_skip_event(pt))
  1104. return 0;
  1105. intel_pt_prep_p_sample(pt, ptq, event, &sample);
  1106. sample.id = ptq->pt->exstop_id;
  1107. sample.stream_id = ptq->pt->exstop_id;
  1108. raw.flags = 0;
  1109. raw.ip = !!(ptq->state->flags & INTEL_PT_FUP_IP);
  1110. sample.raw_size = perf_synth__raw_size(raw);
  1111. sample.raw_data = perf_synth__raw_data(&raw);
  1112. return intel_pt_deliver_synth_event(pt, ptq, event, &sample,
  1113. pt->pwr_events_sample_type);
  1114. }
  1115. static int intel_pt_synth_pwrx_sample(struct intel_pt_queue *ptq)
  1116. {
  1117. struct intel_pt *pt = ptq->pt;
  1118. union perf_event *event = ptq->event_buf;
  1119. struct perf_sample sample = { .ip = 0, };
  1120. struct perf_synth_intel_pwrx raw;
  1121. if (intel_pt_skip_event(pt))
  1122. return 0;
  1123. intel_pt_prep_p_sample(pt, ptq, event, &sample);
  1124. sample.id = ptq->pt->pwrx_id;
  1125. sample.stream_id = ptq->pt->pwrx_id;
  1126. raw.reserved = 0;
  1127. raw.payload = cpu_to_le64(ptq->state->pwrx_payload);
  1128. sample.raw_size = perf_synth__raw_size(raw);
  1129. sample.raw_data = perf_synth__raw_data(&raw);
  1130. return intel_pt_deliver_synth_event(pt, ptq, event, &sample,
  1131. pt->pwr_events_sample_type);
  1132. }
  1133. static int intel_pt_synth_error(struct intel_pt *pt, int code, int cpu,
  1134. pid_t pid, pid_t tid, u64 ip)
  1135. {
  1136. union perf_event event;
  1137. char msg[MAX_AUXTRACE_ERROR_MSG];
  1138. int err;
  1139. intel_pt__strerror(code, msg, MAX_AUXTRACE_ERROR_MSG);
  1140. auxtrace_synth_error(&event.auxtrace_error, PERF_AUXTRACE_ERROR_ITRACE,
  1141. code, cpu, pid, tid, ip, msg);
  1142. err = perf_session__deliver_synth_event(pt->session, &event, NULL);
  1143. if (err)
  1144. pr_err("Intel Processor Trace: failed to deliver error event, error %d\n",
  1145. err);
  1146. return err;
  1147. }
  1148. static int intel_pt_next_tid(struct intel_pt *pt, struct intel_pt_queue *ptq)
  1149. {
  1150. struct auxtrace_queue *queue;
  1151. pid_t tid = ptq->next_tid;
  1152. int err;
  1153. if (tid == -1)
  1154. return 0;
  1155. intel_pt_log("switch: cpu %d tid %d\n", ptq->cpu, tid);
  1156. err = machine__set_current_tid(pt->machine, ptq->cpu, -1, tid);
  1157. queue = &pt->queues.queue_array[ptq->queue_nr];
  1158. intel_pt_set_pid_tid_cpu(pt, queue);
  1159. ptq->next_tid = -1;
  1160. return err;
  1161. }
  1162. static inline bool intel_pt_is_switch_ip(struct intel_pt_queue *ptq, u64 ip)
  1163. {
  1164. struct intel_pt *pt = ptq->pt;
  1165. return ip == pt->switch_ip &&
  1166. (ptq->flags & PERF_IP_FLAG_BRANCH) &&
  1167. !(ptq->flags & (PERF_IP_FLAG_CONDITIONAL | PERF_IP_FLAG_ASYNC |
  1168. PERF_IP_FLAG_INTERRUPT | PERF_IP_FLAG_TX_ABORT));
  1169. }
  1170. #define INTEL_PT_PWR_EVT (INTEL_PT_MWAIT_OP | INTEL_PT_PWR_ENTRY | \
  1171. INTEL_PT_EX_STOP | INTEL_PT_PWR_EXIT | \
  1172. INTEL_PT_CBR_CHG)
  1173. static int intel_pt_sample(struct intel_pt_queue *ptq)
  1174. {
  1175. const struct intel_pt_state *state = ptq->state;
  1176. struct intel_pt *pt = ptq->pt;
  1177. int err;
  1178. if (!ptq->have_sample)
  1179. return 0;
  1180. ptq->have_sample = false;
  1181. if (pt->sample_pwr_events && (state->type & INTEL_PT_PWR_EVT)) {
  1182. if (state->type & INTEL_PT_CBR_CHG) {
  1183. err = intel_pt_synth_cbr_sample(ptq);
  1184. if (err)
  1185. return err;
  1186. }
  1187. if (state->type & INTEL_PT_MWAIT_OP) {
  1188. err = intel_pt_synth_mwait_sample(ptq);
  1189. if (err)
  1190. return err;
  1191. }
  1192. if (state->type & INTEL_PT_PWR_ENTRY) {
  1193. err = intel_pt_synth_pwre_sample(ptq);
  1194. if (err)
  1195. return err;
  1196. }
  1197. if (state->type & INTEL_PT_EX_STOP) {
  1198. err = intel_pt_synth_exstop_sample(ptq);
  1199. if (err)
  1200. return err;
  1201. }
  1202. if (state->type & INTEL_PT_PWR_EXIT) {
  1203. err = intel_pt_synth_pwrx_sample(ptq);
  1204. if (err)
  1205. return err;
  1206. }
  1207. }
  1208. if (pt->sample_instructions && (state->type & INTEL_PT_INSTRUCTION)) {
  1209. err = intel_pt_synth_instruction_sample(ptq);
  1210. if (err)
  1211. return err;
  1212. }
  1213. if (pt->sample_transactions && (state->type & INTEL_PT_TRANSACTION)) {
  1214. err = intel_pt_synth_transaction_sample(ptq);
  1215. if (err)
  1216. return err;
  1217. }
  1218. if (pt->sample_ptwrites && (state->type & INTEL_PT_PTW)) {
  1219. err = intel_pt_synth_ptwrite_sample(ptq);
  1220. if (err)
  1221. return err;
  1222. }
  1223. if (!(state->type & INTEL_PT_BRANCH))
  1224. return 0;
  1225. if (pt->synth_opts.callchain || pt->synth_opts.thread_stack)
  1226. thread_stack__event(ptq->thread, ptq->flags, state->from_ip,
  1227. state->to_ip, ptq->insn_len,
  1228. state->trace_nr);
  1229. else
  1230. thread_stack__set_trace_nr(ptq->thread, state->trace_nr);
  1231. if (pt->sample_branches) {
  1232. err = intel_pt_synth_branch_sample(ptq);
  1233. if (err)
  1234. return err;
  1235. }
  1236. if (pt->synth_opts.last_branch)
  1237. intel_pt_update_last_branch_rb(ptq);
  1238. if (!ptq->sync_switch)
  1239. return 0;
  1240. if (intel_pt_is_switch_ip(ptq, state->to_ip)) {
  1241. switch (ptq->switch_state) {
  1242. case INTEL_PT_SS_UNKNOWN:
  1243. case INTEL_PT_SS_EXPECTING_SWITCH_IP:
  1244. err = intel_pt_next_tid(pt, ptq);
  1245. if (err)
  1246. return err;
  1247. ptq->switch_state = INTEL_PT_SS_TRACING;
  1248. break;
  1249. default:
  1250. ptq->switch_state = INTEL_PT_SS_EXPECTING_SWITCH_EVENT;
  1251. return 1;
  1252. }
  1253. } else if (!state->to_ip) {
  1254. ptq->switch_state = INTEL_PT_SS_NOT_TRACING;
  1255. } else if (ptq->switch_state == INTEL_PT_SS_NOT_TRACING) {
  1256. ptq->switch_state = INTEL_PT_SS_UNKNOWN;
  1257. } else if (ptq->switch_state == INTEL_PT_SS_UNKNOWN &&
  1258. state->to_ip == pt->ptss_ip &&
  1259. (ptq->flags & PERF_IP_FLAG_CALL)) {
  1260. ptq->switch_state = INTEL_PT_SS_TRACING;
  1261. }
  1262. return 0;
  1263. }
  1264. static u64 intel_pt_switch_ip(struct intel_pt *pt, u64 *ptss_ip)
  1265. {
  1266. struct machine *machine = pt->machine;
  1267. struct map *map;
  1268. struct symbol *sym, *start;
  1269. u64 ip, switch_ip = 0;
  1270. const char *ptss;
  1271. if (ptss_ip)
  1272. *ptss_ip = 0;
  1273. map = machine__kernel_map(machine);
  1274. if (!map)
  1275. return 0;
  1276. if (map__load(map))
  1277. return 0;
  1278. start = dso__first_symbol(map->dso, MAP__FUNCTION);
  1279. for (sym = start; sym; sym = dso__next_symbol(sym)) {
  1280. if (sym->binding == STB_GLOBAL &&
  1281. !strcmp(sym->name, "__switch_to")) {
  1282. ip = map->unmap_ip(map, sym->start);
  1283. if (ip >= map->start && ip < map->end) {
  1284. switch_ip = ip;
  1285. break;
  1286. }
  1287. }
  1288. }
  1289. if (!switch_ip || !ptss_ip)
  1290. return 0;
  1291. if (pt->have_sched_switch == 1)
  1292. ptss = "perf_trace_sched_switch";
  1293. else
  1294. ptss = "__perf_event_task_sched_out";
  1295. for (sym = start; sym; sym = dso__next_symbol(sym)) {
  1296. if (!strcmp(sym->name, ptss)) {
  1297. ip = map->unmap_ip(map, sym->start);
  1298. if (ip >= map->start && ip < map->end) {
  1299. *ptss_ip = ip;
  1300. break;
  1301. }
  1302. }
  1303. }
  1304. return switch_ip;
  1305. }
  1306. static void intel_pt_enable_sync_switch(struct intel_pt *pt)
  1307. {
  1308. unsigned int i;
  1309. pt->sync_switch = true;
  1310. for (i = 0; i < pt->queues.nr_queues; i++) {
  1311. struct auxtrace_queue *queue = &pt->queues.queue_array[i];
  1312. struct intel_pt_queue *ptq = queue->priv;
  1313. if (ptq)
  1314. ptq->sync_switch = true;
  1315. }
  1316. }
  1317. static int intel_pt_run_decoder(struct intel_pt_queue *ptq, u64 *timestamp)
  1318. {
  1319. const struct intel_pt_state *state = ptq->state;
  1320. struct intel_pt *pt = ptq->pt;
  1321. int err;
  1322. if (!pt->kernel_start) {
  1323. pt->kernel_start = machine__kernel_start(pt->machine);
  1324. if (pt->per_cpu_mmaps &&
  1325. (pt->have_sched_switch == 1 || pt->have_sched_switch == 3) &&
  1326. !pt->timeless_decoding && intel_pt_tracing_kernel(pt) &&
  1327. !pt->sampling_mode) {
  1328. pt->switch_ip = intel_pt_switch_ip(pt, &pt->ptss_ip);
  1329. if (pt->switch_ip) {
  1330. intel_pt_log("switch_ip: %"PRIx64" ptss_ip: %"PRIx64"\n",
  1331. pt->switch_ip, pt->ptss_ip);
  1332. intel_pt_enable_sync_switch(pt);
  1333. }
  1334. }
  1335. }
  1336. intel_pt_log("queue %u decoding cpu %d pid %d tid %d\n",
  1337. ptq->queue_nr, ptq->cpu, ptq->pid, ptq->tid);
  1338. while (1) {
  1339. err = intel_pt_sample(ptq);
  1340. if (err)
  1341. return err;
  1342. state = intel_pt_decode(ptq->decoder);
  1343. if (state->err) {
  1344. if (state->err == INTEL_PT_ERR_NODATA)
  1345. return 1;
  1346. if (ptq->sync_switch &&
  1347. state->from_ip >= pt->kernel_start) {
  1348. ptq->sync_switch = false;
  1349. intel_pt_next_tid(pt, ptq);
  1350. }
  1351. if (pt->synth_opts.errors) {
  1352. err = intel_pt_synth_error(pt, state->err,
  1353. ptq->cpu, ptq->pid,
  1354. ptq->tid,
  1355. state->from_ip);
  1356. if (err)
  1357. return err;
  1358. }
  1359. continue;
  1360. }
  1361. ptq->state = state;
  1362. ptq->have_sample = true;
  1363. intel_pt_sample_flags(ptq);
  1364. /* Use estimated TSC upon return to user space */
  1365. if (pt->est_tsc &&
  1366. (state->from_ip >= pt->kernel_start || !state->from_ip) &&
  1367. state->to_ip && state->to_ip < pt->kernel_start) {
  1368. intel_pt_log("TSC %"PRIx64" est. TSC %"PRIx64"\n",
  1369. state->timestamp, state->est_timestamp);
  1370. ptq->timestamp = state->est_timestamp;
  1371. /* Use estimated TSC in unknown switch state */
  1372. } else if (ptq->sync_switch &&
  1373. ptq->switch_state == INTEL_PT_SS_UNKNOWN &&
  1374. intel_pt_is_switch_ip(ptq, state->to_ip) &&
  1375. ptq->next_tid == -1) {
  1376. intel_pt_log("TSC %"PRIx64" est. TSC %"PRIx64"\n",
  1377. state->timestamp, state->est_timestamp);
  1378. ptq->timestamp = state->est_timestamp;
  1379. } else if (state->timestamp > ptq->timestamp) {
  1380. ptq->timestamp = state->timestamp;
  1381. }
  1382. if (!pt->timeless_decoding && ptq->timestamp >= *timestamp) {
  1383. *timestamp = ptq->timestamp;
  1384. return 0;
  1385. }
  1386. }
  1387. return 0;
  1388. }
  1389. static inline int intel_pt_update_queues(struct intel_pt *pt)
  1390. {
  1391. if (pt->queues.new_data) {
  1392. pt->queues.new_data = false;
  1393. return intel_pt_setup_queues(pt);
  1394. }
  1395. return 0;
  1396. }
  1397. static int intel_pt_process_queues(struct intel_pt *pt, u64 timestamp)
  1398. {
  1399. unsigned int queue_nr;
  1400. u64 ts;
  1401. int ret;
  1402. while (1) {
  1403. struct auxtrace_queue *queue;
  1404. struct intel_pt_queue *ptq;
  1405. if (!pt->heap.heap_cnt)
  1406. return 0;
  1407. if (pt->heap.heap_array[0].ordinal >= timestamp)
  1408. return 0;
  1409. queue_nr = pt->heap.heap_array[0].queue_nr;
  1410. queue = &pt->queues.queue_array[queue_nr];
  1411. ptq = queue->priv;
  1412. intel_pt_log("queue %u processing 0x%" PRIx64 " to 0x%" PRIx64 "\n",
  1413. queue_nr, pt->heap.heap_array[0].ordinal,
  1414. timestamp);
  1415. auxtrace_heap__pop(&pt->heap);
  1416. if (pt->heap.heap_cnt) {
  1417. ts = pt->heap.heap_array[0].ordinal + 1;
  1418. if (ts > timestamp)
  1419. ts = timestamp;
  1420. } else {
  1421. ts = timestamp;
  1422. }
  1423. intel_pt_set_pid_tid_cpu(pt, queue);
  1424. ret = intel_pt_run_decoder(ptq, &ts);
  1425. if (ret < 0) {
  1426. auxtrace_heap__add(&pt->heap, queue_nr, ts);
  1427. return ret;
  1428. }
  1429. if (!ret) {
  1430. ret = auxtrace_heap__add(&pt->heap, queue_nr, ts);
  1431. if (ret < 0)
  1432. return ret;
  1433. } else {
  1434. ptq->on_heap = false;
  1435. }
  1436. }
  1437. return 0;
  1438. }
  1439. static int intel_pt_process_timeless_queues(struct intel_pt *pt, pid_t tid,
  1440. u64 time_)
  1441. {
  1442. struct auxtrace_queues *queues = &pt->queues;
  1443. unsigned int i;
  1444. u64 ts = 0;
  1445. for (i = 0; i < queues->nr_queues; i++) {
  1446. struct auxtrace_queue *queue = &pt->queues.queue_array[i];
  1447. struct intel_pt_queue *ptq = queue->priv;
  1448. if (ptq && (tid == -1 || ptq->tid == tid)) {
  1449. ptq->time = time_;
  1450. intel_pt_set_pid_tid_cpu(pt, queue);
  1451. intel_pt_run_decoder(ptq, &ts);
  1452. }
  1453. }
  1454. return 0;
  1455. }
  1456. static int intel_pt_lost(struct intel_pt *pt, struct perf_sample *sample)
  1457. {
  1458. return intel_pt_synth_error(pt, INTEL_PT_ERR_LOST, sample->cpu,
  1459. sample->pid, sample->tid, 0);
  1460. }
  1461. static struct intel_pt_queue *intel_pt_cpu_to_ptq(struct intel_pt *pt, int cpu)
  1462. {
  1463. unsigned i, j;
  1464. if (cpu < 0 || !pt->queues.nr_queues)
  1465. return NULL;
  1466. if ((unsigned)cpu >= pt->queues.nr_queues)
  1467. i = pt->queues.nr_queues - 1;
  1468. else
  1469. i = cpu;
  1470. if (pt->queues.queue_array[i].cpu == cpu)
  1471. return pt->queues.queue_array[i].priv;
  1472. for (j = 0; i > 0; j++) {
  1473. if (pt->queues.queue_array[--i].cpu == cpu)
  1474. return pt->queues.queue_array[i].priv;
  1475. }
  1476. for (; j < pt->queues.nr_queues; j++) {
  1477. if (pt->queues.queue_array[j].cpu == cpu)
  1478. return pt->queues.queue_array[j].priv;
  1479. }
  1480. return NULL;
  1481. }
  1482. static int intel_pt_sync_switch(struct intel_pt *pt, int cpu, pid_t tid,
  1483. u64 timestamp)
  1484. {
  1485. struct intel_pt_queue *ptq;
  1486. int err;
  1487. if (!pt->sync_switch)
  1488. return 1;
  1489. ptq = intel_pt_cpu_to_ptq(pt, cpu);
  1490. if (!ptq || !ptq->sync_switch)
  1491. return 1;
  1492. switch (ptq->switch_state) {
  1493. case INTEL_PT_SS_NOT_TRACING:
  1494. ptq->next_tid = -1;
  1495. break;
  1496. case INTEL_PT_SS_UNKNOWN:
  1497. case INTEL_PT_SS_TRACING:
  1498. ptq->next_tid = tid;
  1499. ptq->switch_state = INTEL_PT_SS_EXPECTING_SWITCH_IP;
  1500. return 0;
  1501. case INTEL_PT_SS_EXPECTING_SWITCH_EVENT:
  1502. if (!ptq->on_heap) {
  1503. ptq->timestamp = perf_time_to_tsc(timestamp,
  1504. &pt->tc);
  1505. err = auxtrace_heap__add(&pt->heap, ptq->queue_nr,
  1506. ptq->timestamp);
  1507. if (err)
  1508. return err;
  1509. ptq->on_heap = true;
  1510. }
  1511. ptq->switch_state = INTEL_PT_SS_TRACING;
  1512. break;
  1513. case INTEL_PT_SS_EXPECTING_SWITCH_IP:
  1514. ptq->next_tid = tid;
  1515. intel_pt_log("ERROR: cpu %d expecting switch ip\n", cpu);
  1516. break;
  1517. default:
  1518. break;
  1519. }
  1520. return 1;
  1521. }
  1522. static int intel_pt_process_switch(struct intel_pt *pt,
  1523. struct perf_sample *sample)
  1524. {
  1525. struct perf_evsel *evsel;
  1526. pid_t tid;
  1527. int cpu, ret;
  1528. evsel = perf_evlist__id2evsel(pt->session->evlist, sample->id);
  1529. if (evsel != pt->switch_evsel)
  1530. return 0;
  1531. tid = perf_evsel__intval(evsel, sample, "next_pid");
  1532. cpu = sample->cpu;
  1533. intel_pt_log("sched_switch: cpu %d tid %d time %"PRIu64" tsc %#"PRIx64"\n",
  1534. cpu, tid, sample->time, perf_time_to_tsc(sample->time,
  1535. &pt->tc));
  1536. ret = intel_pt_sync_switch(pt, cpu, tid, sample->time);
  1537. if (ret <= 0)
  1538. return ret;
  1539. return machine__set_current_tid(pt->machine, cpu, -1, tid);
  1540. }
  1541. static int intel_pt_context_switch(struct intel_pt *pt, union perf_event *event,
  1542. struct perf_sample *sample)
  1543. {
  1544. bool out = event->header.misc & PERF_RECORD_MISC_SWITCH_OUT;
  1545. pid_t pid, tid;
  1546. int cpu, ret;
  1547. cpu = sample->cpu;
  1548. if (pt->have_sched_switch == 3) {
  1549. if (!out)
  1550. return 0;
  1551. if (event->header.type != PERF_RECORD_SWITCH_CPU_WIDE) {
  1552. pr_err("Expecting CPU-wide context switch event\n");
  1553. return -EINVAL;
  1554. }
  1555. pid = event->context_switch.next_prev_pid;
  1556. tid = event->context_switch.next_prev_tid;
  1557. } else {
  1558. if (out)
  1559. return 0;
  1560. pid = sample->pid;
  1561. tid = sample->tid;
  1562. }
  1563. if (tid == -1) {
  1564. pr_err("context_switch event has no tid\n");
  1565. return -EINVAL;
  1566. }
  1567. intel_pt_log("context_switch: cpu %d pid %d tid %d time %"PRIu64" tsc %#"PRIx64"\n",
  1568. cpu, pid, tid, sample->time, perf_time_to_tsc(sample->time,
  1569. &pt->tc));
  1570. ret = intel_pt_sync_switch(pt, cpu, tid, sample->time);
  1571. if (ret <= 0)
  1572. return ret;
  1573. return machine__set_current_tid(pt->machine, cpu, pid, tid);
  1574. }
  1575. static int intel_pt_process_itrace_start(struct intel_pt *pt,
  1576. union perf_event *event,
  1577. struct perf_sample *sample)
  1578. {
  1579. if (!pt->per_cpu_mmaps)
  1580. return 0;
  1581. intel_pt_log("itrace_start: cpu %d pid %d tid %d time %"PRIu64" tsc %#"PRIx64"\n",
  1582. sample->cpu, event->itrace_start.pid,
  1583. event->itrace_start.tid, sample->time,
  1584. perf_time_to_tsc(sample->time, &pt->tc));
  1585. return machine__set_current_tid(pt->machine, sample->cpu,
  1586. event->itrace_start.pid,
  1587. event->itrace_start.tid);
  1588. }
  1589. static int intel_pt_process_event(struct perf_session *session,
  1590. union perf_event *event,
  1591. struct perf_sample *sample,
  1592. struct perf_tool *tool)
  1593. {
  1594. struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt,
  1595. auxtrace);
  1596. u64 timestamp;
  1597. int err = 0;
  1598. if (dump_trace)
  1599. return 0;
  1600. if (!tool->ordered_events) {
  1601. pr_err("Intel Processor Trace requires ordered events\n");
  1602. return -EINVAL;
  1603. }
  1604. if (sample->time && sample->time != (u64)-1)
  1605. timestamp = perf_time_to_tsc(sample->time, &pt->tc);
  1606. else
  1607. timestamp = 0;
  1608. if (timestamp || pt->timeless_decoding) {
  1609. err = intel_pt_update_queues(pt);
  1610. if (err)
  1611. return err;
  1612. }
  1613. if (pt->timeless_decoding) {
  1614. if (event->header.type == PERF_RECORD_EXIT) {
  1615. err = intel_pt_process_timeless_queues(pt,
  1616. event->fork.tid,
  1617. sample->time);
  1618. }
  1619. } else if (timestamp) {
  1620. err = intel_pt_process_queues(pt, timestamp);
  1621. }
  1622. if (err)
  1623. return err;
  1624. if (event->header.type == PERF_RECORD_AUX &&
  1625. (event->aux.flags & PERF_AUX_FLAG_TRUNCATED) &&
  1626. pt->synth_opts.errors) {
  1627. err = intel_pt_lost(pt, sample);
  1628. if (err)
  1629. return err;
  1630. }
  1631. if (pt->switch_evsel && event->header.type == PERF_RECORD_SAMPLE)
  1632. err = intel_pt_process_switch(pt, sample);
  1633. else if (event->header.type == PERF_RECORD_ITRACE_START)
  1634. err = intel_pt_process_itrace_start(pt, event, sample);
  1635. else if (event->header.type == PERF_RECORD_SWITCH ||
  1636. event->header.type == PERF_RECORD_SWITCH_CPU_WIDE)
  1637. err = intel_pt_context_switch(pt, event, sample);
  1638. intel_pt_log("event %s (%u): cpu %d time %"PRIu64" tsc %#"PRIx64"\n",
  1639. perf_event__name(event->header.type), event->header.type,
  1640. sample->cpu, sample->time, timestamp);
  1641. return err;
  1642. }
  1643. static int intel_pt_flush(struct perf_session *session, struct perf_tool *tool)
  1644. {
  1645. struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt,
  1646. auxtrace);
  1647. int ret;
  1648. if (dump_trace)
  1649. return 0;
  1650. if (!tool->ordered_events)
  1651. return -EINVAL;
  1652. ret = intel_pt_update_queues(pt);
  1653. if (ret < 0)
  1654. return ret;
  1655. if (pt->timeless_decoding)
  1656. return intel_pt_process_timeless_queues(pt, -1,
  1657. MAX_TIMESTAMP - 1);
  1658. return intel_pt_process_queues(pt, MAX_TIMESTAMP);
  1659. }
  1660. static void intel_pt_free_events(struct perf_session *session)
  1661. {
  1662. struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt,
  1663. auxtrace);
  1664. struct auxtrace_queues *queues = &pt->queues;
  1665. unsigned int i;
  1666. for (i = 0; i < queues->nr_queues; i++) {
  1667. intel_pt_free_queue(queues->queue_array[i].priv);
  1668. queues->queue_array[i].priv = NULL;
  1669. }
  1670. intel_pt_log_disable();
  1671. auxtrace_queues__free(queues);
  1672. }
  1673. static void intel_pt_free(struct perf_session *session)
  1674. {
  1675. struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt,
  1676. auxtrace);
  1677. auxtrace_heap__free(&pt->heap);
  1678. intel_pt_free_events(session);
  1679. session->auxtrace = NULL;
  1680. thread__put(pt->unknown_thread);
  1681. addr_filters__exit(&pt->filts);
  1682. zfree(&pt->filter);
  1683. free(pt);
  1684. }
  1685. static int intel_pt_process_auxtrace_event(struct perf_session *session,
  1686. union perf_event *event,
  1687. struct perf_tool *tool __maybe_unused)
  1688. {
  1689. struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt,
  1690. auxtrace);
  1691. if (!pt->data_queued) {
  1692. struct auxtrace_buffer *buffer;
  1693. off_t data_offset;
  1694. int fd = perf_data__fd(session->data);
  1695. int err;
  1696. if (perf_data__is_pipe(session->data)) {
  1697. data_offset = 0;
  1698. } else {
  1699. data_offset = lseek(fd, 0, SEEK_CUR);
  1700. if (data_offset == -1)
  1701. return -errno;
  1702. }
  1703. err = auxtrace_queues__add_event(&pt->queues, session, event,
  1704. data_offset, &buffer);
  1705. if (err)
  1706. return err;
  1707. /* Dump here now we have copied a piped trace out of the pipe */
  1708. if (dump_trace) {
  1709. if (auxtrace_buffer__get_data(buffer, fd)) {
  1710. intel_pt_dump_event(pt, buffer->data,
  1711. buffer->size);
  1712. auxtrace_buffer__put_data(buffer);
  1713. }
  1714. }
  1715. }
  1716. return 0;
  1717. }
  1718. struct intel_pt_synth {
  1719. struct perf_tool dummy_tool;
  1720. struct perf_session *session;
  1721. };
  1722. static int intel_pt_event_synth(struct perf_tool *tool,
  1723. union perf_event *event,
  1724. struct perf_sample *sample __maybe_unused,
  1725. struct machine *machine __maybe_unused)
  1726. {
  1727. struct intel_pt_synth *intel_pt_synth =
  1728. container_of(tool, struct intel_pt_synth, dummy_tool);
  1729. return perf_session__deliver_synth_event(intel_pt_synth->session, event,
  1730. NULL);
  1731. }
  1732. static int intel_pt_synth_event(struct perf_session *session, const char *name,
  1733. struct perf_event_attr *attr, u64 id)
  1734. {
  1735. struct intel_pt_synth intel_pt_synth;
  1736. int err;
  1737. pr_debug("Synthesizing '%s' event with id %" PRIu64 " sample type %#" PRIx64 "\n",
  1738. name, id, (u64)attr->sample_type);
  1739. memset(&intel_pt_synth, 0, sizeof(struct intel_pt_synth));
  1740. intel_pt_synth.session = session;
  1741. err = perf_event__synthesize_attr(&intel_pt_synth.dummy_tool, attr, 1,
  1742. &id, intel_pt_event_synth);
  1743. if (err)
  1744. pr_err("%s: failed to synthesize '%s' event type\n",
  1745. __func__, name);
  1746. return err;
  1747. }
  1748. static void intel_pt_set_event_name(struct perf_evlist *evlist, u64 id,
  1749. const char *name)
  1750. {
  1751. struct perf_evsel *evsel;
  1752. evlist__for_each_entry(evlist, evsel) {
  1753. if (evsel->id && evsel->id[0] == id) {
  1754. if (evsel->name)
  1755. zfree(&evsel->name);
  1756. evsel->name = strdup(name);
  1757. break;
  1758. }
  1759. }
  1760. }
  1761. static struct perf_evsel *intel_pt_evsel(struct intel_pt *pt,
  1762. struct perf_evlist *evlist)
  1763. {
  1764. struct perf_evsel *evsel;
  1765. evlist__for_each_entry(evlist, evsel) {
  1766. if (evsel->attr.type == pt->pmu_type && evsel->ids)
  1767. return evsel;
  1768. }
  1769. return NULL;
  1770. }
  1771. static int intel_pt_synth_events(struct intel_pt *pt,
  1772. struct perf_session *session)
  1773. {
  1774. struct perf_evlist *evlist = session->evlist;
  1775. struct perf_evsel *evsel = intel_pt_evsel(pt, evlist);
  1776. struct perf_event_attr attr;
  1777. u64 id;
  1778. int err;
  1779. if (!evsel) {
  1780. pr_debug("There are no selected events with Intel Processor Trace data\n");
  1781. return 0;
  1782. }
  1783. memset(&attr, 0, sizeof(struct perf_event_attr));
  1784. attr.size = sizeof(struct perf_event_attr);
  1785. attr.type = PERF_TYPE_HARDWARE;
  1786. attr.sample_type = evsel->attr.sample_type & PERF_SAMPLE_MASK;
  1787. attr.sample_type |= PERF_SAMPLE_IP | PERF_SAMPLE_TID |
  1788. PERF_SAMPLE_PERIOD;
  1789. if (pt->timeless_decoding)
  1790. attr.sample_type &= ~(u64)PERF_SAMPLE_TIME;
  1791. else
  1792. attr.sample_type |= PERF_SAMPLE_TIME;
  1793. if (!pt->per_cpu_mmaps)
  1794. attr.sample_type &= ~(u64)PERF_SAMPLE_CPU;
  1795. attr.exclude_user = evsel->attr.exclude_user;
  1796. attr.exclude_kernel = evsel->attr.exclude_kernel;
  1797. attr.exclude_hv = evsel->attr.exclude_hv;
  1798. attr.exclude_host = evsel->attr.exclude_host;
  1799. attr.exclude_guest = evsel->attr.exclude_guest;
  1800. attr.sample_id_all = evsel->attr.sample_id_all;
  1801. attr.read_format = evsel->attr.read_format;
  1802. id = evsel->id[0] + 1000000000;
  1803. if (!id)
  1804. id = 1;
  1805. if (pt->synth_opts.branches) {
  1806. attr.config = PERF_COUNT_HW_BRANCH_INSTRUCTIONS;
  1807. attr.sample_period = 1;
  1808. attr.sample_type |= PERF_SAMPLE_ADDR;
  1809. err = intel_pt_synth_event(session, "branches", &attr, id);
  1810. if (err)
  1811. return err;
  1812. pt->sample_branches = true;
  1813. pt->branches_sample_type = attr.sample_type;
  1814. pt->branches_id = id;
  1815. id += 1;
  1816. attr.sample_type &= ~(u64)PERF_SAMPLE_ADDR;
  1817. }
  1818. if (pt->synth_opts.callchain)
  1819. attr.sample_type |= PERF_SAMPLE_CALLCHAIN;
  1820. if (pt->synth_opts.last_branch)
  1821. attr.sample_type |= PERF_SAMPLE_BRANCH_STACK;
  1822. if (pt->synth_opts.instructions) {
  1823. attr.config = PERF_COUNT_HW_INSTRUCTIONS;
  1824. if (pt->synth_opts.period_type == PERF_ITRACE_PERIOD_NANOSECS)
  1825. attr.sample_period =
  1826. intel_pt_ns_to_ticks(pt, pt->synth_opts.period);
  1827. else
  1828. attr.sample_period = pt->synth_opts.period;
  1829. err = intel_pt_synth_event(session, "instructions", &attr, id);
  1830. if (err)
  1831. return err;
  1832. pt->sample_instructions = true;
  1833. pt->instructions_sample_type = attr.sample_type;
  1834. pt->instructions_id = id;
  1835. id += 1;
  1836. }
  1837. attr.sample_type &= ~(u64)PERF_SAMPLE_PERIOD;
  1838. attr.sample_period = 1;
  1839. if (pt->synth_opts.transactions) {
  1840. attr.config = PERF_COUNT_HW_INSTRUCTIONS;
  1841. err = intel_pt_synth_event(session, "transactions", &attr, id);
  1842. if (err)
  1843. return err;
  1844. pt->sample_transactions = true;
  1845. pt->transactions_sample_type = attr.sample_type;
  1846. pt->transactions_id = id;
  1847. intel_pt_set_event_name(evlist, id, "transactions");
  1848. id += 1;
  1849. }
  1850. attr.type = PERF_TYPE_SYNTH;
  1851. attr.sample_type |= PERF_SAMPLE_RAW;
  1852. if (pt->synth_opts.ptwrites) {
  1853. attr.config = PERF_SYNTH_INTEL_PTWRITE;
  1854. err = intel_pt_synth_event(session, "ptwrite", &attr, id);
  1855. if (err)
  1856. return err;
  1857. pt->sample_ptwrites = true;
  1858. pt->ptwrites_sample_type = attr.sample_type;
  1859. pt->ptwrites_id = id;
  1860. intel_pt_set_event_name(evlist, id, "ptwrite");
  1861. id += 1;
  1862. }
  1863. if (pt->synth_opts.pwr_events) {
  1864. pt->sample_pwr_events = true;
  1865. pt->pwr_events_sample_type = attr.sample_type;
  1866. attr.config = PERF_SYNTH_INTEL_CBR;
  1867. err = intel_pt_synth_event(session, "cbr", &attr, id);
  1868. if (err)
  1869. return err;
  1870. pt->cbr_id = id;
  1871. intel_pt_set_event_name(evlist, id, "cbr");
  1872. id += 1;
  1873. }
  1874. if (pt->synth_opts.pwr_events && (evsel->attr.config & 0x10)) {
  1875. attr.config = PERF_SYNTH_INTEL_MWAIT;
  1876. err = intel_pt_synth_event(session, "mwait", &attr, id);
  1877. if (err)
  1878. return err;
  1879. pt->mwait_id = id;
  1880. intel_pt_set_event_name(evlist, id, "mwait");
  1881. id += 1;
  1882. attr.config = PERF_SYNTH_INTEL_PWRE;
  1883. err = intel_pt_synth_event(session, "pwre", &attr, id);
  1884. if (err)
  1885. return err;
  1886. pt->pwre_id = id;
  1887. intel_pt_set_event_name(evlist, id, "pwre");
  1888. id += 1;
  1889. attr.config = PERF_SYNTH_INTEL_EXSTOP;
  1890. err = intel_pt_synth_event(session, "exstop", &attr, id);
  1891. if (err)
  1892. return err;
  1893. pt->exstop_id = id;
  1894. intel_pt_set_event_name(evlist, id, "exstop");
  1895. id += 1;
  1896. attr.config = PERF_SYNTH_INTEL_PWRX;
  1897. err = intel_pt_synth_event(session, "pwrx", &attr, id);
  1898. if (err)
  1899. return err;
  1900. pt->pwrx_id = id;
  1901. intel_pt_set_event_name(evlist, id, "pwrx");
  1902. id += 1;
  1903. }
  1904. return 0;
  1905. }
  1906. static struct perf_evsel *intel_pt_find_sched_switch(struct perf_evlist *evlist)
  1907. {
  1908. struct perf_evsel *evsel;
  1909. evlist__for_each_entry_reverse(evlist, evsel) {
  1910. const char *name = perf_evsel__name(evsel);
  1911. if (!strcmp(name, "sched:sched_switch"))
  1912. return evsel;
  1913. }
  1914. return NULL;
  1915. }
  1916. static bool intel_pt_find_switch(struct perf_evlist *evlist)
  1917. {
  1918. struct perf_evsel *evsel;
  1919. evlist__for_each_entry(evlist, evsel) {
  1920. if (evsel->attr.context_switch)
  1921. return true;
  1922. }
  1923. return false;
  1924. }
  1925. static int intel_pt_perf_config(const char *var, const char *value, void *data)
  1926. {
  1927. struct intel_pt *pt = data;
  1928. if (!strcmp(var, "intel-pt.mispred-all"))
  1929. pt->mispred_all = perf_config_bool(var, value);
  1930. return 0;
  1931. }
  1932. static const char * const intel_pt_info_fmts[] = {
  1933. [INTEL_PT_PMU_TYPE] = " PMU Type %"PRId64"\n",
  1934. [INTEL_PT_TIME_SHIFT] = " Time Shift %"PRIu64"\n",
  1935. [INTEL_PT_TIME_MULT] = " Time Muliplier %"PRIu64"\n",
  1936. [INTEL_PT_TIME_ZERO] = " Time Zero %"PRIu64"\n",
  1937. [INTEL_PT_CAP_USER_TIME_ZERO] = " Cap Time Zero %"PRId64"\n",
  1938. [INTEL_PT_TSC_BIT] = " TSC bit %#"PRIx64"\n",
  1939. [INTEL_PT_NORETCOMP_BIT] = " NoRETComp bit %#"PRIx64"\n",
  1940. [INTEL_PT_HAVE_SCHED_SWITCH] = " Have sched_switch %"PRId64"\n",
  1941. [INTEL_PT_SNAPSHOT_MODE] = " Snapshot mode %"PRId64"\n",
  1942. [INTEL_PT_PER_CPU_MMAPS] = " Per-cpu maps %"PRId64"\n",
  1943. [INTEL_PT_MTC_BIT] = " MTC bit %#"PRIx64"\n",
  1944. [INTEL_PT_TSC_CTC_N] = " TSC:CTC numerator %"PRIu64"\n",
  1945. [INTEL_PT_TSC_CTC_D] = " TSC:CTC denominator %"PRIu64"\n",
  1946. [INTEL_PT_CYC_BIT] = " CYC bit %#"PRIx64"\n",
  1947. [INTEL_PT_MAX_NONTURBO_RATIO] = " Max non-turbo ratio %"PRIu64"\n",
  1948. [INTEL_PT_FILTER_STR_LEN] = " Filter string len. %"PRIu64"\n",
  1949. };
  1950. static void intel_pt_print_info(u64 *arr, int start, int finish)
  1951. {
  1952. int i;
  1953. if (!dump_trace)
  1954. return;
  1955. for (i = start; i <= finish; i++)
  1956. fprintf(stdout, intel_pt_info_fmts[i], arr[i]);
  1957. }
  1958. static void intel_pt_print_info_str(const char *name, const char *str)
  1959. {
  1960. if (!dump_trace)
  1961. return;
  1962. fprintf(stdout, " %-20s%s\n", name, str ? str : "");
  1963. }
  1964. static bool intel_pt_has(struct auxtrace_info_event *auxtrace_info, int pos)
  1965. {
  1966. return auxtrace_info->header.size >=
  1967. sizeof(struct auxtrace_info_event) + (sizeof(u64) * (pos + 1));
  1968. }
  1969. int intel_pt_process_auxtrace_info(union perf_event *event,
  1970. struct perf_session *session)
  1971. {
  1972. struct auxtrace_info_event *auxtrace_info = &event->auxtrace_info;
  1973. size_t min_sz = sizeof(u64) * INTEL_PT_PER_CPU_MMAPS;
  1974. struct intel_pt *pt;
  1975. void *info_end;
  1976. u64 *info;
  1977. int err;
  1978. if (auxtrace_info->header.size < sizeof(struct auxtrace_info_event) +
  1979. min_sz)
  1980. return -EINVAL;
  1981. pt = zalloc(sizeof(struct intel_pt));
  1982. if (!pt)
  1983. return -ENOMEM;
  1984. addr_filters__init(&pt->filts);
  1985. err = perf_config(intel_pt_perf_config, pt);
  1986. if (err)
  1987. goto err_free;
  1988. err = auxtrace_queues__init(&pt->queues);
  1989. if (err)
  1990. goto err_free;
  1991. intel_pt_log_set_name(INTEL_PT_PMU_NAME);
  1992. pt->session = session;
  1993. pt->machine = &session->machines.host; /* No kvm support */
  1994. pt->auxtrace_type = auxtrace_info->type;
  1995. pt->pmu_type = auxtrace_info->priv[INTEL_PT_PMU_TYPE];
  1996. pt->tc.time_shift = auxtrace_info->priv[INTEL_PT_TIME_SHIFT];
  1997. pt->tc.time_mult = auxtrace_info->priv[INTEL_PT_TIME_MULT];
  1998. pt->tc.time_zero = auxtrace_info->priv[INTEL_PT_TIME_ZERO];
  1999. pt->cap_user_time_zero = auxtrace_info->priv[INTEL_PT_CAP_USER_TIME_ZERO];
  2000. pt->tsc_bit = auxtrace_info->priv[INTEL_PT_TSC_BIT];
  2001. pt->noretcomp_bit = auxtrace_info->priv[INTEL_PT_NORETCOMP_BIT];
  2002. pt->have_sched_switch = auxtrace_info->priv[INTEL_PT_HAVE_SCHED_SWITCH];
  2003. pt->snapshot_mode = auxtrace_info->priv[INTEL_PT_SNAPSHOT_MODE];
  2004. pt->per_cpu_mmaps = auxtrace_info->priv[INTEL_PT_PER_CPU_MMAPS];
  2005. intel_pt_print_info(&auxtrace_info->priv[0], INTEL_PT_PMU_TYPE,
  2006. INTEL_PT_PER_CPU_MMAPS);
  2007. if (intel_pt_has(auxtrace_info, INTEL_PT_CYC_BIT)) {
  2008. pt->mtc_bit = auxtrace_info->priv[INTEL_PT_MTC_BIT];
  2009. pt->mtc_freq_bits = auxtrace_info->priv[INTEL_PT_MTC_FREQ_BITS];
  2010. pt->tsc_ctc_ratio_n = auxtrace_info->priv[INTEL_PT_TSC_CTC_N];
  2011. pt->tsc_ctc_ratio_d = auxtrace_info->priv[INTEL_PT_TSC_CTC_D];
  2012. pt->cyc_bit = auxtrace_info->priv[INTEL_PT_CYC_BIT];
  2013. intel_pt_print_info(&auxtrace_info->priv[0], INTEL_PT_MTC_BIT,
  2014. INTEL_PT_CYC_BIT);
  2015. }
  2016. if (intel_pt_has(auxtrace_info, INTEL_PT_MAX_NONTURBO_RATIO)) {
  2017. pt->max_non_turbo_ratio =
  2018. auxtrace_info->priv[INTEL_PT_MAX_NONTURBO_RATIO];
  2019. intel_pt_print_info(&auxtrace_info->priv[0],
  2020. INTEL_PT_MAX_NONTURBO_RATIO,
  2021. INTEL_PT_MAX_NONTURBO_RATIO);
  2022. }
  2023. info = &auxtrace_info->priv[INTEL_PT_FILTER_STR_LEN] + 1;
  2024. info_end = (void *)info + auxtrace_info->header.size;
  2025. if (intel_pt_has(auxtrace_info, INTEL_PT_FILTER_STR_LEN)) {
  2026. size_t len;
  2027. len = auxtrace_info->priv[INTEL_PT_FILTER_STR_LEN];
  2028. intel_pt_print_info(&auxtrace_info->priv[0],
  2029. INTEL_PT_FILTER_STR_LEN,
  2030. INTEL_PT_FILTER_STR_LEN);
  2031. if (len) {
  2032. const char *filter = (const char *)info;
  2033. len = roundup(len + 1, 8);
  2034. info += len >> 3;
  2035. if ((void *)info > info_end) {
  2036. pr_err("%s: bad filter string length\n", __func__);
  2037. err = -EINVAL;
  2038. goto err_free_queues;
  2039. }
  2040. pt->filter = memdup(filter, len);
  2041. if (!pt->filter) {
  2042. err = -ENOMEM;
  2043. goto err_free_queues;
  2044. }
  2045. if (session->header.needs_swap)
  2046. mem_bswap_64(pt->filter, len);
  2047. if (pt->filter[len - 1]) {
  2048. pr_err("%s: filter string not null terminated\n", __func__);
  2049. err = -EINVAL;
  2050. goto err_free_queues;
  2051. }
  2052. err = addr_filters__parse_bare_filter(&pt->filts,
  2053. filter);
  2054. if (err)
  2055. goto err_free_queues;
  2056. }
  2057. intel_pt_print_info_str("Filter string", pt->filter);
  2058. }
  2059. pt->timeless_decoding = intel_pt_timeless_decoding(pt);
  2060. pt->have_tsc = intel_pt_have_tsc(pt);
  2061. pt->sampling_mode = false;
  2062. pt->est_tsc = !pt->timeless_decoding;
  2063. pt->unknown_thread = thread__new(999999999, 999999999);
  2064. if (!pt->unknown_thread) {
  2065. err = -ENOMEM;
  2066. goto err_free_queues;
  2067. }
  2068. /*
  2069. * Since this thread will not be kept in any rbtree not in a
  2070. * list, initialize its list node so that at thread__put() the
  2071. * current thread lifetime assuption is kept and we don't segfault
  2072. * at list_del_init().
  2073. */
  2074. INIT_LIST_HEAD(&pt->unknown_thread->node);
  2075. err = thread__set_comm(pt->unknown_thread, "unknown", 0);
  2076. if (err)
  2077. goto err_delete_thread;
  2078. if (thread__init_map_groups(pt->unknown_thread, pt->machine)) {
  2079. err = -ENOMEM;
  2080. goto err_delete_thread;
  2081. }
  2082. pt->auxtrace.process_event = intel_pt_process_event;
  2083. pt->auxtrace.process_auxtrace_event = intel_pt_process_auxtrace_event;
  2084. pt->auxtrace.flush_events = intel_pt_flush;
  2085. pt->auxtrace.free_events = intel_pt_free_events;
  2086. pt->auxtrace.free = intel_pt_free;
  2087. session->auxtrace = &pt->auxtrace;
  2088. if (dump_trace)
  2089. return 0;
  2090. if (pt->have_sched_switch == 1) {
  2091. pt->switch_evsel = intel_pt_find_sched_switch(session->evlist);
  2092. if (!pt->switch_evsel) {
  2093. pr_err("%s: missing sched_switch event\n", __func__);
  2094. err = -EINVAL;
  2095. goto err_delete_thread;
  2096. }
  2097. } else if (pt->have_sched_switch == 2 &&
  2098. !intel_pt_find_switch(session->evlist)) {
  2099. pr_err("%s: missing context_switch attribute flag\n", __func__);
  2100. err = -EINVAL;
  2101. goto err_delete_thread;
  2102. }
  2103. if (session->itrace_synth_opts && session->itrace_synth_opts->set) {
  2104. pt->synth_opts = *session->itrace_synth_opts;
  2105. } else {
  2106. itrace_synth_opts__set_default(&pt->synth_opts);
  2107. if (use_browser != -1) {
  2108. pt->synth_opts.branches = false;
  2109. pt->synth_opts.callchain = true;
  2110. }
  2111. if (session->itrace_synth_opts)
  2112. pt->synth_opts.thread_stack =
  2113. session->itrace_synth_opts->thread_stack;
  2114. }
  2115. if (pt->synth_opts.log)
  2116. intel_pt_log_enable();
  2117. /* Maximum non-turbo ratio is TSC freq / 100 MHz */
  2118. if (pt->tc.time_mult) {
  2119. u64 tsc_freq = intel_pt_ns_to_ticks(pt, 1000000000);
  2120. if (!pt->max_non_turbo_ratio)
  2121. pt->max_non_turbo_ratio =
  2122. (tsc_freq + 50000000) / 100000000;
  2123. intel_pt_log("TSC frequency %"PRIu64"\n", tsc_freq);
  2124. intel_pt_log("Maximum non-turbo ratio %u\n",
  2125. pt->max_non_turbo_ratio);
  2126. pt->cbr2khz = tsc_freq / pt->max_non_turbo_ratio / 1000;
  2127. }
  2128. if (pt->synth_opts.calls)
  2129. pt->branches_filter |= PERF_IP_FLAG_CALL | PERF_IP_FLAG_ASYNC |
  2130. PERF_IP_FLAG_TRACE_END;
  2131. if (pt->synth_opts.returns)
  2132. pt->branches_filter |= PERF_IP_FLAG_RETURN |
  2133. PERF_IP_FLAG_TRACE_BEGIN;
  2134. if (pt->synth_opts.callchain && !symbol_conf.use_callchain) {
  2135. symbol_conf.use_callchain = true;
  2136. if (callchain_register_param(&callchain_param) < 0) {
  2137. symbol_conf.use_callchain = false;
  2138. pt->synth_opts.callchain = false;
  2139. }
  2140. }
  2141. err = intel_pt_synth_events(pt, session);
  2142. if (err)
  2143. goto err_delete_thread;
  2144. err = auxtrace_queues__process_index(&pt->queues, session);
  2145. if (err)
  2146. goto err_delete_thread;
  2147. if (pt->queues.populated)
  2148. pt->data_queued = true;
  2149. if (pt->timeless_decoding)
  2150. pr_debug2("Intel PT decoding without timestamps\n");
  2151. return 0;
  2152. err_delete_thread:
  2153. thread__zput(pt->unknown_thread);
  2154. err_free_queues:
  2155. intel_pt_log_disable();
  2156. auxtrace_queues__free(&pt->queues);
  2157. session->auxtrace = NULL;
  2158. err_free:
  2159. addr_filters__exit(&pt->filts);
  2160. zfree(&pt->filter);
  2161. free(pt);
  2162. return err;
  2163. }