smc_wr.c 18 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Shared Memory Communications over RDMA (SMC-R) and RoCE
  4. *
  5. * Work Requests exploiting Infiniband API
  6. *
  7. * Work requests (WR) of type ib_post_send or ib_post_recv respectively
  8. * are submitted to either RC SQ or RC RQ respectively
  9. * (reliably connected send/receive queue)
  10. * and become work queue entries (WQEs).
  11. * While an SQ WR/WQE is pending, we track it until transmission completion.
  12. * Through a send or receive completion queue (CQ) respectively,
  13. * we get completion queue entries (CQEs) [aka work completions (WCs)].
  14. * Since the CQ callback is called from IRQ context, we split work by using
  15. * bottom halves implemented by tasklets.
  16. *
  17. * SMC uses this to exchange LLC (link layer control)
  18. * and CDC (connection data control) messages.
  19. *
  20. * Copyright IBM Corp. 2016
  21. *
  22. * Author(s): Steffen Maier <maier@linux.vnet.ibm.com>
  23. */
  24. #include <linux/atomic.h>
  25. #include <linux/hashtable.h>
  26. #include <linux/wait.h>
  27. #include <rdma/ib_verbs.h>
  28. #include <asm/div64.h>
  29. #include "smc.h"
  30. #include "smc_wr.h"
  31. #define SMC_WR_MAX_POLL_CQE 10 /* max. # of compl. queue elements in 1 poll */
  32. #define SMC_WR_RX_HASH_BITS 4
  33. static DEFINE_HASHTABLE(smc_wr_rx_hash, SMC_WR_RX_HASH_BITS);
  34. static DEFINE_SPINLOCK(smc_wr_rx_hash_lock);
  35. struct smc_wr_tx_pend { /* control data for a pending send request */
  36. u64 wr_id; /* work request id sent */
  37. smc_wr_tx_handler handler;
  38. enum ib_wc_status wc_status; /* CQE status */
  39. struct smc_link *link;
  40. u32 idx;
  41. struct smc_wr_tx_pend_priv priv;
  42. };
  43. /******************************** send queue *********************************/
  44. /*------------------------------- completion --------------------------------*/
  45. static inline int smc_wr_tx_find_pending_index(struct smc_link *link, u64 wr_id)
  46. {
  47. u32 i;
  48. for (i = 0; i < link->wr_tx_cnt; i++) {
  49. if (link->wr_tx_pends[i].wr_id == wr_id)
  50. return i;
  51. }
  52. return link->wr_tx_cnt;
  53. }
  54. static inline void smc_wr_tx_process_cqe(struct ib_wc *wc)
  55. {
  56. struct smc_wr_tx_pend pnd_snd;
  57. struct smc_link *link;
  58. u32 pnd_snd_idx;
  59. int i;
  60. link = wc->qp->qp_context;
  61. if (wc->opcode == IB_WC_REG_MR) {
  62. if (wc->status)
  63. link->wr_reg_state = FAILED;
  64. else
  65. link->wr_reg_state = CONFIRMED;
  66. wake_up(&link->wr_reg_wait);
  67. return;
  68. }
  69. pnd_snd_idx = smc_wr_tx_find_pending_index(link, wc->wr_id);
  70. if (pnd_snd_idx == link->wr_tx_cnt)
  71. return;
  72. link->wr_tx_pends[pnd_snd_idx].wc_status = wc->status;
  73. memcpy(&pnd_snd, &link->wr_tx_pends[pnd_snd_idx], sizeof(pnd_snd));
  74. /* clear the full struct smc_wr_tx_pend including .priv */
  75. memset(&link->wr_tx_pends[pnd_snd_idx], 0,
  76. sizeof(link->wr_tx_pends[pnd_snd_idx]));
  77. memset(&link->wr_tx_bufs[pnd_snd_idx], 0,
  78. sizeof(link->wr_tx_bufs[pnd_snd_idx]));
  79. if (!test_and_clear_bit(pnd_snd_idx, link->wr_tx_mask))
  80. return;
  81. if (wc->status) {
  82. struct smc_link_group *lgr;
  83. for_each_set_bit(i, link->wr_tx_mask, link->wr_tx_cnt) {
  84. /* clear full struct smc_wr_tx_pend including .priv */
  85. memset(&link->wr_tx_pends[i], 0,
  86. sizeof(link->wr_tx_pends[i]));
  87. memset(&link->wr_tx_bufs[i], 0,
  88. sizeof(link->wr_tx_bufs[i]));
  89. clear_bit(i, link->wr_tx_mask);
  90. }
  91. /* terminate connections of this link group abnormally */
  92. lgr = container_of(link, struct smc_link_group,
  93. lnk[SMC_SINGLE_LINK]);
  94. smc_lgr_terminate(lgr);
  95. }
  96. if (pnd_snd.handler)
  97. pnd_snd.handler(&pnd_snd.priv, link, wc->status);
  98. wake_up(&link->wr_tx_wait);
  99. }
  100. static void smc_wr_tx_tasklet_fn(unsigned long data)
  101. {
  102. struct smc_ib_device *dev = (struct smc_ib_device *)data;
  103. struct ib_wc wc[SMC_WR_MAX_POLL_CQE];
  104. int i = 0, rc;
  105. int polled = 0;
  106. again:
  107. polled++;
  108. do {
  109. rc = ib_poll_cq(dev->roce_cq_send, SMC_WR_MAX_POLL_CQE, wc);
  110. if (polled == 1) {
  111. ib_req_notify_cq(dev->roce_cq_send,
  112. IB_CQ_NEXT_COMP |
  113. IB_CQ_REPORT_MISSED_EVENTS);
  114. }
  115. if (!rc)
  116. break;
  117. for (i = 0; i < rc; i++)
  118. smc_wr_tx_process_cqe(&wc[i]);
  119. } while (rc > 0);
  120. if (polled == 1)
  121. goto again;
  122. }
  123. void smc_wr_tx_cq_handler(struct ib_cq *ib_cq, void *cq_context)
  124. {
  125. struct smc_ib_device *dev = (struct smc_ib_device *)cq_context;
  126. tasklet_schedule(&dev->send_tasklet);
  127. }
  128. /*---------------------------- request submission ---------------------------*/
  129. static inline int smc_wr_tx_get_free_slot_index(struct smc_link *link, u32 *idx)
  130. {
  131. *idx = link->wr_tx_cnt;
  132. for_each_clear_bit(*idx, link->wr_tx_mask, link->wr_tx_cnt) {
  133. if (!test_and_set_bit(*idx, link->wr_tx_mask))
  134. return 0;
  135. }
  136. *idx = link->wr_tx_cnt;
  137. return -EBUSY;
  138. }
  139. /**
  140. * smc_wr_tx_get_free_slot() - returns buffer for message assembly,
  141. * and sets info for pending transmit tracking
  142. * @link: Pointer to smc_link used to later send the message.
  143. * @handler: Send completion handler function pointer.
  144. * @wr_buf: Out value returns pointer to message buffer.
  145. * @wr_pend_priv: Out value returns pointer serving as handler context.
  146. *
  147. * Return: 0 on success, or -errno on error.
  148. */
  149. int smc_wr_tx_get_free_slot(struct smc_link *link,
  150. smc_wr_tx_handler handler,
  151. struct smc_wr_buf **wr_buf,
  152. struct smc_wr_tx_pend_priv **wr_pend_priv)
  153. {
  154. struct smc_wr_tx_pend *wr_pend;
  155. struct ib_send_wr *wr_ib;
  156. u64 wr_id;
  157. u32 idx;
  158. int rc;
  159. *wr_buf = NULL;
  160. *wr_pend_priv = NULL;
  161. if (in_softirq()) {
  162. rc = smc_wr_tx_get_free_slot_index(link, &idx);
  163. if (rc)
  164. return rc;
  165. } else {
  166. rc = wait_event_interruptible_timeout(
  167. link->wr_tx_wait,
  168. (smc_wr_tx_get_free_slot_index(link, &idx) != -EBUSY),
  169. SMC_WR_TX_WAIT_FREE_SLOT_TIME);
  170. if (!rc) {
  171. /* timeout - terminate connections */
  172. struct smc_link_group *lgr;
  173. lgr = container_of(link, struct smc_link_group,
  174. lnk[SMC_SINGLE_LINK]);
  175. smc_lgr_terminate(lgr);
  176. return -EPIPE;
  177. }
  178. if (rc == -ERESTARTSYS)
  179. return -EINTR;
  180. if (idx == link->wr_tx_cnt)
  181. return -EPIPE;
  182. }
  183. wr_id = smc_wr_tx_get_next_wr_id(link);
  184. wr_pend = &link->wr_tx_pends[idx];
  185. wr_pend->wr_id = wr_id;
  186. wr_pend->handler = handler;
  187. wr_pend->link = link;
  188. wr_pend->idx = idx;
  189. wr_ib = &link->wr_tx_ibs[idx];
  190. wr_ib->wr_id = wr_id;
  191. *wr_buf = &link->wr_tx_bufs[idx];
  192. *wr_pend_priv = &wr_pend->priv;
  193. return 0;
  194. }
  195. int smc_wr_tx_put_slot(struct smc_link *link,
  196. struct smc_wr_tx_pend_priv *wr_pend_priv)
  197. {
  198. struct smc_wr_tx_pend *pend;
  199. pend = container_of(wr_pend_priv, struct smc_wr_tx_pend, priv);
  200. if (pend->idx < link->wr_tx_cnt) {
  201. /* clear the full struct smc_wr_tx_pend including .priv */
  202. memset(&link->wr_tx_pends[pend->idx], 0,
  203. sizeof(link->wr_tx_pends[pend->idx]));
  204. memset(&link->wr_tx_bufs[pend->idx], 0,
  205. sizeof(link->wr_tx_bufs[pend->idx]));
  206. test_and_clear_bit(pend->idx, link->wr_tx_mask);
  207. return 1;
  208. }
  209. return 0;
  210. }
  211. /* Send prepared WR slot via ib_post_send.
  212. * @priv: pointer to smc_wr_tx_pend_priv identifying prepared message buffer
  213. */
  214. int smc_wr_tx_send(struct smc_link *link, struct smc_wr_tx_pend_priv *priv)
  215. {
  216. struct ib_send_wr *failed_wr = NULL;
  217. struct smc_wr_tx_pend *pend;
  218. int rc;
  219. ib_req_notify_cq(link->smcibdev->roce_cq_send,
  220. IB_CQ_NEXT_COMP | IB_CQ_REPORT_MISSED_EVENTS);
  221. pend = container_of(priv, struct smc_wr_tx_pend, priv);
  222. rc = ib_post_send(link->roce_qp, &link->wr_tx_ibs[pend->idx],
  223. &failed_wr);
  224. if (rc)
  225. smc_wr_tx_put_slot(link, priv);
  226. return rc;
  227. }
  228. /* Register a memory region and wait for result. */
  229. int smc_wr_reg_send(struct smc_link *link, struct ib_mr *mr)
  230. {
  231. struct ib_send_wr *failed_wr = NULL;
  232. int rc;
  233. ib_req_notify_cq(link->smcibdev->roce_cq_send,
  234. IB_CQ_NEXT_COMP | IB_CQ_REPORT_MISSED_EVENTS);
  235. link->wr_reg_state = POSTED;
  236. link->wr_reg.wr.wr_id = (u64)(uintptr_t)mr;
  237. link->wr_reg.mr = mr;
  238. link->wr_reg.key = mr->rkey;
  239. failed_wr = &link->wr_reg.wr;
  240. rc = ib_post_send(link->roce_qp, &link->wr_reg.wr, &failed_wr);
  241. WARN_ON(failed_wr != &link->wr_reg.wr);
  242. if (rc)
  243. return rc;
  244. rc = wait_event_interruptible_timeout(link->wr_reg_wait,
  245. (link->wr_reg_state != POSTED),
  246. SMC_WR_REG_MR_WAIT_TIME);
  247. if (!rc) {
  248. /* timeout - terminate connections */
  249. struct smc_link_group *lgr;
  250. lgr = container_of(link, struct smc_link_group,
  251. lnk[SMC_SINGLE_LINK]);
  252. smc_lgr_terminate(lgr);
  253. return -EPIPE;
  254. }
  255. if (rc == -ERESTARTSYS)
  256. return -EINTR;
  257. switch (link->wr_reg_state) {
  258. case CONFIRMED:
  259. rc = 0;
  260. break;
  261. case FAILED:
  262. rc = -EIO;
  263. break;
  264. case POSTED:
  265. rc = -EPIPE;
  266. break;
  267. }
  268. return rc;
  269. }
  270. void smc_wr_tx_dismiss_slots(struct smc_link *link, u8 wr_rx_hdr_type,
  271. smc_wr_tx_filter filter,
  272. smc_wr_tx_dismisser dismisser,
  273. unsigned long data)
  274. {
  275. struct smc_wr_tx_pend_priv *tx_pend;
  276. struct smc_wr_rx_hdr *wr_rx;
  277. int i;
  278. for_each_set_bit(i, link->wr_tx_mask, link->wr_tx_cnt) {
  279. wr_rx = (struct smc_wr_rx_hdr *)&link->wr_rx_bufs[i];
  280. if (wr_rx->type != wr_rx_hdr_type)
  281. continue;
  282. tx_pend = &link->wr_tx_pends[i].priv;
  283. if (filter(tx_pend, data))
  284. dismisser(tx_pend);
  285. }
  286. }
  287. bool smc_wr_tx_has_pending(struct smc_link *link, u8 wr_rx_hdr_type,
  288. smc_wr_tx_filter filter, unsigned long data)
  289. {
  290. struct smc_wr_tx_pend_priv *tx_pend;
  291. struct smc_wr_rx_hdr *wr_rx;
  292. int i;
  293. for_each_set_bit(i, link->wr_tx_mask, link->wr_tx_cnt) {
  294. wr_rx = (struct smc_wr_rx_hdr *)&link->wr_rx_bufs[i];
  295. if (wr_rx->type != wr_rx_hdr_type)
  296. continue;
  297. tx_pend = &link->wr_tx_pends[i].priv;
  298. if (filter(tx_pend, data))
  299. return true;
  300. }
  301. return false;
  302. }
  303. /****************************** receive queue ********************************/
  304. int smc_wr_rx_register_handler(struct smc_wr_rx_handler *handler)
  305. {
  306. struct smc_wr_rx_handler *h_iter;
  307. int rc = 0;
  308. spin_lock(&smc_wr_rx_hash_lock);
  309. hash_for_each_possible(smc_wr_rx_hash, h_iter, list, handler->type) {
  310. if (h_iter->type == handler->type) {
  311. rc = -EEXIST;
  312. goto out_unlock;
  313. }
  314. }
  315. hash_add(smc_wr_rx_hash, &handler->list, handler->type);
  316. out_unlock:
  317. spin_unlock(&smc_wr_rx_hash_lock);
  318. return rc;
  319. }
  320. /* Demultiplex a received work request based on the message type to its handler.
  321. * Relies on smc_wr_rx_hash having been completely filled before any IB WRs,
  322. * and not being modified any more afterwards so we don't need to lock it.
  323. */
  324. static inline void smc_wr_rx_demultiplex(struct ib_wc *wc)
  325. {
  326. struct smc_link *link = (struct smc_link *)wc->qp->qp_context;
  327. struct smc_wr_rx_handler *handler;
  328. struct smc_wr_rx_hdr *wr_rx;
  329. u64 temp_wr_id;
  330. u32 index;
  331. if (wc->byte_len < sizeof(*wr_rx))
  332. return; /* short message */
  333. temp_wr_id = wc->wr_id;
  334. index = do_div(temp_wr_id, link->wr_rx_cnt);
  335. wr_rx = (struct smc_wr_rx_hdr *)&link->wr_rx_bufs[index];
  336. hash_for_each_possible(smc_wr_rx_hash, handler, list, wr_rx->type) {
  337. if (handler->type == wr_rx->type)
  338. handler->handler(wc, wr_rx);
  339. }
  340. }
  341. static inline void smc_wr_rx_process_cqes(struct ib_wc wc[], int num)
  342. {
  343. struct smc_link *link;
  344. int i;
  345. for (i = 0; i < num; i++) {
  346. link = wc[i].qp->qp_context;
  347. if (wc[i].status == IB_WC_SUCCESS) {
  348. smc_wr_rx_demultiplex(&wc[i]);
  349. smc_wr_rx_post(link); /* refill WR RX */
  350. } else {
  351. struct smc_link_group *lgr;
  352. /* handle status errors */
  353. switch (wc[i].status) {
  354. case IB_WC_RETRY_EXC_ERR:
  355. case IB_WC_RNR_RETRY_EXC_ERR:
  356. case IB_WC_WR_FLUSH_ERR:
  357. /* terminate connections of this link group
  358. * abnormally
  359. */
  360. lgr = container_of(link, struct smc_link_group,
  361. lnk[SMC_SINGLE_LINK]);
  362. smc_lgr_terminate(lgr);
  363. break;
  364. default:
  365. smc_wr_rx_post(link); /* refill WR RX */
  366. break;
  367. }
  368. }
  369. }
  370. }
  371. static void smc_wr_rx_tasklet_fn(unsigned long data)
  372. {
  373. struct smc_ib_device *dev = (struct smc_ib_device *)data;
  374. struct ib_wc wc[SMC_WR_MAX_POLL_CQE];
  375. int polled = 0;
  376. int rc;
  377. again:
  378. polled++;
  379. do {
  380. memset(&wc, 0, sizeof(wc));
  381. rc = ib_poll_cq(dev->roce_cq_recv, SMC_WR_MAX_POLL_CQE, wc);
  382. if (polled == 1) {
  383. ib_req_notify_cq(dev->roce_cq_recv,
  384. IB_CQ_SOLICITED_MASK
  385. | IB_CQ_REPORT_MISSED_EVENTS);
  386. }
  387. if (!rc)
  388. break;
  389. smc_wr_rx_process_cqes(&wc[0], rc);
  390. } while (rc > 0);
  391. if (polled == 1)
  392. goto again;
  393. }
  394. void smc_wr_rx_cq_handler(struct ib_cq *ib_cq, void *cq_context)
  395. {
  396. struct smc_ib_device *dev = (struct smc_ib_device *)cq_context;
  397. tasklet_schedule(&dev->recv_tasklet);
  398. }
  399. int smc_wr_rx_post_init(struct smc_link *link)
  400. {
  401. u32 i;
  402. int rc = 0;
  403. for (i = 0; i < link->wr_rx_cnt; i++)
  404. rc = smc_wr_rx_post(link);
  405. return rc;
  406. }
  407. /***************************** init, exit, misc ******************************/
  408. void smc_wr_remember_qp_attr(struct smc_link *lnk)
  409. {
  410. struct ib_qp_attr *attr = &lnk->qp_attr;
  411. struct ib_qp_init_attr init_attr;
  412. memset(attr, 0, sizeof(*attr));
  413. memset(&init_attr, 0, sizeof(init_attr));
  414. ib_query_qp(lnk->roce_qp, attr,
  415. IB_QP_STATE |
  416. IB_QP_CUR_STATE |
  417. IB_QP_PKEY_INDEX |
  418. IB_QP_PORT |
  419. IB_QP_QKEY |
  420. IB_QP_AV |
  421. IB_QP_PATH_MTU |
  422. IB_QP_TIMEOUT |
  423. IB_QP_RETRY_CNT |
  424. IB_QP_RNR_RETRY |
  425. IB_QP_RQ_PSN |
  426. IB_QP_ALT_PATH |
  427. IB_QP_MIN_RNR_TIMER |
  428. IB_QP_SQ_PSN |
  429. IB_QP_PATH_MIG_STATE |
  430. IB_QP_CAP |
  431. IB_QP_DEST_QPN,
  432. &init_attr);
  433. lnk->wr_tx_cnt = min_t(size_t, SMC_WR_BUF_CNT,
  434. lnk->qp_attr.cap.max_send_wr);
  435. lnk->wr_rx_cnt = min_t(size_t, SMC_WR_BUF_CNT * 3,
  436. lnk->qp_attr.cap.max_recv_wr);
  437. }
  438. static void smc_wr_init_sge(struct smc_link *lnk)
  439. {
  440. u32 i;
  441. for (i = 0; i < lnk->wr_tx_cnt; i++) {
  442. lnk->wr_tx_sges[i].addr =
  443. lnk->wr_tx_dma_addr + i * SMC_WR_BUF_SIZE;
  444. lnk->wr_tx_sges[i].length = SMC_WR_TX_SIZE;
  445. lnk->wr_tx_sges[i].lkey = lnk->roce_pd->local_dma_lkey;
  446. lnk->wr_tx_ibs[i].next = NULL;
  447. lnk->wr_tx_ibs[i].sg_list = &lnk->wr_tx_sges[i];
  448. lnk->wr_tx_ibs[i].num_sge = 1;
  449. lnk->wr_tx_ibs[i].opcode = IB_WR_SEND;
  450. lnk->wr_tx_ibs[i].send_flags =
  451. IB_SEND_SIGNALED | IB_SEND_SOLICITED;
  452. }
  453. for (i = 0; i < lnk->wr_rx_cnt; i++) {
  454. lnk->wr_rx_sges[i].addr =
  455. lnk->wr_rx_dma_addr + i * SMC_WR_BUF_SIZE;
  456. lnk->wr_rx_sges[i].length = SMC_WR_BUF_SIZE;
  457. lnk->wr_rx_sges[i].lkey = lnk->roce_pd->local_dma_lkey;
  458. lnk->wr_rx_ibs[i].next = NULL;
  459. lnk->wr_rx_ibs[i].sg_list = &lnk->wr_rx_sges[i];
  460. lnk->wr_rx_ibs[i].num_sge = 1;
  461. }
  462. lnk->wr_reg.wr.next = NULL;
  463. lnk->wr_reg.wr.num_sge = 0;
  464. lnk->wr_reg.wr.send_flags = IB_SEND_SIGNALED;
  465. lnk->wr_reg.wr.opcode = IB_WR_REG_MR;
  466. lnk->wr_reg.access = IB_ACCESS_LOCAL_WRITE | IB_ACCESS_REMOTE_WRITE;
  467. }
  468. void smc_wr_free_link(struct smc_link *lnk)
  469. {
  470. struct ib_device *ibdev;
  471. memset(lnk->wr_tx_mask, 0,
  472. BITS_TO_LONGS(SMC_WR_BUF_CNT) * sizeof(*lnk->wr_tx_mask));
  473. if (!lnk->smcibdev)
  474. return;
  475. ibdev = lnk->smcibdev->ibdev;
  476. if (lnk->wr_rx_dma_addr) {
  477. ib_dma_unmap_single(ibdev, lnk->wr_rx_dma_addr,
  478. SMC_WR_BUF_SIZE * lnk->wr_rx_cnt,
  479. DMA_FROM_DEVICE);
  480. lnk->wr_rx_dma_addr = 0;
  481. }
  482. if (lnk->wr_tx_dma_addr) {
  483. ib_dma_unmap_single(ibdev, lnk->wr_tx_dma_addr,
  484. SMC_WR_BUF_SIZE * lnk->wr_tx_cnt,
  485. DMA_TO_DEVICE);
  486. lnk->wr_tx_dma_addr = 0;
  487. }
  488. }
  489. void smc_wr_free_link_mem(struct smc_link *lnk)
  490. {
  491. kfree(lnk->wr_tx_pends);
  492. lnk->wr_tx_pends = NULL;
  493. kfree(lnk->wr_tx_mask);
  494. lnk->wr_tx_mask = NULL;
  495. kfree(lnk->wr_tx_sges);
  496. lnk->wr_tx_sges = NULL;
  497. kfree(lnk->wr_rx_sges);
  498. lnk->wr_rx_sges = NULL;
  499. kfree(lnk->wr_rx_ibs);
  500. lnk->wr_rx_ibs = NULL;
  501. kfree(lnk->wr_tx_ibs);
  502. lnk->wr_tx_ibs = NULL;
  503. kfree(lnk->wr_tx_bufs);
  504. lnk->wr_tx_bufs = NULL;
  505. kfree(lnk->wr_rx_bufs);
  506. lnk->wr_rx_bufs = NULL;
  507. }
  508. int smc_wr_alloc_link_mem(struct smc_link *link)
  509. {
  510. /* allocate link related memory */
  511. link->wr_tx_bufs = kcalloc(SMC_WR_BUF_CNT, SMC_WR_BUF_SIZE, GFP_KERNEL);
  512. if (!link->wr_tx_bufs)
  513. goto no_mem;
  514. link->wr_rx_bufs = kcalloc(SMC_WR_BUF_CNT * 3, SMC_WR_BUF_SIZE,
  515. GFP_KERNEL);
  516. if (!link->wr_rx_bufs)
  517. goto no_mem_wr_tx_bufs;
  518. link->wr_tx_ibs = kcalloc(SMC_WR_BUF_CNT, sizeof(link->wr_tx_ibs[0]),
  519. GFP_KERNEL);
  520. if (!link->wr_tx_ibs)
  521. goto no_mem_wr_rx_bufs;
  522. link->wr_rx_ibs = kcalloc(SMC_WR_BUF_CNT * 3,
  523. sizeof(link->wr_rx_ibs[0]),
  524. GFP_KERNEL);
  525. if (!link->wr_rx_ibs)
  526. goto no_mem_wr_tx_ibs;
  527. link->wr_tx_sges = kcalloc(SMC_WR_BUF_CNT, sizeof(link->wr_tx_sges[0]),
  528. GFP_KERNEL);
  529. if (!link->wr_tx_sges)
  530. goto no_mem_wr_rx_ibs;
  531. link->wr_rx_sges = kcalloc(SMC_WR_BUF_CNT * 3,
  532. sizeof(link->wr_rx_sges[0]),
  533. GFP_KERNEL);
  534. if (!link->wr_rx_sges)
  535. goto no_mem_wr_tx_sges;
  536. link->wr_tx_mask = kzalloc(
  537. BITS_TO_LONGS(SMC_WR_BUF_CNT) * sizeof(*link->wr_tx_mask),
  538. GFP_KERNEL);
  539. if (!link->wr_tx_mask)
  540. goto no_mem_wr_rx_sges;
  541. link->wr_tx_pends = kcalloc(SMC_WR_BUF_CNT,
  542. sizeof(link->wr_tx_pends[0]),
  543. GFP_KERNEL);
  544. if (!link->wr_tx_pends)
  545. goto no_mem_wr_tx_mask;
  546. return 0;
  547. no_mem_wr_tx_mask:
  548. kfree(link->wr_tx_mask);
  549. no_mem_wr_rx_sges:
  550. kfree(link->wr_rx_sges);
  551. no_mem_wr_tx_sges:
  552. kfree(link->wr_tx_sges);
  553. no_mem_wr_rx_ibs:
  554. kfree(link->wr_rx_ibs);
  555. no_mem_wr_tx_ibs:
  556. kfree(link->wr_tx_ibs);
  557. no_mem_wr_rx_bufs:
  558. kfree(link->wr_rx_bufs);
  559. no_mem_wr_tx_bufs:
  560. kfree(link->wr_tx_bufs);
  561. no_mem:
  562. return -ENOMEM;
  563. }
  564. void smc_wr_remove_dev(struct smc_ib_device *smcibdev)
  565. {
  566. tasklet_kill(&smcibdev->recv_tasklet);
  567. tasklet_kill(&smcibdev->send_tasklet);
  568. }
  569. void smc_wr_add_dev(struct smc_ib_device *smcibdev)
  570. {
  571. tasklet_init(&smcibdev->recv_tasklet, smc_wr_rx_tasklet_fn,
  572. (unsigned long)smcibdev);
  573. tasklet_init(&smcibdev->send_tasklet, smc_wr_tx_tasklet_fn,
  574. (unsigned long)smcibdev);
  575. }
  576. int smc_wr_create_link(struct smc_link *lnk)
  577. {
  578. struct ib_device *ibdev = lnk->smcibdev->ibdev;
  579. int rc = 0;
  580. smc_wr_tx_set_wr_id(&lnk->wr_tx_id, 0);
  581. lnk->wr_rx_id = 0;
  582. lnk->wr_rx_dma_addr = ib_dma_map_single(
  583. ibdev, lnk->wr_rx_bufs, SMC_WR_BUF_SIZE * lnk->wr_rx_cnt,
  584. DMA_FROM_DEVICE);
  585. if (ib_dma_mapping_error(ibdev, lnk->wr_rx_dma_addr)) {
  586. lnk->wr_rx_dma_addr = 0;
  587. rc = -EIO;
  588. goto out;
  589. }
  590. lnk->wr_tx_dma_addr = ib_dma_map_single(
  591. ibdev, lnk->wr_tx_bufs, SMC_WR_BUF_SIZE * lnk->wr_tx_cnt,
  592. DMA_TO_DEVICE);
  593. if (ib_dma_mapping_error(ibdev, lnk->wr_tx_dma_addr)) {
  594. rc = -EIO;
  595. goto dma_unmap;
  596. }
  597. smc_wr_init_sge(lnk);
  598. memset(lnk->wr_tx_mask, 0,
  599. BITS_TO_LONGS(SMC_WR_BUF_CNT) * sizeof(*lnk->wr_tx_mask));
  600. init_waitqueue_head(&lnk->wr_tx_wait);
  601. init_waitqueue_head(&lnk->wr_reg_wait);
  602. return rc;
  603. dma_unmap:
  604. ib_dma_unmap_single(ibdev, lnk->wr_rx_dma_addr,
  605. SMC_WR_BUF_SIZE * lnk->wr_rx_cnt,
  606. DMA_FROM_DEVICE);
  607. lnk->wr_rx_dma_addr = 0;
  608. out:
  609. return rc;
  610. }