amdgpu_gart.c 10 KB

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  1. /*
  2. * Copyright 2008 Advanced Micro Devices, Inc.
  3. * Copyright 2008 Red Hat Inc.
  4. * Copyright 2009 Jerome Glisse.
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the "Software"),
  8. * to deal in the Software without restriction, including without limitation
  9. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10. * and/or sell copies of the Software, and to permit persons to whom the
  11. * Software is furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice shall be included in
  14. * all copies or substantial portions of the Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22. * OTHER DEALINGS IN THE SOFTWARE.
  23. *
  24. * Authors: Dave Airlie
  25. * Alex Deucher
  26. * Jerome Glisse
  27. */
  28. #include <drm/drmP.h>
  29. #include <drm/amdgpu_drm.h>
  30. #ifdef CONFIG_X86
  31. #include <asm/set_memory.h>
  32. #endif
  33. #include "amdgpu.h"
  34. /*
  35. * GART
  36. * The GART (Graphics Aperture Remapping Table) is an aperture
  37. * in the GPU's address space. System pages can be mapped into
  38. * the aperture and look like contiguous pages from the GPU's
  39. * perspective. A page table maps the pages in the aperture
  40. * to the actual backing pages in system memory.
  41. *
  42. * Radeon GPUs support both an internal GART, as described above,
  43. * and AGP. AGP works similarly, but the GART table is configured
  44. * and maintained by the northbridge rather than the driver.
  45. * Radeon hw has a separate AGP aperture that is programmed to
  46. * point to the AGP aperture provided by the northbridge and the
  47. * requests are passed through to the northbridge aperture.
  48. * Both AGP and internal GART can be used at the same time, however
  49. * that is not currently supported by the driver.
  50. *
  51. * This file handles the common internal GART management.
  52. */
  53. /*
  54. * Common GART table functions.
  55. */
  56. /**
  57. * amdgpu_dummy_page_init - init dummy page used by the driver
  58. *
  59. * @adev: amdgpu_device pointer
  60. *
  61. * Allocate the dummy page used by the driver (all asics).
  62. * This dummy page is used by the driver as a filler for gart entries
  63. * when pages are taken out of the GART
  64. * Returns 0 on sucess, -ENOMEM on failure.
  65. */
  66. static int amdgpu_gart_dummy_page_init(struct amdgpu_device *adev)
  67. {
  68. struct page *dummy_page = adev->mman.bdev.glob->dummy_read_page;
  69. if (adev->dummy_page_addr)
  70. return 0;
  71. adev->dummy_page_addr = pci_map_page(adev->pdev, dummy_page, 0,
  72. PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
  73. if (pci_dma_mapping_error(adev->pdev, adev->dummy_page_addr)) {
  74. dev_err(&adev->pdev->dev, "Failed to DMA MAP the dummy page\n");
  75. adev->dummy_page_addr = 0;
  76. return -ENOMEM;
  77. }
  78. return 0;
  79. }
  80. /**
  81. * amdgpu_dummy_page_fini - free dummy page used by the driver
  82. *
  83. * @adev: amdgpu_device pointer
  84. *
  85. * Frees the dummy page used by the driver (all asics).
  86. */
  87. static void amdgpu_gart_dummy_page_fini(struct amdgpu_device *adev)
  88. {
  89. if (!adev->dummy_page_addr)
  90. return;
  91. pci_unmap_page(adev->pdev, adev->dummy_page_addr,
  92. PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
  93. adev->dummy_page_addr = 0;
  94. }
  95. /**
  96. * amdgpu_gart_table_vram_alloc - allocate vram for gart page table
  97. *
  98. * @adev: amdgpu_device pointer
  99. *
  100. * Allocate video memory for GART page table
  101. * (pcie r4xx, r5xx+). These asics require the
  102. * gart table to be in video memory.
  103. * Returns 0 for success, error for failure.
  104. */
  105. int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev)
  106. {
  107. int r;
  108. if (adev->gart.robj == NULL) {
  109. r = amdgpu_bo_create(adev, adev->gart.table_size, PAGE_SIZE,
  110. AMDGPU_GEM_DOMAIN_VRAM,
  111. AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
  112. AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
  113. ttm_bo_type_kernel, NULL,
  114. &adev->gart.robj);
  115. if (r) {
  116. return r;
  117. }
  118. }
  119. return 0;
  120. }
  121. /**
  122. * amdgpu_gart_table_vram_pin - pin gart page table in vram
  123. *
  124. * @adev: amdgpu_device pointer
  125. *
  126. * Pin the GART page table in vram so it will not be moved
  127. * by the memory manager (pcie r4xx, r5xx+). These asics require the
  128. * gart table to be in video memory.
  129. * Returns 0 for success, error for failure.
  130. */
  131. int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev)
  132. {
  133. uint64_t gpu_addr;
  134. int r;
  135. r = amdgpu_bo_reserve(adev->gart.robj, false);
  136. if (unlikely(r != 0))
  137. return r;
  138. r = amdgpu_bo_pin(adev->gart.robj,
  139. AMDGPU_GEM_DOMAIN_VRAM, &gpu_addr);
  140. if (r) {
  141. amdgpu_bo_unreserve(adev->gart.robj);
  142. return r;
  143. }
  144. r = amdgpu_bo_kmap(adev->gart.robj, &adev->gart.ptr);
  145. if (r)
  146. amdgpu_bo_unpin(adev->gart.robj);
  147. amdgpu_bo_unreserve(adev->gart.robj);
  148. adev->gart.table_addr = gpu_addr;
  149. return r;
  150. }
  151. /**
  152. * amdgpu_gart_table_vram_unpin - unpin gart page table in vram
  153. *
  154. * @adev: amdgpu_device pointer
  155. *
  156. * Unpin the GART page table in vram (pcie r4xx, r5xx+).
  157. * These asics require the gart table to be in video memory.
  158. */
  159. void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev)
  160. {
  161. int r;
  162. if (adev->gart.robj == NULL) {
  163. return;
  164. }
  165. r = amdgpu_bo_reserve(adev->gart.robj, true);
  166. if (likely(r == 0)) {
  167. amdgpu_bo_kunmap(adev->gart.robj);
  168. amdgpu_bo_unpin(adev->gart.robj);
  169. amdgpu_bo_unreserve(adev->gart.robj);
  170. adev->gart.ptr = NULL;
  171. }
  172. }
  173. /**
  174. * amdgpu_gart_table_vram_free - free gart page table vram
  175. *
  176. * @adev: amdgpu_device pointer
  177. *
  178. * Free the video memory used for the GART page table
  179. * (pcie r4xx, r5xx+). These asics require the gart table to
  180. * be in video memory.
  181. */
  182. void amdgpu_gart_table_vram_free(struct amdgpu_device *adev)
  183. {
  184. if (adev->gart.robj == NULL) {
  185. return;
  186. }
  187. amdgpu_bo_unref(&adev->gart.robj);
  188. }
  189. /*
  190. * Common gart functions.
  191. */
  192. /**
  193. * amdgpu_gart_unbind - unbind pages from the gart page table
  194. *
  195. * @adev: amdgpu_device pointer
  196. * @offset: offset into the GPU's gart aperture
  197. * @pages: number of pages to unbind
  198. *
  199. * Unbinds the requested pages from the gart page table and
  200. * replaces them with the dummy page (all asics).
  201. * Returns 0 for success, -EINVAL for failure.
  202. */
  203. int amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset,
  204. int pages)
  205. {
  206. unsigned t;
  207. unsigned p;
  208. int i, j;
  209. u64 page_base;
  210. /* Starting from VEGA10, system bit must be 0 to mean invalid. */
  211. uint64_t flags = 0;
  212. if (!adev->gart.ready) {
  213. WARN(1, "trying to unbind memory from uninitialized GART !\n");
  214. return -EINVAL;
  215. }
  216. t = offset / AMDGPU_GPU_PAGE_SIZE;
  217. p = t / (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE);
  218. for (i = 0; i < pages; i++, p++) {
  219. #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
  220. adev->gart.pages[p] = NULL;
  221. #endif
  222. page_base = adev->dummy_page_addr;
  223. if (!adev->gart.ptr)
  224. continue;
  225. for (j = 0; j < (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE); j++, t++) {
  226. amdgpu_gmc_set_pte_pde(adev, adev->gart.ptr,
  227. t, page_base, flags);
  228. page_base += AMDGPU_GPU_PAGE_SIZE;
  229. }
  230. }
  231. mb();
  232. amdgpu_asic_flush_hdp(adev, NULL);
  233. amdgpu_gmc_flush_gpu_tlb(adev, 0);
  234. return 0;
  235. }
  236. /**
  237. * amdgpu_gart_map - map dma_addresses into GART entries
  238. *
  239. * @adev: amdgpu_device pointer
  240. * @offset: offset into the GPU's gart aperture
  241. * @pages: number of pages to bind
  242. * @dma_addr: DMA addresses of pages
  243. *
  244. * Map the dma_addresses into GART entries (all asics).
  245. * Returns 0 for success, -EINVAL for failure.
  246. */
  247. int amdgpu_gart_map(struct amdgpu_device *adev, uint64_t offset,
  248. int pages, dma_addr_t *dma_addr, uint64_t flags,
  249. void *dst)
  250. {
  251. uint64_t page_base;
  252. unsigned i, j, t;
  253. if (!adev->gart.ready) {
  254. WARN(1, "trying to bind memory to uninitialized GART !\n");
  255. return -EINVAL;
  256. }
  257. t = offset / AMDGPU_GPU_PAGE_SIZE;
  258. for (i = 0; i < pages; i++) {
  259. page_base = dma_addr[i];
  260. for (j = 0; j < (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE); j++, t++) {
  261. amdgpu_gmc_set_pte_pde(adev, dst, t, page_base, flags);
  262. page_base += AMDGPU_GPU_PAGE_SIZE;
  263. }
  264. }
  265. return 0;
  266. }
  267. /**
  268. * amdgpu_gart_bind - bind pages into the gart page table
  269. *
  270. * @adev: amdgpu_device pointer
  271. * @offset: offset into the GPU's gart aperture
  272. * @pages: number of pages to bind
  273. * @pagelist: pages to bind
  274. * @dma_addr: DMA addresses of pages
  275. *
  276. * Binds the requested pages to the gart page table
  277. * (all asics).
  278. * Returns 0 for success, -EINVAL for failure.
  279. */
  280. int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset,
  281. int pages, struct page **pagelist, dma_addr_t *dma_addr,
  282. uint64_t flags)
  283. {
  284. #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
  285. unsigned i,t,p;
  286. #endif
  287. int r;
  288. if (!adev->gart.ready) {
  289. WARN(1, "trying to bind memory to uninitialized GART !\n");
  290. return -EINVAL;
  291. }
  292. #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
  293. t = offset / AMDGPU_GPU_PAGE_SIZE;
  294. p = t / (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE);
  295. for (i = 0; i < pages; i++, p++)
  296. adev->gart.pages[p] = pagelist ? pagelist[i] : NULL;
  297. #endif
  298. if (!adev->gart.ptr)
  299. return 0;
  300. r = amdgpu_gart_map(adev, offset, pages, dma_addr, flags,
  301. adev->gart.ptr);
  302. if (r)
  303. return r;
  304. mb();
  305. amdgpu_asic_flush_hdp(adev, NULL);
  306. amdgpu_gmc_flush_gpu_tlb(adev, 0);
  307. return 0;
  308. }
  309. /**
  310. * amdgpu_gart_init - init the driver info for managing the gart
  311. *
  312. * @adev: amdgpu_device pointer
  313. *
  314. * Allocate the dummy page and init the gart driver info (all asics).
  315. * Returns 0 for success, error for failure.
  316. */
  317. int amdgpu_gart_init(struct amdgpu_device *adev)
  318. {
  319. int r;
  320. if (adev->dummy_page_addr)
  321. return 0;
  322. /* We need PAGE_SIZE >= AMDGPU_GPU_PAGE_SIZE */
  323. if (PAGE_SIZE < AMDGPU_GPU_PAGE_SIZE) {
  324. DRM_ERROR("Page size is smaller than GPU page size!\n");
  325. return -EINVAL;
  326. }
  327. r = amdgpu_gart_dummy_page_init(adev);
  328. if (r)
  329. return r;
  330. /* Compute table size */
  331. adev->gart.num_cpu_pages = adev->gmc.gart_size / PAGE_SIZE;
  332. adev->gart.num_gpu_pages = adev->gmc.gart_size / AMDGPU_GPU_PAGE_SIZE;
  333. DRM_INFO("GART: num cpu pages %u, num gpu pages %u\n",
  334. adev->gart.num_cpu_pages, adev->gart.num_gpu_pages);
  335. #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
  336. /* Allocate pages table */
  337. adev->gart.pages = vzalloc(sizeof(void *) * adev->gart.num_cpu_pages);
  338. if (adev->gart.pages == NULL)
  339. return -ENOMEM;
  340. #endif
  341. return 0;
  342. }
  343. /**
  344. * amdgpu_gart_fini - tear down the driver info for managing the gart
  345. *
  346. * @adev: amdgpu_device pointer
  347. *
  348. * Tear down the gart driver info and free the dummy page (all asics).
  349. */
  350. void amdgpu_gart_fini(struct amdgpu_device *adev)
  351. {
  352. #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
  353. vfree(adev->gart.pages);
  354. adev->gart.pages = NULL;
  355. #endif
  356. amdgpu_gart_dummy_page_fini(adev);
  357. }