msi.c 10 KB

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  1. /*
  2. * linux/kernel/irq/msi.c
  3. *
  4. * Copyright (C) 2014 Intel Corp.
  5. * Author: Jiang Liu <jiang.liu@linux.intel.com>
  6. *
  7. * This file is licensed under GPLv2.
  8. *
  9. * This file contains common code to support Message Signalled Interrupt for
  10. * PCI compatible and non PCI compatible devices.
  11. */
  12. #include <linux/types.h>
  13. #include <linux/device.h>
  14. #include <linux/irq.h>
  15. #include <linux/irqdomain.h>
  16. #include <linux/msi.h>
  17. /* Temparory solution for building, will be removed later */
  18. #include <linux/pci.h>
  19. struct msi_desc *alloc_msi_entry(struct device *dev)
  20. {
  21. struct msi_desc *desc = kzalloc(sizeof(*desc), GFP_KERNEL);
  22. if (!desc)
  23. return NULL;
  24. INIT_LIST_HEAD(&desc->list);
  25. desc->dev = dev;
  26. return desc;
  27. }
  28. void free_msi_entry(struct msi_desc *entry)
  29. {
  30. kfree(entry);
  31. }
  32. void __get_cached_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
  33. {
  34. *msg = entry->msg;
  35. }
  36. void get_cached_msi_msg(unsigned int irq, struct msi_msg *msg)
  37. {
  38. struct msi_desc *entry = irq_get_msi_desc(irq);
  39. __get_cached_msi_msg(entry, msg);
  40. }
  41. EXPORT_SYMBOL_GPL(get_cached_msi_msg);
  42. #ifdef CONFIG_GENERIC_MSI_IRQ_DOMAIN
  43. static inline void irq_chip_write_msi_msg(struct irq_data *data,
  44. struct msi_msg *msg)
  45. {
  46. data->chip->irq_write_msi_msg(data, msg);
  47. }
  48. /**
  49. * msi_domain_set_affinity - Generic affinity setter function for MSI domains
  50. * @irq_data: The irq data associated to the interrupt
  51. * @mask: The affinity mask to set
  52. * @force: Flag to enforce setting (disable online checks)
  53. *
  54. * Intended to be used by MSI interrupt controllers which are
  55. * implemented with hierarchical domains.
  56. */
  57. int msi_domain_set_affinity(struct irq_data *irq_data,
  58. const struct cpumask *mask, bool force)
  59. {
  60. struct irq_data *parent = irq_data->parent_data;
  61. struct msi_msg msg;
  62. int ret;
  63. ret = parent->chip->irq_set_affinity(parent, mask, force);
  64. if (ret >= 0 && ret != IRQ_SET_MASK_OK_DONE) {
  65. BUG_ON(irq_chip_compose_msi_msg(irq_data, &msg));
  66. irq_chip_write_msi_msg(irq_data, &msg);
  67. }
  68. return ret;
  69. }
  70. static void msi_domain_activate(struct irq_domain *domain,
  71. struct irq_data *irq_data)
  72. {
  73. struct msi_msg msg;
  74. BUG_ON(irq_chip_compose_msi_msg(irq_data, &msg));
  75. irq_chip_write_msi_msg(irq_data, &msg);
  76. }
  77. static void msi_domain_deactivate(struct irq_domain *domain,
  78. struct irq_data *irq_data)
  79. {
  80. struct msi_msg msg;
  81. memset(&msg, 0, sizeof(msg));
  82. irq_chip_write_msi_msg(irq_data, &msg);
  83. }
  84. static int msi_domain_alloc(struct irq_domain *domain, unsigned int virq,
  85. unsigned int nr_irqs, void *arg)
  86. {
  87. struct msi_domain_info *info = domain->host_data;
  88. struct msi_domain_ops *ops = info->ops;
  89. irq_hw_number_t hwirq = ops->get_hwirq(info, arg);
  90. int i, ret;
  91. if (irq_find_mapping(domain, hwirq) > 0)
  92. return -EEXIST;
  93. if (domain->parent) {
  94. ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
  95. if (ret < 0)
  96. return ret;
  97. }
  98. for (i = 0; i < nr_irqs; i++) {
  99. ret = ops->msi_init(domain, info, virq + i, hwirq + i, arg);
  100. if (ret < 0) {
  101. if (ops->msi_free) {
  102. for (i--; i > 0; i--)
  103. ops->msi_free(domain, info, virq + i);
  104. }
  105. irq_domain_free_irqs_top(domain, virq, nr_irqs);
  106. return ret;
  107. }
  108. }
  109. return 0;
  110. }
  111. static void msi_domain_free(struct irq_domain *domain, unsigned int virq,
  112. unsigned int nr_irqs)
  113. {
  114. struct msi_domain_info *info = domain->host_data;
  115. int i;
  116. if (info->ops->msi_free) {
  117. for (i = 0; i < nr_irqs; i++)
  118. info->ops->msi_free(domain, info, virq + i);
  119. }
  120. irq_domain_free_irqs_top(domain, virq, nr_irqs);
  121. }
  122. static const struct irq_domain_ops msi_domain_ops = {
  123. .alloc = msi_domain_alloc,
  124. .free = msi_domain_free,
  125. .activate = msi_domain_activate,
  126. .deactivate = msi_domain_deactivate,
  127. };
  128. #ifdef GENERIC_MSI_DOMAIN_OPS
  129. static irq_hw_number_t msi_domain_ops_get_hwirq(struct msi_domain_info *info,
  130. msi_alloc_info_t *arg)
  131. {
  132. return arg->hwirq;
  133. }
  134. static int msi_domain_ops_prepare(struct irq_domain *domain, struct device *dev,
  135. int nvec, msi_alloc_info_t *arg)
  136. {
  137. memset(arg, 0, sizeof(*arg));
  138. return 0;
  139. }
  140. static void msi_domain_ops_set_desc(msi_alloc_info_t *arg,
  141. struct msi_desc *desc)
  142. {
  143. arg->desc = desc;
  144. }
  145. #else
  146. #define msi_domain_ops_get_hwirq NULL
  147. #define msi_domain_ops_prepare NULL
  148. #define msi_domain_ops_set_desc NULL
  149. #endif /* !GENERIC_MSI_DOMAIN_OPS */
  150. static int msi_domain_ops_init(struct irq_domain *domain,
  151. struct msi_domain_info *info,
  152. unsigned int virq, irq_hw_number_t hwirq,
  153. msi_alloc_info_t *arg)
  154. {
  155. irq_domain_set_hwirq_and_chip(domain, virq, hwirq, info->chip,
  156. info->chip_data);
  157. if (info->handler && info->handler_name) {
  158. __irq_set_handler(virq, info->handler, 0, info->handler_name);
  159. if (info->handler_data)
  160. irq_set_handler_data(virq, info->handler_data);
  161. }
  162. return 0;
  163. }
  164. static int msi_domain_ops_check(struct irq_domain *domain,
  165. struct msi_domain_info *info,
  166. struct device *dev)
  167. {
  168. return 0;
  169. }
  170. static struct msi_domain_ops msi_domain_ops_default = {
  171. .get_hwirq = msi_domain_ops_get_hwirq,
  172. .msi_init = msi_domain_ops_init,
  173. .msi_check = msi_domain_ops_check,
  174. .msi_prepare = msi_domain_ops_prepare,
  175. .set_desc = msi_domain_ops_set_desc,
  176. };
  177. static void msi_domain_update_dom_ops(struct msi_domain_info *info)
  178. {
  179. struct msi_domain_ops *ops = info->ops;
  180. if (ops == NULL) {
  181. info->ops = &msi_domain_ops_default;
  182. return;
  183. }
  184. if (ops->get_hwirq == NULL)
  185. ops->get_hwirq = msi_domain_ops_default.get_hwirq;
  186. if (ops->msi_init == NULL)
  187. ops->msi_init = msi_domain_ops_default.msi_init;
  188. if (ops->msi_check == NULL)
  189. ops->msi_check = msi_domain_ops_default.msi_check;
  190. if (ops->msi_prepare == NULL)
  191. ops->msi_prepare = msi_domain_ops_default.msi_prepare;
  192. if (ops->set_desc == NULL)
  193. ops->set_desc = msi_domain_ops_default.set_desc;
  194. }
  195. static void msi_domain_update_chip_ops(struct msi_domain_info *info)
  196. {
  197. struct irq_chip *chip = info->chip;
  198. BUG_ON(!chip || !chip->irq_mask || !chip->irq_unmask);
  199. if (!chip->irq_set_affinity)
  200. chip->irq_set_affinity = msi_domain_set_affinity;
  201. }
  202. /**
  203. * msi_create_irq_domain - Create a MSI interrupt domain
  204. * @fwnode: Optional fwnode of the interrupt controller
  205. * @info: MSI domain info
  206. * @parent: Parent irq domain
  207. */
  208. struct irq_domain *msi_create_irq_domain(struct fwnode_handle *fwnode,
  209. struct msi_domain_info *info,
  210. struct irq_domain *parent)
  211. {
  212. if (info->flags & MSI_FLAG_USE_DEF_DOM_OPS)
  213. msi_domain_update_dom_ops(info);
  214. if (info->flags & MSI_FLAG_USE_DEF_CHIP_OPS)
  215. msi_domain_update_chip_ops(info);
  216. return irq_domain_create_hierarchy(parent, 0, 0, fwnode,
  217. &msi_domain_ops, info);
  218. }
  219. int msi_domain_prepare_irqs(struct irq_domain *domain, struct device *dev,
  220. int nvec, msi_alloc_info_t *arg)
  221. {
  222. struct msi_domain_info *info = domain->host_data;
  223. struct msi_domain_ops *ops = info->ops;
  224. int ret;
  225. ret = ops->msi_check(domain, info, dev);
  226. if (ret == 0)
  227. ret = ops->msi_prepare(domain, dev, nvec, arg);
  228. return ret;
  229. }
  230. int msi_domain_populate_irqs(struct irq_domain *domain, struct device *dev,
  231. int virq, int nvec, msi_alloc_info_t *arg)
  232. {
  233. struct msi_domain_info *info = domain->host_data;
  234. struct msi_domain_ops *ops = info->ops;
  235. struct msi_desc *desc;
  236. int ret = 0;
  237. for_each_msi_entry(desc, dev) {
  238. /* Don't even try the multi-MSI brain damage. */
  239. if (WARN_ON(!desc->irq || desc->nvec_used != 1)) {
  240. ret = -EINVAL;
  241. break;
  242. }
  243. if (!(desc->irq >= virq && desc->irq < (virq + nvec)))
  244. continue;
  245. ops->set_desc(arg, desc);
  246. /* Assumes the domain mutex is held! */
  247. ret = irq_domain_alloc_irqs_recursive(domain, virq, 1, arg);
  248. if (ret)
  249. break;
  250. irq_set_msi_desc_off(virq, 0, desc);
  251. }
  252. if (ret) {
  253. /* Mop up the damage */
  254. for_each_msi_entry(desc, dev) {
  255. if (!(desc->irq >= virq && desc->irq < (virq + nvec)))
  256. continue;
  257. irq_domain_free_irqs_common(domain, desc->irq, 1);
  258. }
  259. }
  260. return ret;
  261. }
  262. /**
  263. * msi_domain_alloc_irqs - Allocate interrupts from a MSI interrupt domain
  264. * @domain: The domain to allocate from
  265. * @dev: Pointer to device struct of the device for which the interrupts
  266. * are allocated
  267. * @nvec: The number of interrupts to allocate
  268. *
  269. * Returns 0 on success or an error code.
  270. */
  271. int msi_domain_alloc_irqs(struct irq_domain *domain, struct device *dev,
  272. int nvec)
  273. {
  274. struct msi_domain_info *info = domain->host_data;
  275. struct msi_domain_ops *ops = info->ops;
  276. msi_alloc_info_t arg;
  277. struct msi_desc *desc;
  278. int i, ret, virq = -1;
  279. ret = msi_domain_prepare_irqs(domain, dev, nvec, &arg);
  280. if (ret)
  281. return ret;
  282. for_each_msi_entry(desc, dev) {
  283. ops->set_desc(&arg, desc);
  284. if (info->flags & MSI_FLAG_IDENTITY_MAP)
  285. virq = (int)ops->get_hwirq(info, &arg);
  286. else
  287. virq = -1;
  288. virq = __irq_domain_alloc_irqs(domain, virq, desc->nvec_used,
  289. dev_to_node(dev), &arg, false);
  290. if (virq < 0) {
  291. ret = -ENOSPC;
  292. if (ops->handle_error)
  293. ret = ops->handle_error(domain, desc, ret);
  294. if (ops->msi_finish)
  295. ops->msi_finish(&arg, ret);
  296. return ret;
  297. }
  298. for (i = 0; i < desc->nvec_used; i++)
  299. irq_set_msi_desc_off(virq, i, desc);
  300. }
  301. if (ops->msi_finish)
  302. ops->msi_finish(&arg, 0);
  303. for_each_msi_entry(desc, dev) {
  304. if (desc->nvec_used == 1)
  305. dev_dbg(dev, "irq %d for MSI\n", virq);
  306. else
  307. dev_dbg(dev, "irq [%d-%d] for MSI\n",
  308. virq, virq + desc->nvec_used - 1);
  309. }
  310. return 0;
  311. }
  312. /**
  313. * msi_domain_free_irqs - Free interrupts from a MSI interrupt @domain associated tp @dev
  314. * @domain: The domain to managing the interrupts
  315. * @dev: Pointer to device struct of the device for which the interrupts
  316. * are free
  317. */
  318. void msi_domain_free_irqs(struct irq_domain *domain, struct device *dev)
  319. {
  320. struct msi_desc *desc;
  321. for_each_msi_entry(desc, dev) {
  322. /*
  323. * We might have failed to allocate an MSI early
  324. * enough that there is no IRQ associated to this
  325. * entry. If that's the case, don't do anything.
  326. */
  327. if (desc->irq) {
  328. irq_domain_free_irqs(desc->irq, desc->nvec_used);
  329. desc->irq = 0;
  330. }
  331. }
  332. }
  333. /**
  334. * msi_get_domain_info - Get the MSI interrupt domain info for @domain
  335. * @domain: The interrupt domain to retrieve data from
  336. *
  337. * Returns the pointer to the msi_domain_info stored in
  338. * @domain->host_data.
  339. */
  340. struct msi_domain_info *msi_get_domain_info(struct irq_domain *domain)
  341. {
  342. return (struct msi_domain_info *)domain->host_data;
  343. }
  344. #endif /* CONFIG_GENERIC_MSI_IRQ_DOMAIN */