dwc3-pci.c 9.6 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359
  1. /**
  2. * dwc3-pci.c - PCI Specific glue layer
  3. *
  4. * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
  5. *
  6. * Authors: Felipe Balbi <balbi@ti.com>,
  7. * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
  8. *
  9. * This program is free software: you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 of
  11. * the License as published by the Free Software Foundation.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. */
  18. #include <linux/kernel.h>
  19. #include <linux/module.h>
  20. #include <linux/slab.h>
  21. #include <linux/pci.h>
  22. #include <linux/pm_runtime.h>
  23. #include <linux/platform_device.h>
  24. #include <linux/gpio/consumer.h>
  25. #include <linux/acpi.h>
  26. #include <linux/delay.h>
  27. #define PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3 0xabcd
  28. #define PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI 0xabce
  29. #define PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31 0xabcf
  30. #define PCI_DEVICE_ID_INTEL_BYT 0x0f37
  31. #define PCI_DEVICE_ID_INTEL_MRFLD 0x119e
  32. #define PCI_DEVICE_ID_INTEL_BSW 0x22b7
  33. #define PCI_DEVICE_ID_INTEL_SPTLP 0x9d30
  34. #define PCI_DEVICE_ID_INTEL_SPTH 0xa130
  35. #define PCI_DEVICE_ID_INTEL_BXT 0x0aaa
  36. #define PCI_DEVICE_ID_INTEL_BXT_M 0x1aaa
  37. #define PCI_DEVICE_ID_INTEL_APL 0x5aaa
  38. #define PCI_DEVICE_ID_INTEL_KBP 0xa2b0
  39. #define PCI_INTEL_BXT_DSM_UUID "732b85d5-b7a7-4a1b-9ba0-4bbd00ffd511"
  40. #define PCI_INTEL_BXT_FUNC_PMU_PWR 4
  41. #define PCI_INTEL_BXT_STATE_D0 0
  42. #define PCI_INTEL_BXT_STATE_D3 3
  43. /**
  44. * struct dwc3_pci - Driver private structure
  45. * @dwc3: child dwc3 platform_device
  46. * @pci: our link to PCI bus
  47. * @uuid: _DSM UUID
  48. * @has_dsm_for_pm: true for devices which need to run _DSM on runtime PM
  49. */
  50. struct dwc3_pci {
  51. struct platform_device *dwc3;
  52. struct pci_dev *pci;
  53. u8 uuid[16];
  54. unsigned int has_dsm_for_pm:1;
  55. };
  56. static const struct acpi_gpio_params reset_gpios = { 0, 0, false };
  57. static const struct acpi_gpio_params cs_gpios = { 1, 0, false };
  58. static const struct acpi_gpio_mapping acpi_dwc3_byt_gpios[] = {
  59. { "reset-gpios", &reset_gpios, 1 },
  60. { "cs-gpios", &cs_gpios, 1 },
  61. { },
  62. };
  63. static int dwc3_pci_quirks(struct dwc3_pci *dwc)
  64. {
  65. struct platform_device *dwc3 = dwc->dwc3;
  66. struct pci_dev *pdev = dwc->pci;
  67. if (pdev->vendor == PCI_VENDOR_ID_AMD &&
  68. pdev->device == PCI_DEVICE_ID_AMD_NL_USB) {
  69. struct property_entry properties[] = {
  70. PROPERTY_ENTRY_BOOL("snps,has-lpm-erratum"),
  71. PROPERTY_ENTRY_U8("snps,lpm-nyet-threshold", 0xf),
  72. PROPERTY_ENTRY_BOOL("snps,u2exit_lfps_quirk"),
  73. PROPERTY_ENTRY_BOOL("snps,u2ss_inp3_quirk"),
  74. PROPERTY_ENTRY_BOOL("snps,req_p1p2p3_quirk"),
  75. PROPERTY_ENTRY_BOOL("snps,del_p1p2p3_quirk"),
  76. PROPERTY_ENTRY_BOOL("snps,del_phy_power_chg_quirk"),
  77. PROPERTY_ENTRY_BOOL("snps,lfps_filter_quirk"),
  78. PROPERTY_ENTRY_BOOL("snps,rx_detect_poll_quirk"),
  79. PROPERTY_ENTRY_BOOL("snps,tx_de_emphasis_quirk"),
  80. PROPERTY_ENTRY_U8("snps,tx_de_emphasis", 1),
  81. /*
  82. * FIXME these quirks should be removed when AMD NL
  83. * tapes out
  84. */
  85. PROPERTY_ENTRY_BOOL("snps,disable_scramble_quirk"),
  86. PROPERTY_ENTRY_BOOL("snps,dis_u3_susphy_quirk"),
  87. PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"),
  88. { },
  89. };
  90. return platform_device_add_properties(dwc3, properties);
  91. }
  92. if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
  93. int ret;
  94. struct property_entry properties[] = {
  95. PROPERTY_ENTRY_STRING("dr-mode", "peripheral"),
  96. { }
  97. };
  98. ret = platform_device_add_properties(dwc3, properties);
  99. if (ret < 0)
  100. return ret;
  101. if (pdev->device == PCI_DEVICE_ID_INTEL_BXT ||
  102. pdev->device == PCI_DEVICE_ID_INTEL_BXT_M) {
  103. acpi_str_to_uuid(PCI_INTEL_BXT_DSM_UUID, dwc->uuid);
  104. dwc->has_dsm_for_pm = true;
  105. }
  106. if (pdev->device == PCI_DEVICE_ID_INTEL_BYT) {
  107. struct gpio_desc *gpio;
  108. acpi_dev_add_driver_gpios(ACPI_COMPANION(&pdev->dev),
  109. acpi_dwc3_byt_gpios);
  110. /*
  111. * These GPIOs will turn on the USB2 PHY. Note that we have to
  112. * put the gpio descriptors again here because the phy driver
  113. * might want to grab them, too.
  114. */
  115. gpio = gpiod_get_optional(&pdev->dev, "cs", GPIOD_OUT_LOW);
  116. if (IS_ERR(gpio))
  117. return PTR_ERR(gpio);
  118. gpiod_set_value_cansleep(gpio, 1);
  119. gpiod_put(gpio);
  120. gpio = gpiod_get_optional(&pdev->dev, "reset", GPIOD_OUT_LOW);
  121. if (IS_ERR(gpio))
  122. return PTR_ERR(gpio);
  123. if (gpio) {
  124. gpiod_set_value_cansleep(gpio, 1);
  125. gpiod_put(gpio);
  126. usleep_range(10000, 11000);
  127. }
  128. }
  129. }
  130. if (pdev->vendor == PCI_VENDOR_ID_SYNOPSYS &&
  131. (pdev->device == PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3 ||
  132. pdev->device == PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI ||
  133. pdev->device == PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31)) {
  134. struct property_entry properties[] = {
  135. PROPERTY_ENTRY_BOOL("snps,usb3_lpm_capable"),
  136. PROPERTY_ENTRY_BOOL("snps,has-lpm-erratum"),
  137. PROPERTY_ENTRY_BOOL("snps,dis_enblslpm_quirk"),
  138. { },
  139. };
  140. return platform_device_add_properties(dwc3, properties);
  141. }
  142. return 0;
  143. }
  144. static int dwc3_pci_probe(struct pci_dev *pci,
  145. const struct pci_device_id *id)
  146. {
  147. struct dwc3_pci *dwc;
  148. struct resource res[2];
  149. int ret;
  150. struct device *dev = &pci->dev;
  151. ret = pcim_enable_device(pci);
  152. if (ret) {
  153. dev_err(dev, "failed to enable pci device\n");
  154. return -ENODEV;
  155. }
  156. pci_set_master(pci);
  157. dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
  158. if (!dwc)
  159. return -ENOMEM;
  160. dwc->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO);
  161. if (!dwc->dwc3)
  162. return -ENOMEM;
  163. memset(res, 0x00, sizeof(struct resource) * ARRAY_SIZE(res));
  164. res[0].start = pci_resource_start(pci, 0);
  165. res[0].end = pci_resource_end(pci, 0);
  166. res[0].name = "dwc_usb3";
  167. res[0].flags = IORESOURCE_MEM;
  168. res[1].start = pci->irq;
  169. res[1].name = "dwc_usb3";
  170. res[1].flags = IORESOURCE_IRQ;
  171. ret = platform_device_add_resources(dwc->dwc3, res, ARRAY_SIZE(res));
  172. if (ret) {
  173. dev_err(dev, "couldn't add resources to dwc3 device\n");
  174. return ret;
  175. }
  176. dwc->pci = pci;
  177. dwc->dwc3->dev.parent = dev;
  178. ACPI_COMPANION_SET(&dwc->dwc3->dev, ACPI_COMPANION(dev));
  179. ret = dwc3_pci_quirks(dwc);
  180. if (ret)
  181. goto err;
  182. ret = platform_device_add(dwc->dwc3);
  183. if (ret) {
  184. dev_err(dev, "failed to register dwc3 device\n");
  185. goto err;
  186. }
  187. device_init_wakeup(dev, true);
  188. device_set_run_wake(dev, true);
  189. pci_set_drvdata(pci, dwc);
  190. pm_runtime_put(dev);
  191. return 0;
  192. err:
  193. platform_device_put(dwc->dwc3);
  194. return ret;
  195. }
  196. static void dwc3_pci_remove(struct pci_dev *pci)
  197. {
  198. struct dwc3_pci *dwc = pci_get_drvdata(pci);
  199. device_init_wakeup(&pci->dev, false);
  200. pm_runtime_get(&pci->dev);
  201. acpi_dev_remove_driver_gpios(ACPI_COMPANION(&pci->dev));
  202. platform_device_unregister(dwc->dwc3);
  203. }
  204. static const struct pci_device_id dwc3_pci_id_table[] = {
  205. {
  206. PCI_DEVICE(PCI_VENDOR_ID_SYNOPSYS,
  207. PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3),
  208. },
  209. {
  210. PCI_DEVICE(PCI_VENDOR_ID_SYNOPSYS,
  211. PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI),
  212. },
  213. {
  214. PCI_DEVICE(PCI_VENDOR_ID_SYNOPSYS,
  215. PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31),
  216. },
  217. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW), },
  218. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT), },
  219. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MRFLD), },
  220. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SPTLP), },
  221. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SPTH), },
  222. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BXT), },
  223. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BXT_M), },
  224. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_APL), },
  225. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KBP), },
  226. { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB), },
  227. { } /* Terminating Entry */
  228. };
  229. MODULE_DEVICE_TABLE(pci, dwc3_pci_id_table);
  230. #if defined(CONFIG_PM) || defined(CONFIG_PM_SLEEP)
  231. static int dwc3_pci_dsm(struct dwc3_pci *dwc, int param)
  232. {
  233. union acpi_object *obj;
  234. union acpi_object tmp;
  235. union acpi_object argv4 = ACPI_INIT_DSM_ARGV4(1, &tmp);
  236. if (!dwc->has_dsm_for_pm)
  237. return 0;
  238. tmp.type = ACPI_TYPE_INTEGER;
  239. tmp.integer.value = param;
  240. obj = acpi_evaluate_dsm(ACPI_HANDLE(&dwc->pci->dev), dwc->uuid,
  241. 1, PCI_INTEL_BXT_FUNC_PMU_PWR, &argv4);
  242. if (!obj) {
  243. dev_err(&dwc->pci->dev, "failed to evaluate _DSM\n");
  244. return -EIO;
  245. }
  246. ACPI_FREE(obj);
  247. return 0;
  248. }
  249. #endif /* CONFIG_PM || CONFIG_PM_SLEEP */
  250. #ifdef CONFIG_PM
  251. static int dwc3_pci_runtime_suspend(struct device *dev)
  252. {
  253. struct dwc3_pci *dwc = dev_get_drvdata(dev);
  254. if (device_run_wake(dev))
  255. return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3);
  256. return -EBUSY;
  257. }
  258. static int dwc3_pci_runtime_resume(struct device *dev)
  259. {
  260. struct dwc3_pci *dwc = dev_get_drvdata(dev);
  261. struct platform_device *dwc3 = dwc->dwc3;
  262. int ret;
  263. ret = dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0);
  264. if (ret)
  265. return ret;
  266. return pm_runtime_get(&dwc3->dev);
  267. }
  268. #endif /* CONFIG_PM */
  269. #ifdef CONFIG_PM_SLEEP
  270. static int dwc3_pci_suspend(struct device *dev)
  271. {
  272. struct dwc3_pci *dwc = dev_get_drvdata(dev);
  273. return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3);
  274. }
  275. static int dwc3_pci_resume(struct device *dev)
  276. {
  277. struct dwc3_pci *dwc = dev_get_drvdata(dev);
  278. return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0);
  279. }
  280. #endif /* CONFIG_PM_SLEEP */
  281. static struct dev_pm_ops dwc3_pci_dev_pm_ops = {
  282. SET_SYSTEM_SLEEP_PM_OPS(dwc3_pci_suspend, dwc3_pci_resume)
  283. SET_RUNTIME_PM_OPS(dwc3_pci_runtime_suspend, dwc3_pci_runtime_resume,
  284. NULL)
  285. };
  286. static struct pci_driver dwc3_pci_driver = {
  287. .name = "dwc3-pci",
  288. .id_table = dwc3_pci_id_table,
  289. .probe = dwc3_pci_probe,
  290. .remove = dwc3_pci_remove,
  291. .driver = {
  292. .pm = &dwc3_pci_dev_pm_ops,
  293. }
  294. };
  295. MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
  296. MODULE_LICENSE("GPL v2");
  297. MODULE_DESCRIPTION("DesignWare USB3 PCI Glue Layer");
  298. module_pci_driver(dwc3_pci_driver);