pci-layerscape.c 8.2 KB

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  1. /*
  2. * PCIe host controller driver for Freescale Layerscape SoCs
  3. *
  4. * Copyright (C) 2014 Freescale Semiconductor.
  5. *
  6. * Author: Minghuan Lian <Minghuan.Lian@freescale.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. #include <linux/kernel.h>
  13. #include <linux/interrupt.h>
  14. #include <linux/init.h>
  15. #include <linux/of_pci.h>
  16. #include <linux/of_platform.h>
  17. #include <linux/of_irq.h>
  18. #include <linux/of_address.h>
  19. #include <linux/pci.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/resource.h>
  22. #include <linux/mfd/syscon.h>
  23. #include <linux/regmap.h>
  24. #include "pcie-designware.h"
  25. /* PEX1/2 Misc Ports Status Register */
  26. #define SCFG_PEXMSCPORTSR(pex_idx) (0x94 + (pex_idx) * 4)
  27. #define LTSSM_STATE_SHIFT 20
  28. #define LTSSM_STATE_MASK 0x3f
  29. #define LTSSM_PCIE_L0 0x11 /* L0 state */
  30. /* PEX Internal Configuration Registers */
  31. #define PCIE_STRFMR1 0x71c /* Symbol Timer & Filter Mask Register1 */
  32. #define PCIE_ABSERR 0x8d0 /* Bridge Slave Error Response Register */
  33. #define PCIE_ABSERR_SETTING 0x9401 /* Forward error of non-posted request */
  34. #define PCIE_IATU_NUM 6
  35. struct ls_pcie_drvdata {
  36. u32 lut_offset;
  37. u32 ltssm_shift;
  38. u32 lut_dbg;
  39. const struct dw_pcie_host_ops *ops;
  40. const struct dw_pcie_ops *dw_pcie_ops;
  41. };
  42. struct ls_pcie {
  43. struct dw_pcie *pci;
  44. void __iomem *lut;
  45. struct regmap *scfg;
  46. const struct ls_pcie_drvdata *drvdata;
  47. int index;
  48. };
  49. #define to_ls_pcie(x) dev_get_drvdata((x)->dev)
  50. static bool ls_pcie_is_bridge(struct ls_pcie *pcie)
  51. {
  52. struct dw_pcie *pci = pcie->pci;
  53. u32 header_type;
  54. header_type = ioread8(pci->dbi_base + PCI_HEADER_TYPE);
  55. header_type &= 0x7f;
  56. return header_type == PCI_HEADER_TYPE_BRIDGE;
  57. }
  58. /* Clear multi-function bit */
  59. static void ls_pcie_clear_multifunction(struct ls_pcie *pcie)
  60. {
  61. struct dw_pcie *pci = pcie->pci;
  62. iowrite8(PCI_HEADER_TYPE_BRIDGE, pci->dbi_base + PCI_HEADER_TYPE);
  63. }
  64. /* Drop MSG TLP except for Vendor MSG */
  65. static void ls_pcie_drop_msg_tlp(struct ls_pcie *pcie)
  66. {
  67. u32 val;
  68. struct dw_pcie *pci = pcie->pci;
  69. val = ioread32(pci->dbi_base + PCIE_STRFMR1);
  70. val &= 0xDFFFFFFF;
  71. iowrite32(val, pci->dbi_base + PCIE_STRFMR1);
  72. }
  73. static void ls_pcie_disable_outbound_atus(struct ls_pcie *pcie)
  74. {
  75. int i;
  76. for (i = 0; i < PCIE_IATU_NUM; i++)
  77. dw_pcie_disable_atu(pcie->pci, DW_PCIE_REGION_OUTBOUND, i);
  78. }
  79. static int ls1021_pcie_link_up(struct dw_pcie *pci)
  80. {
  81. u32 state;
  82. struct ls_pcie *pcie = to_ls_pcie(pci);
  83. if (!pcie->scfg)
  84. return 0;
  85. regmap_read(pcie->scfg, SCFG_PEXMSCPORTSR(pcie->index), &state);
  86. state = (state >> LTSSM_STATE_SHIFT) & LTSSM_STATE_MASK;
  87. if (state < LTSSM_PCIE_L0)
  88. return 0;
  89. return 1;
  90. }
  91. static int ls_pcie_link_up(struct dw_pcie *pci)
  92. {
  93. struct ls_pcie *pcie = to_ls_pcie(pci);
  94. u32 state;
  95. state = (ioread32(pcie->lut + pcie->drvdata->lut_dbg) >>
  96. pcie->drvdata->ltssm_shift) &
  97. LTSSM_STATE_MASK;
  98. if (state < LTSSM_PCIE_L0)
  99. return 0;
  100. return 1;
  101. }
  102. /* Forward error response of outbound non-posted requests */
  103. static void ls_pcie_fix_error_response(struct ls_pcie *pcie)
  104. {
  105. struct dw_pcie *pci = pcie->pci;
  106. iowrite32(PCIE_ABSERR_SETTING, pci->dbi_base + PCIE_ABSERR);
  107. }
  108. static int ls_pcie_host_init(struct pcie_port *pp)
  109. {
  110. struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
  111. struct ls_pcie *pcie = to_ls_pcie(pci);
  112. /*
  113. * Disable outbound windows configured by the bootloader to avoid
  114. * one transaction hitting multiple outbound windows.
  115. * dw_pcie_setup_rc() will reconfigure the outbound windows.
  116. */
  117. ls_pcie_disable_outbound_atus(pcie);
  118. ls_pcie_fix_error_response(pcie);
  119. dw_pcie_dbi_ro_wr_en(pci);
  120. ls_pcie_clear_multifunction(pcie);
  121. dw_pcie_dbi_ro_wr_dis(pci);
  122. ls_pcie_drop_msg_tlp(pcie);
  123. dw_pcie_setup_rc(pp);
  124. return 0;
  125. }
  126. static int ls1021_pcie_host_init(struct pcie_port *pp)
  127. {
  128. struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
  129. struct ls_pcie *pcie = to_ls_pcie(pci);
  130. struct device *dev = pci->dev;
  131. u32 index[2];
  132. int ret;
  133. pcie->scfg = syscon_regmap_lookup_by_phandle(dev->of_node,
  134. "fsl,pcie-scfg");
  135. if (IS_ERR(pcie->scfg)) {
  136. ret = PTR_ERR(pcie->scfg);
  137. dev_err(dev, "No syscfg phandle specified\n");
  138. pcie->scfg = NULL;
  139. return ret;
  140. }
  141. if (of_property_read_u32_array(dev->of_node,
  142. "fsl,pcie-scfg", index, 2)) {
  143. pcie->scfg = NULL;
  144. return -EINVAL;
  145. }
  146. pcie->index = index[1];
  147. return ls_pcie_host_init(pp);
  148. }
  149. static int ls_pcie_msi_host_init(struct pcie_port *pp,
  150. struct msi_controller *chip)
  151. {
  152. struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
  153. struct device *dev = pci->dev;
  154. struct device_node *np = dev->of_node;
  155. struct device_node *msi_node;
  156. /*
  157. * The MSI domain is set by the generic of_msi_configure(). This
  158. * .msi_host_init() function keeps us from doing the default MSI
  159. * domain setup in dw_pcie_host_init() and also enforces the
  160. * requirement that "msi-parent" exists.
  161. */
  162. msi_node = of_parse_phandle(np, "msi-parent", 0);
  163. if (!msi_node) {
  164. dev_err(dev, "failed to find msi-parent\n");
  165. return -EINVAL;
  166. }
  167. return 0;
  168. }
  169. static const struct dw_pcie_host_ops ls1021_pcie_host_ops = {
  170. .host_init = ls1021_pcie_host_init,
  171. .msi_host_init = ls_pcie_msi_host_init,
  172. };
  173. static const struct dw_pcie_host_ops ls_pcie_host_ops = {
  174. .host_init = ls_pcie_host_init,
  175. .msi_host_init = ls_pcie_msi_host_init,
  176. };
  177. static const struct dw_pcie_ops dw_ls1021_pcie_ops = {
  178. .link_up = ls1021_pcie_link_up,
  179. };
  180. static const struct dw_pcie_ops dw_ls_pcie_ops = {
  181. .link_up = ls_pcie_link_up,
  182. };
  183. static struct ls_pcie_drvdata ls1021_drvdata = {
  184. .ops = &ls1021_pcie_host_ops,
  185. .dw_pcie_ops = &dw_ls1021_pcie_ops,
  186. };
  187. static struct ls_pcie_drvdata ls1043_drvdata = {
  188. .lut_offset = 0x10000,
  189. .ltssm_shift = 24,
  190. .lut_dbg = 0x7fc,
  191. .ops = &ls_pcie_host_ops,
  192. .dw_pcie_ops = &dw_ls_pcie_ops,
  193. };
  194. static struct ls_pcie_drvdata ls1046_drvdata = {
  195. .lut_offset = 0x80000,
  196. .ltssm_shift = 24,
  197. .lut_dbg = 0x407fc,
  198. .ops = &ls_pcie_host_ops,
  199. .dw_pcie_ops = &dw_ls_pcie_ops,
  200. };
  201. static struct ls_pcie_drvdata ls2080_drvdata = {
  202. .lut_offset = 0x80000,
  203. .ltssm_shift = 0,
  204. .lut_dbg = 0x7fc,
  205. .ops = &ls_pcie_host_ops,
  206. .dw_pcie_ops = &dw_ls_pcie_ops,
  207. };
  208. static struct ls_pcie_drvdata ls2088_drvdata = {
  209. .lut_offset = 0x80000,
  210. .ltssm_shift = 0,
  211. .lut_dbg = 0x407fc,
  212. .ops = &ls_pcie_host_ops,
  213. .dw_pcie_ops = &dw_ls_pcie_ops,
  214. };
  215. static const struct of_device_id ls_pcie_of_match[] = {
  216. { .compatible = "fsl,ls1012a-pcie", .data = &ls1046_drvdata },
  217. { .compatible = "fsl,ls1021a-pcie", .data = &ls1021_drvdata },
  218. { .compatible = "fsl,ls1043a-pcie", .data = &ls1043_drvdata },
  219. { .compatible = "fsl,ls1046a-pcie", .data = &ls1046_drvdata },
  220. { .compatible = "fsl,ls2080a-pcie", .data = &ls2080_drvdata },
  221. { .compatible = "fsl,ls2085a-pcie", .data = &ls2080_drvdata },
  222. { .compatible = "fsl,ls2088a-pcie", .data = &ls2088_drvdata },
  223. { .compatible = "fsl,ls1088a-pcie", .data = &ls2088_drvdata },
  224. { },
  225. };
  226. static int __init ls_add_pcie_port(struct ls_pcie *pcie)
  227. {
  228. struct dw_pcie *pci = pcie->pci;
  229. struct pcie_port *pp = &pci->pp;
  230. struct device *dev = pci->dev;
  231. int ret;
  232. pp->ops = pcie->drvdata->ops;
  233. ret = dw_pcie_host_init(pp);
  234. if (ret) {
  235. dev_err(dev, "failed to initialize host\n");
  236. return ret;
  237. }
  238. return 0;
  239. }
  240. static int __init ls_pcie_probe(struct platform_device *pdev)
  241. {
  242. struct device *dev = &pdev->dev;
  243. struct dw_pcie *pci;
  244. struct ls_pcie *pcie;
  245. struct resource *dbi_base;
  246. int ret;
  247. pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
  248. if (!pcie)
  249. return -ENOMEM;
  250. pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
  251. if (!pci)
  252. return -ENOMEM;
  253. pcie->drvdata = of_device_get_match_data(dev);
  254. pci->dev = dev;
  255. pci->ops = pcie->drvdata->dw_pcie_ops;
  256. pcie->pci = pci;
  257. dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
  258. pci->dbi_base = devm_pci_remap_cfg_resource(dev, dbi_base);
  259. if (IS_ERR(pci->dbi_base))
  260. return PTR_ERR(pci->dbi_base);
  261. pcie->lut = pci->dbi_base + pcie->drvdata->lut_offset;
  262. if (!ls_pcie_is_bridge(pcie))
  263. return -ENODEV;
  264. platform_set_drvdata(pdev, pcie);
  265. ret = ls_add_pcie_port(pcie);
  266. if (ret < 0)
  267. return ret;
  268. return 0;
  269. }
  270. static struct platform_driver ls_pcie_driver = {
  271. .driver = {
  272. .name = "layerscape-pcie",
  273. .of_match_table = ls_pcie_of_match,
  274. .suppress_bind_attrs = true,
  275. },
  276. };
  277. builtin_platform_driver_probe(ls_pcie_driver, ls_pcie_probe);