pci_endpoint_test.c 16 KB

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  1. /**
  2. * Host side test driver to test endpoint functionality
  3. *
  4. * Copyright (C) 2017 Texas Instruments
  5. * Author: Kishon Vijay Abraham I <kishon@ti.com>
  6. *
  7. * This program is free software: you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 of
  9. * the License as published by the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program. If not, see <http://www.gnu.org/licenses/>.
  18. */
  19. #include <linux/crc32.h>
  20. #include <linux/delay.h>
  21. #include <linux/fs.h>
  22. #include <linux/io.h>
  23. #include <linux/interrupt.h>
  24. #include <linux/irq.h>
  25. #include <linux/miscdevice.h>
  26. #include <linux/module.h>
  27. #include <linux/mutex.h>
  28. #include <linux/random.h>
  29. #include <linux/slab.h>
  30. #include <linux/pci.h>
  31. #include <linux/pci_ids.h>
  32. #include <linux/pci_regs.h>
  33. #include <uapi/linux/pcitest.h>
  34. #define DRV_MODULE_NAME "pci-endpoint-test"
  35. #define PCI_ENDPOINT_TEST_MAGIC 0x0
  36. #define PCI_ENDPOINT_TEST_COMMAND 0x4
  37. #define COMMAND_RAISE_LEGACY_IRQ BIT(0)
  38. #define COMMAND_RAISE_MSI_IRQ BIT(1)
  39. #define MSI_NUMBER_SHIFT 2
  40. /* 6 bits for MSI number */
  41. #define COMMAND_READ BIT(8)
  42. #define COMMAND_WRITE BIT(9)
  43. #define COMMAND_COPY BIT(10)
  44. #define PCI_ENDPOINT_TEST_STATUS 0x8
  45. #define STATUS_READ_SUCCESS BIT(0)
  46. #define STATUS_READ_FAIL BIT(1)
  47. #define STATUS_WRITE_SUCCESS BIT(2)
  48. #define STATUS_WRITE_FAIL BIT(3)
  49. #define STATUS_COPY_SUCCESS BIT(4)
  50. #define STATUS_COPY_FAIL BIT(5)
  51. #define STATUS_IRQ_RAISED BIT(6)
  52. #define STATUS_SRC_ADDR_INVALID BIT(7)
  53. #define STATUS_DST_ADDR_INVALID BIT(8)
  54. #define PCI_ENDPOINT_TEST_LOWER_SRC_ADDR 0xc
  55. #define PCI_ENDPOINT_TEST_UPPER_SRC_ADDR 0x10
  56. #define PCI_ENDPOINT_TEST_LOWER_DST_ADDR 0x14
  57. #define PCI_ENDPOINT_TEST_UPPER_DST_ADDR 0x18
  58. #define PCI_ENDPOINT_TEST_SIZE 0x1c
  59. #define PCI_ENDPOINT_TEST_CHECKSUM 0x20
  60. static DEFINE_IDA(pci_endpoint_test_ida);
  61. #define to_endpoint_test(priv) container_of((priv), struct pci_endpoint_test, \
  62. miscdev)
  63. static bool no_msi;
  64. module_param(no_msi, bool, 0444);
  65. MODULE_PARM_DESC(no_msi, "Disable MSI interrupt in pci_endpoint_test");
  66. enum pci_barno {
  67. BAR_0,
  68. BAR_1,
  69. BAR_2,
  70. BAR_3,
  71. BAR_4,
  72. BAR_5,
  73. };
  74. struct pci_endpoint_test {
  75. struct pci_dev *pdev;
  76. void __iomem *base;
  77. void __iomem *bar[6];
  78. struct completion irq_raised;
  79. int last_irq;
  80. int num_irqs;
  81. /* mutex to protect the ioctls */
  82. struct mutex mutex;
  83. struct miscdevice miscdev;
  84. enum pci_barno test_reg_bar;
  85. size_t alignment;
  86. };
  87. struct pci_endpoint_test_data {
  88. enum pci_barno test_reg_bar;
  89. size_t alignment;
  90. bool no_msi;
  91. };
  92. static inline u32 pci_endpoint_test_readl(struct pci_endpoint_test *test,
  93. u32 offset)
  94. {
  95. return readl(test->base + offset);
  96. }
  97. static inline void pci_endpoint_test_writel(struct pci_endpoint_test *test,
  98. u32 offset, u32 value)
  99. {
  100. writel(value, test->base + offset);
  101. }
  102. static inline u32 pci_endpoint_test_bar_readl(struct pci_endpoint_test *test,
  103. int bar, int offset)
  104. {
  105. return readl(test->bar[bar] + offset);
  106. }
  107. static inline void pci_endpoint_test_bar_writel(struct pci_endpoint_test *test,
  108. int bar, u32 offset, u32 value)
  109. {
  110. writel(value, test->bar[bar] + offset);
  111. }
  112. static irqreturn_t pci_endpoint_test_irqhandler(int irq, void *dev_id)
  113. {
  114. struct pci_endpoint_test *test = dev_id;
  115. u32 reg;
  116. reg = pci_endpoint_test_readl(test, PCI_ENDPOINT_TEST_STATUS);
  117. if (reg & STATUS_IRQ_RAISED) {
  118. test->last_irq = irq;
  119. complete(&test->irq_raised);
  120. reg &= ~STATUS_IRQ_RAISED;
  121. }
  122. pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_STATUS,
  123. reg);
  124. return IRQ_HANDLED;
  125. }
  126. static bool pci_endpoint_test_bar(struct pci_endpoint_test *test,
  127. enum pci_barno barno)
  128. {
  129. int j;
  130. u32 val;
  131. int size;
  132. struct pci_dev *pdev = test->pdev;
  133. if (!test->bar[barno])
  134. return false;
  135. size = pci_resource_len(pdev, barno);
  136. if (barno == test->test_reg_bar)
  137. size = 0x4;
  138. for (j = 0; j < size; j += 4)
  139. pci_endpoint_test_bar_writel(test, barno, j, 0xA0A0A0A0);
  140. for (j = 0; j < size; j += 4) {
  141. val = pci_endpoint_test_bar_readl(test, barno, j);
  142. if (val != 0xA0A0A0A0)
  143. return false;
  144. }
  145. return true;
  146. }
  147. static bool pci_endpoint_test_legacy_irq(struct pci_endpoint_test *test)
  148. {
  149. u32 val;
  150. pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
  151. COMMAND_RAISE_LEGACY_IRQ);
  152. val = wait_for_completion_timeout(&test->irq_raised,
  153. msecs_to_jiffies(1000));
  154. if (!val)
  155. return false;
  156. return true;
  157. }
  158. static bool pci_endpoint_test_msi_irq(struct pci_endpoint_test *test,
  159. u8 msi_num)
  160. {
  161. u32 val;
  162. struct pci_dev *pdev = test->pdev;
  163. pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
  164. msi_num << MSI_NUMBER_SHIFT |
  165. COMMAND_RAISE_MSI_IRQ);
  166. val = wait_for_completion_timeout(&test->irq_raised,
  167. msecs_to_jiffies(1000));
  168. if (!val)
  169. return false;
  170. if (test->last_irq - pdev->irq == msi_num - 1)
  171. return true;
  172. return false;
  173. }
  174. static bool pci_endpoint_test_copy(struct pci_endpoint_test *test, size_t size)
  175. {
  176. bool ret = false;
  177. void *src_addr;
  178. void *dst_addr;
  179. dma_addr_t src_phys_addr;
  180. dma_addr_t dst_phys_addr;
  181. struct pci_dev *pdev = test->pdev;
  182. struct device *dev = &pdev->dev;
  183. void *orig_src_addr;
  184. dma_addr_t orig_src_phys_addr;
  185. void *orig_dst_addr;
  186. dma_addr_t orig_dst_phys_addr;
  187. size_t offset;
  188. size_t alignment = test->alignment;
  189. u32 src_crc32;
  190. u32 dst_crc32;
  191. if (size > SIZE_MAX - alignment)
  192. goto err;
  193. orig_src_addr = dma_alloc_coherent(dev, size + alignment,
  194. &orig_src_phys_addr, GFP_KERNEL);
  195. if (!orig_src_addr) {
  196. dev_err(dev, "failed to allocate source buffer\n");
  197. ret = false;
  198. goto err;
  199. }
  200. if (alignment && !IS_ALIGNED(orig_src_phys_addr, alignment)) {
  201. src_phys_addr = PTR_ALIGN(orig_src_phys_addr, alignment);
  202. offset = src_phys_addr - orig_src_phys_addr;
  203. src_addr = orig_src_addr + offset;
  204. } else {
  205. src_phys_addr = orig_src_phys_addr;
  206. src_addr = orig_src_addr;
  207. }
  208. pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_SRC_ADDR,
  209. lower_32_bits(src_phys_addr));
  210. pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_SRC_ADDR,
  211. upper_32_bits(src_phys_addr));
  212. get_random_bytes(src_addr, size);
  213. src_crc32 = crc32_le(~0, src_addr, size);
  214. orig_dst_addr = dma_alloc_coherent(dev, size + alignment,
  215. &orig_dst_phys_addr, GFP_KERNEL);
  216. if (!orig_dst_addr) {
  217. dev_err(dev, "failed to allocate destination address\n");
  218. ret = false;
  219. goto err_orig_src_addr;
  220. }
  221. if (alignment && !IS_ALIGNED(orig_dst_phys_addr, alignment)) {
  222. dst_phys_addr = PTR_ALIGN(orig_dst_phys_addr, alignment);
  223. offset = dst_phys_addr - orig_dst_phys_addr;
  224. dst_addr = orig_dst_addr + offset;
  225. } else {
  226. dst_phys_addr = orig_dst_phys_addr;
  227. dst_addr = orig_dst_addr;
  228. }
  229. pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_DST_ADDR,
  230. lower_32_bits(dst_phys_addr));
  231. pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_DST_ADDR,
  232. upper_32_bits(dst_phys_addr));
  233. pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE,
  234. size);
  235. pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
  236. 1 << MSI_NUMBER_SHIFT | COMMAND_COPY);
  237. wait_for_completion(&test->irq_raised);
  238. dst_crc32 = crc32_le(~0, dst_addr, size);
  239. if (dst_crc32 == src_crc32)
  240. ret = true;
  241. dma_free_coherent(dev, size + alignment, orig_dst_addr,
  242. orig_dst_phys_addr);
  243. err_orig_src_addr:
  244. dma_free_coherent(dev, size + alignment, orig_src_addr,
  245. orig_src_phys_addr);
  246. err:
  247. return ret;
  248. }
  249. static bool pci_endpoint_test_write(struct pci_endpoint_test *test, size_t size)
  250. {
  251. bool ret = false;
  252. u32 reg;
  253. void *addr;
  254. dma_addr_t phys_addr;
  255. struct pci_dev *pdev = test->pdev;
  256. struct device *dev = &pdev->dev;
  257. void *orig_addr;
  258. dma_addr_t orig_phys_addr;
  259. size_t offset;
  260. size_t alignment = test->alignment;
  261. u32 crc32;
  262. if (size > SIZE_MAX - alignment)
  263. goto err;
  264. orig_addr = dma_alloc_coherent(dev, size + alignment, &orig_phys_addr,
  265. GFP_KERNEL);
  266. if (!orig_addr) {
  267. dev_err(dev, "failed to allocate address\n");
  268. ret = false;
  269. goto err;
  270. }
  271. if (alignment && !IS_ALIGNED(orig_phys_addr, alignment)) {
  272. phys_addr = PTR_ALIGN(orig_phys_addr, alignment);
  273. offset = phys_addr - orig_phys_addr;
  274. addr = orig_addr + offset;
  275. } else {
  276. phys_addr = orig_phys_addr;
  277. addr = orig_addr;
  278. }
  279. get_random_bytes(addr, size);
  280. crc32 = crc32_le(~0, addr, size);
  281. pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_CHECKSUM,
  282. crc32);
  283. pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_SRC_ADDR,
  284. lower_32_bits(phys_addr));
  285. pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_SRC_ADDR,
  286. upper_32_bits(phys_addr));
  287. pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE, size);
  288. pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
  289. 1 << MSI_NUMBER_SHIFT | COMMAND_READ);
  290. wait_for_completion(&test->irq_raised);
  291. reg = pci_endpoint_test_readl(test, PCI_ENDPOINT_TEST_STATUS);
  292. if (reg & STATUS_READ_SUCCESS)
  293. ret = true;
  294. dma_free_coherent(dev, size + alignment, orig_addr, orig_phys_addr);
  295. err:
  296. return ret;
  297. }
  298. static bool pci_endpoint_test_read(struct pci_endpoint_test *test, size_t size)
  299. {
  300. bool ret = false;
  301. void *addr;
  302. dma_addr_t phys_addr;
  303. struct pci_dev *pdev = test->pdev;
  304. struct device *dev = &pdev->dev;
  305. void *orig_addr;
  306. dma_addr_t orig_phys_addr;
  307. size_t offset;
  308. size_t alignment = test->alignment;
  309. u32 crc32;
  310. if (size > SIZE_MAX - alignment)
  311. goto err;
  312. orig_addr = dma_alloc_coherent(dev, size + alignment, &orig_phys_addr,
  313. GFP_KERNEL);
  314. if (!orig_addr) {
  315. dev_err(dev, "failed to allocate destination address\n");
  316. ret = false;
  317. goto err;
  318. }
  319. if (alignment && !IS_ALIGNED(orig_phys_addr, alignment)) {
  320. phys_addr = PTR_ALIGN(orig_phys_addr, alignment);
  321. offset = phys_addr - orig_phys_addr;
  322. addr = orig_addr + offset;
  323. } else {
  324. phys_addr = orig_phys_addr;
  325. addr = orig_addr;
  326. }
  327. pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_DST_ADDR,
  328. lower_32_bits(phys_addr));
  329. pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_DST_ADDR,
  330. upper_32_bits(phys_addr));
  331. pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE, size);
  332. pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
  333. 1 << MSI_NUMBER_SHIFT | COMMAND_WRITE);
  334. wait_for_completion(&test->irq_raised);
  335. crc32 = crc32_le(~0, addr, size);
  336. if (crc32 == pci_endpoint_test_readl(test, PCI_ENDPOINT_TEST_CHECKSUM))
  337. ret = true;
  338. dma_free_coherent(dev, size + alignment, orig_addr, orig_phys_addr);
  339. err:
  340. return ret;
  341. }
  342. static long pci_endpoint_test_ioctl(struct file *file, unsigned int cmd,
  343. unsigned long arg)
  344. {
  345. int ret = -EINVAL;
  346. enum pci_barno bar;
  347. struct pci_endpoint_test *test = to_endpoint_test(file->private_data);
  348. mutex_lock(&test->mutex);
  349. switch (cmd) {
  350. case PCITEST_BAR:
  351. bar = arg;
  352. if (bar < 0 || bar > 5)
  353. goto ret;
  354. ret = pci_endpoint_test_bar(test, bar);
  355. break;
  356. case PCITEST_LEGACY_IRQ:
  357. ret = pci_endpoint_test_legacy_irq(test);
  358. break;
  359. case PCITEST_MSI:
  360. ret = pci_endpoint_test_msi_irq(test, arg);
  361. break;
  362. case PCITEST_WRITE:
  363. ret = pci_endpoint_test_write(test, arg);
  364. break;
  365. case PCITEST_READ:
  366. ret = pci_endpoint_test_read(test, arg);
  367. break;
  368. case PCITEST_COPY:
  369. ret = pci_endpoint_test_copy(test, arg);
  370. break;
  371. }
  372. ret:
  373. mutex_unlock(&test->mutex);
  374. return ret;
  375. }
  376. static const struct file_operations pci_endpoint_test_fops = {
  377. .owner = THIS_MODULE,
  378. .unlocked_ioctl = pci_endpoint_test_ioctl,
  379. };
  380. static int pci_endpoint_test_probe(struct pci_dev *pdev,
  381. const struct pci_device_id *ent)
  382. {
  383. int i;
  384. int err;
  385. int irq = 0;
  386. int id;
  387. char name[20];
  388. enum pci_barno bar;
  389. void __iomem *base;
  390. struct device *dev = &pdev->dev;
  391. struct pci_endpoint_test *test;
  392. struct pci_endpoint_test_data *data;
  393. enum pci_barno test_reg_bar = BAR_0;
  394. struct miscdevice *misc_device;
  395. if (pci_is_bridge(pdev))
  396. return -ENODEV;
  397. test = devm_kzalloc(dev, sizeof(*test), GFP_KERNEL);
  398. if (!test)
  399. return -ENOMEM;
  400. test->test_reg_bar = 0;
  401. test->alignment = 0;
  402. test->pdev = pdev;
  403. data = (struct pci_endpoint_test_data *)ent->driver_data;
  404. if (data) {
  405. test_reg_bar = data->test_reg_bar;
  406. test->alignment = data->alignment;
  407. no_msi = data->no_msi;
  408. }
  409. init_completion(&test->irq_raised);
  410. mutex_init(&test->mutex);
  411. err = pci_enable_device(pdev);
  412. if (err) {
  413. dev_err(dev, "Cannot enable PCI device\n");
  414. return err;
  415. }
  416. err = pci_request_regions(pdev, DRV_MODULE_NAME);
  417. if (err) {
  418. dev_err(dev, "Cannot obtain PCI resources\n");
  419. goto err_disable_pdev;
  420. }
  421. pci_set_master(pdev);
  422. if (!no_msi) {
  423. irq = pci_alloc_irq_vectors(pdev, 1, 32, PCI_IRQ_MSI);
  424. if (irq < 0)
  425. dev_err(dev, "failed to get MSI interrupts\n");
  426. test->num_irqs = irq;
  427. }
  428. err = devm_request_irq(dev, pdev->irq, pci_endpoint_test_irqhandler,
  429. IRQF_SHARED, DRV_MODULE_NAME, test);
  430. if (err) {
  431. dev_err(dev, "failed to request IRQ %d\n", pdev->irq);
  432. goto err_disable_msi;
  433. }
  434. for (i = 1; i < irq; i++) {
  435. err = devm_request_irq(dev, pdev->irq + i,
  436. pci_endpoint_test_irqhandler,
  437. IRQF_SHARED, DRV_MODULE_NAME, test);
  438. if (err)
  439. dev_err(dev, "failed to request IRQ %d for MSI %d\n",
  440. pdev->irq + i, i + 1);
  441. }
  442. for (bar = BAR_0; bar <= BAR_5; bar++) {
  443. base = pci_ioremap_bar(pdev, bar);
  444. if (!base) {
  445. dev_err(dev, "failed to read BAR%d\n", bar);
  446. WARN_ON(bar == test_reg_bar);
  447. }
  448. test->bar[bar] = base;
  449. }
  450. test->base = test->bar[test_reg_bar];
  451. if (!test->base) {
  452. err = -ENOMEM;
  453. dev_err(dev, "Cannot perform PCI test without BAR%d\n",
  454. test_reg_bar);
  455. goto err_iounmap;
  456. }
  457. pci_set_drvdata(pdev, test);
  458. id = ida_simple_get(&pci_endpoint_test_ida, 0, 0, GFP_KERNEL);
  459. if (id < 0) {
  460. err = id;
  461. dev_err(dev, "unable to get id\n");
  462. goto err_iounmap;
  463. }
  464. snprintf(name, sizeof(name), DRV_MODULE_NAME ".%d", id);
  465. misc_device = &test->miscdev;
  466. misc_device->minor = MISC_DYNAMIC_MINOR;
  467. misc_device->name = kstrdup(name, GFP_KERNEL);
  468. if (!misc_device->name) {
  469. err = -ENOMEM;
  470. goto err_ida_remove;
  471. }
  472. misc_device->fops = &pci_endpoint_test_fops,
  473. err = misc_register(misc_device);
  474. if (err) {
  475. dev_err(dev, "failed to register device\n");
  476. goto err_kfree_name;
  477. }
  478. return 0;
  479. err_kfree_name:
  480. kfree(misc_device->name);
  481. err_ida_remove:
  482. ida_simple_remove(&pci_endpoint_test_ida, id);
  483. err_iounmap:
  484. for (bar = BAR_0; bar <= BAR_5; bar++) {
  485. if (test->bar[bar])
  486. pci_iounmap(pdev, test->bar[bar]);
  487. }
  488. for (i = 0; i < irq; i++)
  489. devm_free_irq(dev, pdev->irq + i, test);
  490. err_disable_msi:
  491. pci_disable_msi(pdev);
  492. pci_release_regions(pdev);
  493. err_disable_pdev:
  494. pci_disable_device(pdev);
  495. return err;
  496. }
  497. static void pci_endpoint_test_remove(struct pci_dev *pdev)
  498. {
  499. int id;
  500. int i;
  501. enum pci_barno bar;
  502. struct pci_endpoint_test *test = pci_get_drvdata(pdev);
  503. struct miscdevice *misc_device = &test->miscdev;
  504. if (sscanf(misc_device->name, DRV_MODULE_NAME ".%d", &id) != 1)
  505. return;
  506. if (id < 0)
  507. return;
  508. misc_deregister(&test->miscdev);
  509. kfree(misc_device->name);
  510. ida_simple_remove(&pci_endpoint_test_ida, id);
  511. for (bar = BAR_0; bar <= BAR_5; bar++) {
  512. if (test->bar[bar])
  513. pci_iounmap(pdev, test->bar[bar]);
  514. }
  515. for (i = 0; i < test->num_irqs; i++)
  516. devm_free_irq(&pdev->dev, pdev->irq + i, test);
  517. pci_disable_msi(pdev);
  518. pci_release_regions(pdev);
  519. pci_disable_device(pdev);
  520. }
  521. static const struct pci_device_id pci_endpoint_test_tbl[] = {
  522. { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA74x) },
  523. { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA72x) },
  524. { }
  525. };
  526. MODULE_DEVICE_TABLE(pci, pci_endpoint_test_tbl);
  527. static struct pci_driver pci_endpoint_test_driver = {
  528. .name = DRV_MODULE_NAME,
  529. .id_table = pci_endpoint_test_tbl,
  530. .probe = pci_endpoint_test_probe,
  531. .remove = pci_endpoint_test_remove,
  532. };
  533. module_pci_driver(pci_endpoint_test_driver);
  534. MODULE_DESCRIPTION("PCI ENDPOINT TEST HOST DRIVER");
  535. MODULE_AUTHOR("Kishon Vijay Abraham I <kishon@ti.com>");
  536. MODULE_LICENSE("GPL v2");