intel-pt.c 64 KB

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  1. /*
  2. * intel_pt.c: Intel Processor Trace support
  3. * Copyright (c) 2013-2015, Intel Corporation.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms and conditions of the GNU General Public License,
  7. * version 2, as published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. */
  15. #include <inttypes.h>
  16. #include <stdio.h>
  17. #include <stdbool.h>
  18. #include <errno.h>
  19. #include <linux/kernel.h>
  20. #include <linux/types.h>
  21. #include "../perf.h"
  22. #include "session.h"
  23. #include "machine.h"
  24. #include "memswap.h"
  25. #include "sort.h"
  26. #include "tool.h"
  27. #include "event.h"
  28. #include "evlist.h"
  29. #include "evsel.h"
  30. #include "map.h"
  31. #include "color.h"
  32. #include "util.h"
  33. #include "thread.h"
  34. #include "thread-stack.h"
  35. #include "symbol.h"
  36. #include "callchain.h"
  37. #include "dso.h"
  38. #include "debug.h"
  39. #include "auxtrace.h"
  40. #include "tsc.h"
  41. #include "intel-pt.h"
  42. #include "config.h"
  43. #include "intel-pt-decoder/intel-pt-log.h"
  44. #include "intel-pt-decoder/intel-pt-decoder.h"
  45. #include "intel-pt-decoder/intel-pt-insn-decoder.h"
  46. #include "intel-pt-decoder/intel-pt-pkt-decoder.h"
  47. #define MAX_TIMESTAMP (~0ULL)
  48. struct intel_pt {
  49. struct auxtrace auxtrace;
  50. struct auxtrace_queues queues;
  51. struct auxtrace_heap heap;
  52. u32 auxtrace_type;
  53. struct perf_session *session;
  54. struct machine *machine;
  55. struct perf_evsel *switch_evsel;
  56. struct thread *unknown_thread;
  57. bool timeless_decoding;
  58. bool sampling_mode;
  59. bool snapshot_mode;
  60. bool per_cpu_mmaps;
  61. bool have_tsc;
  62. bool data_queued;
  63. bool est_tsc;
  64. bool sync_switch;
  65. bool mispred_all;
  66. int have_sched_switch;
  67. u32 pmu_type;
  68. u64 kernel_start;
  69. u64 switch_ip;
  70. u64 ptss_ip;
  71. struct perf_tsc_conversion tc;
  72. bool cap_user_time_zero;
  73. struct itrace_synth_opts synth_opts;
  74. bool sample_instructions;
  75. u64 instructions_sample_type;
  76. u64 instructions_id;
  77. bool sample_branches;
  78. u32 branches_filter;
  79. u64 branches_sample_type;
  80. u64 branches_id;
  81. bool sample_transactions;
  82. u64 transactions_sample_type;
  83. u64 transactions_id;
  84. bool sample_ptwrites;
  85. u64 ptwrites_sample_type;
  86. u64 ptwrites_id;
  87. bool sample_pwr_events;
  88. u64 pwr_events_sample_type;
  89. u64 mwait_id;
  90. u64 pwre_id;
  91. u64 exstop_id;
  92. u64 pwrx_id;
  93. u64 cbr_id;
  94. u64 tsc_bit;
  95. u64 mtc_bit;
  96. u64 mtc_freq_bits;
  97. u32 tsc_ctc_ratio_n;
  98. u32 tsc_ctc_ratio_d;
  99. u64 cyc_bit;
  100. u64 noretcomp_bit;
  101. unsigned max_non_turbo_ratio;
  102. unsigned cbr2khz;
  103. unsigned long num_events;
  104. char *filter;
  105. struct addr_filters filts;
  106. };
  107. enum switch_state {
  108. INTEL_PT_SS_NOT_TRACING,
  109. INTEL_PT_SS_UNKNOWN,
  110. INTEL_PT_SS_TRACING,
  111. INTEL_PT_SS_EXPECTING_SWITCH_EVENT,
  112. INTEL_PT_SS_EXPECTING_SWITCH_IP,
  113. };
  114. struct intel_pt_queue {
  115. struct intel_pt *pt;
  116. unsigned int queue_nr;
  117. struct auxtrace_buffer *buffer;
  118. struct auxtrace_buffer *old_buffer;
  119. void *decoder;
  120. const struct intel_pt_state *state;
  121. struct ip_callchain *chain;
  122. struct branch_stack *last_branch;
  123. struct branch_stack *last_branch_rb;
  124. size_t last_branch_pos;
  125. union perf_event *event_buf;
  126. bool on_heap;
  127. bool stop;
  128. bool step_through_buffers;
  129. bool use_buffer_pid_tid;
  130. bool sync_switch;
  131. pid_t pid, tid;
  132. int cpu;
  133. int switch_state;
  134. pid_t next_tid;
  135. struct thread *thread;
  136. bool exclude_kernel;
  137. bool have_sample;
  138. u64 time;
  139. u64 timestamp;
  140. u32 flags;
  141. u16 insn_len;
  142. u64 last_insn_cnt;
  143. char insn[INTEL_PT_INSN_BUF_SZ];
  144. };
  145. static void intel_pt_dump(struct intel_pt *pt __maybe_unused,
  146. unsigned char *buf, size_t len)
  147. {
  148. struct intel_pt_pkt packet;
  149. size_t pos = 0;
  150. int ret, pkt_len, i;
  151. char desc[INTEL_PT_PKT_DESC_MAX];
  152. const char *color = PERF_COLOR_BLUE;
  153. color_fprintf(stdout, color,
  154. ". ... Intel Processor Trace data: size %zu bytes\n",
  155. len);
  156. while (len) {
  157. ret = intel_pt_get_packet(buf, len, &packet);
  158. if (ret > 0)
  159. pkt_len = ret;
  160. else
  161. pkt_len = 1;
  162. printf(".");
  163. color_fprintf(stdout, color, " %08x: ", pos);
  164. for (i = 0; i < pkt_len; i++)
  165. color_fprintf(stdout, color, " %02x", buf[i]);
  166. for (; i < 16; i++)
  167. color_fprintf(stdout, color, " ");
  168. if (ret > 0) {
  169. ret = intel_pt_pkt_desc(&packet, desc,
  170. INTEL_PT_PKT_DESC_MAX);
  171. if (ret > 0)
  172. color_fprintf(stdout, color, " %s\n", desc);
  173. } else {
  174. color_fprintf(stdout, color, " Bad packet!\n");
  175. }
  176. pos += pkt_len;
  177. buf += pkt_len;
  178. len -= pkt_len;
  179. }
  180. }
  181. static void intel_pt_dump_event(struct intel_pt *pt, unsigned char *buf,
  182. size_t len)
  183. {
  184. printf(".\n");
  185. intel_pt_dump(pt, buf, len);
  186. }
  187. static int intel_pt_do_fix_overlap(struct intel_pt *pt, struct auxtrace_buffer *a,
  188. struct auxtrace_buffer *b)
  189. {
  190. bool consecutive = false;
  191. void *start;
  192. start = intel_pt_find_overlap(a->data, a->size, b->data, b->size,
  193. pt->have_tsc, &consecutive);
  194. if (!start)
  195. return -EINVAL;
  196. b->use_size = b->data + b->size - start;
  197. b->use_data = start;
  198. if (b->use_size && consecutive)
  199. b->consecutive = true;
  200. return 0;
  201. }
  202. /* This function assumes data is processed sequentially only */
  203. static int intel_pt_get_trace(struct intel_pt_buffer *b, void *data)
  204. {
  205. struct intel_pt_queue *ptq = data;
  206. struct auxtrace_buffer *buffer = ptq->buffer;
  207. struct auxtrace_buffer *old_buffer = ptq->old_buffer;
  208. struct auxtrace_queue *queue;
  209. bool might_overlap;
  210. if (ptq->stop) {
  211. b->len = 0;
  212. return 0;
  213. }
  214. queue = &ptq->pt->queues.queue_array[ptq->queue_nr];
  215. buffer = auxtrace_buffer__next(queue, buffer);
  216. if (!buffer) {
  217. if (old_buffer)
  218. auxtrace_buffer__drop_data(old_buffer);
  219. b->len = 0;
  220. return 0;
  221. }
  222. ptq->buffer = buffer;
  223. if (!buffer->data) {
  224. int fd = perf_data__fd(ptq->pt->session->data);
  225. buffer->data = auxtrace_buffer__get_data(buffer, fd);
  226. if (!buffer->data)
  227. return -ENOMEM;
  228. }
  229. might_overlap = ptq->pt->snapshot_mode || ptq->pt->sampling_mode;
  230. if (might_overlap && !buffer->consecutive && old_buffer &&
  231. intel_pt_do_fix_overlap(ptq->pt, old_buffer, buffer))
  232. return -ENOMEM;
  233. if (buffer->use_data) {
  234. b->len = buffer->use_size;
  235. b->buf = buffer->use_data;
  236. } else {
  237. b->len = buffer->size;
  238. b->buf = buffer->data;
  239. }
  240. b->ref_timestamp = buffer->reference;
  241. if (!old_buffer || (might_overlap && !buffer->consecutive)) {
  242. b->consecutive = false;
  243. b->trace_nr = buffer->buffer_nr + 1;
  244. } else {
  245. b->consecutive = true;
  246. }
  247. if (ptq->step_through_buffers)
  248. ptq->stop = true;
  249. if (b->len) {
  250. if (old_buffer)
  251. auxtrace_buffer__drop_data(old_buffer);
  252. ptq->old_buffer = buffer;
  253. } else {
  254. auxtrace_buffer__drop_data(buffer);
  255. return intel_pt_get_trace(b, data);
  256. }
  257. return 0;
  258. }
  259. struct intel_pt_cache_entry {
  260. struct auxtrace_cache_entry entry;
  261. u64 insn_cnt;
  262. u64 byte_cnt;
  263. enum intel_pt_insn_op op;
  264. enum intel_pt_insn_branch branch;
  265. int length;
  266. int32_t rel;
  267. char insn[INTEL_PT_INSN_BUF_SZ];
  268. };
  269. static int intel_pt_config_div(const char *var, const char *value, void *data)
  270. {
  271. int *d = data;
  272. long val;
  273. if (!strcmp(var, "intel-pt.cache-divisor")) {
  274. val = strtol(value, NULL, 0);
  275. if (val > 0 && val <= INT_MAX)
  276. *d = val;
  277. }
  278. return 0;
  279. }
  280. static int intel_pt_cache_divisor(void)
  281. {
  282. static int d;
  283. if (d)
  284. return d;
  285. perf_config(intel_pt_config_div, &d);
  286. if (!d)
  287. d = 64;
  288. return d;
  289. }
  290. static unsigned int intel_pt_cache_size(struct dso *dso,
  291. struct machine *machine)
  292. {
  293. off_t size;
  294. size = dso__data_size(dso, machine);
  295. size /= intel_pt_cache_divisor();
  296. if (size < 1000)
  297. return 10;
  298. if (size > (1 << 21))
  299. return 21;
  300. return 32 - __builtin_clz(size);
  301. }
  302. static struct auxtrace_cache *intel_pt_cache(struct dso *dso,
  303. struct machine *machine)
  304. {
  305. struct auxtrace_cache *c;
  306. unsigned int bits;
  307. if (dso->auxtrace_cache)
  308. return dso->auxtrace_cache;
  309. bits = intel_pt_cache_size(dso, machine);
  310. /* Ignoring cache creation failure */
  311. c = auxtrace_cache__new(bits, sizeof(struct intel_pt_cache_entry), 200);
  312. dso->auxtrace_cache = c;
  313. return c;
  314. }
  315. static int intel_pt_cache_add(struct dso *dso, struct machine *machine,
  316. u64 offset, u64 insn_cnt, u64 byte_cnt,
  317. struct intel_pt_insn *intel_pt_insn)
  318. {
  319. struct auxtrace_cache *c = intel_pt_cache(dso, machine);
  320. struct intel_pt_cache_entry *e;
  321. int err;
  322. if (!c)
  323. return -ENOMEM;
  324. e = auxtrace_cache__alloc_entry(c);
  325. if (!e)
  326. return -ENOMEM;
  327. e->insn_cnt = insn_cnt;
  328. e->byte_cnt = byte_cnt;
  329. e->op = intel_pt_insn->op;
  330. e->branch = intel_pt_insn->branch;
  331. e->length = intel_pt_insn->length;
  332. e->rel = intel_pt_insn->rel;
  333. memcpy(e->insn, intel_pt_insn->buf, INTEL_PT_INSN_BUF_SZ);
  334. err = auxtrace_cache__add(c, offset, &e->entry);
  335. if (err)
  336. auxtrace_cache__free_entry(c, e);
  337. return err;
  338. }
  339. static struct intel_pt_cache_entry *
  340. intel_pt_cache_lookup(struct dso *dso, struct machine *machine, u64 offset)
  341. {
  342. struct auxtrace_cache *c = intel_pt_cache(dso, machine);
  343. if (!c)
  344. return NULL;
  345. return auxtrace_cache__lookup(dso->auxtrace_cache, offset);
  346. }
  347. static int intel_pt_walk_next_insn(struct intel_pt_insn *intel_pt_insn,
  348. uint64_t *insn_cnt_ptr, uint64_t *ip,
  349. uint64_t to_ip, uint64_t max_insn_cnt,
  350. void *data)
  351. {
  352. struct intel_pt_queue *ptq = data;
  353. struct machine *machine = ptq->pt->machine;
  354. struct thread *thread;
  355. struct addr_location al;
  356. unsigned char buf[INTEL_PT_INSN_BUF_SZ];
  357. ssize_t len;
  358. int x86_64;
  359. u8 cpumode;
  360. u64 offset, start_offset, start_ip;
  361. u64 insn_cnt = 0;
  362. bool one_map = true;
  363. intel_pt_insn->length = 0;
  364. if (to_ip && *ip == to_ip)
  365. goto out_no_cache;
  366. if (*ip >= ptq->pt->kernel_start)
  367. cpumode = PERF_RECORD_MISC_KERNEL;
  368. else
  369. cpumode = PERF_RECORD_MISC_USER;
  370. thread = ptq->thread;
  371. if (!thread) {
  372. if (cpumode != PERF_RECORD_MISC_KERNEL)
  373. return -EINVAL;
  374. thread = ptq->pt->unknown_thread;
  375. }
  376. while (1) {
  377. if (!thread__find_map(thread, cpumode, *ip, &al) || !al.map->dso)
  378. return -EINVAL;
  379. if (al.map->dso->data.status == DSO_DATA_STATUS_ERROR &&
  380. dso__data_status_seen(al.map->dso,
  381. DSO_DATA_STATUS_SEEN_ITRACE))
  382. return -ENOENT;
  383. offset = al.map->map_ip(al.map, *ip);
  384. if (!to_ip && one_map) {
  385. struct intel_pt_cache_entry *e;
  386. e = intel_pt_cache_lookup(al.map->dso, machine, offset);
  387. if (e &&
  388. (!max_insn_cnt || e->insn_cnt <= max_insn_cnt)) {
  389. *insn_cnt_ptr = e->insn_cnt;
  390. *ip += e->byte_cnt;
  391. intel_pt_insn->op = e->op;
  392. intel_pt_insn->branch = e->branch;
  393. intel_pt_insn->length = e->length;
  394. intel_pt_insn->rel = e->rel;
  395. memcpy(intel_pt_insn->buf, e->insn,
  396. INTEL_PT_INSN_BUF_SZ);
  397. intel_pt_log_insn_no_data(intel_pt_insn, *ip);
  398. return 0;
  399. }
  400. }
  401. start_offset = offset;
  402. start_ip = *ip;
  403. /* Load maps to ensure dso->is_64_bit has been updated */
  404. map__load(al.map);
  405. x86_64 = al.map->dso->is_64_bit;
  406. while (1) {
  407. len = dso__data_read_offset(al.map->dso, machine,
  408. offset, buf,
  409. INTEL_PT_INSN_BUF_SZ);
  410. if (len <= 0)
  411. return -EINVAL;
  412. if (intel_pt_get_insn(buf, len, x86_64, intel_pt_insn))
  413. return -EINVAL;
  414. intel_pt_log_insn(intel_pt_insn, *ip);
  415. insn_cnt += 1;
  416. if (intel_pt_insn->branch != INTEL_PT_BR_NO_BRANCH)
  417. goto out;
  418. if (max_insn_cnt && insn_cnt >= max_insn_cnt)
  419. goto out_no_cache;
  420. *ip += intel_pt_insn->length;
  421. if (to_ip && *ip == to_ip)
  422. goto out_no_cache;
  423. if (*ip >= al.map->end)
  424. break;
  425. offset += intel_pt_insn->length;
  426. }
  427. one_map = false;
  428. }
  429. out:
  430. *insn_cnt_ptr = insn_cnt;
  431. if (!one_map)
  432. goto out_no_cache;
  433. /*
  434. * Didn't lookup in the 'to_ip' case, so do it now to prevent duplicate
  435. * entries.
  436. */
  437. if (to_ip) {
  438. struct intel_pt_cache_entry *e;
  439. e = intel_pt_cache_lookup(al.map->dso, machine, start_offset);
  440. if (e)
  441. return 0;
  442. }
  443. /* Ignore cache errors */
  444. intel_pt_cache_add(al.map->dso, machine, start_offset, insn_cnt,
  445. *ip - start_ip, intel_pt_insn);
  446. return 0;
  447. out_no_cache:
  448. *insn_cnt_ptr = insn_cnt;
  449. return 0;
  450. }
  451. static bool intel_pt_match_pgd_ip(struct intel_pt *pt, uint64_t ip,
  452. uint64_t offset, const char *filename)
  453. {
  454. struct addr_filter *filt;
  455. bool have_filter = false;
  456. bool hit_tracestop = false;
  457. bool hit_filter = false;
  458. list_for_each_entry(filt, &pt->filts.head, list) {
  459. if (filt->start)
  460. have_filter = true;
  461. if ((filename && !filt->filename) ||
  462. (!filename && filt->filename) ||
  463. (filename && strcmp(filename, filt->filename)))
  464. continue;
  465. if (!(offset >= filt->addr && offset < filt->addr + filt->size))
  466. continue;
  467. intel_pt_log("TIP.PGD ip %#"PRIx64" offset %#"PRIx64" in %s hit filter: %s offset %#"PRIx64" size %#"PRIx64"\n",
  468. ip, offset, filename ? filename : "[kernel]",
  469. filt->start ? "filter" : "stop",
  470. filt->addr, filt->size);
  471. if (filt->start)
  472. hit_filter = true;
  473. else
  474. hit_tracestop = true;
  475. }
  476. if (!hit_tracestop && !hit_filter)
  477. intel_pt_log("TIP.PGD ip %#"PRIx64" offset %#"PRIx64" in %s is not in a filter region\n",
  478. ip, offset, filename ? filename : "[kernel]");
  479. return hit_tracestop || (have_filter && !hit_filter);
  480. }
  481. static int __intel_pt_pgd_ip(uint64_t ip, void *data)
  482. {
  483. struct intel_pt_queue *ptq = data;
  484. struct thread *thread;
  485. struct addr_location al;
  486. u8 cpumode;
  487. u64 offset;
  488. if (ip >= ptq->pt->kernel_start)
  489. return intel_pt_match_pgd_ip(ptq->pt, ip, ip, NULL);
  490. cpumode = PERF_RECORD_MISC_USER;
  491. thread = ptq->thread;
  492. if (!thread)
  493. return -EINVAL;
  494. if (!thread__find_map(thread, cpumode, ip, &al) || !al.map->dso)
  495. return -EINVAL;
  496. offset = al.map->map_ip(al.map, ip);
  497. return intel_pt_match_pgd_ip(ptq->pt, ip, offset,
  498. al.map->dso->long_name);
  499. }
  500. static bool intel_pt_pgd_ip(uint64_t ip, void *data)
  501. {
  502. return __intel_pt_pgd_ip(ip, data) > 0;
  503. }
  504. static bool intel_pt_get_config(struct intel_pt *pt,
  505. struct perf_event_attr *attr, u64 *config)
  506. {
  507. if (attr->type == pt->pmu_type) {
  508. if (config)
  509. *config = attr->config;
  510. return true;
  511. }
  512. return false;
  513. }
  514. static bool intel_pt_exclude_kernel(struct intel_pt *pt)
  515. {
  516. struct perf_evsel *evsel;
  517. evlist__for_each_entry(pt->session->evlist, evsel) {
  518. if (intel_pt_get_config(pt, &evsel->attr, NULL) &&
  519. !evsel->attr.exclude_kernel)
  520. return false;
  521. }
  522. return true;
  523. }
  524. static bool intel_pt_return_compression(struct intel_pt *pt)
  525. {
  526. struct perf_evsel *evsel;
  527. u64 config;
  528. if (!pt->noretcomp_bit)
  529. return true;
  530. evlist__for_each_entry(pt->session->evlist, evsel) {
  531. if (intel_pt_get_config(pt, &evsel->attr, &config) &&
  532. (config & pt->noretcomp_bit))
  533. return false;
  534. }
  535. return true;
  536. }
  537. static bool intel_pt_branch_enable(struct intel_pt *pt)
  538. {
  539. struct perf_evsel *evsel;
  540. u64 config;
  541. evlist__for_each_entry(pt->session->evlist, evsel) {
  542. if (intel_pt_get_config(pt, &evsel->attr, &config) &&
  543. (config & 1) && !(config & 0x2000))
  544. return false;
  545. }
  546. return true;
  547. }
  548. static unsigned int intel_pt_mtc_period(struct intel_pt *pt)
  549. {
  550. struct perf_evsel *evsel;
  551. unsigned int shift;
  552. u64 config;
  553. if (!pt->mtc_freq_bits)
  554. return 0;
  555. for (shift = 0, config = pt->mtc_freq_bits; !(config & 1); shift++)
  556. config >>= 1;
  557. evlist__for_each_entry(pt->session->evlist, evsel) {
  558. if (intel_pt_get_config(pt, &evsel->attr, &config))
  559. return (config & pt->mtc_freq_bits) >> shift;
  560. }
  561. return 0;
  562. }
  563. static bool intel_pt_timeless_decoding(struct intel_pt *pt)
  564. {
  565. struct perf_evsel *evsel;
  566. bool timeless_decoding = true;
  567. u64 config;
  568. if (!pt->tsc_bit || !pt->cap_user_time_zero)
  569. return true;
  570. evlist__for_each_entry(pt->session->evlist, evsel) {
  571. if (!(evsel->attr.sample_type & PERF_SAMPLE_TIME))
  572. return true;
  573. if (intel_pt_get_config(pt, &evsel->attr, &config)) {
  574. if (config & pt->tsc_bit)
  575. timeless_decoding = false;
  576. else
  577. return true;
  578. }
  579. }
  580. return timeless_decoding;
  581. }
  582. static bool intel_pt_tracing_kernel(struct intel_pt *pt)
  583. {
  584. struct perf_evsel *evsel;
  585. evlist__for_each_entry(pt->session->evlist, evsel) {
  586. if (intel_pt_get_config(pt, &evsel->attr, NULL) &&
  587. !evsel->attr.exclude_kernel)
  588. return true;
  589. }
  590. return false;
  591. }
  592. static bool intel_pt_have_tsc(struct intel_pt *pt)
  593. {
  594. struct perf_evsel *evsel;
  595. bool have_tsc = false;
  596. u64 config;
  597. if (!pt->tsc_bit)
  598. return false;
  599. evlist__for_each_entry(pt->session->evlist, evsel) {
  600. if (intel_pt_get_config(pt, &evsel->attr, &config)) {
  601. if (config & pt->tsc_bit)
  602. have_tsc = true;
  603. else
  604. return false;
  605. }
  606. }
  607. return have_tsc;
  608. }
  609. static u64 intel_pt_ns_to_ticks(const struct intel_pt *pt, u64 ns)
  610. {
  611. u64 quot, rem;
  612. quot = ns / pt->tc.time_mult;
  613. rem = ns % pt->tc.time_mult;
  614. return (quot << pt->tc.time_shift) + (rem << pt->tc.time_shift) /
  615. pt->tc.time_mult;
  616. }
  617. static struct intel_pt_queue *intel_pt_alloc_queue(struct intel_pt *pt,
  618. unsigned int queue_nr)
  619. {
  620. struct intel_pt_params params = { .get_trace = 0, };
  621. struct perf_env *env = pt->machine->env;
  622. struct intel_pt_queue *ptq;
  623. ptq = zalloc(sizeof(struct intel_pt_queue));
  624. if (!ptq)
  625. return NULL;
  626. if (pt->synth_opts.callchain) {
  627. size_t sz = sizeof(struct ip_callchain);
  628. sz += pt->synth_opts.callchain_sz * sizeof(u64);
  629. ptq->chain = zalloc(sz);
  630. if (!ptq->chain)
  631. goto out_free;
  632. }
  633. if (pt->synth_opts.last_branch) {
  634. size_t sz = sizeof(struct branch_stack);
  635. sz += pt->synth_opts.last_branch_sz *
  636. sizeof(struct branch_entry);
  637. ptq->last_branch = zalloc(sz);
  638. if (!ptq->last_branch)
  639. goto out_free;
  640. ptq->last_branch_rb = zalloc(sz);
  641. if (!ptq->last_branch_rb)
  642. goto out_free;
  643. }
  644. ptq->event_buf = malloc(PERF_SAMPLE_MAX_SIZE);
  645. if (!ptq->event_buf)
  646. goto out_free;
  647. ptq->pt = pt;
  648. ptq->queue_nr = queue_nr;
  649. ptq->exclude_kernel = intel_pt_exclude_kernel(pt);
  650. ptq->pid = -1;
  651. ptq->tid = -1;
  652. ptq->cpu = -1;
  653. ptq->next_tid = -1;
  654. params.get_trace = intel_pt_get_trace;
  655. params.walk_insn = intel_pt_walk_next_insn;
  656. params.data = ptq;
  657. params.return_compression = intel_pt_return_compression(pt);
  658. params.branch_enable = intel_pt_branch_enable(pt);
  659. params.max_non_turbo_ratio = pt->max_non_turbo_ratio;
  660. params.mtc_period = intel_pt_mtc_period(pt);
  661. params.tsc_ctc_ratio_n = pt->tsc_ctc_ratio_n;
  662. params.tsc_ctc_ratio_d = pt->tsc_ctc_ratio_d;
  663. if (pt->filts.cnt > 0)
  664. params.pgd_ip = intel_pt_pgd_ip;
  665. if (pt->synth_opts.instructions) {
  666. if (pt->synth_opts.period) {
  667. switch (pt->synth_opts.period_type) {
  668. case PERF_ITRACE_PERIOD_INSTRUCTIONS:
  669. params.period_type =
  670. INTEL_PT_PERIOD_INSTRUCTIONS;
  671. params.period = pt->synth_opts.period;
  672. break;
  673. case PERF_ITRACE_PERIOD_TICKS:
  674. params.period_type = INTEL_PT_PERIOD_TICKS;
  675. params.period = pt->synth_opts.period;
  676. break;
  677. case PERF_ITRACE_PERIOD_NANOSECS:
  678. params.period_type = INTEL_PT_PERIOD_TICKS;
  679. params.period = intel_pt_ns_to_ticks(pt,
  680. pt->synth_opts.period);
  681. break;
  682. default:
  683. break;
  684. }
  685. }
  686. if (!params.period) {
  687. params.period_type = INTEL_PT_PERIOD_INSTRUCTIONS;
  688. params.period = 1;
  689. }
  690. }
  691. if (env->cpuid && !strncmp(env->cpuid, "GenuineIntel,6,92,", 18))
  692. params.flags |= INTEL_PT_FUP_WITH_NLIP;
  693. ptq->decoder = intel_pt_decoder_new(&params);
  694. if (!ptq->decoder)
  695. goto out_free;
  696. return ptq;
  697. out_free:
  698. zfree(&ptq->event_buf);
  699. zfree(&ptq->last_branch);
  700. zfree(&ptq->last_branch_rb);
  701. zfree(&ptq->chain);
  702. free(ptq);
  703. return NULL;
  704. }
  705. static void intel_pt_free_queue(void *priv)
  706. {
  707. struct intel_pt_queue *ptq = priv;
  708. if (!ptq)
  709. return;
  710. thread__zput(ptq->thread);
  711. intel_pt_decoder_free(ptq->decoder);
  712. zfree(&ptq->event_buf);
  713. zfree(&ptq->last_branch);
  714. zfree(&ptq->last_branch_rb);
  715. zfree(&ptq->chain);
  716. free(ptq);
  717. }
  718. static void intel_pt_set_pid_tid_cpu(struct intel_pt *pt,
  719. struct auxtrace_queue *queue)
  720. {
  721. struct intel_pt_queue *ptq = queue->priv;
  722. if (queue->tid == -1 || pt->have_sched_switch) {
  723. ptq->tid = machine__get_current_tid(pt->machine, ptq->cpu);
  724. thread__zput(ptq->thread);
  725. }
  726. if (!ptq->thread && ptq->tid != -1)
  727. ptq->thread = machine__find_thread(pt->machine, -1, ptq->tid);
  728. if (ptq->thread) {
  729. ptq->pid = ptq->thread->pid_;
  730. if (queue->cpu == -1)
  731. ptq->cpu = ptq->thread->cpu;
  732. }
  733. }
  734. static void intel_pt_sample_flags(struct intel_pt_queue *ptq)
  735. {
  736. if (ptq->state->flags & INTEL_PT_ABORT_TX) {
  737. ptq->flags = PERF_IP_FLAG_BRANCH | PERF_IP_FLAG_TX_ABORT;
  738. } else if (ptq->state->flags & INTEL_PT_ASYNC) {
  739. if (ptq->state->to_ip)
  740. ptq->flags = PERF_IP_FLAG_BRANCH | PERF_IP_FLAG_CALL |
  741. PERF_IP_FLAG_ASYNC |
  742. PERF_IP_FLAG_INTERRUPT;
  743. else
  744. ptq->flags = PERF_IP_FLAG_BRANCH |
  745. PERF_IP_FLAG_TRACE_END;
  746. ptq->insn_len = 0;
  747. } else {
  748. if (ptq->state->from_ip)
  749. ptq->flags = intel_pt_insn_type(ptq->state->insn_op);
  750. else
  751. ptq->flags = PERF_IP_FLAG_BRANCH |
  752. PERF_IP_FLAG_TRACE_BEGIN;
  753. if (ptq->state->flags & INTEL_PT_IN_TX)
  754. ptq->flags |= PERF_IP_FLAG_IN_TX;
  755. ptq->insn_len = ptq->state->insn_len;
  756. memcpy(ptq->insn, ptq->state->insn, INTEL_PT_INSN_BUF_SZ);
  757. }
  758. }
  759. static int intel_pt_setup_queue(struct intel_pt *pt,
  760. struct auxtrace_queue *queue,
  761. unsigned int queue_nr)
  762. {
  763. struct intel_pt_queue *ptq = queue->priv;
  764. if (list_empty(&queue->head))
  765. return 0;
  766. if (!ptq) {
  767. ptq = intel_pt_alloc_queue(pt, queue_nr);
  768. if (!ptq)
  769. return -ENOMEM;
  770. queue->priv = ptq;
  771. if (queue->cpu != -1)
  772. ptq->cpu = queue->cpu;
  773. ptq->tid = queue->tid;
  774. if (pt->sampling_mode && !pt->snapshot_mode &&
  775. pt->timeless_decoding)
  776. ptq->step_through_buffers = true;
  777. ptq->sync_switch = pt->sync_switch;
  778. }
  779. if (!ptq->on_heap &&
  780. (!ptq->sync_switch ||
  781. ptq->switch_state != INTEL_PT_SS_EXPECTING_SWITCH_EVENT)) {
  782. const struct intel_pt_state *state;
  783. int ret;
  784. if (pt->timeless_decoding)
  785. return 0;
  786. intel_pt_log("queue %u getting timestamp\n", queue_nr);
  787. intel_pt_log("queue %u decoding cpu %d pid %d tid %d\n",
  788. queue_nr, ptq->cpu, ptq->pid, ptq->tid);
  789. while (1) {
  790. state = intel_pt_decode(ptq->decoder);
  791. if (state->err) {
  792. if (state->err == INTEL_PT_ERR_NODATA) {
  793. intel_pt_log("queue %u has no timestamp\n",
  794. queue_nr);
  795. return 0;
  796. }
  797. continue;
  798. }
  799. if (state->timestamp)
  800. break;
  801. }
  802. ptq->timestamp = state->timestamp;
  803. intel_pt_log("queue %u timestamp 0x%" PRIx64 "\n",
  804. queue_nr, ptq->timestamp);
  805. ptq->state = state;
  806. ptq->have_sample = true;
  807. intel_pt_sample_flags(ptq);
  808. ret = auxtrace_heap__add(&pt->heap, queue_nr, ptq->timestamp);
  809. if (ret)
  810. return ret;
  811. ptq->on_heap = true;
  812. }
  813. return 0;
  814. }
  815. static int intel_pt_setup_queues(struct intel_pt *pt)
  816. {
  817. unsigned int i;
  818. int ret;
  819. for (i = 0; i < pt->queues.nr_queues; i++) {
  820. ret = intel_pt_setup_queue(pt, &pt->queues.queue_array[i], i);
  821. if (ret)
  822. return ret;
  823. }
  824. return 0;
  825. }
  826. static inline void intel_pt_copy_last_branch_rb(struct intel_pt_queue *ptq)
  827. {
  828. struct branch_stack *bs_src = ptq->last_branch_rb;
  829. struct branch_stack *bs_dst = ptq->last_branch;
  830. size_t nr = 0;
  831. bs_dst->nr = bs_src->nr;
  832. if (!bs_src->nr)
  833. return;
  834. nr = ptq->pt->synth_opts.last_branch_sz - ptq->last_branch_pos;
  835. memcpy(&bs_dst->entries[0],
  836. &bs_src->entries[ptq->last_branch_pos],
  837. sizeof(struct branch_entry) * nr);
  838. if (bs_src->nr >= ptq->pt->synth_opts.last_branch_sz) {
  839. memcpy(&bs_dst->entries[nr],
  840. &bs_src->entries[0],
  841. sizeof(struct branch_entry) * ptq->last_branch_pos);
  842. }
  843. }
  844. static inline void intel_pt_reset_last_branch_rb(struct intel_pt_queue *ptq)
  845. {
  846. ptq->last_branch_pos = 0;
  847. ptq->last_branch_rb->nr = 0;
  848. }
  849. static void intel_pt_update_last_branch_rb(struct intel_pt_queue *ptq)
  850. {
  851. const struct intel_pt_state *state = ptq->state;
  852. struct branch_stack *bs = ptq->last_branch_rb;
  853. struct branch_entry *be;
  854. if (!ptq->last_branch_pos)
  855. ptq->last_branch_pos = ptq->pt->synth_opts.last_branch_sz;
  856. ptq->last_branch_pos -= 1;
  857. be = &bs->entries[ptq->last_branch_pos];
  858. be->from = state->from_ip;
  859. be->to = state->to_ip;
  860. be->flags.abort = !!(state->flags & INTEL_PT_ABORT_TX);
  861. be->flags.in_tx = !!(state->flags & INTEL_PT_IN_TX);
  862. /* No support for mispredict */
  863. be->flags.mispred = ptq->pt->mispred_all;
  864. if (bs->nr < ptq->pt->synth_opts.last_branch_sz)
  865. bs->nr += 1;
  866. }
  867. static inline bool intel_pt_skip_event(struct intel_pt *pt)
  868. {
  869. return pt->synth_opts.initial_skip &&
  870. pt->num_events++ < pt->synth_opts.initial_skip;
  871. }
  872. static void intel_pt_prep_b_sample(struct intel_pt *pt,
  873. struct intel_pt_queue *ptq,
  874. union perf_event *event,
  875. struct perf_sample *sample)
  876. {
  877. event->sample.header.type = PERF_RECORD_SAMPLE;
  878. event->sample.header.misc = PERF_RECORD_MISC_USER;
  879. event->sample.header.size = sizeof(struct perf_event_header);
  880. if (!pt->timeless_decoding)
  881. sample->time = tsc_to_perf_time(ptq->timestamp, &pt->tc);
  882. sample->cpumode = PERF_RECORD_MISC_USER;
  883. sample->ip = ptq->state->from_ip;
  884. sample->pid = ptq->pid;
  885. sample->tid = ptq->tid;
  886. sample->addr = ptq->state->to_ip;
  887. sample->period = 1;
  888. sample->cpu = ptq->cpu;
  889. sample->flags = ptq->flags;
  890. sample->insn_len = ptq->insn_len;
  891. memcpy(sample->insn, ptq->insn, INTEL_PT_INSN_BUF_SZ);
  892. }
  893. static int intel_pt_inject_event(union perf_event *event,
  894. struct perf_sample *sample, u64 type)
  895. {
  896. event->header.size = perf_event__sample_event_size(sample, type, 0);
  897. return perf_event__synthesize_sample(event, type, 0, sample);
  898. }
  899. static inline int intel_pt_opt_inject(struct intel_pt *pt,
  900. union perf_event *event,
  901. struct perf_sample *sample, u64 type)
  902. {
  903. if (!pt->synth_opts.inject)
  904. return 0;
  905. return intel_pt_inject_event(event, sample, type);
  906. }
  907. static int intel_pt_deliver_synth_b_event(struct intel_pt *pt,
  908. union perf_event *event,
  909. struct perf_sample *sample, u64 type)
  910. {
  911. int ret;
  912. ret = intel_pt_opt_inject(pt, event, sample, type);
  913. if (ret)
  914. return ret;
  915. ret = perf_session__deliver_synth_event(pt->session, event, sample);
  916. if (ret)
  917. pr_err("Intel PT: failed to deliver event, error %d\n", ret);
  918. return ret;
  919. }
  920. static int intel_pt_synth_branch_sample(struct intel_pt_queue *ptq)
  921. {
  922. struct intel_pt *pt = ptq->pt;
  923. union perf_event *event = ptq->event_buf;
  924. struct perf_sample sample = { .ip = 0, };
  925. struct dummy_branch_stack {
  926. u64 nr;
  927. struct branch_entry entries;
  928. } dummy_bs;
  929. if (pt->branches_filter && !(pt->branches_filter & ptq->flags))
  930. return 0;
  931. if (intel_pt_skip_event(pt))
  932. return 0;
  933. intel_pt_prep_b_sample(pt, ptq, event, &sample);
  934. sample.id = ptq->pt->branches_id;
  935. sample.stream_id = ptq->pt->branches_id;
  936. /*
  937. * perf report cannot handle events without a branch stack when using
  938. * SORT_MODE__BRANCH so make a dummy one.
  939. */
  940. if (pt->synth_opts.last_branch && sort__mode == SORT_MODE__BRANCH) {
  941. dummy_bs = (struct dummy_branch_stack){
  942. .nr = 1,
  943. .entries = {
  944. .from = sample.ip,
  945. .to = sample.addr,
  946. },
  947. };
  948. sample.branch_stack = (struct branch_stack *)&dummy_bs;
  949. }
  950. return intel_pt_deliver_synth_b_event(pt, event, &sample,
  951. pt->branches_sample_type);
  952. }
  953. static void intel_pt_prep_sample(struct intel_pt *pt,
  954. struct intel_pt_queue *ptq,
  955. union perf_event *event,
  956. struct perf_sample *sample)
  957. {
  958. intel_pt_prep_b_sample(pt, ptq, event, sample);
  959. if (pt->synth_opts.callchain) {
  960. thread_stack__sample(ptq->thread, ptq->chain,
  961. pt->synth_opts.callchain_sz, sample->ip);
  962. sample->callchain = ptq->chain;
  963. }
  964. if (pt->synth_opts.last_branch) {
  965. intel_pt_copy_last_branch_rb(ptq);
  966. sample->branch_stack = ptq->last_branch;
  967. }
  968. }
  969. static inline int intel_pt_deliver_synth_event(struct intel_pt *pt,
  970. struct intel_pt_queue *ptq,
  971. union perf_event *event,
  972. struct perf_sample *sample,
  973. u64 type)
  974. {
  975. int ret;
  976. ret = intel_pt_deliver_synth_b_event(pt, event, sample, type);
  977. if (pt->synth_opts.last_branch)
  978. intel_pt_reset_last_branch_rb(ptq);
  979. return ret;
  980. }
  981. static int intel_pt_synth_instruction_sample(struct intel_pt_queue *ptq)
  982. {
  983. struct intel_pt *pt = ptq->pt;
  984. union perf_event *event = ptq->event_buf;
  985. struct perf_sample sample = { .ip = 0, };
  986. if (intel_pt_skip_event(pt))
  987. return 0;
  988. intel_pt_prep_sample(pt, ptq, event, &sample);
  989. sample.id = ptq->pt->instructions_id;
  990. sample.stream_id = ptq->pt->instructions_id;
  991. sample.period = ptq->state->tot_insn_cnt - ptq->last_insn_cnt;
  992. ptq->last_insn_cnt = ptq->state->tot_insn_cnt;
  993. return intel_pt_deliver_synth_event(pt, ptq, event, &sample,
  994. pt->instructions_sample_type);
  995. }
  996. static int intel_pt_synth_transaction_sample(struct intel_pt_queue *ptq)
  997. {
  998. struct intel_pt *pt = ptq->pt;
  999. union perf_event *event = ptq->event_buf;
  1000. struct perf_sample sample = { .ip = 0, };
  1001. if (intel_pt_skip_event(pt))
  1002. return 0;
  1003. intel_pt_prep_sample(pt, ptq, event, &sample);
  1004. sample.id = ptq->pt->transactions_id;
  1005. sample.stream_id = ptq->pt->transactions_id;
  1006. return intel_pt_deliver_synth_event(pt, ptq, event, &sample,
  1007. pt->transactions_sample_type);
  1008. }
  1009. static void intel_pt_prep_p_sample(struct intel_pt *pt,
  1010. struct intel_pt_queue *ptq,
  1011. union perf_event *event,
  1012. struct perf_sample *sample)
  1013. {
  1014. intel_pt_prep_sample(pt, ptq, event, sample);
  1015. /*
  1016. * Zero IP is used to mean "trace start" but that is not the case for
  1017. * power or PTWRITE events with no IP, so clear the flags.
  1018. */
  1019. if (!sample->ip)
  1020. sample->flags = 0;
  1021. }
  1022. static int intel_pt_synth_ptwrite_sample(struct intel_pt_queue *ptq)
  1023. {
  1024. struct intel_pt *pt = ptq->pt;
  1025. union perf_event *event = ptq->event_buf;
  1026. struct perf_sample sample = { .ip = 0, };
  1027. struct perf_synth_intel_ptwrite raw;
  1028. if (intel_pt_skip_event(pt))
  1029. return 0;
  1030. intel_pt_prep_p_sample(pt, ptq, event, &sample);
  1031. sample.id = ptq->pt->ptwrites_id;
  1032. sample.stream_id = ptq->pt->ptwrites_id;
  1033. raw.flags = 0;
  1034. raw.ip = !!(ptq->state->flags & INTEL_PT_FUP_IP);
  1035. raw.payload = cpu_to_le64(ptq->state->ptw_payload);
  1036. sample.raw_size = perf_synth__raw_size(raw);
  1037. sample.raw_data = perf_synth__raw_data(&raw);
  1038. return intel_pt_deliver_synth_event(pt, ptq, event, &sample,
  1039. pt->ptwrites_sample_type);
  1040. }
  1041. static int intel_pt_synth_cbr_sample(struct intel_pt_queue *ptq)
  1042. {
  1043. struct intel_pt *pt = ptq->pt;
  1044. union perf_event *event = ptq->event_buf;
  1045. struct perf_sample sample = { .ip = 0, };
  1046. struct perf_synth_intel_cbr raw;
  1047. u32 flags;
  1048. if (intel_pt_skip_event(pt))
  1049. return 0;
  1050. intel_pt_prep_p_sample(pt, ptq, event, &sample);
  1051. sample.id = ptq->pt->cbr_id;
  1052. sample.stream_id = ptq->pt->cbr_id;
  1053. flags = (u16)ptq->state->cbr_payload | (pt->max_non_turbo_ratio << 16);
  1054. raw.flags = cpu_to_le32(flags);
  1055. raw.freq = cpu_to_le32(raw.cbr * pt->cbr2khz);
  1056. raw.reserved3 = 0;
  1057. sample.raw_size = perf_synth__raw_size(raw);
  1058. sample.raw_data = perf_synth__raw_data(&raw);
  1059. return intel_pt_deliver_synth_event(pt, ptq, event, &sample,
  1060. pt->pwr_events_sample_type);
  1061. }
  1062. static int intel_pt_synth_mwait_sample(struct intel_pt_queue *ptq)
  1063. {
  1064. struct intel_pt *pt = ptq->pt;
  1065. union perf_event *event = ptq->event_buf;
  1066. struct perf_sample sample = { .ip = 0, };
  1067. struct perf_synth_intel_mwait raw;
  1068. if (intel_pt_skip_event(pt))
  1069. return 0;
  1070. intel_pt_prep_p_sample(pt, ptq, event, &sample);
  1071. sample.id = ptq->pt->mwait_id;
  1072. sample.stream_id = ptq->pt->mwait_id;
  1073. raw.reserved = 0;
  1074. raw.payload = cpu_to_le64(ptq->state->mwait_payload);
  1075. sample.raw_size = perf_synth__raw_size(raw);
  1076. sample.raw_data = perf_synth__raw_data(&raw);
  1077. return intel_pt_deliver_synth_event(pt, ptq, event, &sample,
  1078. pt->pwr_events_sample_type);
  1079. }
  1080. static int intel_pt_synth_pwre_sample(struct intel_pt_queue *ptq)
  1081. {
  1082. struct intel_pt *pt = ptq->pt;
  1083. union perf_event *event = ptq->event_buf;
  1084. struct perf_sample sample = { .ip = 0, };
  1085. struct perf_synth_intel_pwre raw;
  1086. if (intel_pt_skip_event(pt))
  1087. return 0;
  1088. intel_pt_prep_p_sample(pt, ptq, event, &sample);
  1089. sample.id = ptq->pt->pwre_id;
  1090. sample.stream_id = ptq->pt->pwre_id;
  1091. raw.reserved = 0;
  1092. raw.payload = cpu_to_le64(ptq->state->pwre_payload);
  1093. sample.raw_size = perf_synth__raw_size(raw);
  1094. sample.raw_data = perf_synth__raw_data(&raw);
  1095. return intel_pt_deliver_synth_event(pt, ptq, event, &sample,
  1096. pt->pwr_events_sample_type);
  1097. }
  1098. static int intel_pt_synth_exstop_sample(struct intel_pt_queue *ptq)
  1099. {
  1100. struct intel_pt *pt = ptq->pt;
  1101. union perf_event *event = ptq->event_buf;
  1102. struct perf_sample sample = { .ip = 0, };
  1103. struct perf_synth_intel_exstop raw;
  1104. if (intel_pt_skip_event(pt))
  1105. return 0;
  1106. intel_pt_prep_p_sample(pt, ptq, event, &sample);
  1107. sample.id = ptq->pt->exstop_id;
  1108. sample.stream_id = ptq->pt->exstop_id;
  1109. raw.flags = 0;
  1110. raw.ip = !!(ptq->state->flags & INTEL_PT_FUP_IP);
  1111. sample.raw_size = perf_synth__raw_size(raw);
  1112. sample.raw_data = perf_synth__raw_data(&raw);
  1113. return intel_pt_deliver_synth_event(pt, ptq, event, &sample,
  1114. pt->pwr_events_sample_type);
  1115. }
  1116. static int intel_pt_synth_pwrx_sample(struct intel_pt_queue *ptq)
  1117. {
  1118. struct intel_pt *pt = ptq->pt;
  1119. union perf_event *event = ptq->event_buf;
  1120. struct perf_sample sample = { .ip = 0, };
  1121. struct perf_synth_intel_pwrx raw;
  1122. if (intel_pt_skip_event(pt))
  1123. return 0;
  1124. intel_pt_prep_p_sample(pt, ptq, event, &sample);
  1125. sample.id = ptq->pt->pwrx_id;
  1126. sample.stream_id = ptq->pt->pwrx_id;
  1127. raw.reserved = 0;
  1128. raw.payload = cpu_to_le64(ptq->state->pwrx_payload);
  1129. sample.raw_size = perf_synth__raw_size(raw);
  1130. sample.raw_data = perf_synth__raw_data(&raw);
  1131. return intel_pt_deliver_synth_event(pt, ptq, event, &sample,
  1132. pt->pwr_events_sample_type);
  1133. }
  1134. static int intel_pt_synth_error(struct intel_pt *pt, int code, int cpu,
  1135. pid_t pid, pid_t tid, u64 ip)
  1136. {
  1137. union perf_event event;
  1138. char msg[MAX_AUXTRACE_ERROR_MSG];
  1139. int err;
  1140. intel_pt__strerror(code, msg, MAX_AUXTRACE_ERROR_MSG);
  1141. auxtrace_synth_error(&event.auxtrace_error, PERF_AUXTRACE_ERROR_ITRACE,
  1142. code, cpu, pid, tid, ip, msg);
  1143. err = perf_session__deliver_synth_event(pt->session, &event, NULL);
  1144. if (err)
  1145. pr_err("Intel Processor Trace: failed to deliver error event, error %d\n",
  1146. err);
  1147. return err;
  1148. }
  1149. static int intel_pt_next_tid(struct intel_pt *pt, struct intel_pt_queue *ptq)
  1150. {
  1151. struct auxtrace_queue *queue;
  1152. pid_t tid = ptq->next_tid;
  1153. int err;
  1154. if (tid == -1)
  1155. return 0;
  1156. intel_pt_log("switch: cpu %d tid %d\n", ptq->cpu, tid);
  1157. err = machine__set_current_tid(pt->machine, ptq->cpu, -1, tid);
  1158. queue = &pt->queues.queue_array[ptq->queue_nr];
  1159. intel_pt_set_pid_tid_cpu(pt, queue);
  1160. ptq->next_tid = -1;
  1161. return err;
  1162. }
  1163. static inline bool intel_pt_is_switch_ip(struct intel_pt_queue *ptq, u64 ip)
  1164. {
  1165. struct intel_pt *pt = ptq->pt;
  1166. return ip == pt->switch_ip &&
  1167. (ptq->flags & PERF_IP_FLAG_BRANCH) &&
  1168. !(ptq->flags & (PERF_IP_FLAG_CONDITIONAL | PERF_IP_FLAG_ASYNC |
  1169. PERF_IP_FLAG_INTERRUPT | PERF_IP_FLAG_TX_ABORT));
  1170. }
  1171. #define INTEL_PT_PWR_EVT (INTEL_PT_MWAIT_OP | INTEL_PT_PWR_ENTRY | \
  1172. INTEL_PT_EX_STOP | INTEL_PT_PWR_EXIT | \
  1173. INTEL_PT_CBR_CHG)
  1174. static int intel_pt_sample(struct intel_pt_queue *ptq)
  1175. {
  1176. const struct intel_pt_state *state = ptq->state;
  1177. struct intel_pt *pt = ptq->pt;
  1178. int err;
  1179. if (!ptq->have_sample)
  1180. return 0;
  1181. ptq->have_sample = false;
  1182. if (pt->sample_pwr_events && (state->type & INTEL_PT_PWR_EVT)) {
  1183. if (state->type & INTEL_PT_CBR_CHG) {
  1184. err = intel_pt_synth_cbr_sample(ptq);
  1185. if (err)
  1186. return err;
  1187. }
  1188. if (state->type & INTEL_PT_MWAIT_OP) {
  1189. err = intel_pt_synth_mwait_sample(ptq);
  1190. if (err)
  1191. return err;
  1192. }
  1193. if (state->type & INTEL_PT_PWR_ENTRY) {
  1194. err = intel_pt_synth_pwre_sample(ptq);
  1195. if (err)
  1196. return err;
  1197. }
  1198. if (state->type & INTEL_PT_EX_STOP) {
  1199. err = intel_pt_synth_exstop_sample(ptq);
  1200. if (err)
  1201. return err;
  1202. }
  1203. if (state->type & INTEL_PT_PWR_EXIT) {
  1204. err = intel_pt_synth_pwrx_sample(ptq);
  1205. if (err)
  1206. return err;
  1207. }
  1208. }
  1209. if (pt->sample_instructions && (state->type & INTEL_PT_INSTRUCTION)) {
  1210. err = intel_pt_synth_instruction_sample(ptq);
  1211. if (err)
  1212. return err;
  1213. }
  1214. if (pt->sample_transactions && (state->type & INTEL_PT_TRANSACTION)) {
  1215. err = intel_pt_synth_transaction_sample(ptq);
  1216. if (err)
  1217. return err;
  1218. }
  1219. if (pt->sample_ptwrites && (state->type & INTEL_PT_PTW)) {
  1220. err = intel_pt_synth_ptwrite_sample(ptq);
  1221. if (err)
  1222. return err;
  1223. }
  1224. if (!(state->type & INTEL_PT_BRANCH))
  1225. return 0;
  1226. if (pt->synth_opts.callchain || pt->synth_opts.thread_stack)
  1227. thread_stack__event(ptq->thread, ptq->flags, state->from_ip,
  1228. state->to_ip, ptq->insn_len,
  1229. state->trace_nr);
  1230. else
  1231. thread_stack__set_trace_nr(ptq->thread, state->trace_nr);
  1232. if (pt->sample_branches) {
  1233. err = intel_pt_synth_branch_sample(ptq);
  1234. if (err)
  1235. return err;
  1236. }
  1237. if (pt->synth_opts.last_branch)
  1238. intel_pt_update_last_branch_rb(ptq);
  1239. if (!ptq->sync_switch)
  1240. return 0;
  1241. if (intel_pt_is_switch_ip(ptq, state->to_ip)) {
  1242. switch (ptq->switch_state) {
  1243. case INTEL_PT_SS_NOT_TRACING:
  1244. case INTEL_PT_SS_UNKNOWN:
  1245. case INTEL_PT_SS_EXPECTING_SWITCH_IP:
  1246. err = intel_pt_next_tid(pt, ptq);
  1247. if (err)
  1248. return err;
  1249. ptq->switch_state = INTEL_PT_SS_TRACING;
  1250. break;
  1251. default:
  1252. ptq->switch_state = INTEL_PT_SS_EXPECTING_SWITCH_EVENT;
  1253. return 1;
  1254. }
  1255. } else if (!state->to_ip) {
  1256. ptq->switch_state = INTEL_PT_SS_NOT_TRACING;
  1257. } else if (ptq->switch_state == INTEL_PT_SS_NOT_TRACING) {
  1258. ptq->switch_state = INTEL_PT_SS_UNKNOWN;
  1259. } else if (ptq->switch_state == INTEL_PT_SS_UNKNOWN &&
  1260. state->to_ip == pt->ptss_ip &&
  1261. (ptq->flags & PERF_IP_FLAG_CALL)) {
  1262. ptq->switch_state = INTEL_PT_SS_TRACING;
  1263. }
  1264. return 0;
  1265. }
  1266. static u64 intel_pt_switch_ip(struct intel_pt *pt, u64 *ptss_ip)
  1267. {
  1268. struct machine *machine = pt->machine;
  1269. struct map *map;
  1270. struct symbol *sym, *start;
  1271. u64 ip, switch_ip = 0;
  1272. const char *ptss;
  1273. if (ptss_ip)
  1274. *ptss_ip = 0;
  1275. map = machine__kernel_map(machine);
  1276. if (!map)
  1277. return 0;
  1278. if (map__load(map))
  1279. return 0;
  1280. start = dso__first_symbol(map->dso);
  1281. for (sym = start; sym; sym = dso__next_symbol(sym)) {
  1282. if (sym->binding == STB_GLOBAL &&
  1283. !strcmp(sym->name, "__switch_to")) {
  1284. ip = map->unmap_ip(map, sym->start);
  1285. if (ip >= map->start && ip < map->end) {
  1286. switch_ip = ip;
  1287. break;
  1288. }
  1289. }
  1290. }
  1291. if (!switch_ip || !ptss_ip)
  1292. return 0;
  1293. if (pt->have_sched_switch == 1)
  1294. ptss = "perf_trace_sched_switch";
  1295. else
  1296. ptss = "__perf_event_task_sched_out";
  1297. for (sym = start; sym; sym = dso__next_symbol(sym)) {
  1298. if (!strcmp(sym->name, ptss)) {
  1299. ip = map->unmap_ip(map, sym->start);
  1300. if (ip >= map->start && ip < map->end) {
  1301. *ptss_ip = ip;
  1302. break;
  1303. }
  1304. }
  1305. }
  1306. return switch_ip;
  1307. }
  1308. static void intel_pt_enable_sync_switch(struct intel_pt *pt)
  1309. {
  1310. unsigned int i;
  1311. pt->sync_switch = true;
  1312. for (i = 0; i < pt->queues.nr_queues; i++) {
  1313. struct auxtrace_queue *queue = &pt->queues.queue_array[i];
  1314. struct intel_pt_queue *ptq = queue->priv;
  1315. if (ptq)
  1316. ptq->sync_switch = true;
  1317. }
  1318. }
  1319. static int intel_pt_run_decoder(struct intel_pt_queue *ptq, u64 *timestamp)
  1320. {
  1321. const struct intel_pt_state *state = ptq->state;
  1322. struct intel_pt *pt = ptq->pt;
  1323. int err;
  1324. if (!pt->kernel_start) {
  1325. pt->kernel_start = machine__kernel_start(pt->machine);
  1326. if (pt->per_cpu_mmaps &&
  1327. (pt->have_sched_switch == 1 || pt->have_sched_switch == 3) &&
  1328. !pt->timeless_decoding && intel_pt_tracing_kernel(pt) &&
  1329. !pt->sampling_mode) {
  1330. pt->switch_ip = intel_pt_switch_ip(pt, &pt->ptss_ip);
  1331. if (pt->switch_ip) {
  1332. intel_pt_log("switch_ip: %"PRIx64" ptss_ip: %"PRIx64"\n",
  1333. pt->switch_ip, pt->ptss_ip);
  1334. intel_pt_enable_sync_switch(pt);
  1335. }
  1336. }
  1337. }
  1338. intel_pt_log("queue %u decoding cpu %d pid %d tid %d\n",
  1339. ptq->queue_nr, ptq->cpu, ptq->pid, ptq->tid);
  1340. while (1) {
  1341. err = intel_pt_sample(ptq);
  1342. if (err)
  1343. return err;
  1344. state = intel_pt_decode(ptq->decoder);
  1345. if (state->err) {
  1346. if (state->err == INTEL_PT_ERR_NODATA)
  1347. return 1;
  1348. if (ptq->sync_switch &&
  1349. state->from_ip >= pt->kernel_start) {
  1350. ptq->sync_switch = false;
  1351. intel_pt_next_tid(pt, ptq);
  1352. }
  1353. if (pt->synth_opts.errors) {
  1354. err = intel_pt_synth_error(pt, state->err,
  1355. ptq->cpu, ptq->pid,
  1356. ptq->tid,
  1357. state->from_ip);
  1358. if (err)
  1359. return err;
  1360. }
  1361. continue;
  1362. }
  1363. ptq->state = state;
  1364. ptq->have_sample = true;
  1365. intel_pt_sample_flags(ptq);
  1366. /* Use estimated TSC upon return to user space */
  1367. if (pt->est_tsc &&
  1368. (state->from_ip >= pt->kernel_start || !state->from_ip) &&
  1369. state->to_ip && state->to_ip < pt->kernel_start) {
  1370. intel_pt_log("TSC %"PRIx64" est. TSC %"PRIx64"\n",
  1371. state->timestamp, state->est_timestamp);
  1372. ptq->timestamp = state->est_timestamp;
  1373. /* Use estimated TSC in unknown switch state */
  1374. } else if (ptq->sync_switch &&
  1375. ptq->switch_state == INTEL_PT_SS_UNKNOWN &&
  1376. intel_pt_is_switch_ip(ptq, state->to_ip) &&
  1377. ptq->next_tid == -1) {
  1378. intel_pt_log("TSC %"PRIx64" est. TSC %"PRIx64"\n",
  1379. state->timestamp, state->est_timestamp);
  1380. ptq->timestamp = state->est_timestamp;
  1381. } else if (state->timestamp > ptq->timestamp) {
  1382. ptq->timestamp = state->timestamp;
  1383. }
  1384. if (!pt->timeless_decoding && ptq->timestamp >= *timestamp) {
  1385. *timestamp = ptq->timestamp;
  1386. return 0;
  1387. }
  1388. }
  1389. return 0;
  1390. }
  1391. static inline int intel_pt_update_queues(struct intel_pt *pt)
  1392. {
  1393. if (pt->queues.new_data) {
  1394. pt->queues.new_data = false;
  1395. return intel_pt_setup_queues(pt);
  1396. }
  1397. return 0;
  1398. }
  1399. static int intel_pt_process_queues(struct intel_pt *pt, u64 timestamp)
  1400. {
  1401. unsigned int queue_nr;
  1402. u64 ts;
  1403. int ret;
  1404. while (1) {
  1405. struct auxtrace_queue *queue;
  1406. struct intel_pt_queue *ptq;
  1407. if (!pt->heap.heap_cnt)
  1408. return 0;
  1409. if (pt->heap.heap_array[0].ordinal >= timestamp)
  1410. return 0;
  1411. queue_nr = pt->heap.heap_array[0].queue_nr;
  1412. queue = &pt->queues.queue_array[queue_nr];
  1413. ptq = queue->priv;
  1414. intel_pt_log("queue %u processing 0x%" PRIx64 " to 0x%" PRIx64 "\n",
  1415. queue_nr, pt->heap.heap_array[0].ordinal,
  1416. timestamp);
  1417. auxtrace_heap__pop(&pt->heap);
  1418. if (pt->heap.heap_cnt) {
  1419. ts = pt->heap.heap_array[0].ordinal + 1;
  1420. if (ts > timestamp)
  1421. ts = timestamp;
  1422. } else {
  1423. ts = timestamp;
  1424. }
  1425. intel_pt_set_pid_tid_cpu(pt, queue);
  1426. ret = intel_pt_run_decoder(ptq, &ts);
  1427. if (ret < 0) {
  1428. auxtrace_heap__add(&pt->heap, queue_nr, ts);
  1429. return ret;
  1430. }
  1431. if (!ret) {
  1432. ret = auxtrace_heap__add(&pt->heap, queue_nr, ts);
  1433. if (ret < 0)
  1434. return ret;
  1435. } else {
  1436. ptq->on_heap = false;
  1437. }
  1438. }
  1439. return 0;
  1440. }
  1441. static int intel_pt_process_timeless_queues(struct intel_pt *pt, pid_t tid,
  1442. u64 time_)
  1443. {
  1444. struct auxtrace_queues *queues = &pt->queues;
  1445. unsigned int i;
  1446. u64 ts = 0;
  1447. for (i = 0; i < queues->nr_queues; i++) {
  1448. struct auxtrace_queue *queue = &pt->queues.queue_array[i];
  1449. struct intel_pt_queue *ptq = queue->priv;
  1450. if (ptq && (tid == -1 || ptq->tid == tid)) {
  1451. ptq->time = time_;
  1452. intel_pt_set_pid_tid_cpu(pt, queue);
  1453. intel_pt_run_decoder(ptq, &ts);
  1454. }
  1455. }
  1456. return 0;
  1457. }
  1458. static int intel_pt_lost(struct intel_pt *pt, struct perf_sample *sample)
  1459. {
  1460. return intel_pt_synth_error(pt, INTEL_PT_ERR_LOST, sample->cpu,
  1461. sample->pid, sample->tid, 0);
  1462. }
  1463. static struct intel_pt_queue *intel_pt_cpu_to_ptq(struct intel_pt *pt, int cpu)
  1464. {
  1465. unsigned i, j;
  1466. if (cpu < 0 || !pt->queues.nr_queues)
  1467. return NULL;
  1468. if ((unsigned)cpu >= pt->queues.nr_queues)
  1469. i = pt->queues.nr_queues - 1;
  1470. else
  1471. i = cpu;
  1472. if (pt->queues.queue_array[i].cpu == cpu)
  1473. return pt->queues.queue_array[i].priv;
  1474. for (j = 0; i > 0; j++) {
  1475. if (pt->queues.queue_array[--i].cpu == cpu)
  1476. return pt->queues.queue_array[i].priv;
  1477. }
  1478. for (; j < pt->queues.nr_queues; j++) {
  1479. if (pt->queues.queue_array[j].cpu == cpu)
  1480. return pt->queues.queue_array[j].priv;
  1481. }
  1482. return NULL;
  1483. }
  1484. static int intel_pt_sync_switch(struct intel_pt *pt, int cpu, pid_t tid,
  1485. u64 timestamp)
  1486. {
  1487. struct intel_pt_queue *ptq;
  1488. int err;
  1489. if (!pt->sync_switch)
  1490. return 1;
  1491. ptq = intel_pt_cpu_to_ptq(pt, cpu);
  1492. if (!ptq || !ptq->sync_switch)
  1493. return 1;
  1494. switch (ptq->switch_state) {
  1495. case INTEL_PT_SS_NOT_TRACING:
  1496. ptq->next_tid = -1;
  1497. break;
  1498. case INTEL_PT_SS_UNKNOWN:
  1499. case INTEL_PT_SS_TRACING:
  1500. ptq->next_tid = tid;
  1501. ptq->switch_state = INTEL_PT_SS_EXPECTING_SWITCH_IP;
  1502. return 0;
  1503. case INTEL_PT_SS_EXPECTING_SWITCH_EVENT:
  1504. if (!ptq->on_heap) {
  1505. ptq->timestamp = perf_time_to_tsc(timestamp,
  1506. &pt->tc);
  1507. err = auxtrace_heap__add(&pt->heap, ptq->queue_nr,
  1508. ptq->timestamp);
  1509. if (err)
  1510. return err;
  1511. ptq->on_heap = true;
  1512. }
  1513. ptq->switch_state = INTEL_PT_SS_TRACING;
  1514. break;
  1515. case INTEL_PT_SS_EXPECTING_SWITCH_IP:
  1516. ptq->next_tid = tid;
  1517. intel_pt_log("ERROR: cpu %d expecting switch ip\n", cpu);
  1518. break;
  1519. default:
  1520. break;
  1521. }
  1522. return 1;
  1523. }
  1524. static int intel_pt_process_switch(struct intel_pt *pt,
  1525. struct perf_sample *sample)
  1526. {
  1527. struct perf_evsel *evsel;
  1528. pid_t tid;
  1529. int cpu, ret;
  1530. evsel = perf_evlist__id2evsel(pt->session->evlist, sample->id);
  1531. if (evsel != pt->switch_evsel)
  1532. return 0;
  1533. tid = perf_evsel__intval(evsel, sample, "next_pid");
  1534. cpu = sample->cpu;
  1535. intel_pt_log("sched_switch: cpu %d tid %d time %"PRIu64" tsc %#"PRIx64"\n",
  1536. cpu, tid, sample->time, perf_time_to_tsc(sample->time,
  1537. &pt->tc));
  1538. ret = intel_pt_sync_switch(pt, cpu, tid, sample->time);
  1539. if (ret <= 0)
  1540. return ret;
  1541. return machine__set_current_tid(pt->machine, cpu, -1, tid);
  1542. }
  1543. static int intel_pt_context_switch(struct intel_pt *pt, union perf_event *event,
  1544. struct perf_sample *sample)
  1545. {
  1546. bool out = event->header.misc & PERF_RECORD_MISC_SWITCH_OUT;
  1547. pid_t pid, tid;
  1548. int cpu, ret;
  1549. cpu = sample->cpu;
  1550. if (pt->have_sched_switch == 3) {
  1551. if (!out)
  1552. return 0;
  1553. if (event->header.type != PERF_RECORD_SWITCH_CPU_WIDE) {
  1554. pr_err("Expecting CPU-wide context switch event\n");
  1555. return -EINVAL;
  1556. }
  1557. pid = event->context_switch.next_prev_pid;
  1558. tid = event->context_switch.next_prev_tid;
  1559. } else {
  1560. if (out)
  1561. return 0;
  1562. pid = sample->pid;
  1563. tid = sample->tid;
  1564. }
  1565. if (tid == -1) {
  1566. pr_err("context_switch event has no tid\n");
  1567. return -EINVAL;
  1568. }
  1569. intel_pt_log("context_switch: cpu %d pid %d tid %d time %"PRIu64" tsc %#"PRIx64"\n",
  1570. cpu, pid, tid, sample->time, perf_time_to_tsc(sample->time,
  1571. &pt->tc));
  1572. ret = intel_pt_sync_switch(pt, cpu, tid, sample->time);
  1573. if (ret <= 0)
  1574. return ret;
  1575. return machine__set_current_tid(pt->machine, cpu, pid, tid);
  1576. }
  1577. static int intel_pt_process_itrace_start(struct intel_pt *pt,
  1578. union perf_event *event,
  1579. struct perf_sample *sample)
  1580. {
  1581. if (!pt->per_cpu_mmaps)
  1582. return 0;
  1583. intel_pt_log("itrace_start: cpu %d pid %d tid %d time %"PRIu64" tsc %#"PRIx64"\n",
  1584. sample->cpu, event->itrace_start.pid,
  1585. event->itrace_start.tid, sample->time,
  1586. perf_time_to_tsc(sample->time, &pt->tc));
  1587. return machine__set_current_tid(pt->machine, sample->cpu,
  1588. event->itrace_start.pid,
  1589. event->itrace_start.tid);
  1590. }
  1591. static int intel_pt_process_event(struct perf_session *session,
  1592. union perf_event *event,
  1593. struct perf_sample *sample,
  1594. struct perf_tool *tool)
  1595. {
  1596. struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt,
  1597. auxtrace);
  1598. u64 timestamp;
  1599. int err = 0;
  1600. if (dump_trace)
  1601. return 0;
  1602. if (!tool->ordered_events) {
  1603. pr_err("Intel Processor Trace requires ordered events\n");
  1604. return -EINVAL;
  1605. }
  1606. if (sample->time && sample->time != (u64)-1)
  1607. timestamp = perf_time_to_tsc(sample->time, &pt->tc);
  1608. else
  1609. timestamp = 0;
  1610. if (timestamp || pt->timeless_decoding) {
  1611. err = intel_pt_update_queues(pt);
  1612. if (err)
  1613. return err;
  1614. }
  1615. if (pt->timeless_decoding) {
  1616. if (event->header.type == PERF_RECORD_EXIT) {
  1617. err = intel_pt_process_timeless_queues(pt,
  1618. event->fork.tid,
  1619. sample->time);
  1620. }
  1621. } else if (timestamp) {
  1622. err = intel_pt_process_queues(pt, timestamp);
  1623. }
  1624. if (err)
  1625. return err;
  1626. if (event->header.type == PERF_RECORD_AUX &&
  1627. (event->aux.flags & PERF_AUX_FLAG_TRUNCATED) &&
  1628. pt->synth_opts.errors) {
  1629. err = intel_pt_lost(pt, sample);
  1630. if (err)
  1631. return err;
  1632. }
  1633. if (pt->switch_evsel && event->header.type == PERF_RECORD_SAMPLE)
  1634. err = intel_pt_process_switch(pt, sample);
  1635. else if (event->header.type == PERF_RECORD_ITRACE_START)
  1636. err = intel_pt_process_itrace_start(pt, event, sample);
  1637. else if (event->header.type == PERF_RECORD_SWITCH ||
  1638. event->header.type == PERF_RECORD_SWITCH_CPU_WIDE)
  1639. err = intel_pt_context_switch(pt, event, sample);
  1640. intel_pt_log("event %s (%u): cpu %d time %"PRIu64" tsc %#"PRIx64"\n",
  1641. perf_event__name(event->header.type), event->header.type,
  1642. sample->cpu, sample->time, timestamp);
  1643. return err;
  1644. }
  1645. static int intel_pt_flush(struct perf_session *session, struct perf_tool *tool)
  1646. {
  1647. struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt,
  1648. auxtrace);
  1649. int ret;
  1650. if (dump_trace)
  1651. return 0;
  1652. if (!tool->ordered_events)
  1653. return -EINVAL;
  1654. ret = intel_pt_update_queues(pt);
  1655. if (ret < 0)
  1656. return ret;
  1657. if (pt->timeless_decoding)
  1658. return intel_pt_process_timeless_queues(pt, -1,
  1659. MAX_TIMESTAMP - 1);
  1660. return intel_pt_process_queues(pt, MAX_TIMESTAMP);
  1661. }
  1662. static void intel_pt_free_events(struct perf_session *session)
  1663. {
  1664. struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt,
  1665. auxtrace);
  1666. struct auxtrace_queues *queues = &pt->queues;
  1667. unsigned int i;
  1668. for (i = 0; i < queues->nr_queues; i++) {
  1669. intel_pt_free_queue(queues->queue_array[i].priv);
  1670. queues->queue_array[i].priv = NULL;
  1671. }
  1672. intel_pt_log_disable();
  1673. auxtrace_queues__free(queues);
  1674. }
  1675. static void intel_pt_free(struct perf_session *session)
  1676. {
  1677. struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt,
  1678. auxtrace);
  1679. auxtrace_heap__free(&pt->heap);
  1680. intel_pt_free_events(session);
  1681. session->auxtrace = NULL;
  1682. thread__put(pt->unknown_thread);
  1683. addr_filters__exit(&pt->filts);
  1684. zfree(&pt->filter);
  1685. free(pt);
  1686. }
  1687. static int intel_pt_process_auxtrace_event(struct perf_session *session,
  1688. union perf_event *event,
  1689. struct perf_tool *tool __maybe_unused)
  1690. {
  1691. struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt,
  1692. auxtrace);
  1693. if (!pt->data_queued) {
  1694. struct auxtrace_buffer *buffer;
  1695. off_t data_offset;
  1696. int fd = perf_data__fd(session->data);
  1697. int err;
  1698. if (perf_data__is_pipe(session->data)) {
  1699. data_offset = 0;
  1700. } else {
  1701. data_offset = lseek(fd, 0, SEEK_CUR);
  1702. if (data_offset == -1)
  1703. return -errno;
  1704. }
  1705. err = auxtrace_queues__add_event(&pt->queues, session, event,
  1706. data_offset, &buffer);
  1707. if (err)
  1708. return err;
  1709. /* Dump here now we have copied a piped trace out of the pipe */
  1710. if (dump_trace) {
  1711. if (auxtrace_buffer__get_data(buffer, fd)) {
  1712. intel_pt_dump_event(pt, buffer->data,
  1713. buffer->size);
  1714. auxtrace_buffer__put_data(buffer);
  1715. }
  1716. }
  1717. }
  1718. return 0;
  1719. }
  1720. struct intel_pt_synth {
  1721. struct perf_tool dummy_tool;
  1722. struct perf_session *session;
  1723. };
  1724. static int intel_pt_event_synth(struct perf_tool *tool,
  1725. union perf_event *event,
  1726. struct perf_sample *sample __maybe_unused,
  1727. struct machine *machine __maybe_unused)
  1728. {
  1729. struct intel_pt_synth *intel_pt_synth =
  1730. container_of(tool, struct intel_pt_synth, dummy_tool);
  1731. return perf_session__deliver_synth_event(intel_pt_synth->session, event,
  1732. NULL);
  1733. }
  1734. static int intel_pt_synth_event(struct perf_session *session, const char *name,
  1735. struct perf_event_attr *attr, u64 id)
  1736. {
  1737. struct intel_pt_synth intel_pt_synth;
  1738. int err;
  1739. pr_debug("Synthesizing '%s' event with id %" PRIu64 " sample type %#" PRIx64 "\n",
  1740. name, id, (u64)attr->sample_type);
  1741. memset(&intel_pt_synth, 0, sizeof(struct intel_pt_synth));
  1742. intel_pt_synth.session = session;
  1743. err = perf_event__synthesize_attr(&intel_pt_synth.dummy_tool, attr, 1,
  1744. &id, intel_pt_event_synth);
  1745. if (err)
  1746. pr_err("%s: failed to synthesize '%s' event type\n",
  1747. __func__, name);
  1748. return err;
  1749. }
  1750. static void intel_pt_set_event_name(struct perf_evlist *evlist, u64 id,
  1751. const char *name)
  1752. {
  1753. struct perf_evsel *evsel;
  1754. evlist__for_each_entry(evlist, evsel) {
  1755. if (evsel->id && evsel->id[0] == id) {
  1756. if (evsel->name)
  1757. zfree(&evsel->name);
  1758. evsel->name = strdup(name);
  1759. break;
  1760. }
  1761. }
  1762. }
  1763. static struct perf_evsel *intel_pt_evsel(struct intel_pt *pt,
  1764. struct perf_evlist *evlist)
  1765. {
  1766. struct perf_evsel *evsel;
  1767. evlist__for_each_entry(evlist, evsel) {
  1768. if (evsel->attr.type == pt->pmu_type && evsel->ids)
  1769. return evsel;
  1770. }
  1771. return NULL;
  1772. }
  1773. static int intel_pt_synth_events(struct intel_pt *pt,
  1774. struct perf_session *session)
  1775. {
  1776. struct perf_evlist *evlist = session->evlist;
  1777. struct perf_evsel *evsel = intel_pt_evsel(pt, evlist);
  1778. struct perf_event_attr attr;
  1779. u64 id;
  1780. int err;
  1781. if (!evsel) {
  1782. pr_debug("There are no selected events with Intel Processor Trace data\n");
  1783. return 0;
  1784. }
  1785. memset(&attr, 0, sizeof(struct perf_event_attr));
  1786. attr.size = sizeof(struct perf_event_attr);
  1787. attr.type = PERF_TYPE_HARDWARE;
  1788. attr.sample_type = evsel->attr.sample_type & PERF_SAMPLE_MASK;
  1789. attr.sample_type |= PERF_SAMPLE_IP | PERF_SAMPLE_TID |
  1790. PERF_SAMPLE_PERIOD;
  1791. if (pt->timeless_decoding)
  1792. attr.sample_type &= ~(u64)PERF_SAMPLE_TIME;
  1793. else
  1794. attr.sample_type |= PERF_SAMPLE_TIME;
  1795. if (!pt->per_cpu_mmaps)
  1796. attr.sample_type &= ~(u64)PERF_SAMPLE_CPU;
  1797. attr.exclude_user = evsel->attr.exclude_user;
  1798. attr.exclude_kernel = evsel->attr.exclude_kernel;
  1799. attr.exclude_hv = evsel->attr.exclude_hv;
  1800. attr.exclude_host = evsel->attr.exclude_host;
  1801. attr.exclude_guest = evsel->attr.exclude_guest;
  1802. attr.sample_id_all = evsel->attr.sample_id_all;
  1803. attr.read_format = evsel->attr.read_format;
  1804. id = evsel->id[0] + 1000000000;
  1805. if (!id)
  1806. id = 1;
  1807. if (pt->synth_opts.branches) {
  1808. attr.config = PERF_COUNT_HW_BRANCH_INSTRUCTIONS;
  1809. attr.sample_period = 1;
  1810. attr.sample_type |= PERF_SAMPLE_ADDR;
  1811. err = intel_pt_synth_event(session, "branches", &attr, id);
  1812. if (err)
  1813. return err;
  1814. pt->sample_branches = true;
  1815. pt->branches_sample_type = attr.sample_type;
  1816. pt->branches_id = id;
  1817. id += 1;
  1818. attr.sample_type &= ~(u64)PERF_SAMPLE_ADDR;
  1819. }
  1820. if (pt->synth_opts.callchain)
  1821. attr.sample_type |= PERF_SAMPLE_CALLCHAIN;
  1822. if (pt->synth_opts.last_branch)
  1823. attr.sample_type |= PERF_SAMPLE_BRANCH_STACK;
  1824. if (pt->synth_opts.instructions) {
  1825. attr.config = PERF_COUNT_HW_INSTRUCTIONS;
  1826. if (pt->synth_opts.period_type == PERF_ITRACE_PERIOD_NANOSECS)
  1827. attr.sample_period =
  1828. intel_pt_ns_to_ticks(pt, pt->synth_opts.period);
  1829. else
  1830. attr.sample_period = pt->synth_opts.period;
  1831. err = intel_pt_synth_event(session, "instructions", &attr, id);
  1832. if (err)
  1833. return err;
  1834. pt->sample_instructions = true;
  1835. pt->instructions_sample_type = attr.sample_type;
  1836. pt->instructions_id = id;
  1837. id += 1;
  1838. }
  1839. attr.sample_type &= ~(u64)PERF_SAMPLE_PERIOD;
  1840. attr.sample_period = 1;
  1841. if (pt->synth_opts.transactions) {
  1842. attr.config = PERF_COUNT_HW_INSTRUCTIONS;
  1843. err = intel_pt_synth_event(session, "transactions", &attr, id);
  1844. if (err)
  1845. return err;
  1846. pt->sample_transactions = true;
  1847. pt->transactions_sample_type = attr.sample_type;
  1848. pt->transactions_id = id;
  1849. intel_pt_set_event_name(evlist, id, "transactions");
  1850. id += 1;
  1851. }
  1852. attr.type = PERF_TYPE_SYNTH;
  1853. attr.sample_type |= PERF_SAMPLE_RAW;
  1854. if (pt->synth_opts.ptwrites) {
  1855. attr.config = PERF_SYNTH_INTEL_PTWRITE;
  1856. err = intel_pt_synth_event(session, "ptwrite", &attr, id);
  1857. if (err)
  1858. return err;
  1859. pt->sample_ptwrites = true;
  1860. pt->ptwrites_sample_type = attr.sample_type;
  1861. pt->ptwrites_id = id;
  1862. intel_pt_set_event_name(evlist, id, "ptwrite");
  1863. id += 1;
  1864. }
  1865. if (pt->synth_opts.pwr_events) {
  1866. pt->sample_pwr_events = true;
  1867. pt->pwr_events_sample_type = attr.sample_type;
  1868. attr.config = PERF_SYNTH_INTEL_CBR;
  1869. err = intel_pt_synth_event(session, "cbr", &attr, id);
  1870. if (err)
  1871. return err;
  1872. pt->cbr_id = id;
  1873. intel_pt_set_event_name(evlist, id, "cbr");
  1874. id += 1;
  1875. }
  1876. if (pt->synth_opts.pwr_events && (evsel->attr.config & 0x10)) {
  1877. attr.config = PERF_SYNTH_INTEL_MWAIT;
  1878. err = intel_pt_synth_event(session, "mwait", &attr, id);
  1879. if (err)
  1880. return err;
  1881. pt->mwait_id = id;
  1882. intel_pt_set_event_name(evlist, id, "mwait");
  1883. id += 1;
  1884. attr.config = PERF_SYNTH_INTEL_PWRE;
  1885. err = intel_pt_synth_event(session, "pwre", &attr, id);
  1886. if (err)
  1887. return err;
  1888. pt->pwre_id = id;
  1889. intel_pt_set_event_name(evlist, id, "pwre");
  1890. id += 1;
  1891. attr.config = PERF_SYNTH_INTEL_EXSTOP;
  1892. err = intel_pt_synth_event(session, "exstop", &attr, id);
  1893. if (err)
  1894. return err;
  1895. pt->exstop_id = id;
  1896. intel_pt_set_event_name(evlist, id, "exstop");
  1897. id += 1;
  1898. attr.config = PERF_SYNTH_INTEL_PWRX;
  1899. err = intel_pt_synth_event(session, "pwrx", &attr, id);
  1900. if (err)
  1901. return err;
  1902. pt->pwrx_id = id;
  1903. intel_pt_set_event_name(evlist, id, "pwrx");
  1904. id += 1;
  1905. }
  1906. return 0;
  1907. }
  1908. static struct perf_evsel *intel_pt_find_sched_switch(struct perf_evlist *evlist)
  1909. {
  1910. struct perf_evsel *evsel;
  1911. evlist__for_each_entry_reverse(evlist, evsel) {
  1912. const char *name = perf_evsel__name(evsel);
  1913. if (!strcmp(name, "sched:sched_switch"))
  1914. return evsel;
  1915. }
  1916. return NULL;
  1917. }
  1918. static bool intel_pt_find_switch(struct perf_evlist *evlist)
  1919. {
  1920. struct perf_evsel *evsel;
  1921. evlist__for_each_entry(evlist, evsel) {
  1922. if (evsel->attr.context_switch)
  1923. return true;
  1924. }
  1925. return false;
  1926. }
  1927. static int intel_pt_perf_config(const char *var, const char *value, void *data)
  1928. {
  1929. struct intel_pt *pt = data;
  1930. if (!strcmp(var, "intel-pt.mispred-all"))
  1931. pt->mispred_all = perf_config_bool(var, value);
  1932. return 0;
  1933. }
  1934. static const char * const intel_pt_info_fmts[] = {
  1935. [INTEL_PT_PMU_TYPE] = " PMU Type %"PRId64"\n",
  1936. [INTEL_PT_TIME_SHIFT] = " Time Shift %"PRIu64"\n",
  1937. [INTEL_PT_TIME_MULT] = " Time Muliplier %"PRIu64"\n",
  1938. [INTEL_PT_TIME_ZERO] = " Time Zero %"PRIu64"\n",
  1939. [INTEL_PT_CAP_USER_TIME_ZERO] = " Cap Time Zero %"PRId64"\n",
  1940. [INTEL_PT_TSC_BIT] = " TSC bit %#"PRIx64"\n",
  1941. [INTEL_PT_NORETCOMP_BIT] = " NoRETComp bit %#"PRIx64"\n",
  1942. [INTEL_PT_HAVE_SCHED_SWITCH] = " Have sched_switch %"PRId64"\n",
  1943. [INTEL_PT_SNAPSHOT_MODE] = " Snapshot mode %"PRId64"\n",
  1944. [INTEL_PT_PER_CPU_MMAPS] = " Per-cpu maps %"PRId64"\n",
  1945. [INTEL_PT_MTC_BIT] = " MTC bit %#"PRIx64"\n",
  1946. [INTEL_PT_TSC_CTC_N] = " TSC:CTC numerator %"PRIu64"\n",
  1947. [INTEL_PT_TSC_CTC_D] = " TSC:CTC denominator %"PRIu64"\n",
  1948. [INTEL_PT_CYC_BIT] = " CYC bit %#"PRIx64"\n",
  1949. [INTEL_PT_MAX_NONTURBO_RATIO] = " Max non-turbo ratio %"PRIu64"\n",
  1950. [INTEL_PT_FILTER_STR_LEN] = " Filter string len. %"PRIu64"\n",
  1951. };
  1952. static void intel_pt_print_info(u64 *arr, int start, int finish)
  1953. {
  1954. int i;
  1955. if (!dump_trace)
  1956. return;
  1957. for (i = start; i <= finish; i++)
  1958. fprintf(stdout, intel_pt_info_fmts[i], arr[i]);
  1959. }
  1960. static void intel_pt_print_info_str(const char *name, const char *str)
  1961. {
  1962. if (!dump_trace)
  1963. return;
  1964. fprintf(stdout, " %-20s%s\n", name, str ? str : "");
  1965. }
  1966. static bool intel_pt_has(struct auxtrace_info_event *auxtrace_info, int pos)
  1967. {
  1968. return auxtrace_info->header.size >=
  1969. sizeof(struct auxtrace_info_event) + (sizeof(u64) * (pos + 1));
  1970. }
  1971. int intel_pt_process_auxtrace_info(union perf_event *event,
  1972. struct perf_session *session)
  1973. {
  1974. struct auxtrace_info_event *auxtrace_info = &event->auxtrace_info;
  1975. size_t min_sz = sizeof(u64) * INTEL_PT_PER_CPU_MMAPS;
  1976. struct intel_pt *pt;
  1977. void *info_end;
  1978. u64 *info;
  1979. int err;
  1980. if (auxtrace_info->header.size < sizeof(struct auxtrace_info_event) +
  1981. min_sz)
  1982. return -EINVAL;
  1983. pt = zalloc(sizeof(struct intel_pt));
  1984. if (!pt)
  1985. return -ENOMEM;
  1986. addr_filters__init(&pt->filts);
  1987. err = perf_config(intel_pt_perf_config, pt);
  1988. if (err)
  1989. goto err_free;
  1990. err = auxtrace_queues__init(&pt->queues);
  1991. if (err)
  1992. goto err_free;
  1993. intel_pt_log_set_name(INTEL_PT_PMU_NAME);
  1994. pt->session = session;
  1995. pt->machine = &session->machines.host; /* No kvm support */
  1996. pt->auxtrace_type = auxtrace_info->type;
  1997. pt->pmu_type = auxtrace_info->priv[INTEL_PT_PMU_TYPE];
  1998. pt->tc.time_shift = auxtrace_info->priv[INTEL_PT_TIME_SHIFT];
  1999. pt->tc.time_mult = auxtrace_info->priv[INTEL_PT_TIME_MULT];
  2000. pt->tc.time_zero = auxtrace_info->priv[INTEL_PT_TIME_ZERO];
  2001. pt->cap_user_time_zero = auxtrace_info->priv[INTEL_PT_CAP_USER_TIME_ZERO];
  2002. pt->tsc_bit = auxtrace_info->priv[INTEL_PT_TSC_BIT];
  2003. pt->noretcomp_bit = auxtrace_info->priv[INTEL_PT_NORETCOMP_BIT];
  2004. pt->have_sched_switch = auxtrace_info->priv[INTEL_PT_HAVE_SCHED_SWITCH];
  2005. pt->snapshot_mode = auxtrace_info->priv[INTEL_PT_SNAPSHOT_MODE];
  2006. pt->per_cpu_mmaps = auxtrace_info->priv[INTEL_PT_PER_CPU_MMAPS];
  2007. intel_pt_print_info(&auxtrace_info->priv[0], INTEL_PT_PMU_TYPE,
  2008. INTEL_PT_PER_CPU_MMAPS);
  2009. if (intel_pt_has(auxtrace_info, INTEL_PT_CYC_BIT)) {
  2010. pt->mtc_bit = auxtrace_info->priv[INTEL_PT_MTC_BIT];
  2011. pt->mtc_freq_bits = auxtrace_info->priv[INTEL_PT_MTC_FREQ_BITS];
  2012. pt->tsc_ctc_ratio_n = auxtrace_info->priv[INTEL_PT_TSC_CTC_N];
  2013. pt->tsc_ctc_ratio_d = auxtrace_info->priv[INTEL_PT_TSC_CTC_D];
  2014. pt->cyc_bit = auxtrace_info->priv[INTEL_PT_CYC_BIT];
  2015. intel_pt_print_info(&auxtrace_info->priv[0], INTEL_PT_MTC_BIT,
  2016. INTEL_PT_CYC_BIT);
  2017. }
  2018. if (intel_pt_has(auxtrace_info, INTEL_PT_MAX_NONTURBO_RATIO)) {
  2019. pt->max_non_turbo_ratio =
  2020. auxtrace_info->priv[INTEL_PT_MAX_NONTURBO_RATIO];
  2021. intel_pt_print_info(&auxtrace_info->priv[0],
  2022. INTEL_PT_MAX_NONTURBO_RATIO,
  2023. INTEL_PT_MAX_NONTURBO_RATIO);
  2024. }
  2025. info = &auxtrace_info->priv[INTEL_PT_FILTER_STR_LEN] + 1;
  2026. info_end = (void *)info + auxtrace_info->header.size;
  2027. if (intel_pt_has(auxtrace_info, INTEL_PT_FILTER_STR_LEN)) {
  2028. size_t len;
  2029. len = auxtrace_info->priv[INTEL_PT_FILTER_STR_LEN];
  2030. intel_pt_print_info(&auxtrace_info->priv[0],
  2031. INTEL_PT_FILTER_STR_LEN,
  2032. INTEL_PT_FILTER_STR_LEN);
  2033. if (len) {
  2034. const char *filter = (const char *)info;
  2035. len = roundup(len + 1, 8);
  2036. info += len >> 3;
  2037. if ((void *)info > info_end) {
  2038. pr_err("%s: bad filter string length\n", __func__);
  2039. err = -EINVAL;
  2040. goto err_free_queues;
  2041. }
  2042. pt->filter = memdup(filter, len);
  2043. if (!pt->filter) {
  2044. err = -ENOMEM;
  2045. goto err_free_queues;
  2046. }
  2047. if (session->header.needs_swap)
  2048. mem_bswap_64(pt->filter, len);
  2049. if (pt->filter[len - 1]) {
  2050. pr_err("%s: filter string not null terminated\n", __func__);
  2051. err = -EINVAL;
  2052. goto err_free_queues;
  2053. }
  2054. err = addr_filters__parse_bare_filter(&pt->filts,
  2055. filter);
  2056. if (err)
  2057. goto err_free_queues;
  2058. }
  2059. intel_pt_print_info_str("Filter string", pt->filter);
  2060. }
  2061. pt->timeless_decoding = intel_pt_timeless_decoding(pt);
  2062. pt->have_tsc = intel_pt_have_tsc(pt);
  2063. pt->sampling_mode = false;
  2064. pt->est_tsc = !pt->timeless_decoding;
  2065. pt->unknown_thread = thread__new(999999999, 999999999);
  2066. if (!pt->unknown_thread) {
  2067. err = -ENOMEM;
  2068. goto err_free_queues;
  2069. }
  2070. /*
  2071. * Since this thread will not be kept in any rbtree not in a
  2072. * list, initialize its list node so that at thread__put() the
  2073. * current thread lifetime assuption is kept and we don't segfault
  2074. * at list_del_init().
  2075. */
  2076. INIT_LIST_HEAD(&pt->unknown_thread->node);
  2077. err = thread__set_comm(pt->unknown_thread, "unknown", 0);
  2078. if (err)
  2079. goto err_delete_thread;
  2080. if (thread__init_map_groups(pt->unknown_thread, pt->machine)) {
  2081. err = -ENOMEM;
  2082. goto err_delete_thread;
  2083. }
  2084. pt->auxtrace.process_event = intel_pt_process_event;
  2085. pt->auxtrace.process_auxtrace_event = intel_pt_process_auxtrace_event;
  2086. pt->auxtrace.flush_events = intel_pt_flush;
  2087. pt->auxtrace.free_events = intel_pt_free_events;
  2088. pt->auxtrace.free = intel_pt_free;
  2089. session->auxtrace = &pt->auxtrace;
  2090. if (dump_trace)
  2091. return 0;
  2092. if (pt->have_sched_switch == 1) {
  2093. pt->switch_evsel = intel_pt_find_sched_switch(session->evlist);
  2094. if (!pt->switch_evsel) {
  2095. pr_err("%s: missing sched_switch event\n", __func__);
  2096. err = -EINVAL;
  2097. goto err_delete_thread;
  2098. }
  2099. } else if (pt->have_sched_switch == 2 &&
  2100. !intel_pt_find_switch(session->evlist)) {
  2101. pr_err("%s: missing context_switch attribute flag\n", __func__);
  2102. err = -EINVAL;
  2103. goto err_delete_thread;
  2104. }
  2105. if (session->itrace_synth_opts && session->itrace_synth_opts->set) {
  2106. pt->synth_opts = *session->itrace_synth_opts;
  2107. } else {
  2108. itrace_synth_opts__set_default(&pt->synth_opts);
  2109. if (use_browser != -1) {
  2110. pt->synth_opts.branches = false;
  2111. pt->synth_opts.callchain = true;
  2112. }
  2113. if (session->itrace_synth_opts)
  2114. pt->synth_opts.thread_stack =
  2115. session->itrace_synth_opts->thread_stack;
  2116. }
  2117. if (pt->synth_opts.log)
  2118. intel_pt_log_enable();
  2119. /* Maximum non-turbo ratio is TSC freq / 100 MHz */
  2120. if (pt->tc.time_mult) {
  2121. u64 tsc_freq = intel_pt_ns_to_ticks(pt, 1000000000);
  2122. if (!pt->max_non_turbo_ratio)
  2123. pt->max_non_turbo_ratio =
  2124. (tsc_freq + 50000000) / 100000000;
  2125. intel_pt_log("TSC frequency %"PRIu64"\n", tsc_freq);
  2126. intel_pt_log("Maximum non-turbo ratio %u\n",
  2127. pt->max_non_turbo_ratio);
  2128. pt->cbr2khz = tsc_freq / pt->max_non_turbo_ratio / 1000;
  2129. }
  2130. if (pt->synth_opts.calls)
  2131. pt->branches_filter |= PERF_IP_FLAG_CALL | PERF_IP_FLAG_ASYNC |
  2132. PERF_IP_FLAG_TRACE_END;
  2133. if (pt->synth_opts.returns)
  2134. pt->branches_filter |= PERF_IP_FLAG_RETURN |
  2135. PERF_IP_FLAG_TRACE_BEGIN;
  2136. if (pt->synth_opts.callchain && !symbol_conf.use_callchain) {
  2137. symbol_conf.use_callchain = true;
  2138. if (callchain_register_param(&callchain_param) < 0) {
  2139. symbol_conf.use_callchain = false;
  2140. pt->synth_opts.callchain = false;
  2141. }
  2142. }
  2143. err = intel_pt_synth_events(pt, session);
  2144. if (err)
  2145. goto err_delete_thread;
  2146. err = auxtrace_queues__process_index(&pt->queues, session);
  2147. if (err)
  2148. goto err_delete_thread;
  2149. if (pt->queues.populated)
  2150. pt->data_queued = true;
  2151. if (pt->timeless_decoding)
  2152. pr_debug2("Intel PT decoding without timestamps\n");
  2153. return 0;
  2154. err_delete_thread:
  2155. thread__zput(pt->unknown_thread);
  2156. err_free_queues:
  2157. intel_pt_log_disable();
  2158. auxtrace_queues__free(&pt->queues);
  2159. session->auxtrace = NULL;
  2160. err_free:
  2161. addr_filters__exit(&pt->filts);
  2162. zfree(&pt->filter);
  2163. free(pt);
  2164. return err;
  2165. }