patch_ca0132.c 209 KB

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  1. /*
  2. * HD audio interface patch for Creative CA0132 chip
  3. *
  4. * Copyright (c) 2011, Creative Technology Ltd.
  5. *
  6. * Based on patch_ca0110.c
  7. * Copyright (c) 2008 Takashi Iwai <tiwai@suse.de>
  8. *
  9. * This driver is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; either version 2 of the License, or
  12. * (at your option) any later version.
  13. *
  14. * This driver is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  22. */
  23. #include <linux/init.h>
  24. #include <linux/delay.h>
  25. #include <linux/slab.h>
  26. #include <linux/mutex.h>
  27. #include <linux/module.h>
  28. #include <linux/firmware.h>
  29. #include <linux/kernel.h>
  30. #include <linux/types.h>
  31. #include <linux/io.h>
  32. #include <linux/pci.h>
  33. #include <sound/core.h>
  34. #include "hda_codec.h"
  35. #include "hda_local.h"
  36. #include "hda_auto_parser.h"
  37. #include "hda_jack.h"
  38. #include "ca0132_regs.h"
  39. /* Enable this to see controls for tuning purpose. */
  40. /*#define ENABLE_TUNING_CONTROLS*/
  41. #ifdef ENABLE_TUNING_CONTROLS
  42. #include <sound/tlv.h>
  43. #endif
  44. #define FLOAT_ZERO 0x00000000
  45. #define FLOAT_ONE 0x3f800000
  46. #define FLOAT_TWO 0x40000000
  47. #define FLOAT_THREE 0x40400000
  48. #define FLOAT_EIGHT 0x41000000
  49. #define FLOAT_MINUS_5 0xc0a00000
  50. #define UNSOL_TAG_DSP 0x16
  51. #define DSP_DMA_WRITE_BUFLEN_INIT (1UL<<18)
  52. #define DSP_DMA_WRITE_BUFLEN_OVLY (1UL<<15)
  53. #define DMA_TRANSFER_FRAME_SIZE_NWORDS 8
  54. #define DMA_TRANSFER_MAX_FRAME_SIZE_NWORDS 32
  55. #define DMA_OVERLAY_FRAME_SIZE_NWORDS 2
  56. #define MASTERCONTROL 0x80
  57. #define MASTERCONTROL_ALLOC_DMA_CHAN 10
  58. #define MASTERCONTROL_QUERY_SPEAKER_EQ_ADDRESS 60
  59. #define WIDGET_CHIP_CTRL 0x15
  60. #define WIDGET_DSP_CTRL 0x16
  61. #define MEM_CONNID_MICIN1 3
  62. #define MEM_CONNID_MICIN2 5
  63. #define MEM_CONNID_MICOUT1 12
  64. #define MEM_CONNID_MICOUT2 14
  65. #define MEM_CONNID_WUH 10
  66. #define MEM_CONNID_DSP 16
  67. #define MEM_CONNID_DMIC 100
  68. #define SCP_SET 0
  69. #define SCP_GET 1
  70. #define EFX_FILE "ctefx.bin"
  71. #define SBZ_EFX_FILE "ctefx-sbz.bin"
  72. #define R3DI_EFX_FILE "ctefx-r3di.bin"
  73. #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
  74. MODULE_FIRMWARE(EFX_FILE);
  75. MODULE_FIRMWARE(SBZ_EFX_FILE);
  76. MODULE_FIRMWARE(R3DI_EFX_FILE);
  77. #endif
  78. static const char *const dirstr[2] = { "Playback", "Capture" };
  79. #define NUM_OF_OUTPUTS 3
  80. enum {
  81. SPEAKER_OUT,
  82. HEADPHONE_OUT,
  83. SURROUND_OUT
  84. };
  85. enum {
  86. DIGITAL_MIC,
  87. LINE_MIC_IN
  88. };
  89. /* Strings for Input Source Enum Control */
  90. static const char *const in_src_str[3] = {"Rear Mic", "Line", "Front Mic" };
  91. #define IN_SRC_NUM_OF_INPUTS 3
  92. enum {
  93. REAR_MIC,
  94. REAR_LINE_IN,
  95. FRONT_MIC,
  96. };
  97. enum {
  98. #define VNODE_START_NID 0x80
  99. VNID_SPK = VNODE_START_NID, /* Speaker vnid */
  100. VNID_MIC,
  101. VNID_HP_SEL,
  102. VNID_AMIC1_SEL,
  103. VNID_HP_ASEL,
  104. VNID_AMIC1_ASEL,
  105. VNODE_END_NID,
  106. #define VNODES_COUNT (VNODE_END_NID - VNODE_START_NID)
  107. #define EFFECT_START_NID 0x90
  108. #define OUT_EFFECT_START_NID EFFECT_START_NID
  109. SURROUND = OUT_EFFECT_START_NID,
  110. CRYSTALIZER,
  111. DIALOG_PLUS,
  112. SMART_VOLUME,
  113. X_BASS,
  114. EQUALIZER,
  115. OUT_EFFECT_END_NID,
  116. #define OUT_EFFECTS_COUNT (OUT_EFFECT_END_NID - OUT_EFFECT_START_NID)
  117. #define IN_EFFECT_START_NID OUT_EFFECT_END_NID
  118. ECHO_CANCELLATION = IN_EFFECT_START_NID,
  119. VOICE_FOCUS,
  120. MIC_SVM,
  121. NOISE_REDUCTION,
  122. IN_EFFECT_END_NID,
  123. #define IN_EFFECTS_COUNT (IN_EFFECT_END_NID - IN_EFFECT_START_NID)
  124. VOICEFX = IN_EFFECT_END_NID,
  125. PLAY_ENHANCEMENT,
  126. CRYSTAL_VOICE,
  127. EFFECT_END_NID,
  128. OUTPUT_SOURCE_ENUM,
  129. INPUT_SOURCE_ENUM,
  130. XBASS_XOVER,
  131. EQ_PRESET_ENUM,
  132. SMART_VOLUME_ENUM,
  133. MIC_BOOST_ENUM
  134. #define EFFECTS_COUNT (EFFECT_END_NID - EFFECT_START_NID)
  135. };
  136. /* Effects values size*/
  137. #define EFFECT_VALS_MAX_COUNT 12
  138. /*
  139. * Default values for the effect slider controls, they are in order of their
  140. * effect NID's. Surround, Crystalizer, Dialog Plus, Smart Volume, and then
  141. * X-bass.
  142. */
  143. static const unsigned int effect_slider_defaults[] = {67, 65, 50, 74, 50};
  144. /* Amount of effect level sliders for ca0132_alt controls. */
  145. #define EFFECT_LEVEL_SLIDERS 5
  146. /* Latency introduced by DSP blocks in milliseconds. */
  147. #define DSP_CAPTURE_INIT_LATENCY 0
  148. #define DSP_CRYSTAL_VOICE_LATENCY 124
  149. #define DSP_PLAYBACK_INIT_LATENCY 13
  150. #define DSP_PLAY_ENHANCEMENT_LATENCY 30
  151. #define DSP_SPEAKER_OUT_LATENCY 7
  152. struct ct_effect {
  153. char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
  154. hda_nid_t nid;
  155. int mid; /*effect module ID*/
  156. int reqs[EFFECT_VALS_MAX_COUNT]; /*effect module request*/
  157. int direct; /* 0:output; 1:input*/
  158. int params; /* number of default non-on/off params */
  159. /*effect default values, 1st is on/off. */
  160. unsigned int def_vals[EFFECT_VALS_MAX_COUNT];
  161. };
  162. #define EFX_DIR_OUT 0
  163. #define EFX_DIR_IN 1
  164. static const struct ct_effect ca0132_effects[EFFECTS_COUNT] = {
  165. { .name = "Surround",
  166. .nid = SURROUND,
  167. .mid = 0x96,
  168. .reqs = {0, 1},
  169. .direct = EFX_DIR_OUT,
  170. .params = 1,
  171. .def_vals = {0x3F800000, 0x3F2B851F}
  172. },
  173. { .name = "Crystalizer",
  174. .nid = CRYSTALIZER,
  175. .mid = 0x96,
  176. .reqs = {7, 8},
  177. .direct = EFX_DIR_OUT,
  178. .params = 1,
  179. .def_vals = {0x3F800000, 0x3F266666}
  180. },
  181. { .name = "Dialog Plus",
  182. .nid = DIALOG_PLUS,
  183. .mid = 0x96,
  184. .reqs = {2, 3},
  185. .direct = EFX_DIR_OUT,
  186. .params = 1,
  187. .def_vals = {0x00000000, 0x3F000000}
  188. },
  189. { .name = "Smart Volume",
  190. .nid = SMART_VOLUME,
  191. .mid = 0x96,
  192. .reqs = {4, 5, 6},
  193. .direct = EFX_DIR_OUT,
  194. .params = 2,
  195. .def_vals = {0x3F800000, 0x3F3D70A4, 0x00000000}
  196. },
  197. { .name = "X-Bass",
  198. .nid = X_BASS,
  199. .mid = 0x96,
  200. .reqs = {24, 23, 25},
  201. .direct = EFX_DIR_OUT,
  202. .params = 2,
  203. .def_vals = {0x3F800000, 0x42A00000, 0x3F000000}
  204. },
  205. { .name = "Equalizer",
  206. .nid = EQUALIZER,
  207. .mid = 0x96,
  208. .reqs = {9, 10, 11, 12, 13, 14,
  209. 15, 16, 17, 18, 19, 20},
  210. .direct = EFX_DIR_OUT,
  211. .params = 11,
  212. .def_vals = {0x00000000, 0x00000000, 0x00000000, 0x00000000,
  213. 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  214. 0x00000000, 0x00000000, 0x00000000, 0x00000000}
  215. },
  216. { .name = "Echo Cancellation",
  217. .nid = ECHO_CANCELLATION,
  218. .mid = 0x95,
  219. .reqs = {0, 1, 2, 3},
  220. .direct = EFX_DIR_IN,
  221. .params = 3,
  222. .def_vals = {0x00000000, 0x3F3A9692, 0x00000000, 0x00000000}
  223. },
  224. { .name = "Voice Focus",
  225. .nid = VOICE_FOCUS,
  226. .mid = 0x95,
  227. .reqs = {6, 7, 8, 9},
  228. .direct = EFX_DIR_IN,
  229. .params = 3,
  230. .def_vals = {0x3F800000, 0x3D7DF3B6, 0x41F00000, 0x41F00000}
  231. },
  232. { .name = "Mic SVM",
  233. .nid = MIC_SVM,
  234. .mid = 0x95,
  235. .reqs = {44, 45},
  236. .direct = EFX_DIR_IN,
  237. .params = 1,
  238. .def_vals = {0x00000000, 0x3F3D70A4}
  239. },
  240. { .name = "Noise Reduction",
  241. .nid = NOISE_REDUCTION,
  242. .mid = 0x95,
  243. .reqs = {4, 5},
  244. .direct = EFX_DIR_IN,
  245. .params = 1,
  246. .def_vals = {0x3F800000, 0x3F000000}
  247. },
  248. { .name = "VoiceFX",
  249. .nid = VOICEFX,
  250. .mid = 0x95,
  251. .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18},
  252. .direct = EFX_DIR_IN,
  253. .params = 8,
  254. .def_vals = {0x00000000, 0x43C80000, 0x44AF0000, 0x44FA0000,
  255. 0x3F800000, 0x3F800000, 0x3F800000, 0x00000000,
  256. 0x00000000}
  257. }
  258. };
  259. /* Tuning controls */
  260. #ifdef ENABLE_TUNING_CONTROLS
  261. enum {
  262. #define TUNING_CTL_START_NID 0xC0
  263. WEDGE_ANGLE = TUNING_CTL_START_NID,
  264. SVM_LEVEL,
  265. EQUALIZER_BAND_0,
  266. EQUALIZER_BAND_1,
  267. EQUALIZER_BAND_2,
  268. EQUALIZER_BAND_3,
  269. EQUALIZER_BAND_4,
  270. EQUALIZER_BAND_5,
  271. EQUALIZER_BAND_6,
  272. EQUALIZER_BAND_7,
  273. EQUALIZER_BAND_8,
  274. EQUALIZER_BAND_9,
  275. TUNING_CTL_END_NID
  276. #define TUNING_CTLS_COUNT (TUNING_CTL_END_NID - TUNING_CTL_START_NID)
  277. };
  278. struct ct_tuning_ctl {
  279. char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
  280. hda_nid_t parent_nid;
  281. hda_nid_t nid;
  282. int mid; /*effect module ID*/
  283. int req; /*effect module request*/
  284. int direct; /* 0:output; 1:input*/
  285. unsigned int def_val;/*effect default values*/
  286. };
  287. static const struct ct_tuning_ctl ca0132_tuning_ctls[] = {
  288. { .name = "Wedge Angle",
  289. .parent_nid = VOICE_FOCUS,
  290. .nid = WEDGE_ANGLE,
  291. .mid = 0x95,
  292. .req = 8,
  293. .direct = EFX_DIR_IN,
  294. .def_val = 0x41F00000
  295. },
  296. { .name = "SVM Level",
  297. .parent_nid = MIC_SVM,
  298. .nid = SVM_LEVEL,
  299. .mid = 0x95,
  300. .req = 45,
  301. .direct = EFX_DIR_IN,
  302. .def_val = 0x3F3D70A4
  303. },
  304. { .name = "EQ Band0",
  305. .parent_nid = EQUALIZER,
  306. .nid = EQUALIZER_BAND_0,
  307. .mid = 0x96,
  308. .req = 11,
  309. .direct = EFX_DIR_OUT,
  310. .def_val = 0x00000000
  311. },
  312. { .name = "EQ Band1",
  313. .parent_nid = EQUALIZER,
  314. .nid = EQUALIZER_BAND_1,
  315. .mid = 0x96,
  316. .req = 12,
  317. .direct = EFX_DIR_OUT,
  318. .def_val = 0x00000000
  319. },
  320. { .name = "EQ Band2",
  321. .parent_nid = EQUALIZER,
  322. .nid = EQUALIZER_BAND_2,
  323. .mid = 0x96,
  324. .req = 13,
  325. .direct = EFX_DIR_OUT,
  326. .def_val = 0x00000000
  327. },
  328. { .name = "EQ Band3",
  329. .parent_nid = EQUALIZER,
  330. .nid = EQUALIZER_BAND_3,
  331. .mid = 0x96,
  332. .req = 14,
  333. .direct = EFX_DIR_OUT,
  334. .def_val = 0x00000000
  335. },
  336. { .name = "EQ Band4",
  337. .parent_nid = EQUALIZER,
  338. .nid = EQUALIZER_BAND_4,
  339. .mid = 0x96,
  340. .req = 15,
  341. .direct = EFX_DIR_OUT,
  342. .def_val = 0x00000000
  343. },
  344. { .name = "EQ Band5",
  345. .parent_nid = EQUALIZER,
  346. .nid = EQUALIZER_BAND_5,
  347. .mid = 0x96,
  348. .req = 16,
  349. .direct = EFX_DIR_OUT,
  350. .def_val = 0x00000000
  351. },
  352. { .name = "EQ Band6",
  353. .parent_nid = EQUALIZER,
  354. .nid = EQUALIZER_BAND_6,
  355. .mid = 0x96,
  356. .req = 17,
  357. .direct = EFX_DIR_OUT,
  358. .def_val = 0x00000000
  359. },
  360. { .name = "EQ Band7",
  361. .parent_nid = EQUALIZER,
  362. .nid = EQUALIZER_BAND_7,
  363. .mid = 0x96,
  364. .req = 18,
  365. .direct = EFX_DIR_OUT,
  366. .def_val = 0x00000000
  367. },
  368. { .name = "EQ Band8",
  369. .parent_nid = EQUALIZER,
  370. .nid = EQUALIZER_BAND_8,
  371. .mid = 0x96,
  372. .req = 19,
  373. .direct = EFX_DIR_OUT,
  374. .def_val = 0x00000000
  375. },
  376. { .name = "EQ Band9",
  377. .parent_nid = EQUALIZER,
  378. .nid = EQUALIZER_BAND_9,
  379. .mid = 0x96,
  380. .req = 20,
  381. .direct = EFX_DIR_OUT,
  382. .def_val = 0x00000000
  383. }
  384. };
  385. #endif
  386. /* Voice FX Presets */
  387. #define VOICEFX_MAX_PARAM_COUNT 9
  388. struct ct_voicefx {
  389. char *name;
  390. hda_nid_t nid;
  391. int mid;
  392. int reqs[VOICEFX_MAX_PARAM_COUNT]; /*effect module request*/
  393. };
  394. struct ct_voicefx_preset {
  395. char *name; /*preset name*/
  396. unsigned int vals[VOICEFX_MAX_PARAM_COUNT];
  397. };
  398. static const struct ct_voicefx ca0132_voicefx = {
  399. .name = "VoiceFX Capture Switch",
  400. .nid = VOICEFX,
  401. .mid = 0x95,
  402. .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18}
  403. };
  404. static const struct ct_voicefx_preset ca0132_voicefx_presets[] = {
  405. { .name = "Neutral",
  406. .vals = { 0x00000000, 0x43C80000, 0x44AF0000,
  407. 0x44FA0000, 0x3F800000, 0x3F800000,
  408. 0x3F800000, 0x00000000, 0x00000000 }
  409. },
  410. { .name = "Female2Male",
  411. .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
  412. 0x44FA0000, 0x3F19999A, 0x3F866666,
  413. 0x3F800000, 0x00000000, 0x00000000 }
  414. },
  415. { .name = "Male2Female",
  416. .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
  417. 0x450AC000, 0x4017AE14, 0x3F6B851F,
  418. 0x3F800000, 0x00000000, 0x00000000 }
  419. },
  420. { .name = "ScrappyKid",
  421. .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
  422. 0x44FA0000, 0x40400000, 0x3F28F5C3,
  423. 0x3F800000, 0x00000000, 0x00000000 }
  424. },
  425. { .name = "Elderly",
  426. .vals = { 0x3F800000, 0x44324000, 0x44BB8000,
  427. 0x44E10000, 0x3FB33333, 0x3FB9999A,
  428. 0x3F800000, 0x3E3A2E43, 0x00000000 }
  429. },
  430. { .name = "Orc",
  431. .vals = { 0x3F800000, 0x43EA0000, 0x44A52000,
  432. 0x45098000, 0x3F266666, 0x3FC00000,
  433. 0x3F800000, 0x00000000, 0x00000000 }
  434. },
  435. { .name = "Elf",
  436. .vals = { 0x3F800000, 0x43C70000, 0x44AE6000,
  437. 0x45193000, 0x3F8E147B, 0x3F75C28F,
  438. 0x3F800000, 0x00000000, 0x00000000 }
  439. },
  440. { .name = "Dwarf",
  441. .vals = { 0x3F800000, 0x43930000, 0x44BEE000,
  442. 0x45007000, 0x3F451EB8, 0x3F7851EC,
  443. 0x3F800000, 0x00000000, 0x00000000 }
  444. },
  445. { .name = "AlienBrute",
  446. .vals = { 0x3F800000, 0x43BFC5AC, 0x44B28FDF,
  447. 0x451F6000, 0x3F266666, 0x3FA7D945,
  448. 0x3F800000, 0x3CF5C28F, 0x00000000 }
  449. },
  450. { .name = "Robot",
  451. .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
  452. 0x44FA0000, 0x3FB2718B, 0x3F800000,
  453. 0xBC07010E, 0x00000000, 0x00000000 }
  454. },
  455. { .name = "Marine",
  456. .vals = { 0x3F800000, 0x43C20000, 0x44906000,
  457. 0x44E70000, 0x3F4CCCCD, 0x3F8A3D71,
  458. 0x3F0A3D71, 0x00000000, 0x00000000 }
  459. },
  460. { .name = "Emo",
  461. .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
  462. 0x44FA0000, 0x3F800000, 0x3F800000,
  463. 0x3E4CCCCD, 0x00000000, 0x00000000 }
  464. },
  465. { .name = "DeepVoice",
  466. .vals = { 0x3F800000, 0x43A9C5AC, 0x44AA4FDF,
  467. 0x44FFC000, 0x3EDBB56F, 0x3F99C4CA,
  468. 0x3F800000, 0x00000000, 0x00000000 }
  469. },
  470. { .name = "Munchkin",
  471. .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
  472. 0x44FA0000, 0x3F800000, 0x3F1A043C,
  473. 0x3F800000, 0x00000000, 0x00000000 }
  474. }
  475. };
  476. /* ca0132 EQ presets, taken from Windows Sound Blaster Z Driver */
  477. #define EQ_PRESET_MAX_PARAM_COUNT 11
  478. struct ct_eq {
  479. char *name;
  480. hda_nid_t nid;
  481. int mid;
  482. int reqs[EQ_PRESET_MAX_PARAM_COUNT]; /*effect module request*/
  483. };
  484. struct ct_eq_preset {
  485. char *name; /*preset name*/
  486. unsigned int vals[EQ_PRESET_MAX_PARAM_COUNT];
  487. };
  488. static const struct ct_eq ca0132_alt_eq_enum = {
  489. .name = "FX: Equalizer Preset Switch",
  490. .nid = EQ_PRESET_ENUM,
  491. .mid = 0x96,
  492. .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20}
  493. };
  494. static const struct ct_eq_preset ca0132_alt_eq_presets[] = {
  495. { .name = "Flat",
  496. .vals = { 0x00000000, 0x00000000, 0x00000000,
  497. 0x00000000, 0x00000000, 0x00000000,
  498. 0x00000000, 0x00000000, 0x00000000,
  499. 0x00000000, 0x00000000 }
  500. },
  501. { .name = "Acoustic",
  502. .vals = { 0x00000000, 0x00000000, 0x3F8CCCCD,
  503. 0x40000000, 0x00000000, 0x00000000,
  504. 0x00000000, 0x00000000, 0x40000000,
  505. 0x40000000, 0x40000000 }
  506. },
  507. { .name = "Classical",
  508. .vals = { 0x00000000, 0x00000000, 0x40C00000,
  509. 0x40C00000, 0x40466666, 0x00000000,
  510. 0x00000000, 0x00000000, 0x00000000,
  511. 0x40466666, 0x40466666 }
  512. },
  513. { .name = "Country",
  514. .vals = { 0x00000000, 0xBF99999A, 0x00000000,
  515. 0x3FA66666, 0x3FA66666, 0x3F8CCCCD,
  516. 0x00000000, 0x00000000, 0x40000000,
  517. 0x40466666, 0x40800000 }
  518. },
  519. { .name = "Dance",
  520. .vals = { 0x00000000, 0xBF99999A, 0x40000000,
  521. 0x40466666, 0x40866666, 0xBF99999A,
  522. 0xBF99999A, 0x00000000, 0x00000000,
  523. 0x40800000, 0x40800000 }
  524. },
  525. { .name = "Jazz",
  526. .vals = { 0x00000000, 0x00000000, 0x00000000,
  527. 0x3F8CCCCD, 0x40800000, 0x40800000,
  528. 0x40800000, 0x00000000, 0x3F8CCCCD,
  529. 0x40466666, 0x40466666 }
  530. },
  531. { .name = "New Age",
  532. .vals = { 0x00000000, 0x00000000, 0x40000000,
  533. 0x40000000, 0x00000000, 0x00000000,
  534. 0x00000000, 0x3F8CCCCD, 0x40000000,
  535. 0x40000000, 0x40000000 }
  536. },
  537. { .name = "Pop",
  538. .vals = { 0x00000000, 0xBFCCCCCD, 0x00000000,
  539. 0x40000000, 0x40000000, 0x00000000,
  540. 0xBF99999A, 0xBF99999A, 0x00000000,
  541. 0x40466666, 0x40C00000 }
  542. },
  543. { .name = "Rock",
  544. .vals = { 0x00000000, 0xBF99999A, 0xBF99999A,
  545. 0x3F8CCCCD, 0x40000000, 0xBF99999A,
  546. 0xBF99999A, 0x00000000, 0x00000000,
  547. 0x40800000, 0x40800000 }
  548. },
  549. { .name = "Vocal",
  550. .vals = { 0x00000000, 0xC0000000, 0xBF99999A,
  551. 0xBF99999A, 0x00000000, 0x40466666,
  552. 0x40800000, 0x40466666, 0x00000000,
  553. 0x00000000, 0x3F8CCCCD }
  554. }
  555. };
  556. /* DSP command sequences for ca0132_alt_select_out */
  557. #define ALT_OUT_SET_MAX_COMMANDS 9 /* Max number of commands in sequence */
  558. struct ca0132_alt_out_set {
  559. char *name; /*preset name*/
  560. unsigned char commands;
  561. unsigned int mids[ALT_OUT_SET_MAX_COMMANDS];
  562. unsigned int reqs[ALT_OUT_SET_MAX_COMMANDS];
  563. unsigned int vals[ALT_OUT_SET_MAX_COMMANDS];
  564. };
  565. static const struct ca0132_alt_out_set alt_out_presets[] = {
  566. { .name = "Line Out",
  567. .commands = 7,
  568. .mids = { 0x96, 0x96, 0x96, 0x8F,
  569. 0x96, 0x96, 0x96 },
  570. .reqs = { 0x19, 0x17, 0x18, 0x01,
  571. 0x1F, 0x15, 0x3A },
  572. .vals = { 0x3F000000, 0x42A00000, 0x00000000,
  573. 0x00000000, 0x00000000, 0x00000000,
  574. 0x00000000 }
  575. },
  576. { .name = "Headphone",
  577. .commands = 7,
  578. .mids = { 0x96, 0x96, 0x96, 0x8F,
  579. 0x96, 0x96, 0x96 },
  580. .reqs = { 0x19, 0x17, 0x18, 0x01,
  581. 0x1F, 0x15, 0x3A },
  582. .vals = { 0x3F000000, 0x42A00000, 0x00000000,
  583. 0x00000000, 0x00000000, 0x00000000,
  584. 0x00000000 }
  585. },
  586. { .name = "Surround",
  587. .commands = 8,
  588. .mids = { 0x96, 0x8F, 0x96, 0x96,
  589. 0x96, 0x96, 0x96, 0x96 },
  590. .reqs = { 0x18, 0x01, 0x1F, 0x15,
  591. 0x3A, 0x1A, 0x1B, 0x1C },
  592. .vals = { 0x00000000, 0x00000000, 0x00000000,
  593. 0x00000000, 0x00000000, 0x00000000,
  594. 0x00000000, 0x00000000 }
  595. }
  596. };
  597. /*
  598. * DSP volume setting structs. Req 1 is left volume, req 2 is right volume,
  599. * and I don't know what the third req is, but it's always zero. I assume it's
  600. * some sort of update or set command to tell the DSP there's new volume info.
  601. */
  602. #define DSP_VOL_OUT 0
  603. #define DSP_VOL_IN 1
  604. struct ct_dsp_volume_ctl {
  605. hda_nid_t vnid;
  606. int mid; /* module ID*/
  607. unsigned int reqs[3]; /* scp req ID */
  608. };
  609. static const struct ct_dsp_volume_ctl ca0132_alt_vol_ctls[] = {
  610. { .vnid = VNID_SPK,
  611. .mid = 0x32,
  612. .reqs = {3, 4, 2}
  613. },
  614. { .vnid = VNID_MIC,
  615. .mid = 0x37,
  616. .reqs = {2, 3, 1}
  617. }
  618. };
  619. enum hda_cmd_vendor_io {
  620. /* for DspIO node */
  621. VENDOR_DSPIO_SCP_WRITE_DATA_LOW = 0x000,
  622. VENDOR_DSPIO_SCP_WRITE_DATA_HIGH = 0x100,
  623. VENDOR_DSPIO_STATUS = 0xF01,
  624. VENDOR_DSPIO_SCP_POST_READ_DATA = 0x702,
  625. VENDOR_DSPIO_SCP_READ_DATA = 0xF02,
  626. VENDOR_DSPIO_DSP_INIT = 0x703,
  627. VENDOR_DSPIO_SCP_POST_COUNT_QUERY = 0x704,
  628. VENDOR_DSPIO_SCP_READ_COUNT = 0xF04,
  629. /* for ChipIO node */
  630. VENDOR_CHIPIO_ADDRESS_LOW = 0x000,
  631. VENDOR_CHIPIO_ADDRESS_HIGH = 0x100,
  632. VENDOR_CHIPIO_STREAM_FORMAT = 0x200,
  633. VENDOR_CHIPIO_DATA_LOW = 0x300,
  634. VENDOR_CHIPIO_DATA_HIGH = 0x400,
  635. VENDOR_CHIPIO_GET_PARAMETER = 0xF00,
  636. VENDOR_CHIPIO_STATUS = 0xF01,
  637. VENDOR_CHIPIO_HIC_POST_READ = 0x702,
  638. VENDOR_CHIPIO_HIC_READ_DATA = 0xF03,
  639. VENDOR_CHIPIO_8051_DATA_WRITE = 0x707,
  640. VENDOR_CHIPIO_8051_DATA_READ = 0xF07,
  641. VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE = 0x70A,
  642. VENDOR_CHIPIO_CT_EXTENSIONS_GET = 0xF0A,
  643. VENDOR_CHIPIO_PLL_PMU_WRITE = 0x70C,
  644. VENDOR_CHIPIO_PLL_PMU_READ = 0xF0C,
  645. VENDOR_CHIPIO_8051_ADDRESS_LOW = 0x70D,
  646. VENDOR_CHIPIO_8051_ADDRESS_HIGH = 0x70E,
  647. VENDOR_CHIPIO_FLAG_SET = 0x70F,
  648. VENDOR_CHIPIO_FLAGS_GET = 0xF0F,
  649. VENDOR_CHIPIO_PARAM_SET = 0x710,
  650. VENDOR_CHIPIO_PARAM_GET = 0xF10,
  651. VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET = 0x711,
  652. VENDOR_CHIPIO_PORT_ALLOC_SET = 0x712,
  653. VENDOR_CHIPIO_PORT_ALLOC_GET = 0xF12,
  654. VENDOR_CHIPIO_PORT_FREE_SET = 0x713,
  655. VENDOR_CHIPIO_PARAM_EX_ID_GET = 0xF17,
  656. VENDOR_CHIPIO_PARAM_EX_ID_SET = 0x717,
  657. VENDOR_CHIPIO_PARAM_EX_VALUE_GET = 0xF18,
  658. VENDOR_CHIPIO_PARAM_EX_VALUE_SET = 0x718,
  659. VENDOR_CHIPIO_DMIC_CTL_SET = 0x788,
  660. VENDOR_CHIPIO_DMIC_CTL_GET = 0xF88,
  661. VENDOR_CHIPIO_DMIC_PIN_SET = 0x789,
  662. VENDOR_CHIPIO_DMIC_PIN_GET = 0xF89,
  663. VENDOR_CHIPIO_DMIC_MCLK_SET = 0x78A,
  664. VENDOR_CHIPIO_DMIC_MCLK_GET = 0xF8A,
  665. VENDOR_CHIPIO_EAPD_SEL_SET = 0x78D
  666. };
  667. /*
  668. * Control flag IDs
  669. */
  670. enum control_flag_id {
  671. /* Connection manager stream setup is bypassed/enabled */
  672. CONTROL_FLAG_C_MGR = 0,
  673. /* DSP DMA is bypassed/enabled */
  674. CONTROL_FLAG_DMA = 1,
  675. /* 8051 'idle' mode is disabled/enabled */
  676. CONTROL_FLAG_IDLE_ENABLE = 2,
  677. /* Tracker for the SPDIF-in path is bypassed/enabled */
  678. CONTROL_FLAG_TRACKER = 3,
  679. /* DigitalOut to Spdif2Out connection is disabled/enabled */
  680. CONTROL_FLAG_SPDIF2OUT = 4,
  681. /* Digital Microphone is disabled/enabled */
  682. CONTROL_FLAG_DMIC = 5,
  683. /* ADC_B rate is 48 kHz/96 kHz */
  684. CONTROL_FLAG_ADC_B_96KHZ = 6,
  685. /* ADC_C rate is 48 kHz/96 kHz */
  686. CONTROL_FLAG_ADC_C_96KHZ = 7,
  687. /* DAC rate is 48 kHz/96 kHz (affects all DACs) */
  688. CONTROL_FLAG_DAC_96KHZ = 8,
  689. /* DSP rate is 48 kHz/96 kHz */
  690. CONTROL_FLAG_DSP_96KHZ = 9,
  691. /* SRC clock is 98 MHz/196 MHz (196 MHz forces rate to 96 KHz) */
  692. CONTROL_FLAG_SRC_CLOCK_196MHZ = 10,
  693. /* SRC rate is 48 kHz/96 kHz (48 kHz disabled when clock is 196 MHz) */
  694. CONTROL_FLAG_SRC_RATE_96KHZ = 11,
  695. /* Decode Loop (DSP->SRC->DSP) is disabled/enabled */
  696. CONTROL_FLAG_DECODE_LOOP = 12,
  697. /* De-emphasis filter on DAC-1 disabled/enabled */
  698. CONTROL_FLAG_DAC1_DEEMPHASIS = 13,
  699. /* De-emphasis filter on DAC-2 disabled/enabled */
  700. CONTROL_FLAG_DAC2_DEEMPHASIS = 14,
  701. /* De-emphasis filter on DAC-3 disabled/enabled */
  702. CONTROL_FLAG_DAC3_DEEMPHASIS = 15,
  703. /* High-pass filter on ADC_B disabled/enabled */
  704. CONTROL_FLAG_ADC_B_HIGH_PASS = 16,
  705. /* High-pass filter on ADC_C disabled/enabled */
  706. CONTROL_FLAG_ADC_C_HIGH_PASS = 17,
  707. /* Common mode on Port_A disabled/enabled */
  708. CONTROL_FLAG_PORT_A_COMMON_MODE = 18,
  709. /* Common mode on Port_D disabled/enabled */
  710. CONTROL_FLAG_PORT_D_COMMON_MODE = 19,
  711. /* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */
  712. CONTROL_FLAG_PORT_A_10KOHM_LOAD = 20,
  713. /* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */
  714. CONTROL_FLAG_PORT_D_10KOHM_LOAD = 21,
  715. /* ASI rate is 48kHz/96kHz */
  716. CONTROL_FLAG_ASI_96KHZ = 22,
  717. /* DAC power settings able to control attached ports no/yes */
  718. CONTROL_FLAG_DACS_CONTROL_PORTS = 23,
  719. /* Clock Stop OK reporting is disabled/enabled */
  720. CONTROL_FLAG_CONTROL_STOP_OK_ENABLE = 24,
  721. /* Number of control flags */
  722. CONTROL_FLAGS_MAX = (CONTROL_FLAG_CONTROL_STOP_OK_ENABLE+1)
  723. };
  724. /*
  725. * Control parameter IDs
  726. */
  727. enum control_param_id {
  728. /* 0: None, 1: Mic1In*/
  729. CONTROL_PARAM_VIP_SOURCE = 1,
  730. /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */
  731. CONTROL_PARAM_SPDIF1_SOURCE = 2,
  732. /* Port A output stage gain setting to use when 16 Ohm output
  733. * impedance is selected*/
  734. CONTROL_PARAM_PORTA_160OHM_GAIN = 8,
  735. /* Port D output stage gain setting to use when 16 Ohm output
  736. * impedance is selected*/
  737. CONTROL_PARAM_PORTD_160OHM_GAIN = 10,
  738. /* Stream Control */
  739. /* Select stream with the given ID */
  740. CONTROL_PARAM_STREAM_ID = 24,
  741. /* Source connection point for the selected stream */
  742. CONTROL_PARAM_STREAM_SOURCE_CONN_POINT = 25,
  743. /* Destination connection point for the selected stream */
  744. CONTROL_PARAM_STREAM_DEST_CONN_POINT = 26,
  745. /* Number of audio channels in the selected stream */
  746. CONTROL_PARAM_STREAMS_CHANNELS = 27,
  747. /*Enable control for the selected stream */
  748. CONTROL_PARAM_STREAM_CONTROL = 28,
  749. /* Connection Point Control */
  750. /* Select connection point with the given ID */
  751. CONTROL_PARAM_CONN_POINT_ID = 29,
  752. /* Connection point sample rate */
  753. CONTROL_PARAM_CONN_POINT_SAMPLE_RATE = 30,
  754. /* Node Control */
  755. /* Select HDA node with the given ID */
  756. CONTROL_PARAM_NODE_ID = 31
  757. };
  758. /*
  759. * Dsp Io Status codes
  760. */
  761. enum hda_vendor_status_dspio {
  762. /* Success */
  763. VENDOR_STATUS_DSPIO_OK = 0x00,
  764. /* Busy, unable to accept new command, the host must retry */
  765. VENDOR_STATUS_DSPIO_BUSY = 0x01,
  766. /* SCP command queue is full */
  767. VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL = 0x02,
  768. /* SCP response queue is empty */
  769. VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03
  770. };
  771. /*
  772. * Chip Io Status codes
  773. */
  774. enum hda_vendor_status_chipio {
  775. /* Success */
  776. VENDOR_STATUS_CHIPIO_OK = 0x00,
  777. /* Busy, unable to accept new command, the host must retry */
  778. VENDOR_STATUS_CHIPIO_BUSY = 0x01
  779. };
  780. /*
  781. * CA0132 sample rate
  782. */
  783. enum ca0132_sample_rate {
  784. SR_6_000 = 0x00,
  785. SR_8_000 = 0x01,
  786. SR_9_600 = 0x02,
  787. SR_11_025 = 0x03,
  788. SR_16_000 = 0x04,
  789. SR_22_050 = 0x05,
  790. SR_24_000 = 0x06,
  791. SR_32_000 = 0x07,
  792. SR_44_100 = 0x08,
  793. SR_48_000 = 0x09,
  794. SR_88_200 = 0x0A,
  795. SR_96_000 = 0x0B,
  796. SR_144_000 = 0x0C,
  797. SR_176_400 = 0x0D,
  798. SR_192_000 = 0x0E,
  799. SR_384_000 = 0x0F,
  800. SR_COUNT = 0x10,
  801. SR_RATE_UNKNOWN = 0x1F
  802. };
  803. enum dsp_download_state {
  804. DSP_DOWNLOAD_FAILED = -1,
  805. DSP_DOWNLOAD_INIT = 0,
  806. DSP_DOWNLOADING = 1,
  807. DSP_DOWNLOADED = 2
  808. };
  809. /* retrieve parameters from hda format */
  810. #define get_hdafmt_chs(fmt) (fmt & 0xf)
  811. #define get_hdafmt_bits(fmt) ((fmt >> 4) & 0x7)
  812. #define get_hdafmt_rate(fmt) ((fmt >> 8) & 0x7f)
  813. #define get_hdafmt_type(fmt) ((fmt >> 15) & 0x1)
  814. /*
  815. * CA0132 specific
  816. */
  817. struct ca0132_spec {
  818. const struct snd_kcontrol_new *mixers[5];
  819. unsigned int num_mixers;
  820. const struct hda_verb *base_init_verbs;
  821. const struct hda_verb *base_exit_verbs;
  822. const struct hda_verb *chip_init_verbs;
  823. const struct hda_verb *desktop_init_verbs;
  824. struct hda_verb *spec_init_verbs;
  825. struct auto_pin_cfg autocfg;
  826. /* Nodes configurations */
  827. struct hda_multi_out multiout;
  828. hda_nid_t out_pins[AUTO_CFG_MAX_OUTS];
  829. hda_nid_t dacs[AUTO_CFG_MAX_OUTS];
  830. unsigned int num_outputs;
  831. hda_nid_t input_pins[AUTO_PIN_LAST];
  832. hda_nid_t adcs[AUTO_PIN_LAST];
  833. hda_nid_t dig_out;
  834. hda_nid_t dig_in;
  835. unsigned int num_inputs;
  836. hda_nid_t shared_mic_nid;
  837. hda_nid_t shared_out_nid;
  838. hda_nid_t unsol_tag_hp;
  839. hda_nid_t unsol_tag_front_hp; /* for desktop ca0132 codecs */
  840. hda_nid_t unsol_tag_amic1;
  841. /* chip access */
  842. struct mutex chipio_mutex; /* chip access mutex */
  843. u32 curr_chip_addx;
  844. /* DSP download related */
  845. enum dsp_download_state dsp_state;
  846. unsigned int dsp_stream_id;
  847. unsigned int wait_scp;
  848. unsigned int wait_scp_header;
  849. unsigned int wait_num_data;
  850. unsigned int scp_resp_header;
  851. unsigned int scp_resp_data[4];
  852. unsigned int scp_resp_count;
  853. bool alt_firmware_present;
  854. bool startup_check_entered;
  855. bool dsp_reload;
  856. /* mixer and effects related */
  857. unsigned char dmic_ctl;
  858. int cur_out_type;
  859. int cur_mic_type;
  860. long vnode_lvol[VNODES_COUNT];
  861. long vnode_rvol[VNODES_COUNT];
  862. long vnode_lswitch[VNODES_COUNT];
  863. long vnode_rswitch[VNODES_COUNT];
  864. long effects_switch[EFFECTS_COUNT];
  865. long voicefx_val;
  866. long cur_mic_boost;
  867. /* ca0132_alt control related values */
  868. unsigned char in_enum_val;
  869. unsigned char out_enum_val;
  870. unsigned char mic_boost_enum_val;
  871. unsigned char smart_volume_setting;
  872. long fx_ctl_val[EFFECT_LEVEL_SLIDERS];
  873. long xbass_xover_freq;
  874. long eq_preset_val;
  875. unsigned int tlv[4];
  876. struct hda_vmaster_mute_hook vmaster_mute;
  877. struct hda_codec *codec;
  878. struct delayed_work unsol_hp_work;
  879. int quirk;
  880. #ifdef ENABLE_TUNING_CONTROLS
  881. long cur_ctl_vals[TUNING_CTLS_COUNT];
  882. #endif
  883. /*
  884. * The Recon3D, Sound Blaster Z, Sound Blaster ZxR, and Sound Blaster
  885. * AE-5 all use PCI region 2 to toggle GPIO and other currently unknown
  886. * things.
  887. */
  888. bool use_pci_mmio;
  889. void __iomem *mem_base;
  890. /*
  891. * Whether or not to use the alt functions like alt_select_out,
  892. * alt_select_in, etc. Only used on desktop codecs for now, because of
  893. * surround sound support.
  894. */
  895. bool use_alt_functions;
  896. /*
  897. * Whether or not to use alt controls: volume effect sliders, EQ
  898. * presets, smart volume presets, and new control names with FX prefix.
  899. * Renames PlayEnhancement and CrystalVoice too.
  900. */
  901. bool use_alt_controls;
  902. };
  903. /*
  904. * CA0132 quirks table
  905. */
  906. enum {
  907. QUIRK_NONE,
  908. QUIRK_ALIENWARE,
  909. QUIRK_ALIENWARE_M17XR4,
  910. QUIRK_SBZ,
  911. QUIRK_R3DI,
  912. QUIRK_R3D,
  913. };
  914. static const struct hda_pintbl alienware_pincfgs[] = {
  915. { 0x0b, 0x90170110 }, /* Builtin Speaker */
  916. { 0x0c, 0x411111f0 }, /* N/A */
  917. { 0x0d, 0x411111f0 }, /* N/A */
  918. { 0x0e, 0x411111f0 }, /* N/A */
  919. { 0x0f, 0x0321101f }, /* HP */
  920. { 0x10, 0x411111f0 }, /* Headset? disabled for now */
  921. { 0x11, 0x03a11021 }, /* Mic */
  922. { 0x12, 0xd5a30140 }, /* Builtin Mic */
  923. { 0x13, 0x411111f0 }, /* N/A */
  924. { 0x18, 0x411111f0 }, /* N/A */
  925. {}
  926. };
  927. /* Sound Blaster Z pin configs taken from Windows Driver */
  928. static const struct hda_pintbl sbz_pincfgs[] = {
  929. { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */
  930. { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
  931. { 0x0d, 0x014510f0 }, /* Digital Out */
  932. { 0x0e, 0x01c510f0 }, /* SPDIF In */
  933. { 0x0f, 0x0221701f }, /* Port A -- BackPanel HP */
  934. { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */
  935. { 0x11, 0x01017014 }, /* Port B -- LineMicIn2 / Rear L/R */
  936. { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */
  937. { 0x13, 0x908700f0 }, /* What U Hear In*/
  938. { 0x18, 0x50d000f0 }, /* N/A */
  939. {}
  940. };
  941. /* Recon3D pin configs taken from Windows Driver */
  942. static const struct hda_pintbl r3d_pincfgs[] = {
  943. { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */
  944. { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
  945. { 0x0d, 0x014510f0 }, /* Digital Out */
  946. { 0x0e, 0x01c520f0 }, /* SPDIF In */
  947. { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */
  948. { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */
  949. { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */
  950. { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */
  951. { 0x13, 0x908700f0 }, /* What U Hear In*/
  952. { 0x18, 0x50d000f0 }, /* N/A */
  953. {}
  954. };
  955. /* Recon3D integrated pin configs taken from Windows Driver */
  956. static const struct hda_pintbl r3di_pincfgs[] = {
  957. { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */
  958. { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
  959. { 0x0d, 0x014510f0 }, /* Digital Out */
  960. { 0x0e, 0x41c520f0 }, /* SPDIF In */
  961. { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */
  962. { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */
  963. { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */
  964. { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */
  965. { 0x13, 0x908700f0 }, /* What U Hear In*/
  966. { 0x18, 0x500000f0 }, /* N/A */
  967. {}
  968. };
  969. static const struct snd_pci_quirk ca0132_quirks[] = {
  970. SND_PCI_QUIRK(0x1028, 0x057b, "Alienware M17x R4", QUIRK_ALIENWARE_M17XR4),
  971. SND_PCI_QUIRK(0x1028, 0x0685, "Alienware 15 2015", QUIRK_ALIENWARE),
  972. SND_PCI_QUIRK(0x1028, 0x0688, "Alienware 17 2015", QUIRK_ALIENWARE),
  973. SND_PCI_QUIRK(0x1028, 0x0708, "Alienware 15 R2 2016", QUIRK_ALIENWARE),
  974. SND_PCI_QUIRK(0x1102, 0x0010, "Sound Blaster Z", QUIRK_SBZ),
  975. SND_PCI_QUIRK(0x1102, 0x0023, "Sound Blaster Z", QUIRK_SBZ),
  976. SND_PCI_QUIRK(0x1458, 0xA016, "Recon3Di", QUIRK_R3DI),
  977. SND_PCI_QUIRK(0x1458, 0xA026, "Gigabyte G1.Sniper Z97", QUIRK_R3DI),
  978. SND_PCI_QUIRK(0x1458, 0xA036, "Gigabyte GA-Z170X-Gaming 7", QUIRK_R3DI),
  979. SND_PCI_QUIRK(0x1102, 0x0013, "Recon3D", QUIRK_R3D),
  980. {}
  981. };
  982. /*
  983. * CA0132 codec access
  984. */
  985. static unsigned int codec_send_command(struct hda_codec *codec, hda_nid_t nid,
  986. unsigned int verb, unsigned int parm, unsigned int *res)
  987. {
  988. unsigned int response;
  989. response = snd_hda_codec_read(codec, nid, 0, verb, parm);
  990. *res = response;
  991. return ((response == -1) ? -1 : 0);
  992. }
  993. static int codec_set_converter_format(struct hda_codec *codec, hda_nid_t nid,
  994. unsigned short converter_format, unsigned int *res)
  995. {
  996. return codec_send_command(codec, nid, VENDOR_CHIPIO_STREAM_FORMAT,
  997. converter_format & 0xffff, res);
  998. }
  999. static int codec_set_converter_stream_channel(struct hda_codec *codec,
  1000. hda_nid_t nid, unsigned char stream,
  1001. unsigned char channel, unsigned int *res)
  1002. {
  1003. unsigned char converter_stream_channel = 0;
  1004. converter_stream_channel = (stream << 4) | (channel & 0x0f);
  1005. return codec_send_command(codec, nid, AC_VERB_SET_CHANNEL_STREAMID,
  1006. converter_stream_channel, res);
  1007. }
  1008. /* Chip access helper function */
  1009. static int chipio_send(struct hda_codec *codec,
  1010. unsigned int reg,
  1011. unsigned int data)
  1012. {
  1013. unsigned int res;
  1014. unsigned long timeout = jiffies + msecs_to_jiffies(1000);
  1015. /* send bits of data specified by reg */
  1016. do {
  1017. res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
  1018. reg, data);
  1019. if (res == VENDOR_STATUS_CHIPIO_OK)
  1020. return 0;
  1021. msleep(20);
  1022. } while (time_before(jiffies, timeout));
  1023. return -EIO;
  1024. }
  1025. /*
  1026. * Write chip address through the vendor widget -- NOT protected by the Mutex!
  1027. */
  1028. static int chipio_write_address(struct hda_codec *codec,
  1029. unsigned int chip_addx)
  1030. {
  1031. struct ca0132_spec *spec = codec->spec;
  1032. int res;
  1033. if (spec->curr_chip_addx == chip_addx)
  1034. return 0;
  1035. /* send low 16 bits of the address */
  1036. res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW,
  1037. chip_addx & 0xffff);
  1038. if (res != -EIO) {
  1039. /* send high 16 bits of the address */
  1040. res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH,
  1041. chip_addx >> 16);
  1042. }
  1043. spec->curr_chip_addx = (res < 0) ? ~0U : chip_addx;
  1044. return res;
  1045. }
  1046. /*
  1047. * Write data through the vendor widget -- NOT protected by the Mutex!
  1048. */
  1049. static int chipio_write_data(struct hda_codec *codec, unsigned int data)
  1050. {
  1051. struct ca0132_spec *spec = codec->spec;
  1052. int res;
  1053. /* send low 16 bits of the data */
  1054. res = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff);
  1055. if (res != -EIO) {
  1056. /* send high 16 bits of the data */
  1057. res = chipio_send(codec, VENDOR_CHIPIO_DATA_HIGH,
  1058. data >> 16);
  1059. }
  1060. /*If no error encountered, automatically increment the address
  1061. as per chip behaviour*/
  1062. spec->curr_chip_addx = (res != -EIO) ?
  1063. (spec->curr_chip_addx + 4) : ~0U;
  1064. return res;
  1065. }
  1066. /*
  1067. * Write multiple data through the vendor widget -- NOT protected by the Mutex!
  1068. */
  1069. static int chipio_write_data_multiple(struct hda_codec *codec,
  1070. const u32 *data,
  1071. unsigned int count)
  1072. {
  1073. int status = 0;
  1074. if (data == NULL) {
  1075. codec_dbg(codec, "chipio_write_data null ptr\n");
  1076. return -EINVAL;
  1077. }
  1078. while ((count-- != 0) && (status == 0))
  1079. status = chipio_write_data(codec, *data++);
  1080. return status;
  1081. }
  1082. /*
  1083. * Read data through the vendor widget -- NOT protected by the Mutex!
  1084. */
  1085. static int chipio_read_data(struct hda_codec *codec, unsigned int *data)
  1086. {
  1087. struct ca0132_spec *spec = codec->spec;
  1088. int res;
  1089. /* post read */
  1090. res = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0);
  1091. if (res != -EIO) {
  1092. /* read status */
  1093. res = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
  1094. }
  1095. if (res != -EIO) {
  1096. /* read data */
  1097. *data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
  1098. VENDOR_CHIPIO_HIC_READ_DATA,
  1099. 0);
  1100. }
  1101. /*If no error encountered, automatically increment the address
  1102. as per chip behaviour*/
  1103. spec->curr_chip_addx = (res != -EIO) ?
  1104. (spec->curr_chip_addx + 4) : ~0U;
  1105. return res;
  1106. }
  1107. /*
  1108. * Write given value to the given address through the chip I/O widget.
  1109. * protected by the Mutex
  1110. */
  1111. static int chipio_write(struct hda_codec *codec,
  1112. unsigned int chip_addx, const unsigned int data)
  1113. {
  1114. struct ca0132_spec *spec = codec->spec;
  1115. int err;
  1116. mutex_lock(&spec->chipio_mutex);
  1117. /* write the address, and if successful proceed to write data */
  1118. err = chipio_write_address(codec, chip_addx);
  1119. if (err < 0)
  1120. goto exit;
  1121. err = chipio_write_data(codec, data);
  1122. if (err < 0)
  1123. goto exit;
  1124. exit:
  1125. mutex_unlock(&spec->chipio_mutex);
  1126. return err;
  1127. }
  1128. /*
  1129. * Write given value to the given address through the chip I/O widget.
  1130. * not protected by the Mutex
  1131. */
  1132. static int chipio_write_no_mutex(struct hda_codec *codec,
  1133. unsigned int chip_addx, const unsigned int data)
  1134. {
  1135. int err;
  1136. /* write the address, and if successful proceed to write data */
  1137. err = chipio_write_address(codec, chip_addx);
  1138. if (err < 0)
  1139. goto exit;
  1140. err = chipio_write_data(codec, data);
  1141. if (err < 0)
  1142. goto exit;
  1143. exit:
  1144. return err;
  1145. }
  1146. /*
  1147. * Write multiple values to the given address through the chip I/O widget.
  1148. * protected by the Mutex
  1149. */
  1150. static int chipio_write_multiple(struct hda_codec *codec,
  1151. u32 chip_addx,
  1152. const u32 *data,
  1153. unsigned int count)
  1154. {
  1155. struct ca0132_spec *spec = codec->spec;
  1156. int status;
  1157. mutex_lock(&spec->chipio_mutex);
  1158. status = chipio_write_address(codec, chip_addx);
  1159. if (status < 0)
  1160. goto error;
  1161. status = chipio_write_data_multiple(codec, data, count);
  1162. error:
  1163. mutex_unlock(&spec->chipio_mutex);
  1164. return status;
  1165. }
  1166. /*
  1167. * Read the given address through the chip I/O widget
  1168. * protected by the Mutex
  1169. */
  1170. static int chipio_read(struct hda_codec *codec,
  1171. unsigned int chip_addx, unsigned int *data)
  1172. {
  1173. struct ca0132_spec *spec = codec->spec;
  1174. int err;
  1175. mutex_lock(&spec->chipio_mutex);
  1176. /* write the address, and if successful proceed to write data */
  1177. err = chipio_write_address(codec, chip_addx);
  1178. if (err < 0)
  1179. goto exit;
  1180. err = chipio_read_data(codec, data);
  1181. if (err < 0)
  1182. goto exit;
  1183. exit:
  1184. mutex_unlock(&spec->chipio_mutex);
  1185. return err;
  1186. }
  1187. /*
  1188. * Set chip control flags through the chip I/O widget.
  1189. */
  1190. static void chipio_set_control_flag(struct hda_codec *codec,
  1191. enum control_flag_id flag_id,
  1192. bool flag_state)
  1193. {
  1194. unsigned int val;
  1195. unsigned int flag_bit;
  1196. flag_bit = (flag_state ? 1 : 0);
  1197. val = (flag_bit << 7) | (flag_id);
  1198. snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
  1199. VENDOR_CHIPIO_FLAG_SET, val);
  1200. }
  1201. /*
  1202. * Set chip parameters through the chip I/O widget.
  1203. */
  1204. static void chipio_set_control_param(struct hda_codec *codec,
  1205. enum control_param_id param_id, int param_val)
  1206. {
  1207. struct ca0132_spec *spec = codec->spec;
  1208. int val;
  1209. if ((param_id < 32) && (param_val < 8)) {
  1210. val = (param_val << 5) | (param_id);
  1211. snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
  1212. VENDOR_CHIPIO_PARAM_SET, val);
  1213. } else {
  1214. mutex_lock(&spec->chipio_mutex);
  1215. if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
  1216. snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
  1217. VENDOR_CHIPIO_PARAM_EX_ID_SET,
  1218. param_id);
  1219. snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
  1220. VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
  1221. param_val);
  1222. }
  1223. mutex_unlock(&spec->chipio_mutex);
  1224. }
  1225. }
  1226. /*
  1227. * Set chip parameters through the chip I/O widget. NO MUTEX.
  1228. */
  1229. static void chipio_set_control_param_no_mutex(struct hda_codec *codec,
  1230. enum control_param_id param_id, int param_val)
  1231. {
  1232. int val;
  1233. if ((param_id < 32) && (param_val < 8)) {
  1234. val = (param_val << 5) | (param_id);
  1235. snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
  1236. VENDOR_CHIPIO_PARAM_SET, val);
  1237. } else {
  1238. if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
  1239. snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
  1240. VENDOR_CHIPIO_PARAM_EX_ID_SET,
  1241. param_id);
  1242. snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
  1243. VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
  1244. param_val);
  1245. }
  1246. }
  1247. }
  1248. /*
  1249. * Connect stream to a source point, and then connect
  1250. * that source point to a destination point.
  1251. */
  1252. static void chipio_set_stream_source_dest(struct hda_codec *codec,
  1253. int streamid, int source_point, int dest_point)
  1254. {
  1255. chipio_set_control_param_no_mutex(codec,
  1256. CONTROL_PARAM_STREAM_ID, streamid);
  1257. chipio_set_control_param_no_mutex(codec,
  1258. CONTROL_PARAM_STREAM_SOURCE_CONN_POINT, source_point);
  1259. chipio_set_control_param_no_mutex(codec,
  1260. CONTROL_PARAM_STREAM_DEST_CONN_POINT, dest_point);
  1261. }
  1262. /*
  1263. * Set number of channels in the selected stream.
  1264. */
  1265. static void chipio_set_stream_channels(struct hda_codec *codec,
  1266. int streamid, unsigned int channels)
  1267. {
  1268. chipio_set_control_param_no_mutex(codec,
  1269. CONTROL_PARAM_STREAM_ID, streamid);
  1270. chipio_set_control_param_no_mutex(codec,
  1271. CONTROL_PARAM_STREAMS_CHANNELS, channels);
  1272. }
  1273. /*
  1274. * Enable/Disable audio stream.
  1275. */
  1276. static void chipio_set_stream_control(struct hda_codec *codec,
  1277. int streamid, int enable)
  1278. {
  1279. chipio_set_control_param_no_mutex(codec,
  1280. CONTROL_PARAM_STREAM_ID, streamid);
  1281. chipio_set_control_param_no_mutex(codec,
  1282. CONTROL_PARAM_STREAM_CONTROL, enable);
  1283. }
  1284. /*
  1285. * Set sampling rate of the connection point. NO MUTEX.
  1286. */
  1287. static void chipio_set_conn_rate_no_mutex(struct hda_codec *codec,
  1288. int connid, enum ca0132_sample_rate rate)
  1289. {
  1290. chipio_set_control_param_no_mutex(codec,
  1291. CONTROL_PARAM_CONN_POINT_ID, connid);
  1292. chipio_set_control_param_no_mutex(codec,
  1293. CONTROL_PARAM_CONN_POINT_SAMPLE_RATE, rate);
  1294. }
  1295. /*
  1296. * Set sampling rate of the connection point.
  1297. */
  1298. static void chipio_set_conn_rate(struct hda_codec *codec,
  1299. int connid, enum ca0132_sample_rate rate)
  1300. {
  1301. chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_ID, connid);
  1302. chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_SAMPLE_RATE,
  1303. rate);
  1304. }
  1305. /*
  1306. * Enable clocks.
  1307. */
  1308. static void chipio_enable_clocks(struct hda_codec *codec)
  1309. {
  1310. struct ca0132_spec *spec = codec->spec;
  1311. mutex_lock(&spec->chipio_mutex);
  1312. snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
  1313. VENDOR_CHIPIO_8051_ADDRESS_LOW, 0);
  1314. snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
  1315. VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
  1316. snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
  1317. VENDOR_CHIPIO_8051_ADDRESS_LOW, 5);
  1318. snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
  1319. VENDOR_CHIPIO_PLL_PMU_WRITE, 0x0b);
  1320. snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
  1321. VENDOR_CHIPIO_8051_ADDRESS_LOW, 6);
  1322. snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
  1323. VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
  1324. mutex_unlock(&spec->chipio_mutex);
  1325. }
  1326. /*
  1327. * CA0132 DSP IO stuffs
  1328. */
  1329. static int dspio_send(struct hda_codec *codec, unsigned int reg,
  1330. unsigned int data)
  1331. {
  1332. int res;
  1333. unsigned long timeout = jiffies + msecs_to_jiffies(1000);
  1334. /* send bits of data specified by reg to dsp */
  1335. do {
  1336. res = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, reg, data);
  1337. if ((res >= 0) && (res != VENDOR_STATUS_DSPIO_BUSY))
  1338. return res;
  1339. msleep(20);
  1340. } while (time_before(jiffies, timeout));
  1341. return -EIO;
  1342. }
  1343. /*
  1344. * Wait for DSP to be ready for commands
  1345. */
  1346. static void dspio_write_wait(struct hda_codec *codec)
  1347. {
  1348. int status;
  1349. unsigned long timeout = jiffies + msecs_to_jiffies(1000);
  1350. do {
  1351. status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
  1352. VENDOR_DSPIO_STATUS, 0);
  1353. if ((status == VENDOR_STATUS_DSPIO_OK) ||
  1354. (status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY))
  1355. break;
  1356. msleep(1);
  1357. } while (time_before(jiffies, timeout));
  1358. }
  1359. /*
  1360. * Write SCP data to DSP
  1361. */
  1362. static int dspio_write(struct hda_codec *codec, unsigned int scp_data)
  1363. {
  1364. struct ca0132_spec *spec = codec->spec;
  1365. int status;
  1366. dspio_write_wait(codec);
  1367. mutex_lock(&spec->chipio_mutex);
  1368. status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_LOW,
  1369. scp_data & 0xffff);
  1370. if (status < 0)
  1371. goto error;
  1372. status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_HIGH,
  1373. scp_data >> 16);
  1374. if (status < 0)
  1375. goto error;
  1376. /* OK, now check if the write itself has executed*/
  1377. status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
  1378. VENDOR_DSPIO_STATUS, 0);
  1379. error:
  1380. mutex_unlock(&spec->chipio_mutex);
  1381. return (status == VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL) ?
  1382. -EIO : 0;
  1383. }
  1384. /*
  1385. * Write multiple SCP data to DSP
  1386. */
  1387. static int dspio_write_multiple(struct hda_codec *codec,
  1388. unsigned int *buffer, unsigned int size)
  1389. {
  1390. int status = 0;
  1391. unsigned int count;
  1392. if (buffer == NULL)
  1393. return -EINVAL;
  1394. count = 0;
  1395. while (count < size) {
  1396. status = dspio_write(codec, *buffer++);
  1397. if (status != 0)
  1398. break;
  1399. count++;
  1400. }
  1401. return status;
  1402. }
  1403. static int dspio_read(struct hda_codec *codec, unsigned int *data)
  1404. {
  1405. int status;
  1406. status = dspio_send(codec, VENDOR_DSPIO_SCP_POST_READ_DATA, 0);
  1407. if (status == -EIO)
  1408. return status;
  1409. status = dspio_send(codec, VENDOR_DSPIO_STATUS, 0);
  1410. if (status == -EIO ||
  1411. status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY)
  1412. return -EIO;
  1413. *data = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
  1414. VENDOR_DSPIO_SCP_READ_DATA, 0);
  1415. return 0;
  1416. }
  1417. static int dspio_read_multiple(struct hda_codec *codec, unsigned int *buffer,
  1418. unsigned int *buf_size, unsigned int size_count)
  1419. {
  1420. int status = 0;
  1421. unsigned int size = *buf_size;
  1422. unsigned int count;
  1423. unsigned int skip_count;
  1424. unsigned int dummy;
  1425. if (buffer == NULL)
  1426. return -1;
  1427. count = 0;
  1428. while (count < size && count < size_count) {
  1429. status = dspio_read(codec, buffer++);
  1430. if (status != 0)
  1431. break;
  1432. count++;
  1433. }
  1434. skip_count = count;
  1435. if (status == 0) {
  1436. while (skip_count < size) {
  1437. status = dspio_read(codec, &dummy);
  1438. if (status != 0)
  1439. break;
  1440. skip_count++;
  1441. }
  1442. }
  1443. *buf_size = count;
  1444. return status;
  1445. }
  1446. /*
  1447. * Construct the SCP header using corresponding fields
  1448. */
  1449. static inline unsigned int
  1450. make_scp_header(unsigned int target_id, unsigned int source_id,
  1451. unsigned int get_flag, unsigned int req,
  1452. unsigned int device_flag, unsigned int resp_flag,
  1453. unsigned int error_flag, unsigned int data_size)
  1454. {
  1455. unsigned int header = 0;
  1456. header = (data_size & 0x1f) << 27;
  1457. header |= (error_flag & 0x01) << 26;
  1458. header |= (resp_flag & 0x01) << 25;
  1459. header |= (device_flag & 0x01) << 24;
  1460. header |= (req & 0x7f) << 17;
  1461. header |= (get_flag & 0x01) << 16;
  1462. header |= (source_id & 0xff) << 8;
  1463. header |= target_id & 0xff;
  1464. return header;
  1465. }
  1466. /*
  1467. * Extract corresponding fields from SCP header
  1468. */
  1469. static inline void
  1470. extract_scp_header(unsigned int header,
  1471. unsigned int *target_id, unsigned int *source_id,
  1472. unsigned int *get_flag, unsigned int *req,
  1473. unsigned int *device_flag, unsigned int *resp_flag,
  1474. unsigned int *error_flag, unsigned int *data_size)
  1475. {
  1476. if (data_size)
  1477. *data_size = (header >> 27) & 0x1f;
  1478. if (error_flag)
  1479. *error_flag = (header >> 26) & 0x01;
  1480. if (resp_flag)
  1481. *resp_flag = (header >> 25) & 0x01;
  1482. if (device_flag)
  1483. *device_flag = (header >> 24) & 0x01;
  1484. if (req)
  1485. *req = (header >> 17) & 0x7f;
  1486. if (get_flag)
  1487. *get_flag = (header >> 16) & 0x01;
  1488. if (source_id)
  1489. *source_id = (header >> 8) & 0xff;
  1490. if (target_id)
  1491. *target_id = header & 0xff;
  1492. }
  1493. #define SCP_MAX_DATA_WORDS (16)
  1494. /* Structure to contain any SCP message */
  1495. struct scp_msg {
  1496. unsigned int hdr;
  1497. unsigned int data[SCP_MAX_DATA_WORDS];
  1498. };
  1499. static void dspio_clear_response_queue(struct hda_codec *codec)
  1500. {
  1501. unsigned int dummy = 0;
  1502. int status = -1;
  1503. /* clear all from the response queue */
  1504. do {
  1505. status = dspio_read(codec, &dummy);
  1506. } while (status == 0);
  1507. }
  1508. static int dspio_get_response_data(struct hda_codec *codec)
  1509. {
  1510. struct ca0132_spec *spec = codec->spec;
  1511. unsigned int data = 0;
  1512. unsigned int count;
  1513. if (dspio_read(codec, &data) < 0)
  1514. return -EIO;
  1515. if ((data & 0x00ffffff) == spec->wait_scp_header) {
  1516. spec->scp_resp_header = data;
  1517. spec->scp_resp_count = data >> 27;
  1518. count = spec->wait_num_data;
  1519. dspio_read_multiple(codec, spec->scp_resp_data,
  1520. &spec->scp_resp_count, count);
  1521. return 0;
  1522. }
  1523. return -EIO;
  1524. }
  1525. /*
  1526. * Send SCP message to DSP
  1527. */
  1528. static int dspio_send_scp_message(struct hda_codec *codec,
  1529. unsigned char *send_buf,
  1530. unsigned int send_buf_size,
  1531. unsigned char *return_buf,
  1532. unsigned int return_buf_size,
  1533. unsigned int *bytes_returned)
  1534. {
  1535. struct ca0132_spec *spec = codec->spec;
  1536. int status = -1;
  1537. unsigned int scp_send_size = 0;
  1538. unsigned int total_size;
  1539. bool waiting_for_resp = false;
  1540. unsigned int header;
  1541. struct scp_msg *ret_msg;
  1542. unsigned int resp_src_id, resp_target_id;
  1543. unsigned int data_size, src_id, target_id, get_flag, device_flag;
  1544. if (bytes_returned)
  1545. *bytes_returned = 0;
  1546. /* get scp header from buffer */
  1547. header = *((unsigned int *)send_buf);
  1548. extract_scp_header(header, &target_id, &src_id, &get_flag, NULL,
  1549. &device_flag, NULL, NULL, &data_size);
  1550. scp_send_size = data_size + 1;
  1551. total_size = (scp_send_size * 4);
  1552. if (send_buf_size < total_size)
  1553. return -EINVAL;
  1554. if (get_flag || device_flag) {
  1555. if (!return_buf || return_buf_size < 4 || !bytes_returned)
  1556. return -EINVAL;
  1557. spec->wait_scp_header = *((unsigned int *)send_buf);
  1558. /* swap source id with target id */
  1559. resp_target_id = src_id;
  1560. resp_src_id = target_id;
  1561. spec->wait_scp_header &= 0xffff0000;
  1562. spec->wait_scp_header |= (resp_src_id << 8) | (resp_target_id);
  1563. spec->wait_num_data = return_buf_size/sizeof(unsigned int) - 1;
  1564. spec->wait_scp = 1;
  1565. waiting_for_resp = true;
  1566. }
  1567. status = dspio_write_multiple(codec, (unsigned int *)send_buf,
  1568. scp_send_size);
  1569. if (status < 0) {
  1570. spec->wait_scp = 0;
  1571. return status;
  1572. }
  1573. if (waiting_for_resp) {
  1574. unsigned long timeout = jiffies + msecs_to_jiffies(1000);
  1575. memset(return_buf, 0, return_buf_size);
  1576. do {
  1577. msleep(20);
  1578. } while (spec->wait_scp && time_before(jiffies, timeout));
  1579. waiting_for_resp = false;
  1580. if (!spec->wait_scp) {
  1581. ret_msg = (struct scp_msg *)return_buf;
  1582. memcpy(&ret_msg->hdr, &spec->scp_resp_header, 4);
  1583. memcpy(&ret_msg->data, spec->scp_resp_data,
  1584. spec->wait_num_data);
  1585. *bytes_returned = (spec->scp_resp_count + 1) * 4;
  1586. status = 0;
  1587. } else {
  1588. status = -EIO;
  1589. }
  1590. spec->wait_scp = 0;
  1591. }
  1592. return status;
  1593. }
  1594. /**
  1595. * Prepare and send the SCP message to DSP
  1596. * @codec: the HDA codec
  1597. * @mod_id: ID of the DSP module to send the command
  1598. * @req: ID of request to send to the DSP module
  1599. * @dir: SET or GET
  1600. * @data: pointer to the data to send with the request, request specific
  1601. * @len: length of the data, in bytes
  1602. * @reply: point to the buffer to hold data returned for a reply
  1603. * @reply_len: length of the reply buffer returned from GET
  1604. *
  1605. * Returns zero or a negative error code.
  1606. */
  1607. static int dspio_scp(struct hda_codec *codec,
  1608. int mod_id, int src_id, int req, int dir, const void *data,
  1609. unsigned int len, void *reply, unsigned int *reply_len)
  1610. {
  1611. int status = 0;
  1612. struct scp_msg scp_send, scp_reply;
  1613. unsigned int ret_bytes, send_size, ret_size;
  1614. unsigned int send_get_flag, reply_resp_flag, reply_error_flag;
  1615. unsigned int reply_data_size;
  1616. memset(&scp_send, 0, sizeof(scp_send));
  1617. memset(&scp_reply, 0, sizeof(scp_reply));
  1618. if ((len != 0 && data == NULL) || (len > SCP_MAX_DATA_WORDS))
  1619. return -EINVAL;
  1620. if (dir == SCP_GET && reply == NULL) {
  1621. codec_dbg(codec, "dspio_scp get but has no buffer\n");
  1622. return -EINVAL;
  1623. }
  1624. if (reply != NULL && (reply_len == NULL || (*reply_len == 0))) {
  1625. codec_dbg(codec, "dspio_scp bad resp buf len parms\n");
  1626. return -EINVAL;
  1627. }
  1628. scp_send.hdr = make_scp_header(mod_id, src_id, (dir == SCP_GET), req,
  1629. 0, 0, 0, len/sizeof(unsigned int));
  1630. if (data != NULL && len > 0) {
  1631. len = min((unsigned int)(sizeof(scp_send.data)), len);
  1632. memcpy(scp_send.data, data, len);
  1633. }
  1634. ret_bytes = 0;
  1635. send_size = sizeof(unsigned int) + len;
  1636. status = dspio_send_scp_message(codec, (unsigned char *)&scp_send,
  1637. send_size, (unsigned char *)&scp_reply,
  1638. sizeof(scp_reply), &ret_bytes);
  1639. if (status < 0) {
  1640. codec_dbg(codec, "dspio_scp: send scp msg failed\n");
  1641. return status;
  1642. }
  1643. /* extract send and reply headers members */
  1644. extract_scp_header(scp_send.hdr, NULL, NULL, &send_get_flag,
  1645. NULL, NULL, NULL, NULL, NULL);
  1646. extract_scp_header(scp_reply.hdr, NULL, NULL, NULL, NULL, NULL,
  1647. &reply_resp_flag, &reply_error_flag,
  1648. &reply_data_size);
  1649. if (!send_get_flag)
  1650. return 0;
  1651. if (reply_resp_flag && !reply_error_flag) {
  1652. ret_size = (ret_bytes - sizeof(scp_reply.hdr))
  1653. / sizeof(unsigned int);
  1654. if (*reply_len < ret_size*sizeof(unsigned int)) {
  1655. codec_dbg(codec, "reply too long for buf\n");
  1656. return -EINVAL;
  1657. } else if (ret_size != reply_data_size) {
  1658. codec_dbg(codec, "RetLen and HdrLen .NE.\n");
  1659. return -EINVAL;
  1660. } else if (!reply) {
  1661. codec_dbg(codec, "NULL reply\n");
  1662. return -EINVAL;
  1663. } else {
  1664. *reply_len = ret_size*sizeof(unsigned int);
  1665. memcpy(reply, scp_reply.data, *reply_len);
  1666. }
  1667. } else {
  1668. codec_dbg(codec, "reply ill-formed or errflag set\n");
  1669. return -EIO;
  1670. }
  1671. return status;
  1672. }
  1673. /*
  1674. * Set DSP parameters
  1675. */
  1676. static int dspio_set_param(struct hda_codec *codec, int mod_id,
  1677. int src_id, int req, const void *data, unsigned int len)
  1678. {
  1679. return dspio_scp(codec, mod_id, src_id, req, SCP_SET, data, len, NULL,
  1680. NULL);
  1681. }
  1682. static int dspio_set_uint_param(struct hda_codec *codec, int mod_id,
  1683. int req, const unsigned int data)
  1684. {
  1685. return dspio_set_param(codec, mod_id, 0x20, req, &data,
  1686. sizeof(unsigned int));
  1687. }
  1688. static int dspio_set_uint_param_no_source(struct hda_codec *codec, int mod_id,
  1689. int req, const unsigned int data)
  1690. {
  1691. return dspio_set_param(codec, mod_id, 0x00, req, &data,
  1692. sizeof(unsigned int));
  1693. }
  1694. /*
  1695. * Allocate a DSP DMA channel via an SCP message
  1696. */
  1697. static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan)
  1698. {
  1699. int status = 0;
  1700. unsigned int size = sizeof(dma_chan);
  1701. codec_dbg(codec, " dspio_alloc_dma_chan() -- begin\n");
  1702. status = dspio_scp(codec, MASTERCONTROL, 0x20,
  1703. MASTERCONTROL_ALLOC_DMA_CHAN, SCP_GET, NULL, 0,
  1704. dma_chan, &size);
  1705. if (status < 0) {
  1706. codec_dbg(codec, "dspio_alloc_dma_chan: SCP Failed\n");
  1707. return status;
  1708. }
  1709. if ((*dma_chan + 1) == 0) {
  1710. codec_dbg(codec, "no free dma channels to allocate\n");
  1711. return -EBUSY;
  1712. }
  1713. codec_dbg(codec, "dspio_alloc_dma_chan: chan=%d\n", *dma_chan);
  1714. codec_dbg(codec, " dspio_alloc_dma_chan() -- complete\n");
  1715. return status;
  1716. }
  1717. /*
  1718. * Free a DSP DMA via an SCP message
  1719. */
  1720. static int dspio_free_dma_chan(struct hda_codec *codec, unsigned int dma_chan)
  1721. {
  1722. int status = 0;
  1723. unsigned int dummy = 0;
  1724. codec_dbg(codec, " dspio_free_dma_chan() -- begin\n");
  1725. codec_dbg(codec, "dspio_free_dma_chan: chan=%d\n", dma_chan);
  1726. status = dspio_scp(codec, MASTERCONTROL, 0x20,
  1727. MASTERCONTROL_ALLOC_DMA_CHAN, SCP_SET, &dma_chan,
  1728. sizeof(dma_chan), NULL, &dummy);
  1729. if (status < 0) {
  1730. codec_dbg(codec, "dspio_free_dma_chan: SCP Failed\n");
  1731. return status;
  1732. }
  1733. codec_dbg(codec, " dspio_free_dma_chan() -- complete\n");
  1734. return status;
  1735. }
  1736. /*
  1737. * (Re)start the DSP
  1738. */
  1739. static int dsp_set_run_state(struct hda_codec *codec)
  1740. {
  1741. unsigned int dbg_ctrl_reg;
  1742. unsigned int halt_state;
  1743. int err;
  1744. err = chipio_read(codec, DSP_DBGCNTL_INST_OFFSET, &dbg_ctrl_reg);
  1745. if (err < 0)
  1746. return err;
  1747. halt_state = (dbg_ctrl_reg & DSP_DBGCNTL_STATE_MASK) >>
  1748. DSP_DBGCNTL_STATE_LOBIT;
  1749. if (halt_state != 0) {
  1750. dbg_ctrl_reg &= ~((halt_state << DSP_DBGCNTL_SS_LOBIT) &
  1751. DSP_DBGCNTL_SS_MASK);
  1752. err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
  1753. dbg_ctrl_reg);
  1754. if (err < 0)
  1755. return err;
  1756. dbg_ctrl_reg |= (halt_state << DSP_DBGCNTL_EXEC_LOBIT) &
  1757. DSP_DBGCNTL_EXEC_MASK;
  1758. err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
  1759. dbg_ctrl_reg);
  1760. if (err < 0)
  1761. return err;
  1762. }
  1763. return 0;
  1764. }
  1765. /*
  1766. * Reset the DSP
  1767. */
  1768. static int dsp_reset(struct hda_codec *codec)
  1769. {
  1770. unsigned int res;
  1771. int retry = 20;
  1772. codec_dbg(codec, "dsp_reset\n");
  1773. do {
  1774. res = dspio_send(codec, VENDOR_DSPIO_DSP_INIT, 0);
  1775. retry--;
  1776. } while (res == -EIO && retry);
  1777. if (!retry) {
  1778. codec_dbg(codec, "dsp_reset timeout\n");
  1779. return -EIO;
  1780. }
  1781. return 0;
  1782. }
  1783. /*
  1784. * Convert chip address to DSP address
  1785. */
  1786. static unsigned int dsp_chip_to_dsp_addx(unsigned int chip_addx,
  1787. bool *code, bool *yram)
  1788. {
  1789. *code = *yram = false;
  1790. if (UC_RANGE(chip_addx, 1)) {
  1791. *code = true;
  1792. return UC_OFF(chip_addx);
  1793. } else if (X_RANGE_ALL(chip_addx, 1)) {
  1794. return X_OFF(chip_addx);
  1795. } else if (Y_RANGE_ALL(chip_addx, 1)) {
  1796. *yram = true;
  1797. return Y_OFF(chip_addx);
  1798. }
  1799. return INVALID_CHIP_ADDRESS;
  1800. }
  1801. /*
  1802. * Check if the DSP DMA is active
  1803. */
  1804. static bool dsp_is_dma_active(struct hda_codec *codec, unsigned int dma_chan)
  1805. {
  1806. unsigned int dma_chnlstart_reg;
  1807. chipio_read(codec, DSPDMAC_CHNLSTART_INST_OFFSET, &dma_chnlstart_reg);
  1808. return ((dma_chnlstart_reg & (1 <<
  1809. (DSPDMAC_CHNLSTART_EN_LOBIT + dma_chan))) != 0);
  1810. }
  1811. static int dsp_dma_setup_common(struct hda_codec *codec,
  1812. unsigned int chip_addx,
  1813. unsigned int dma_chan,
  1814. unsigned int port_map_mask,
  1815. bool ovly)
  1816. {
  1817. int status = 0;
  1818. unsigned int chnl_prop;
  1819. unsigned int dsp_addx;
  1820. unsigned int active;
  1821. bool code, yram;
  1822. codec_dbg(codec, "-- dsp_dma_setup_common() -- Begin ---------\n");
  1823. if (dma_chan >= DSPDMAC_DMA_CFG_CHANNEL_COUNT) {
  1824. codec_dbg(codec, "dma chan num invalid\n");
  1825. return -EINVAL;
  1826. }
  1827. if (dsp_is_dma_active(codec, dma_chan)) {
  1828. codec_dbg(codec, "dma already active\n");
  1829. return -EBUSY;
  1830. }
  1831. dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
  1832. if (dsp_addx == INVALID_CHIP_ADDRESS) {
  1833. codec_dbg(codec, "invalid chip addr\n");
  1834. return -ENXIO;
  1835. }
  1836. chnl_prop = DSPDMAC_CHNLPROP_AC_MASK;
  1837. active = 0;
  1838. codec_dbg(codec, " dsp_dma_setup_common() start reg pgm\n");
  1839. if (ovly) {
  1840. status = chipio_read(codec, DSPDMAC_CHNLPROP_INST_OFFSET,
  1841. &chnl_prop);
  1842. if (status < 0) {
  1843. codec_dbg(codec, "read CHNLPROP Reg fail\n");
  1844. return status;
  1845. }
  1846. codec_dbg(codec, "dsp_dma_setup_common() Read CHNLPROP\n");
  1847. }
  1848. if (!code)
  1849. chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
  1850. else
  1851. chnl_prop |= (1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
  1852. chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_DCON_LOBIT + dma_chan));
  1853. status = chipio_write(codec, DSPDMAC_CHNLPROP_INST_OFFSET, chnl_prop);
  1854. if (status < 0) {
  1855. codec_dbg(codec, "write CHNLPROP Reg fail\n");
  1856. return status;
  1857. }
  1858. codec_dbg(codec, " dsp_dma_setup_common() Write CHNLPROP\n");
  1859. if (ovly) {
  1860. status = chipio_read(codec, DSPDMAC_ACTIVE_INST_OFFSET,
  1861. &active);
  1862. if (status < 0) {
  1863. codec_dbg(codec, "read ACTIVE Reg fail\n");
  1864. return status;
  1865. }
  1866. codec_dbg(codec, "dsp_dma_setup_common() Read ACTIVE\n");
  1867. }
  1868. active &= (~(1 << (DSPDMAC_ACTIVE_AAR_LOBIT + dma_chan))) &
  1869. DSPDMAC_ACTIVE_AAR_MASK;
  1870. status = chipio_write(codec, DSPDMAC_ACTIVE_INST_OFFSET, active);
  1871. if (status < 0) {
  1872. codec_dbg(codec, "write ACTIVE Reg fail\n");
  1873. return status;
  1874. }
  1875. codec_dbg(codec, " dsp_dma_setup_common() Write ACTIVE\n");
  1876. status = chipio_write(codec, DSPDMAC_AUDCHSEL_INST_OFFSET(dma_chan),
  1877. port_map_mask);
  1878. if (status < 0) {
  1879. codec_dbg(codec, "write AUDCHSEL Reg fail\n");
  1880. return status;
  1881. }
  1882. codec_dbg(codec, " dsp_dma_setup_common() Write AUDCHSEL\n");
  1883. status = chipio_write(codec, DSPDMAC_IRQCNT_INST_OFFSET(dma_chan),
  1884. DSPDMAC_IRQCNT_BICNT_MASK | DSPDMAC_IRQCNT_CICNT_MASK);
  1885. if (status < 0) {
  1886. codec_dbg(codec, "write IRQCNT Reg fail\n");
  1887. return status;
  1888. }
  1889. codec_dbg(codec, " dsp_dma_setup_common() Write IRQCNT\n");
  1890. codec_dbg(codec,
  1891. "ChipA=0x%x,DspA=0x%x,dmaCh=%u, "
  1892. "CHSEL=0x%x,CHPROP=0x%x,Active=0x%x\n",
  1893. chip_addx, dsp_addx, dma_chan,
  1894. port_map_mask, chnl_prop, active);
  1895. codec_dbg(codec, "-- dsp_dma_setup_common() -- Complete ------\n");
  1896. return 0;
  1897. }
  1898. /*
  1899. * Setup the DSP DMA per-transfer-specific registers
  1900. */
  1901. static int dsp_dma_setup(struct hda_codec *codec,
  1902. unsigned int chip_addx,
  1903. unsigned int count,
  1904. unsigned int dma_chan)
  1905. {
  1906. int status = 0;
  1907. bool code, yram;
  1908. unsigned int dsp_addx;
  1909. unsigned int addr_field;
  1910. unsigned int incr_field;
  1911. unsigned int base_cnt;
  1912. unsigned int cur_cnt;
  1913. unsigned int dma_cfg = 0;
  1914. unsigned int adr_ofs = 0;
  1915. unsigned int xfr_cnt = 0;
  1916. const unsigned int max_dma_count = 1 << (DSPDMAC_XFRCNT_BCNT_HIBIT -
  1917. DSPDMAC_XFRCNT_BCNT_LOBIT + 1);
  1918. codec_dbg(codec, "-- dsp_dma_setup() -- Begin ---------\n");
  1919. if (count > max_dma_count) {
  1920. codec_dbg(codec, "count too big\n");
  1921. return -EINVAL;
  1922. }
  1923. dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
  1924. if (dsp_addx == INVALID_CHIP_ADDRESS) {
  1925. codec_dbg(codec, "invalid chip addr\n");
  1926. return -ENXIO;
  1927. }
  1928. codec_dbg(codec, " dsp_dma_setup() start reg pgm\n");
  1929. addr_field = dsp_addx << DSPDMAC_DMACFG_DBADR_LOBIT;
  1930. incr_field = 0;
  1931. if (!code) {
  1932. addr_field <<= 1;
  1933. if (yram)
  1934. addr_field |= (1 << DSPDMAC_DMACFG_DBADR_LOBIT);
  1935. incr_field = (1 << DSPDMAC_DMACFG_AINCR_LOBIT);
  1936. }
  1937. dma_cfg = addr_field + incr_field;
  1938. status = chipio_write(codec, DSPDMAC_DMACFG_INST_OFFSET(dma_chan),
  1939. dma_cfg);
  1940. if (status < 0) {
  1941. codec_dbg(codec, "write DMACFG Reg fail\n");
  1942. return status;
  1943. }
  1944. codec_dbg(codec, " dsp_dma_setup() Write DMACFG\n");
  1945. adr_ofs = (count - 1) << (DSPDMAC_DSPADROFS_BOFS_LOBIT +
  1946. (code ? 0 : 1));
  1947. status = chipio_write(codec, DSPDMAC_DSPADROFS_INST_OFFSET(dma_chan),
  1948. adr_ofs);
  1949. if (status < 0) {
  1950. codec_dbg(codec, "write DSPADROFS Reg fail\n");
  1951. return status;
  1952. }
  1953. codec_dbg(codec, " dsp_dma_setup() Write DSPADROFS\n");
  1954. base_cnt = (count - 1) << DSPDMAC_XFRCNT_BCNT_LOBIT;
  1955. cur_cnt = (count - 1) << DSPDMAC_XFRCNT_CCNT_LOBIT;
  1956. xfr_cnt = base_cnt | cur_cnt;
  1957. status = chipio_write(codec,
  1958. DSPDMAC_XFRCNT_INST_OFFSET(dma_chan), xfr_cnt);
  1959. if (status < 0) {
  1960. codec_dbg(codec, "write XFRCNT Reg fail\n");
  1961. return status;
  1962. }
  1963. codec_dbg(codec, " dsp_dma_setup() Write XFRCNT\n");
  1964. codec_dbg(codec,
  1965. "ChipA=0x%x, cnt=0x%x, DMACFG=0x%x, "
  1966. "ADROFS=0x%x, XFRCNT=0x%x\n",
  1967. chip_addx, count, dma_cfg, adr_ofs, xfr_cnt);
  1968. codec_dbg(codec, "-- dsp_dma_setup() -- Complete ---------\n");
  1969. return 0;
  1970. }
  1971. /*
  1972. * Start the DSP DMA
  1973. */
  1974. static int dsp_dma_start(struct hda_codec *codec,
  1975. unsigned int dma_chan, bool ovly)
  1976. {
  1977. unsigned int reg = 0;
  1978. int status = 0;
  1979. codec_dbg(codec, "-- dsp_dma_start() -- Begin ---------\n");
  1980. if (ovly) {
  1981. status = chipio_read(codec,
  1982. DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
  1983. if (status < 0) {
  1984. codec_dbg(codec, "read CHNLSTART reg fail\n");
  1985. return status;
  1986. }
  1987. codec_dbg(codec, "-- dsp_dma_start() Read CHNLSTART\n");
  1988. reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
  1989. DSPDMAC_CHNLSTART_DIS_MASK);
  1990. }
  1991. status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
  1992. reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_EN_LOBIT)));
  1993. if (status < 0) {
  1994. codec_dbg(codec, "write CHNLSTART reg fail\n");
  1995. return status;
  1996. }
  1997. codec_dbg(codec, "-- dsp_dma_start() -- Complete ---------\n");
  1998. return status;
  1999. }
  2000. /*
  2001. * Stop the DSP DMA
  2002. */
  2003. static int dsp_dma_stop(struct hda_codec *codec,
  2004. unsigned int dma_chan, bool ovly)
  2005. {
  2006. unsigned int reg = 0;
  2007. int status = 0;
  2008. codec_dbg(codec, "-- dsp_dma_stop() -- Begin ---------\n");
  2009. if (ovly) {
  2010. status = chipio_read(codec,
  2011. DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
  2012. if (status < 0) {
  2013. codec_dbg(codec, "read CHNLSTART reg fail\n");
  2014. return status;
  2015. }
  2016. codec_dbg(codec, "-- dsp_dma_stop() Read CHNLSTART\n");
  2017. reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
  2018. DSPDMAC_CHNLSTART_DIS_MASK);
  2019. }
  2020. status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
  2021. reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_DIS_LOBIT)));
  2022. if (status < 0) {
  2023. codec_dbg(codec, "write CHNLSTART reg fail\n");
  2024. return status;
  2025. }
  2026. codec_dbg(codec, "-- dsp_dma_stop() -- Complete ---------\n");
  2027. return status;
  2028. }
  2029. /**
  2030. * Allocate router ports
  2031. *
  2032. * @codec: the HDA codec
  2033. * @num_chans: number of channels in the stream
  2034. * @ports_per_channel: number of ports per channel
  2035. * @start_device: start device
  2036. * @port_map: pointer to the port list to hold the allocated ports
  2037. *
  2038. * Returns zero or a negative error code.
  2039. */
  2040. static int dsp_allocate_router_ports(struct hda_codec *codec,
  2041. unsigned int num_chans,
  2042. unsigned int ports_per_channel,
  2043. unsigned int start_device,
  2044. unsigned int *port_map)
  2045. {
  2046. int status = 0;
  2047. int res;
  2048. u8 val;
  2049. status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
  2050. if (status < 0)
  2051. return status;
  2052. val = start_device << 6;
  2053. val |= (ports_per_channel - 1) << 4;
  2054. val |= num_chans - 1;
  2055. snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
  2056. VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET,
  2057. val);
  2058. snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
  2059. VENDOR_CHIPIO_PORT_ALLOC_SET,
  2060. MEM_CONNID_DSP);
  2061. status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
  2062. if (status < 0)
  2063. return status;
  2064. res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
  2065. VENDOR_CHIPIO_PORT_ALLOC_GET, 0);
  2066. *port_map = res;
  2067. return (res < 0) ? res : 0;
  2068. }
  2069. /*
  2070. * Free router ports
  2071. */
  2072. static int dsp_free_router_ports(struct hda_codec *codec)
  2073. {
  2074. int status = 0;
  2075. status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
  2076. if (status < 0)
  2077. return status;
  2078. snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
  2079. VENDOR_CHIPIO_PORT_FREE_SET,
  2080. MEM_CONNID_DSP);
  2081. status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
  2082. return status;
  2083. }
  2084. /*
  2085. * Allocate DSP ports for the download stream
  2086. */
  2087. static int dsp_allocate_ports(struct hda_codec *codec,
  2088. unsigned int num_chans,
  2089. unsigned int rate_multi, unsigned int *port_map)
  2090. {
  2091. int status;
  2092. codec_dbg(codec, " dsp_allocate_ports() -- begin\n");
  2093. if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
  2094. codec_dbg(codec, "bad rate multiple\n");
  2095. return -EINVAL;
  2096. }
  2097. status = dsp_allocate_router_ports(codec, num_chans,
  2098. rate_multi, 0, port_map);
  2099. codec_dbg(codec, " dsp_allocate_ports() -- complete\n");
  2100. return status;
  2101. }
  2102. static int dsp_allocate_ports_format(struct hda_codec *codec,
  2103. const unsigned short fmt,
  2104. unsigned int *port_map)
  2105. {
  2106. int status;
  2107. unsigned int num_chans;
  2108. unsigned int sample_rate_div = ((get_hdafmt_rate(fmt) >> 0) & 3) + 1;
  2109. unsigned int sample_rate_mul = ((get_hdafmt_rate(fmt) >> 3) & 3) + 1;
  2110. unsigned int rate_multi = sample_rate_mul / sample_rate_div;
  2111. if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
  2112. codec_dbg(codec, "bad rate multiple\n");
  2113. return -EINVAL;
  2114. }
  2115. num_chans = get_hdafmt_chs(fmt) + 1;
  2116. status = dsp_allocate_ports(codec, num_chans, rate_multi, port_map);
  2117. return status;
  2118. }
  2119. /*
  2120. * free DSP ports
  2121. */
  2122. static int dsp_free_ports(struct hda_codec *codec)
  2123. {
  2124. int status;
  2125. codec_dbg(codec, " dsp_free_ports() -- begin\n");
  2126. status = dsp_free_router_ports(codec);
  2127. if (status < 0) {
  2128. codec_dbg(codec, "free router ports fail\n");
  2129. return status;
  2130. }
  2131. codec_dbg(codec, " dsp_free_ports() -- complete\n");
  2132. return status;
  2133. }
  2134. /*
  2135. * HDA DMA engine stuffs for DSP code download
  2136. */
  2137. struct dma_engine {
  2138. struct hda_codec *codec;
  2139. unsigned short m_converter_format;
  2140. struct snd_dma_buffer *dmab;
  2141. unsigned int buf_size;
  2142. };
  2143. enum dma_state {
  2144. DMA_STATE_STOP = 0,
  2145. DMA_STATE_RUN = 1
  2146. };
  2147. static int dma_convert_to_hda_format(struct hda_codec *codec,
  2148. unsigned int sample_rate,
  2149. unsigned short channels,
  2150. unsigned short *hda_format)
  2151. {
  2152. unsigned int format_val;
  2153. format_val = snd_hdac_calc_stream_format(sample_rate,
  2154. channels, SNDRV_PCM_FORMAT_S32_LE, 32, 0);
  2155. if (hda_format)
  2156. *hda_format = (unsigned short)format_val;
  2157. return 0;
  2158. }
  2159. /*
  2160. * Reset DMA for DSP download
  2161. */
  2162. static int dma_reset(struct dma_engine *dma)
  2163. {
  2164. struct hda_codec *codec = dma->codec;
  2165. struct ca0132_spec *spec = codec->spec;
  2166. int status;
  2167. if (dma->dmab->area)
  2168. snd_hda_codec_load_dsp_cleanup(codec, dma->dmab);
  2169. status = snd_hda_codec_load_dsp_prepare(codec,
  2170. dma->m_converter_format,
  2171. dma->buf_size,
  2172. dma->dmab);
  2173. if (status < 0)
  2174. return status;
  2175. spec->dsp_stream_id = status;
  2176. return 0;
  2177. }
  2178. static int dma_set_state(struct dma_engine *dma, enum dma_state state)
  2179. {
  2180. bool cmd;
  2181. switch (state) {
  2182. case DMA_STATE_STOP:
  2183. cmd = false;
  2184. break;
  2185. case DMA_STATE_RUN:
  2186. cmd = true;
  2187. break;
  2188. default:
  2189. return 0;
  2190. }
  2191. snd_hda_codec_load_dsp_trigger(dma->codec, cmd);
  2192. return 0;
  2193. }
  2194. static unsigned int dma_get_buffer_size(struct dma_engine *dma)
  2195. {
  2196. return dma->dmab->bytes;
  2197. }
  2198. static unsigned char *dma_get_buffer_addr(struct dma_engine *dma)
  2199. {
  2200. return dma->dmab->area;
  2201. }
  2202. static int dma_xfer(struct dma_engine *dma,
  2203. const unsigned int *data,
  2204. unsigned int count)
  2205. {
  2206. memcpy(dma->dmab->area, data, count);
  2207. return 0;
  2208. }
  2209. static void dma_get_converter_format(
  2210. struct dma_engine *dma,
  2211. unsigned short *format)
  2212. {
  2213. if (format)
  2214. *format = dma->m_converter_format;
  2215. }
  2216. static unsigned int dma_get_stream_id(struct dma_engine *dma)
  2217. {
  2218. struct ca0132_spec *spec = dma->codec->spec;
  2219. return spec->dsp_stream_id;
  2220. }
  2221. struct dsp_image_seg {
  2222. u32 magic;
  2223. u32 chip_addr;
  2224. u32 count;
  2225. u32 data[0];
  2226. };
  2227. static const u32 g_magic_value = 0x4c46584d;
  2228. static const u32 g_chip_addr_magic_value = 0xFFFFFF01;
  2229. static bool is_valid(const struct dsp_image_seg *p)
  2230. {
  2231. return p->magic == g_magic_value;
  2232. }
  2233. static bool is_hci_prog_list_seg(const struct dsp_image_seg *p)
  2234. {
  2235. return g_chip_addr_magic_value == p->chip_addr;
  2236. }
  2237. static bool is_last(const struct dsp_image_seg *p)
  2238. {
  2239. return p->count == 0;
  2240. }
  2241. static size_t dsp_sizeof(const struct dsp_image_seg *p)
  2242. {
  2243. return sizeof(*p) + p->count*sizeof(u32);
  2244. }
  2245. static const struct dsp_image_seg *get_next_seg_ptr(
  2246. const struct dsp_image_seg *p)
  2247. {
  2248. return (struct dsp_image_seg *)((unsigned char *)(p) + dsp_sizeof(p));
  2249. }
  2250. /*
  2251. * CA0132 chip DSP transfer stuffs. For DSP download.
  2252. */
  2253. #define INVALID_DMA_CHANNEL (~0U)
  2254. /*
  2255. * Program a list of address/data pairs via the ChipIO widget.
  2256. * The segment data is in the format of successive pairs of words.
  2257. * These are repeated as indicated by the segment's count field.
  2258. */
  2259. static int dspxfr_hci_write(struct hda_codec *codec,
  2260. const struct dsp_image_seg *fls)
  2261. {
  2262. int status;
  2263. const u32 *data;
  2264. unsigned int count;
  2265. if (fls == NULL || fls->chip_addr != g_chip_addr_magic_value) {
  2266. codec_dbg(codec, "hci_write invalid params\n");
  2267. return -EINVAL;
  2268. }
  2269. count = fls->count;
  2270. data = (u32 *)(fls->data);
  2271. while (count >= 2) {
  2272. status = chipio_write(codec, data[0], data[1]);
  2273. if (status < 0) {
  2274. codec_dbg(codec, "hci_write chipio failed\n");
  2275. return status;
  2276. }
  2277. count -= 2;
  2278. data += 2;
  2279. }
  2280. return 0;
  2281. }
  2282. /**
  2283. * Write a block of data into DSP code or data RAM using pre-allocated
  2284. * DMA engine.
  2285. *
  2286. * @codec: the HDA codec
  2287. * @fls: pointer to a fast load image
  2288. * @reloc: Relocation address for loading single-segment overlays, or 0 for
  2289. * no relocation
  2290. * @dma_engine: pointer to DMA engine to be used for DSP download
  2291. * @dma_chan: The number of DMA channels used for DSP download
  2292. * @port_map_mask: port mapping
  2293. * @ovly: TRUE if overlay format is required
  2294. *
  2295. * Returns zero or a negative error code.
  2296. */
  2297. static int dspxfr_one_seg(struct hda_codec *codec,
  2298. const struct dsp_image_seg *fls,
  2299. unsigned int reloc,
  2300. struct dma_engine *dma_engine,
  2301. unsigned int dma_chan,
  2302. unsigned int port_map_mask,
  2303. bool ovly)
  2304. {
  2305. int status = 0;
  2306. bool comm_dma_setup_done = false;
  2307. const unsigned int *data;
  2308. unsigned int chip_addx;
  2309. unsigned int words_to_write;
  2310. unsigned int buffer_size_words;
  2311. unsigned char *buffer_addx;
  2312. unsigned short hda_format;
  2313. unsigned int sample_rate_div;
  2314. unsigned int sample_rate_mul;
  2315. unsigned int num_chans;
  2316. unsigned int hda_frame_size_words;
  2317. unsigned int remainder_words;
  2318. const u32 *data_remainder;
  2319. u32 chip_addx_remainder;
  2320. unsigned int run_size_words;
  2321. const struct dsp_image_seg *hci_write = NULL;
  2322. unsigned long timeout;
  2323. bool dma_active;
  2324. if (fls == NULL)
  2325. return -EINVAL;
  2326. if (is_hci_prog_list_seg(fls)) {
  2327. hci_write = fls;
  2328. fls = get_next_seg_ptr(fls);
  2329. }
  2330. if (hci_write && (!fls || is_last(fls))) {
  2331. codec_dbg(codec, "hci_write\n");
  2332. return dspxfr_hci_write(codec, hci_write);
  2333. }
  2334. if (fls == NULL || dma_engine == NULL || port_map_mask == 0) {
  2335. codec_dbg(codec, "Invalid Params\n");
  2336. return -EINVAL;
  2337. }
  2338. data = fls->data;
  2339. chip_addx = fls->chip_addr,
  2340. words_to_write = fls->count;
  2341. if (!words_to_write)
  2342. return hci_write ? dspxfr_hci_write(codec, hci_write) : 0;
  2343. if (reloc)
  2344. chip_addx = (chip_addx & (0xFFFF0000 << 2)) + (reloc << 2);
  2345. if (!UC_RANGE(chip_addx, words_to_write) &&
  2346. !X_RANGE_ALL(chip_addx, words_to_write) &&
  2347. !Y_RANGE_ALL(chip_addx, words_to_write)) {
  2348. codec_dbg(codec, "Invalid chip_addx Params\n");
  2349. return -EINVAL;
  2350. }
  2351. buffer_size_words = (unsigned int)dma_get_buffer_size(dma_engine) /
  2352. sizeof(u32);
  2353. buffer_addx = dma_get_buffer_addr(dma_engine);
  2354. if (buffer_addx == NULL) {
  2355. codec_dbg(codec, "dma_engine buffer NULL\n");
  2356. return -EINVAL;
  2357. }
  2358. dma_get_converter_format(dma_engine, &hda_format);
  2359. sample_rate_div = ((get_hdafmt_rate(hda_format) >> 0) & 3) + 1;
  2360. sample_rate_mul = ((get_hdafmt_rate(hda_format) >> 3) & 3) + 1;
  2361. num_chans = get_hdafmt_chs(hda_format) + 1;
  2362. hda_frame_size_words = ((sample_rate_div == 0) ? 0 :
  2363. (num_chans * sample_rate_mul / sample_rate_div));
  2364. if (hda_frame_size_words == 0) {
  2365. codec_dbg(codec, "frmsz zero\n");
  2366. return -EINVAL;
  2367. }
  2368. buffer_size_words = min(buffer_size_words,
  2369. (unsigned int)(UC_RANGE(chip_addx, 1) ?
  2370. 65536 : 32768));
  2371. buffer_size_words -= buffer_size_words % hda_frame_size_words;
  2372. codec_dbg(codec,
  2373. "chpadr=0x%08x frmsz=%u nchan=%u "
  2374. "rate_mul=%u div=%u bufsz=%u\n",
  2375. chip_addx, hda_frame_size_words, num_chans,
  2376. sample_rate_mul, sample_rate_div, buffer_size_words);
  2377. if (buffer_size_words < hda_frame_size_words) {
  2378. codec_dbg(codec, "dspxfr_one_seg:failed\n");
  2379. return -EINVAL;
  2380. }
  2381. remainder_words = words_to_write % hda_frame_size_words;
  2382. data_remainder = data;
  2383. chip_addx_remainder = chip_addx;
  2384. data += remainder_words;
  2385. chip_addx += remainder_words*sizeof(u32);
  2386. words_to_write -= remainder_words;
  2387. while (words_to_write != 0) {
  2388. run_size_words = min(buffer_size_words, words_to_write);
  2389. codec_dbg(codec, "dspxfr (seg loop)cnt=%u rs=%u remainder=%u\n",
  2390. words_to_write, run_size_words, remainder_words);
  2391. dma_xfer(dma_engine, data, run_size_words*sizeof(u32));
  2392. if (!comm_dma_setup_done) {
  2393. status = dsp_dma_stop(codec, dma_chan, ovly);
  2394. if (status < 0)
  2395. return status;
  2396. status = dsp_dma_setup_common(codec, chip_addx,
  2397. dma_chan, port_map_mask, ovly);
  2398. if (status < 0)
  2399. return status;
  2400. comm_dma_setup_done = true;
  2401. }
  2402. status = dsp_dma_setup(codec, chip_addx,
  2403. run_size_words, dma_chan);
  2404. if (status < 0)
  2405. return status;
  2406. status = dsp_dma_start(codec, dma_chan, ovly);
  2407. if (status < 0)
  2408. return status;
  2409. if (!dsp_is_dma_active(codec, dma_chan)) {
  2410. codec_dbg(codec, "dspxfr:DMA did not start\n");
  2411. return -EIO;
  2412. }
  2413. status = dma_set_state(dma_engine, DMA_STATE_RUN);
  2414. if (status < 0)
  2415. return status;
  2416. if (remainder_words != 0) {
  2417. status = chipio_write_multiple(codec,
  2418. chip_addx_remainder,
  2419. data_remainder,
  2420. remainder_words);
  2421. if (status < 0)
  2422. return status;
  2423. remainder_words = 0;
  2424. }
  2425. if (hci_write) {
  2426. status = dspxfr_hci_write(codec, hci_write);
  2427. if (status < 0)
  2428. return status;
  2429. hci_write = NULL;
  2430. }
  2431. timeout = jiffies + msecs_to_jiffies(2000);
  2432. do {
  2433. dma_active = dsp_is_dma_active(codec, dma_chan);
  2434. if (!dma_active)
  2435. break;
  2436. msleep(20);
  2437. } while (time_before(jiffies, timeout));
  2438. if (dma_active)
  2439. break;
  2440. codec_dbg(codec, "+++++ DMA complete\n");
  2441. dma_set_state(dma_engine, DMA_STATE_STOP);
  2442. status = dma_reset(dma_engine);
  2443. if (status < 0)
  2444. return status;
  2445. data += run_size_words;
  2446. chip_addx += run_size_words*sizeof(u32);
  2447. words_to_write -= run_size_words;
  2448. }
  2449. if (remainder_words != 0) {
  2450. status = chipio_write_multiple(codec, chip_addx_remainder,
  2451. data_remainder, remainder_words);
  2452. }
  2453. return status;
  2454. }
  2455. /**
  2456. * Write the entire DSP image of a DSP code/data overlay to DSP memories
  2457. *
  2458. * @codec: the HDA codec
  2459. * @fls_data: pointer to a fast load image
  2460. * @reloc: Relocation address for loading single-segment overlays, or 0 for
  2461. * no relocation
  2462. * @sample_rate: sampling rate of the stream used for DSP download
  2463. * @channels: channels of the stream used for DSP download
  2464. * @ovly: TRUE if overlay format is required
  2465. *
  2466. * Returns zero or a negative error code.
  2467. */
  2468. static int dspxfr_image(struct hda_codec *codec,
  2469. const struct dsp_image_seg *fls_data,
  2470. unsigned int reloc,
  2471. unsigned int sample_rate,
  2472. unsigned short channels,
  2473. bool ovly)
  2474. {
  2475. struct ca0132_spec *spec = codec->spec;
  2476. int status;
  2477. unsigned short hda_format = 0;
  2478. unsigned int response;
  2479. unsigned char stream_id = 0;
  2480. struct dma_engine *dma_engine;
  2481. unsigned int dma_chan;
  2482. unsigned int port_map_mask;
  2483. if (fls_data == NULL)
  2484. return -EINVAL;
  2485. dma_engine = kzalloc(sizeof(*dma_engine), GFP_KERNEL);
  2486. if (!dma_engine)
  2487. return -ENOMEM;
  2488. dma_engine->dmab = kzalloc(sizeof(*dma_engine->dmab), GFP_KERNEL);
  2489. if (!dma_engine->dmab) {
  2490. kfree(dma_engine);
  2491. return -ENOMEM;
  2492. }
  2493. dma_engine->codec = codec;
  2494. dma_convert_to_hda_format(codec, sample_rate, channels, &hda_format);
  2495. dma_engine->m_converter_format = hda_format;
  2496. dma_engine->buf_size = (ovly ? DSP_DMA_WRITE_BUFLEN_OVLY :
  2497. DSP_DMA_WRITE_BUFLEN_INIT) * 2;
  2498. dma_chan = ovly ? INVALID_DMA_CHANNEL : 0;
  2499. status = codec_set_converter_format(codec, WIDGET_CHIP_CTRL,
  2500. hda_format, &response);
  2501. if (status < 0) {
  2502. codec_dbg(codec, "set converter format fail\n");
  2503. goto exit;
  2504. }
  2505. status = snd_hda_codec_load_dsp_prepare(codec,
  2506. dma_engine->m_converter_format,
  2507. dma_engine->buf_size,
  2508. dma_engine->dmab);
  2509. if (status < 0)
  2510. goto exit;
  2511. spec->dsp_stream_id = status;
  2512. if (ovly) {
  2513. status = dspio_alloc_dma_chan(codec, &dma_chan);
  2514. if (status < 0) {
  2515. codec_dbg(codec, "alloc dmachan fail\n");
  2516. dma_chan = INVALID_DMA_CHANNEL;
  2517. goto exit;
  2518. }
  2519. }
  2520. port_map_mask = 0;
  2521. status = dsp_allocate_ports_format(codec, hda_format,
  2522. &port_map_mask);
  2523. if (status < 0) {
  2524. codec_dbg(codec, "alloc ports fail\n");
  2525. goto exit;
  2526. }
  2527. stream_id = dma_get_stream_id(dma_engine);
  2528. status = codec_set_converter_stream_channel(codec,
  2529. WIDGET_CHIP_CTRL, stream_id, 0, &response);
  2530. if (status < 0) {
  2531. codec_dbg(codec, "set stream chan fail\n");
  2532. goto exit;
  2533. }
  2534. while ((fls_data != NULL) && !is_last(fls_data)) {
  2535. if (!is_valid(fls_data)) {
  2536. codec_dbg(codec, "FLS check fail\n");
  2537. status = -EINVAL;
  2538. goto exit;
  2539. }
  2540. status = dspxfr_one_seg(codec, fls_data, reloc,
  2541. dma_engine, dma_chan,
  2542. port_map_mask, ovly);
  2543. if (status < 0)
  2544. break;
  2545. if (is_hci_prog_list_seg(fls_data))
  2546. fls_data = get_next_seg_ptr(fls_data);
  2547. if ((fls_data != NULL) && !is_last(fls_data))
  2548. fls_data = get_next_seg_ptr(fls_data);
  2549. }
  2550. if (port_map_mask != 0)
  2551. status = dsp_free_ports(codec);
  2552. if (status < 0)
  2553. goto exit;
  2554. status = codec_set_converter_stream_channel(codec,
  2555. WIDGET_CHIP_CTRL, 0, 0, &response);
  2556. exit:
  2557. if (ovly && (dma_chan != INVALID_DMA_CHANNEL))
  2558. dspio_free_dma_chan(codec, dma_chan);
  2559. if (dma_engine->dmab->area)
  2560. snd_hda_codec_load_dsp_cleanup(codec, dma_engine->dmab);
  2561. kfree(dma_engine->dmab);
  2562. kfree(dma_engine);
  2563. return status;
  2564. }
  2565. /*
  2566. * CA0132 DSP download stuffs.
  2567. */
  2568. static void dspload_post_setup(struct hda_codec *codec)
  2569. {
  2570. struct ca0132_spec *spec = codec->spec;
  2571. codec_dbg(codec, "---- dspload_post_setup ------\n");
  2572. if (!spec->use_alt_functions) {
  2573. /*set DSP speaker to 2.0 configuration*/
  2574. chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x18), 0x08080080);
  2575. chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x19), 0x3f800000);
  2576. /*update write pointer*/
  2577. chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x29), 0x00000002);
  2578. }
  2579. }
  2580. /**
  2581. * dspload_image - Download DSP from a DSP Image Fast Load structure.
  2582. *
  2583. * @codec: the HDA codec
  2584. * @fls: pointer to a fast load image
  2585. * @ovly: TRUE if overlay format is required
  2586. * @reloc: Relocation address for loading single-segment overlays, or 0 for
  2587. * no relocation
  2588. * @autostart: TRUE if DSP starts after loading; ignored if ovly is TRUE
  2589. * @router_chans: number of audio router channels to be allocated (0 means use
  2590. * internal defaults; max is 32)
  2591. *
  2592. * Download DSP from a DSP Image Fast Load structure. This structure is a
  2593. * linear, non-constant sized element array of structures, each of which
  2594. * contain the count of the data to be loaded, the data itself, and the
  2595. * corresponding starting chip address of the starting data location.
  2596. * Returns zero or a negative error code.
  2597. */
  2598. static int dspload_image(struct hda_codec *codec,
  2599. const struct dsp_image_seg *fls,
  2600. bool ovly,
  2601. unsigned int reloc,
  2602. bool autostart,
  2603. int router_chans)
  2604. {
  2605. int status = 0;
  2606. unsigned int sample_rate;
  2607. unsigned short channels;
  2608. codec_dbg(codec, "---- dspload_image begin ------\n");
  2609. if (router_chans == 0) {
  2610. if (!ovly)
  2611. router_chans = DMA_TRANSFER_FRAME_SIZE_NWORDS;
  2612. else
  2613. router_chans = DMA_OVERLAY_FRAME_SIZE_NWORDS;
  2614. }
  2615. sample_rate = 48000;
  2616. channels = (unsigned short)router_chans;
  2617. while (channels > 16) {
  2618. sample_rate *= 2;
  2619. channels /= 2;
  2620. }
  2621. do {
  2622. codec_dbg(codec, "Ready to program DMA\n");
  2623. if (!ovly)
  2624. status = dsp_reset(codec);
  2625. if (status < 0)
  2626. break;
  2627. codec_dbg(codec, "dsp_reset() complete\n");
  2628. status = dspxfr_image(codec, fls, reloc, sample_rate, channels,
  2629. ovly);
  2630. if (status < 0)
  2631. break;
  2632. codec_dbg(codec, "dspxfr_image() complete\n");
  2633. if (autostart && !ovly) {
  2634. dspload_post_setup(codec);
  2635. status = dsp_set_run_state(codec);
  2636. }
  2637. codec_dbg(codec, "LOAD FINISHED\n");
  2638. } while (0);
  2639. return status;
  2640. }
  2641. #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
  2642. static bool dspload_is_loaded(struct hda_codec *codec)
  2643. {
  2644. unsigned int data = 0;
  2645. int status = 0;
  2646. status = chipio_read(codec, 0x40004, &data);
  2647. if ((status < 0) || (data != 1))
  2648. return false;
  2649. return true;
  2650. }
  2651. #else
  2652. #define dspload_is_loaded(codec) false
  2653. #endif
  2654. static bool dspload_wait_loaded(struct hda_codec *codec)
  2655. {
  2656. unsigned long timeout = jiffies + msecs_to_jiffies(2000);
  2657. do {
  2658. if (dspload_is_loaded(codec)) {
  2659. codec_info(codec, "ca0132 DSP downloaded and running\n");
  2660. return true;
  2661. }
  2662. msleep(20);
  2663. } while (time_before(jiffies, timeout));
  2664. codec_err(codec, "ca0132 failed to download DSP\n");
  2665. return false;
  2666. }
  2667. /*
  2668. * Setup GPIO for the other variants of Core3D.
  2669. */
  2670. /*
  2671. * For cards with PCI-E region2 (Sound Blaster Z/ZxR, Recon3D, and AE-5)
  2672. * the mmio address 0x320 is used to set GPIO pins. The format for the data
  2673. * The first eight bits are just the number of the pin. So far, I've only seen
  2674. * this number go to 7.
  2675. */
  2676. static void ca0132_mmio_gpio_set(struct hda_codec *codec, unsigned int gpio_pin,
  2677. bool enable)
  2678. {
  2679. struct ca0132_spec *spec = codec->spec;
  2680. unsigned short gpio_data;
  2681. gpio_data = gpio_pin & 0xF;
  2682. gpio_data |= ((enable << 8) & 0x100);
  2683. writew(gpio_data, spec->mem_base + 0x320);
  2684. }
  2685. /*
  2686. * Sets up the GPIO pins so that they are discoverable. If this isn't done,
  2687. * the card shows as having no GPIO pins.
  2688. */
  2689. static void ca0132_gpio_init(struct hda_codec *codec)
  2690. {
  2691. struct ca0132_spec *spec = codec->spec;
  2692. switch (spec->quirk) {
  2693. case QUIRK_SBZ:
  2694. snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
  2695. snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
  2696. snd_hda_codec_write(codec, 0x01, 0, 0x790, 0x23);
  2697. break;
  2698. case QUIRK_R3DI:
  2699. snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
  2700. snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5B);
  2701. break;
  2702. }
  2703. }
  2704. /* Sets the GPIO for audio output. */
  2705. static void ca0132_gpio_setup(struct hda_codec *codec)
  2706. {
  2707. struct ca0132_spec *spec = codec->spec;
  2708. switch (spec->quirk) {
  2709. case QUIRK_SBZ:
  2710. snd_hda_codec_write(codec, 0x01, 0,
  2711. AC_VERB_SET_GPIO_DIRECTION, 0x07);
  2712. snd_hda_codec_write(codec, 0x01, 0,
  2713. AC_VERB_SET_GPIO_MASK, 0x07);
  2714. snd_hda_codec_write(codec, 0x01, 0,
  2715. AC_VERB_SET_GPIO_DATA, 0x04);
  2716. snd_hda_codec_write(codec, 0x01, 0,
  2717. AC_VERB_SET_GPIO_DATA, 0x06);
  2718. break;
  2719. case QUIRK_R3DI:
  2720. snd_hda_codec_write(codec, 0x01, 0,
  2721. AC_VERB_SET_GPIO_DIRECTION, 0x1E);
  2722. snd_hda_codec_write(codec, 0x01, 0,
  2723. AC_VERB_SET_GPIO_MASK, 0x1F);
  2724. snd_hda_codec_write(codec, 0x01, 0,
  2725. AC_VERB_SET_GPIO_DATA, 0x0C);
  2726. break;
  2727. }
  2728. }
  2729. /*
  2730. * GPIO control functions for the Recon3D integrated.
  2731. */
  2732. enum r3di_gpio_bit {
  2733. /* Bit 1 - Switch between front/rear mic. 0 = rear, 1 = front */
  2734. R3DI_MIC_SELECT_BIT = 1,
  2735. /* Bit 2 - Switch between headphone/line out. 0 = Headphone, 1 = Line */
  2736. R3DI_OUT_SELECT_BIT = 2,
  2737. /*
  2738. * I dunno what this actually does, but it stays on until the dsp
  2739. * is downloaded.
  2740. */
  2741. R3DI_GPIO_DSP_DOWNLOADING = 3,
  2742. /*
  2743. * Same as above, no clue what it does, but it comes on after the dsp
  2744. * is downloaded.
  2745. */
  2746. R3DI_GPIO_DSP_DOWNLOADED = 4
  2747. };
  2748. enum r3di_mic_select {
  2749. /* Set GPIO bit 1 to 0 for rear mic */
  2750. R3DI_REAR_MIC = 0,
  2751. /* Set GPIO bit 1 to 1 for front microphone*/
  2752. R3DI_FRONT_MIC = 1
  2753. };
  2754. enum r3di_out_select {
  2755. /* Set GPIO bit 2 to 0 for headphone */
  2756. R3DI_HEADPHONE_OUT = 0,
  2757. /* Set GPIO bit 2 to 1 for speaker */
  2758. R3DI_LINE_OUT = 1
  2759. };
  2760. enum r3di_dsp_status {
  2761. /* Set GPIO bit 3 to 1 until DSP is downloaded */
  2762. R3DI_DSP_DOWNLOADING = 0,
  2763. /* Set GPIO bit 4 to 1 once DSP is downloaded */
  2764. R3DI_DSP_DOWNLOADED = 1
  2765. };
  2766. static void r3di_gpio_mic_set(struct hda_codec *codec,
  2767. enum r3di_mic_select cur_mic)
  2768. {
  2769. unsigned int cur_gpio;
  2770. /* Get the current GPIO Data setup */
  2771. cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
  2772. switch (cur_mic) {
  2773. case R3DI_REAR_MIC:
  2774. cur_gpio &= ~(1 << R3DI_MIC_SELECT_BIT);
  2775. break;
  2776. case R3DI_FRONT_MIC:
  2777. cur_gpio |= (1 << R3DI_MIC_SELECT_BIT);
  2778. break;
  2779. }
  2780. snd_hda_codec_write(codec, codec->core.afg, 0,
  2781. AC_VERB_SET_GPIO_DATA, cur_gpio);
  2782. }
  2783. static void r3di_gpio_out_set(struct hda_codec *codec,
  2784. enum r3di_out_select cur_out)
  2785. {
  2786. unsigned int cur_gpio;
  2787. /* Get the current GPIO Data setup */
  2788. cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
  2789. switch (cur_out) {
  2790. case R3DI_HEADPHONE_OUT:
  2791. cur_gpio &= ~(1 << R3DI_OUT_SELECT_BIT);
  2792. break;
  2793. case R3DI_LINE_OUT:
  2794. cur_gpio |= (1 << R3DI_OUT_SELECT_BIT);
  2795. break;
  2796. }
  2797. snd_hda_codec_write(codec, codec->core.afg, 0,
  2798. AC_VERB_SET_GPIO_DATA, cur_gpio);
  2799. }
  2800. static void r3di_gpio_dsp_status_set(struct hda_codec *codec,
  2801. enum r3di_dsp_status dsp_status)
  2802. {
  2803. unsigned int cur_gpio;
  2804. /* Get the current GPIO Data setup */
  2805. cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
  2806. switch (dsp_status) {
  2807. case R3DI_DSP_DOWNLOADING:
  2808. cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADING);
  2809. snd_hda_codec_write(codec, codec->core.afg, 0,
  2810. AC_VERB_SET_GPIO_DATA, cur_gpio);
  2811. break;
  2812. case R3DI_DSP_DOWNLOADED:
  2813. /* Set DOWNLOADING bit to 0. */
  2814. cur_gpio &= ~(1 << R3DI_GPIO_DSP_DOWNLOADING);
  2815. snd_hda_codec_write(codec, codec->core.afg, 0,
  2816. AC_VERB_SET_GPIO_DATA, cur_gpio);
  2817. cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADED);
  2818. break;
  2819. }
  2820. snd_hda_codec_write(codec, codec->core.afg, 0,
  2821. AC_VERB_SET_GPIO_DATA, cur_gpio);
  2822. }
  2823. /*
  2824. * PCM callbacks
  2825. */
  2826. static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
  2827. struct hda_codec *codec,
  2828. unsigned int stream_tag,
  2829. unsigned int format,
  2830. struct snd_pcm_substream *substream)
  2831. {
  2832. struct ca0132_spec *spec = codec->spec;
  2833. snd_hda_codec_setup_stream(codec, spec->dacs[0], stream_tag, 0, format);
  2834. return 0;
  2835. }
  2836. static int ca0132_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
  2837. struct hda_codec *codec,
  2838. struct snd_pcm_substream *substream)
  2839. {
  2840. struct ca0132_spec *spec = codec->spec;
  2841. if (spec->dsp_state == DSP_DOWNLOADING)
  2842. return 0;
  2843. /*If Playback effects are on, allow stream some time to flush
  2844. *effects tail*/
  2845. if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
  2846. msleep(50);
  2847. snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
  2848. return 0;
  2849. }
  2850. static unsigned int ca0132_playback_pcm_delay(struct hda_pcm_stream *info,
  2851. struct hda_codec *codec,
  2852. struct snd_pcm_substream *substream)
  2853. {
  2854. struct ca0132_spec *spec = codec->spec;
  2855. unsigned int latency = DSP_PLAYBACK_INIT_LATENCY;
  2856. struct snd_pcm_runtime *runtime = substream->runtime;
  2857. if (spec->dsp_state != DSP_DOWNLOADED)
  2858. return 0;
  2859. /* Add latency if playback enhancement and either effect is enabled. */
  2860. if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) {
  2861. if ((spec->effects_switch[SURROUND - EFFECT_START_NID]) ||
  2862. (spec->effects_switch[DIALOG_PLUS - EFFECT_START_NID]))
  2863. latency += DSP_PLAY_ENHANCEMENT_LATENCY;
  2864. }
  2865. /* Applying Speaker EQ adds latency as well. */
  2866. if (spec->cur_out_type == SPEAKER_OUT)
  2867. latency += DSP_SPEAKER_OUT_LATENCY;
  2868. return (latency * runtime->rate) / 1000;
  2869. }
  2870. /*
  2871. * Digital out
  2872. */
  2873. static int ca0132_dig_playback_pcm_open(struct hda_pcm_stream *hinfo,
  2874. struct hda_codec *codec,
  2875. struct snd_pcm_substream *substream)
  2876. {
  2877. struct ca0132_spec *spec = codec->spec;
  2878. return snd_hda_multi_out_dig_open(codec, &spec->multiout);
  2879. }
  2880. static int ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
  2881. struct hda_codec *codec,
  2882. unsigned int stream_tag,
  2883. unsigned int format,
  2884. struct snd_pcm_substream *substream)
  2885. {
  2886. struct ca0132_spec *spec = codec->spec;
  2887. return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
  2888. stream_tag, format, substream);
  2889. }
  2890. static int ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
  2891. struct hda_codec *codec,
  2892. struct snd_pcm_substream *substream)
  2893. {
  2894. struct ca0132_spec *spec = codec->spec;
  2895. return snd_hda_multi_out_dig_cleanup(codec, &spec->multiout);
  2896. }
  2897. static int ca0132_dig_playback_pcm_close(struct hda_pcm_stream *hinfo,
  2898. struct hda_codec *codec,
  2899. struct snd_pcm_substream *substream)
  2900. {
  2901. struct ca0132_spec *spec = codec->spec;
  2902. return snd_hda_multi_out_dig_close(codec, &spec->multiout);
  2903. }
  2904. /*
  2905. * Analog capture
  2906. */
  2907. static int ca0132_capture_pcm_prepare(struct hda_pcm_stream *hinfo,
  2908. struct hda_codec *codec,
  2909. unsigned int stream_tag,
  2910. unsigned int format,
  2911. struct snd_pcm_substream *substream)
  2912. {
  2913. snd_hda_codec_setup_stream(codec, hinfo->nid,
  2914. stream_tag, 0, format);
  2915. return 0;
  2916. }
  2917. static int ca0132_capture_pcm_cleanup(struct hda_pcm_stream *hinfo,
  2918. struct hda_codec *codec,
  2919. struct snd_pcm_substream *substream)
  2920. {
  2921. struct ca0132_spec *spec = codec->spec;
  2922. if (spec->dsp_state == DSP_DOWNLOADING)
  2923. return 0;
  2924. snd_hda_codec_cleanup_stream(codec, hinfo->nid);
  2925. return 0;
  2926. }
  2927. static unsigned int ca0132_capture_pcm_delay(struct hda_pcm_stream *info,
  2928. struct hda_codec *codec,
  2929. struct snd_pcm_substream *substream)
  2930. {
  2931. struct ca0132_spec *spec = codec->spec;
  2932. unsigned int latency = DSP_CAPTURE_INIT_LATENCY;
  2933. struct snd_pcm_runtime *runtime = substream->runtime;
  2934. if (spec->dsp_state != DSP_DOWNLOADED)
  2935. return 0;
  2936. if (spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
  2937. latency += DSP_CRYSTAL_VOICE_LATENCY;
  2938. return (latency * runtime->rate) / 1000;
  2939. }
  2940. /*
  2941. * Controls stuffs.
  2942. */
  2943. /*
  2944. * Mixer controls helpers.
  2945. */
  2946. #define CA0132_CODEC_VOL_MONO(xname, nid, channel, dir) \
  2947. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
  2948. .name = xname, \
  2949. .subdevice = HDA_SUBDEV_AMP_FLAG, \
  2950. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
  2951. SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
  2952. SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
  2953. .info = ca0132_volume_info, \
  2954. .get = ca0132_volume_get, \
  2955. .put = ca0132_volume_put, \
  2956. .tlv = { .c = ca0132_volume_tlv }, \
  2957. .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
  2958. /*
  2959. * Creates a mixer control that uses defaults of HDA_CODEC_VOL except for the
  2960. * volume put, which is used for setting the DSP volume. This was done because
  2961. * the ca0132 functions were taking too much time and causing lag.
  2962. */
  2963. #define CA0132_ALT_CODEC_VOL_MONO(xname, nid, channel, dir) \
  2964. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
  2965. .name = xname, \
  2966. .subdevice = HDA_SUBDEV_AMP_FLAG, \
  2967. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
  2968. SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
  2969. SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
  2970. .info = snd_hda_mixer_amp_volume_info, \
  2971. .get = snd_hda_mixer_amp_volume_get, \
  2972. .put = ca0132_alt_volume_put, \
  2973. .tlv = { .c = snd_hda_mixer_amp_tlv }, \
  2974. .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
  2975. #define CA0132_CODEC_MUTE_MONO(xname, nid, channel, dir) \
  2976. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
  2977. .name = xname, \
  2978. .subdevice = HDA_SUBDEV_AMP_FLAG, \
  2979. .info = snd_hda_mixer_amp_switch_info, \
  2980. .get = ca0132_switch_get, \
  2981. .put = ca0132_switch_put, \
  2982. .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
  2983. /* stereo */
  2984. #define CA0132_CODEC_VOL(xname, nid, dir) \
  2985. CA0132_CODEC_VOL_MONO(xname, nid, 3, dir)
  2986. #define CA0132_ALT_CODEC_VOL(xname, nid, dir) \
  2987. CA0132_ALT_CODEC_VOL_MONO(xname, nid, 3, dir)
  2988. #define CA0132_CODEC_MUTE(xname, nid, dir) \
  2989. CA0132_CODEC_MUTE_MONO(xname, nid, 3, dir)
  2990. /* lookup tables */
  2991. /*
  2992. * Lookup table with decibel values for the DSP. When volume is changed in
  2993. * Windows, the DSP is also sent the dB value in floating point. In Windows,
  2994. * these values have decimal points, probably because the Windows driver
  2995. * actually uses floating point. We can't here, so I made a lookup table of
  2996. * values -90 to 9. -90 is the lowest decibel value for both the ADC's and the
  2997. * DAC's, and 9 is the maximum.
  2998. */
  2999. static const unsigned int float_vol_db_lookup[] = {
  3000. 0xC2B40000, 0xC2B20000, 0xC2B00000, 0xC2AE0000, 0xC2AC0000, 0xC2AA0000,
  3001. 0xC2A80000, 0xC2A60000, 0xC2A40000, 0xC2A20000, 0xC2A00000, 0xC29E0000,
  3002. 0xC29C0000, 0xC29A0000, 0xC2980000, 0xC2960000, 0xC2940000, 0xC2920000,
  3003. 0xC2900000, 0xC28E0000, 0xC28C0000, 0xC28A0000, 0xC2880000, 0xC2860000,
  3004. 0xC2840000, 0xC2820000, 0xC2800000, 0xC27C0000, 0xC2780000, 0xC2740000,
  3005. 0xC2700000, 0xC26C0000, 0xC2680000, 0xC2640000, 0xC2600000, 0xC25C0000,
  3006. 0xC2580000, 0xC2540000, 0xC2500000, 0xC24C0000, 0xC2480000, 0xC2440000,
  3007. 0xC2400000, 0xC23C0000, 0xC2380000, 0xC2340000, 0xC2300000, 0xC22C0000,
  3008. 0xC2280000, 0xC2240000, 0xC2200000, 0xC21C0000, 0xC2180000, 0xC2140000,
  3009. 0xC2100000, 0xC20C0000, 0xC2080000, 0xC2040000, 0xC2000000, 0xC1F80000,
  3010. 0xC1F00000, 0xC1E80000, 0xC1E00000, 0xC1D80000, 0xC1D00000, 0xC1C80000,
  3011. 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
  3012. 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
  3013. 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
  3014. 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
  3015. 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
  3016. 0x40C00000, 0x40E00000, 0x41000000, 0x41100000
  3017. };
  3018. /*
  3019. * This table counts from float 0 to 1 in increments of .01, which is
  3020. * useful for a few different sliders.
  3021. */
  3022. static const unsigned int float_zero_to_one_lookup[] = {
  3023. 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
  3024. 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
  3025. 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
  3026. 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
  3027. 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
  3028. 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
  3029. 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
  3030. 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
  3031. 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
  3032. 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
  3033. 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
  3034. 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
  3035. 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
  3036. 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
  3037. 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
  3038. 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
  3039. 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
  3040. };
  3041. /*
  3042. * This table counts from float 10 to 1000, which is the range of the x-bass
  3043. * crossover slider in Windows.
  3044. */
  3045. static const unsigned int float_xbass_xover_lookup[] = {
  3046. 0x41200000, 0x41A00000, 0x41F00000, 0x42200000, 0x42480000, 0x42700000,
  3047. 0x428C0000, 0x42A00000, 0x42B40000, 0x42C80000, 0x42DC0000, 0x42F00000,
  3048. 0x43020000, 0x430C0000, 0x43160000, 0x43200000, 0x432A0000, 0x43340000,
  3049. 0x433E0000, 0x43480000, 0x43520000, 0x435C0000, 0x43660000, 0x43700000,
  3050. 0x437A0000, 0x43820000, 0x43870000, 0x438C0000, 0x43910000, 0x43960000,
  3051. 0x439B0000, 0x43A00000, 0x43A50000, 0x43AA0000, 0x43AF0000, 0x43B40000,
  3052. 0x43B90000, 0x43BE0000, 0x43C30000, 0x43C80000, 0x43CD0000, 0x43D20000,
  3053. 0x43D70000, 0x43DC0000, 0x43E10000, 0x43E60000, 0x43EB0000, 0x43F00000,
  3054. 0x43F50000, 0x43FA0000, 0x43FF0000, 0x44020000, 0x44048000, 0x44070000,
  3055. 0x44098000, 0x440C0000, 0x440E8000, 0x44110000, 0x44138000, 0x44160000,
  3056. 0x44188000, 0x441B0000, 0x441D8000, 0x44200000, 0x44228000, 0x44250000,
  3057. 0x44278000, 0x442A0000, 0x442C8000, 0x442F0000, 0x44318000, 0x44340000,
  3058. 0x44368000, 0x44390000, 0x443B8000, 0x443E0000, 0x44408000, 0x44430000,
  3059. 0x44458000, 0x44480000, 0x444A8000, 0x444D0000, 0x444F8000, 0x44520000,
  3060. 0x44548000, 0x44570000, 0x44598000, 0x445C0000, 0x445E8000, 0x44610000,
  3061. 0x44638000, 0x44660000, 0x44688000, 0x446B0000, 0x446D8000, 0x44700000,
  3062. 0x44728000, 0x44750000, 0x44778000, 0x447A0000
  3063. };
  3064. /* The following are for tuning of products */
  3065. #ifdef ENABLE_TUNING_CONTROLS
  3066. static unsigned int voice_focus_vals_lookup[] = {
  3067. 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 0x41C00000, 0x41C80000,
  3068. 0x41D00000, 0x41D80000, 0x41E00000, 0x41E80000, 0x41F00000, 0x41F80000,
  3069. 0x42000000, 0x42040000, 0x42080000, 0x420C0000, 0x42100000, 0x42140000,
  3070. 0x42180000, 0x421C0000, 0x42200000, 0x42240000, 0x42280000, 0x422C0000,
  3071. 0x42300000, 0x42340000, 0x42380000, 0x423C0000, 0x42400000, 0x42440000,
  3072. 0x42480000, 0x424C0000, 0x42500000, 0x42540000, 0x42580000, 0x425C0000,
  3073. 0x42600000, 0x42640000, 0x42680000, 0x426C0000, 0x42700000, 0x42740000,
  3074. 0x42780000, 0x427C0000, 0x42800000, 0x42820000, 0x42840000, 0x42860000,
  3075. 0x42880000, 0x428A0000, 0x428C0000, 0x428E0000, 0x42900000, 0x42920000,
  3076. 0x42940000, 0x42960000, 0x42980000, 0x429A0000, 0x429C0000, 0x429E0000,
  3077. 0x42A00000, 0x42A20000, 0x42A40000, 0x42A60000, 0x42A80000, 0x42AA0000,
  3078. 0x42AC0000, 0x42AE0000, 0x42B00000, 0x42B20000, 0x42B40000, 0x42B60000,
  3079. 0x42B80000, 0x42BA0000, 0x42BC0000, 0x42BE0000, 0x42C00000, 0x42C20000,
  3080. 0x42C40000, 0x42C60000, 0x42C80000, 0x42CA0000, 0x42CC0000, 0x42CE0000,
  3081. 0x42D00000, 0x42D20000, 0x42D40000, 0x42D60000, 0x42D80000, 0x42DA0000,
  3082. 0x42DC0000, 0x42DE0000, 0x42E00000, 0x42E20000, 0x42E40000, 0x42E60000,
  3083. 0x42E80000, 0x42EA0000, 0x42EC0000, 0x42EE0000, 0x42F00000, 0x42F20000,
  3084. 0x42F40000, 0x42F60000, 0x42F80000, 0x42FA0000, 0x42FC0000, 0x42FE0000,
  3085. 0x43000000, 0x43010000, 0x43020000, 0x43030000, 0x43040000, 0x43050000,
  3086. 0x43060000, 0x43070000, 0x43080000, 0x43090000, 0x430A0000, 0x430B0000,
  3087. 0x430C0000, 0x430D0000, 0x430E0000, 0x430F0000, 0x43100000, 0x43110000,
  3088. 0x43120000, 0x43130000, 0x43140000, 0x43150000, 0x43160000, 0x43170000,
  3089. 0x43180000, 0x43190000, 0x431A0000, 0x431B0000, 0x431C0000, 0x431D0000,
  3090. 0x431E0000, 0x431F0000, 0x43200000, 0x43210000, 0x43220000, 0x43230000,
  3091. 0x43240000, 0x43250000, 0x43260000, 0x43270000, 0x43280000, 0x43290000,
  3092. 0x432A0000, 0x432B0000, 0x432C0000, 0x432D0000, 0x432E0000, 0x432F0000,
  3093. 0x43300000, 0x43310000, 0x43320000, 0x43330000, 0x43340000
  3094. };
  3095. static unsigned int mic_svm_vals_lookup[] = {
  3096. 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
  3097. 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
  3098. 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
  3099. 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
  3100. 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
  3101. 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
  3102. 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
  3103. 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
  3104. 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
  3105. 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
  3106. 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
  3107. 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
  3108. 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
  3109. 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
  3110. 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
  3111. 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
  3112. 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
  3113. };
  3114. static unsigned int equalizer_vals_lookup[] = {
  3115. 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
  3116. 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
  3117. 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
  3118. 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
  3119. 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
  3120. 0x40C00000, 0x40E00000, 0x41000000, 0x41100000, 0x41200000, 0x41300000,
  3121. 0x41400000, 0x41500000, 0x41600000, 0x41700000, 0x41800000, 0x41880000,
  3122. 0x41900000, 0x41980000, 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000,
  3123. 0x41C00000
  3124. };
  3125. static int tuning_ctl_set(struct hda_codec *codec, hda_nid_t nid,
  3126. unsigned int *lookup, int idx)
  3127. {
  3128. int i = 0;
  3129. for (i = 0; i < TUNING_CTLS_COUNT; i++)
  3130. if (nid == ca0132_tuning_ctls[i].nid)
  3131. break;
  3132. snd_hda_power_up(codec);
  3133. dspio_set_param(codec, ca0132_tuning_ctls[i].mid, 0x20,
  3134. ca0132_tuning_ctls[i].req,
  3135. &(lookup[idx]), sizeof(unsigned int));
  3136. snd_hda_power_down(codec);
  3137. return 1;
  3138. }
  3139. static int tuning_ctl_get(struct snd_kcontrol *kcontrol,
  3140. struct snd_ctl_elem_value *ucontrol)
  3141. {
  3142. struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
  3143. struct ca0132_spec *spec = codec->spec;
  3144. hda_nid_t nid = get_amp_nid(kcontrol);
  3145. long *valp = ucontrol->value.integer.value;
  3146. int idx = nid - TUNING_CTL_START_NID;
  3147. *valp = spec->cur_ctl_vals[idx];
  3148. return 0;
  3149. }
  3150. static int voice_focus_ctl_info(struct snd_kcontrol *kcontrol,
  3151. struct snd_ctl_elem_info *uinfo)
  3152. {
  3153. int chs = get_amp_channels(kcontrol);
  3154. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  3155. uinfo->count = chs == 3 ? 2 : 1;
  3156. uinfo->value.integer.min = 20;
  3157. uinfo->value.integer.max = 180;
  3158. uinfo->value.integer.step = 1;
  3159. return 0;
  3160. }
  3161. static int voice_focus_ctl_put(struct snd_kcontrol *kcontrol,
  3162. struct snd_ctl_elem_value *ucontrol)
  3163. {
  3164. struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
  3165. struct ca0132_spec *spec = codec->spec;
  3166. hda_nid_t nid = get_amp_nid(kcontrol);
  3167. long *valp = ucontrol->value.integer.value;
  3168. int idx;
  3169. idx = nid - TUNING_CTL_START_NID;
  3170. /* any change? */
  3171. if (spec->cur_ctl_vals[idx] == *valp)
  3172. return 0;
  3173. spec->cur_ctl_vals[idx] = *valp;
  3174. idx = *valp - 20;
  3175. tuning_ctl_set(codec, nid, voice_focus_vals_lookup, idx);
  3176. return 1;
  3177. }
  3178. static int mic_svm_ctl_info(struct snd_kcontrol *kcontrol,
  3179. struct snd_ctl_elem_info *uinfo)
  3180. {
  3181. int chs = get_amp_channels(kcontrol);
  3182. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  3183. uinfo->count = chs == 3 ? 2 : 1;
  3184. uinfo->value.integer.min = 0;
  3185. uinfo->value.integer.max = 100;
  3186. uinfo->value.integer.step = 1;
  3187. return 0;
  3188. }
  3189. static int mic_svm_ctl_put(struct snd_kcontrol *kcontrol,
  3190. struct snd_ctl_elem_value *ucontrol)
  3191. {
  3192. struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
  3193. struct ca0132_spec *spec = codec->spec;
  3194. hda_nid_t nid = get_amp_nid(kcontrol);
  3195. long *valp = ucontrol->value.integer.value;
  3196. int idx;
  3197. idx = nid - TUNING_CTL_START_NID;
  3198. /* any change? */
  3199. if (spec->cur_ctl_vals[idx] == *valp)
  3200. return 0;
  3201. spec->cur_ctl_vals[idx] = *valp;
  3202. idx = *valp;
  3203. tuning_ctl_set(codec, nid, mic_svm_vals_lookup, idx);
  3204. return 0;
  3205. }
  3206. static int equalizer_ctl_info(struct snd_kcontrol *kcontrol,
  3207. struct snd_ctl_elem_info *uinfo)
  3208. {
  3209. int chs = get_amp_channels(kcontrol);
  3210. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  3211. uinfo->count = chs == 3 ? 2 : 1;
  3212. uinfo->value.integer.min = 0;
  3213. uinfo->value.integer.max = 48;
  3214. uinfo->value.integer.step = 1;
  3215. return 0;
  3216. }
  3217. static int equalizer_ctl_put(struct snd_kcontrol *kcontrol,
  3218. struct snd_ctl_elem_value *ucontrol)
  3219. {
  3220. struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
  3221. struct ca0132_spec *spec = codec->spec;
  3222. hda_nid_t nid = get_amp_nid(kcontrol);
  3223. long *valp = ucontrol->value.integer.value;
  3224. int idx;
  3225. idx = nid - TUNING_CTL_START_NID;
  3226. /* any change? */
  3227. if (spec->cur_ctl_vals[idx] == *valp)
  3228. return 0;
  3229. spec->cur_ctl_vals[idx] = *valp;
  3230. idx = *valp;
  3231. tuning_ctl_set(codec, nid, equalizer_vals_lookup, idx);
  3232. return 1;
  3233. }
  3234. static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(voice_focus_db_scale, 2000, 100, 0);
  3235. static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(eq_db_scale, -2400, 100, 0);
  3236. static int add_tuning_control(struct hda_codec *codec,
  3237. hda_nid_t pnid, hda_nid_t nid,
  3238. const char *name, int dir)
  3239. {
  3240. char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
  3241. int type = dir ? HDA_INPUT : HDA_OUTPUT;
  3242. struct snd_kcontrol_new knew =
  3243. HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
  3244. knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
  3245. SNDRV_CTL_ELEM_ACCESS_TLV_READ;
  3246. knew.tlv.c = 0;
  3247. knew.tlv.p = 0;
  3248. switch (pnid) {
  3249. case VOICE_FOCUS:
  3250. knew.info = voice_focus_ctl_info;
  3251. knew.get = tuning_ctl_get;
  3252. knew.put = voice_focus_ctl_put;
  3253. knew.tlv.p = voice_focus_db_scale;
  3254. break;
  3255. case MIC_SVM:
  3256. knew.info = mic_svm_ctl_info;
  3257. knew.get = tuning_ctl_get;
  3258. knew.put = mic_svm_ctl_put;
  3259. break;
  3260. case EQUALIZER:
  3261. knew.info = equalizer_ctl_info;
  3262. knew.get = tuning_ctl_get;
  3263. knew.put = equalizer_ctl_put;
  3264. knew.tlv.p = eq_db_scale;
  3265. break;
  3266. default:
  3267. return 0;
  3268. }
  3269. knew.private_value =
  3270. HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
  3271. sprintf(namestr, "%s %s Volume", name, dirstr[dir]);
  3272. return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
  3273. }
  3274. static int add_tuning_ctls(struct hda_codec *codec)
  3275. {
  3276. int i;
  3277. int err;
  3278. for (i = 0; i < TUNING_CTLS_COUNT; i++) {
  3279. err = add_tuning_control(codec,
  3280. ca0132_tuning_ctls[i].parent_nid,
  3281. ca0132_tuning_ctls[i].nid,
  3282. ca0132_tuning_ctls[i].name,
  3283. ca0132_tuning_ctls[i].direct);
  3284. if (err < 0)
  3285. return err;
  3286. }
  3287. return 0;
  3288. }
  3289. static void ca0132_init_tuning_defaults(struct hda_codec *codec)
  3290. {
  3291. struct ca0132_spec *spec = codec->spec;
  3292. int i;
  3293. /* Wedge Angle defaults to 30. 10 below is 30 - 20. 20 is min. */
  3294. spec->cur_ctl_vals[WEDGE_ANGLE - TUNING_CTL_START_NID] = 10;
  3295. /* SVM level defaults to 0.74. */
  3296. spec->cur_ctl_vals[SVM_LEVEL - TUNING_CTL_START_NID] = 74;
  3297. /* EQ defaults to 0dB. */
  3298. for (i = 2; i < TUNING_CTLS_COUNT; i++)
  3299. spec->cur_ctl_vals[i] = 24;
  3300. }
  3301. #endif /*ENABLE_TUNING_CONTROLS*/
  3302. /*
  3303. * Select the active output.
  3304. * If autodetect is enabled, output will be selected based on jack detection.
  3305. * If jack inserted, headphone will be selected, else built-in speakers
  3306. * If autodetect is disabled, output will be selected based on selection.
  3307. */
  3308. static int ca0132_select_out(struct hda_codec *codec)
  3309. {
  3310. struct ca0132_spec *spec = codec->spec;
  3311. unsigned int pin_ctl;
  3312. int jack_present;
  3313. int auto_jack;
  3314. unsigned int tmp;
  3315. int err;
  3316. codec_dbg(codec, "ca0132_select_out\n");
  3317. snd_hda_power_up_pm(codec);
  3318. auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
  3319. if (auto_jack)
  3320. jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp);
  3321. else
  3322. jack_present =
  3323. spec->vnode_lswitch[VNID_HP_SEL - VNODE_START_NID];
  3324. if (jack_present)
  3325. spec->cur_out_type = HEADPHONE_OUT;
  3326. else
  3327. spec->cur_out_type = SPEAKER_OUT;
  3328. if (spec->cur_out_type == SPEAKER_OUT) {
  3329. codec_dbg(codec, "ca0132_select_out speaker\n");
  3330. /*speaker out config*/
  3331. tmp = FLOAT_ONE;
  3332. err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
  3333. if (err < 0)
  3334. goto exit;
  3335. /*enable speaker EQ*/
  3336. tmp = FLOAT_ONE;
  3337. err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
  3338. if (err < 0)
  3339. goto exit;
  3340. /* Setup EAPD */
  3341. snd_hda_codec_write(codec, spec->out_pins[1], 0,
  3342. VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
  3343. snd_hda_codec_write(codec, spec->out_pins[0], 0,
  3344. AC_VERB_SET_EAPD_BTLENABLE, 0x00);
  3345. snd_hda_codec_write(codec, spec->out_pins[0], 0,
  3346. VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
  3347. snd_hda_codec_write(codec, spec->out_pins[0], 0,
  3348. AC_VERB_SET_EAPD_BTLENABLE, 0x02);
  3349. /* disable headphone node */
  3350. pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
  3351. AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
  3352. snd_hda_set_pin_ctl(codec, spec->out_pins[1],
  3353. pin_ctl & ~PIN_HP);
  3354. /* enable speaker node */
  3355. pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
  3356. AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
  3357. snd_hda_set_pin_ctl(codec, spec->out_pins[0],
  3358. pin_ctl | PIN_OUT);
  3359. } else {
  3360. codec_dbg(codec, "ca0132_select_out hp\n");
  3361. /*headphone out config*/
  3362. tmp = FLOAT_ZERO;
  3363. err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
  3364. if (err < 0)
  3365. goto exit;
  3366. /*disable speaker EQ*/
  3367. tmp = FLOAT_ZERO;
  3368. err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
  3369. if (err < 0)
  3370. goto exit;
  3371. /* Setup EAPD */
  3372. snd_hda_codec_write(codec, spec->out_pins[0], 0,
  3373. VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
  3374. snd_hda_codec_write(codec, spec->out_pins[0], 0,
  3375. AC_VERB_SET_EAPD_BTLENABLE, 0x00);
  3376. snd_hda_codec_write(codec, spec->out_pins[1], 0,
  3377. VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
  3378. snd_hda_codec_write(codec, spec->out_pins[0], 0,
  3379. AC_VERB_SET_EAPD_BTLENABLE, 0x02);
  3380. /* disable speaker*/
  3381. pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
  3382. AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
  3383. snd_hda_set_pin_ctl(codec, spec->out_pins[0],
  3384. pin_ctl & ~PIN_HP);
  3385. /* enable headphone*/
  3386. pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
  3387. AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
  3388. snd_hda_set_pin_ctl(codec, spec->out_pins[1],
  3389. pin_ctl | PIN_HP);
  3390. }
  3391. exit:
  3392. snd_hda_power_down_pm(codec);
  3393. return err < 0 ? err : 0;
  3394. }
  3395. /*
  3396. * This function behaves similarly to the ca0132_select_out funciton above,
  3397. * except with a few differences. It adds the ability to select the current
  3398. * output with an enumerated control "output source" if the auto detect
  3399. * mute switch is set to off. If the auto detect mute switch is enabled, it
  3400. * will detect either headphone or lineout(SPEAKER_OUT) from jack detection.
  3401. * It also adds the ability to auto-detect the front headphone port. The only
  3402. * way to select surround is to disable auto detect, and set Surround with the
  3403. * enumerated control.
  3404. */
  3405. static int ca0132_alt_select_out(struct hda_codec *codec)
  3406. {
  3407. struct ca0132_spec *spec = codec->spec;
  3408. unsigned int pin_ctl;
  3409. int jack_present;
  3410. int auto_jack;
  3411. unsigned int i;
  3412. unsigned int tmp;
  3413. int err;
  3414. /* Default Headphone is rear headphone */
  3415. hda_nid_t headphone_nid = spec->out_pins[1];
  3416. codec_dbg(codec, "%s\n", __func__);
  3417. snd_hda_power_up_pm(codec);
  3418. auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
  3419. /*
  3420. * If headphone rear or front is plugged in, set to headphone.
  3421. * If neither is plugged in, set to rear line out. Only if
  3422. * hp/speaker auto detect is enabled.
  3423. */
  3424. if (auto_jack) {
  3425. jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp) ||
  3426. snd_hda_jack_detect(codec, spec->unsol_tag_front_hp);
  3427. if (jack_present)
  3428. spec->cur_out_type = HEADPHONE_OUT;
  3429. else
  3430. spec->cur_out_type = SPEAKER_OUT;
  3431. } else
  3432. spec->cur_out_type = spec->out_enum_val;
  3433. /* Begin DSP output switch */
  3434. tmp = FLOAT_ONE;
  3435. err = dspio_set_uint_param(codec, 0x96, 0x3A, tmp);
  3436. if (err < 0)
  3437. goto exit;
  3438. switch (spec->cur_out_type) {
  3439. case SPEAKER_OUT:
  3440. codec_dbg(codec, "%s speaker\n", __func__);
  3441. /*speaker out config*/
  3442. switch (spec->quirk) {
  3443. case QUIRK_SBZ:
  3444. ca0132_mmio_gpio_set(codec, 7, false);
  3445. ca0132_mmio_gpio_set(codec, 4, true);
  3446. ca0132_mmio_gpio_set(codec, 1, true);
  3447. chipio_set_control_param(codec, 0x0D, 0x18);
  3448. break;
  3449. case QUIRK_R3DI:
  3450. chipio_set_control_param(codec, 0x0D, 0x24);
  3451. r3di_gpio_out_set(codec, R3DI_LINE_OUT);
  3452. break;
  3453. case QUIRK_R3D:
  3454. chipio_set_control_param(codec, 0x0D, 0x24);
  3455. ca0132_mmio_gpio_set(codec, 1, true);
  3456. break;
  3457. }
  3458. /* disable headphone node */
  3459. pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
  3460. AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
  3461. snd_hda_set_pin_ctl(codec, spec->out_pins[1],
  3462. pin_ctl & ~PIN_HP);
  3463. /* enable line-out node */
  3464. pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
  3465. AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
  3466. snd_hda_set_pin_ctl(codec, spec->out_pins[0],
  3467. pin_ctl | PIN_OUT);
  3468. /* Enable EAPD */
  3469. snd_hda_codec_write(codec, spec->out_pins[0], 0,
  3470. AC_VERB_SET_EAPD_BTLENABLE, 0x01);
  3471. /* If PlayEnhancement is enabled, set different source */
  3472. if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
  3473. dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE);
  3474. else
  3475. dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_EIGHT);
  3476. break;
  3477. case HEADPHONE_OUT:
  3478. codec_dbg(codec, "%s hp\n", __func__);
  3479. /* Headphone out config*/
  3480. switch (spec->quirk) {
  3481. case QUIRK_SBZ:
  3482. ca0132_mmio_gpio_set(codec, 7, true);
  3483. ca0132_mmio_gpio_set(codec, 4, true);
  3484. ca0132_mmio_gpio_set(codec, 1, false);
  3485. chipio_set_control_param(codec, 0x0D, 0x12);
  3486. break;
  3487. case QUIRK_R3DI:
  3488. chipio_set_control_param(codec, 0x0D, 0x21);
  3489. r3di_gpio_out_set(codec, R3DI_HEADPHONE_OUT);
  3490. break;
  3491. case QUIRK_R3D:
  3492. chipio_set_control_param(codec, 0x0D, 0x21);
  3493. ca0132_mmio_gpio_set(codec, 0x1, false);
  3494. break;
  3495. }
  3496. snd_hda_codec_write(codec, spec->out_pins[0], 0,
  3497. AC_VERB_SET_EAPD_BTLENABLE, 0x00);
  3498. /* disable speaker*/
  3499. pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
  3500. AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
  3501. snd_hda_set_pin_ctl(codec, spec->out_pins[0],
  3502. pin_ctl & ~PIN_HP);
  3503. /* enable headphone, either front or rear */
  3504. if (snd_hda_jack_detect(codec, spec->unsol_tag_front_hp))
  3505. headphone_nid = spec->out_pins[2];
  3506. else if (snd_hda_jack_detect(codec, spec->unsol_tag_hp))
  3507. headphone_nid = spec->out_pins[1];
  3508. pin_ctl = snd_hda_codec_read(codec, headphone_nid, 0,
  3509. AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
  3510. snd_hda_set_pin_ctl(codec, headphone_nid,
  3511. pin_ctl | PIN_HP);
  3512. if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
  3513. dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE);
  3514. else
  3515. dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ZERO);
  3516. break;
  3517. case SURROUND_OUT:
  3518. codec_dbg(codec, "%s surround\n", __func__);
  3519. /* Surround out config*/
  3520. switch (spec->quirk) {
  3521. case QUIRK_SBZ:
  3522. ca0132_mmio_gpio_set(codec, 7, false);
  3523. ca0132_mmio_gpio_set(codec, 4, true);
  3524. ca0132_mmio_gpio_set(codec, 1, true);
  3525. chipio_set_control_param(codec, 0x0D, 0x18);
  3526. break;
  3527. case QUIRK_R3DI:
  3528. chipio_set_control_param(codec, 0x0D, 0x24);
  3529. r3di_gpio_out_set(codec, R3DI_LINE_OUT);
  3530. break;
  3531. case QUIRK_R3D:
  3532. ca0132_mmio_gpio_set(codec, 1, true);
  3533. chipio_set_control_param(codec, 0x0D, 0x24);
  3534. break;
  3535. }
  3536. /* enable line out node */
  3537. pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
  3538. AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
  3539. snd_hda_set_pin_ctl(codec, spec->out_pins[0],
  3540. pin_ctl | PIN_OUT);
  3541. /* Disable headphone out */
  3542. pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
  3543. AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
  3544. snd_hda_set_pin_ctl(codec, spec->out_pins[1],
  3545. pin_ctl & ~PIN_HP);
  3546. /* Enable EAPD on line out */
  3547. snd_hda_codec_write(codec, spec->out_pins[0], 0,
  3548. AC_VERB_SET_EAPD_BTLENABLE, 0x01);
  3549. /* enable center/lfe out node */
  3550. pin_ctl = snd_hda_codec_read(codec, spec->out_pins[2], 0,
  3551. AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
  3552. snd_hda_set_pin_ctl(codec, spec->out_pins[2],
  3553. pin_ctl | PIN_OUT);
  3554. /* Now set rear surround node as out. */
  3555. pin_ctl = snd_hda_codec_read(codec, spec->out_pins[3], 0,
  3556. AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
  3557. snd_hda_set_pin_ctl(codec, spec->out_pins[3],
  3558. pin_ctl | PIN_OUT);
  3559. if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
  3560. dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE);
  3561. else
  3562. dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_EIGHT);
  3563. break;
  3564. }
  3565. /* run through the output dsp commands for line-out */
  3566. for (i = 0; i < alt_out_presets[spec->cur_out_type].commands; i++) {
  3567. err = dspio_set_uint_param(codec,
  3568. alt_out_presets[spec->cur_out_type].mids[i],
  3569. alt_out_presets[spec->cur_out_type].reqs[i],
  3570. alt_out_presets[spec->cur_out_type].vals[i]);
  3571. if (err < 0)
  3572. goto exit;
  3573. }
  3574. exit:
  3575. snd_hda_power_down_pm(codec);
  3576. return err < 0 ? err : 0;
  3577. }
  3578. static void ca0132_unsol_hp_delayed(struct work_struct *work)
  3579. {
  3580. struct ca0132_spec *spec = container_of(
  3581. to_delayed_work(work), struct ca0132_spec, unsol_hp_work);
  3582. struct hda_jack_tbl *jack;
  3583. if (spec->use_alt_functions)
  3584. ca0132_alt_select_out(spec->codec);
  3585. else
  3586. ca0132_select_out(spec->codec);
  3587. jack = snd_hda_jack_tbl_get(spec->codec, spec->unsol_tag_hp);
  3588. if (jack) {
  3589. jack->block_report = 0;
  3590. snd_hda_jack_report_sync(spec->codec);
  3591. }
  3592. }
  3593. static void ca0132_set_dmic(struct hda_codec *codec, int enable);
  3594. static int ca0132_mic_boost_set(struct hda_codec *codec, long val);
  3595. static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val);
  3596. static void resume_mic1(struct hda_codec *codec, unsigned int oldval);
  3597. static int stop_mic1(struct hda_codec *codec);
  3598. static int ca0132_cvoice_switch_set(struct hda_codec *codec);
  3599. static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val);
  3600. /*
  3601. * Select the active VIP source
  3602. */
  3603. static int ca0132_set_vipsource(struct hda_codec *codec, int val)
  3604. {
  3605. struct ca0132_spec *spec = codec->spec;
  3606. unsigned int tmp;
  3607. if (spec->dsp_state != DSP_DOWNLOADED)
  3608. return 0;
  3609. /* if CrystalVoice if off, vipsource should be 0 */
  3610. if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
  3611. (val == 0)) {
  3612. chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
  3613. chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
  3614. chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
  3615. if (spec->cur_mic_type == DIGITAL_MIC)
  3616. tmp = FLOAT_TWO;
  3617. else
  3618. tmp = FLOAT_ONE;
  3619. dspio_set_uint_param(codec, 0x80, 0x00, tmp);
  3620. tmp = FLOAT_ZERO;
  3621. dspio_set_uint_param(codec, 0x80, 0x05, tmp);
  3622. } else {
  3623. chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
  3624. chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
  3625. if (spec->cur_mic_type == DIGITAL_MIC)
  3626. tmp = FLOAT_TWO;
  3627. else
  3628. tmp = FLOAT_ONE;
  3629. dspio_set_uint_param(codec, 0x80, 0x00, tmp);
  3630. tmp = FLOAT_ONE;
  3631. dspio_set_uint_param(codec, 0x80, 0x05, tmp);
  3632. msleep(20);
  3633. chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
  3634. }
  3635. return 1;
  3636. }
  3637. static int ca0132_alt_set_vipsource(struct hda_codec *codec, int val)
  3638. {
  3639. struct ca0132_spec *spec = codec->spec;
  3640. unsigned int tmp;
  3641. if (spec->dsp_state != DSP_DOWNLOADED)
  3642. return 0;
  3643. codec_dbg(codec, "%s\n", __func__);
  3644. chipio_set_stream_control(codec, 0x03, 0);
  3645. chipio_set_stream_control(codec, 0x04, 0);
  3646. /* if CrystalVoice is off, vipsource should be 0 */
  3647. if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
  3648. (val == 0) || spec->in_enum_val == REAR_LINE_IN) {
  3649. codec_dbg(codec, "%s: off.", __func__);
  3650. chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
  3651. tmp = FLOAT_ZERO;
  3652. dspio_set_uint_param(codec, 0x80, 0x05, tmp);
  3653. chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
  3654. chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
  3655. if (spec->quirk == QUIRK_R3DI)
  3656. chipio_set_conn_rate(codec, 0x0F, SR_96_000);
  3657. if (spec->in_enum_val == REAR_LINE_IN)
  3658. tmp = FLOAT_ZERO;
  3659. else {
  3660. if (spec->quirk == QUIRK_SBZ)
  3661. tmp = FLOAT_THREE;
  3662. else
  3663. tmp = FLOAT_ONE;
  3664. }
  3665. dspio_set_uint_param(codec, 0x80, 0x00, tmp);
  3666. } else {
  3667. codec_dbg(codec, "%s: on.", __func__);
  3668. chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
  3669. chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
  3670. if (spec->quirk == QUIRK_R3DI)
  3671. chipio_set_conn_rate(codec, 0x0F, SR_16_000);
  3672. if (spec->effects_switch[VOICE_FOCUS - EFFECT_START_NID])
  3673. tmp = FLOAT_TWO;
  3674. else
  3675. tmp = FLOAT_ONE;
  3676. dspio_set_uint_param(codec, 0x80, 0x00, tmp);
  3677. tmp = FLOAT_ONE;
  3678. dspio_set_uint_param(codec, 0x80, 0x05, tmp);
  3679. msleep(20);
  3680. chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
  3681. }
  3682. chipio_set_stream_control(codec, 0x03, 1);
  3683. chipio_set_stream_control(codec, 0x04, 1);
  3684. return 1;
  3685. }
  3686. /*
  3687. * Select the active microphone.
  3688. * If autodetect is enabled, mic will be selected based on jack detection.
  3689. * If jack inserted, ext.mic will be selected, else built-in mic
  3690. * If autodetect is disabled, mic will be selected based on selection.
  3691. */
  3692. static int ca0132_select_mic(struct hda_codec *codec)
  3693. {
  3694. struct ca0132_spec *spec = codec->spec;
  3695. int jack_present;
  3696. int auto_jack;
  3697. codec_dbg(codec, "ca0132_select_mic\n");
  3698. snd_hda_power_up_pm(codec);
  3699. auto_jack = spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
  3700. if (auto_jack)
  3701. jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_amic1);
  3702. else
  3703. jack_present =
  3704. spec->vnode_lswitch[VNID_AMIC1_SEL - VNODE_START_NID];
  3705. if (jack_present)
  3706. spec->cur_mic_type = LINE_MIC_IN;
  3707. else
  3708. spec->cur_mic_type = DIGITAL_MIC;
  3709. if (spec->cur_mic_type == DIGITAL_MIC) {
  3710. /* enable digital Mic */
  3711. chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_32_000);
  3712. ca0132_set_dmic(codec, 1);
  3713. ca0132_mic_boost_set(codec, 0);
  3714. /* set voice focus */
  3715. ca0132_effects_set(codec, VOICE_FOCUS,
  3716. spec->effects_switch
  3717. [VOICE_FOCUS - EFFECT_START_NID]);
  3718. } else {
  3719. /* disable digital Mic */
  3720. chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_96_000);
  3721. ca0132_set_dmic(codec, 0);
  3722. ca0132_mic_boost_set(codec, spec->cur_mic_boost);
  3723. /* disable voice focus */
  3724. ca0132_effects_set(codec, VOICE_FOCUS, 0);
  3725. }
  3726. snd_hda_power_down_pm(codec);
  3727. return 0;
  3728. }
  3729. /*
  3730. * Select the active input.
  3731. * Mic detection isn't used, because it's kind of pointless on the SBZ.
  3732. * The front mic has no jack-detection, so the only way to switch to it
  3733. * is to do it manually in alsamixer.
  3734. */
  3735. static int ca0132_alt_select_in(struct hda_codec *codec)
  3736. {
  3737. struct ca0132_spec *spec = codec->spec;
  3738. unsigned int tmp;
  3739. codec_dbg(codec, "%s\n", __func__);
  3740. snd_hda_power_up_pm(codec);
  3741. chipio_set_stream_control(codec, 0x03, 0);
  3742. chipio_set_stream_control(codec, 0x04, 0);
  3743. spec->cur_mic_type = spec->in_enum_val;
  3744. switch (spec->cur_mic_type) {
  3745. case REAR_MIC:
  3746. switch (spec->quirk) {
  3747. case QUIRK_SBZ:
  3748. case QUIRK_R3D:
  3749. ca0132_mmio_gpio_set(codec, 0, false);
  3750. tmp = FLOAT_THREE;
  3751. break;
  3752. case QUIRK_R3DI:
  3753. r3di_gpio_mic_set(codec, R3DI_REAR_MIC);
  3754. tmp = FLOAT_ONE;
  3755. break;
  3756. default:
  3757. tmp = FLOAT_ONE;
  3758. break;
  3759. }
  3760. chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
  3761. chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
  3762. if (spec->quirk == QUIRK_R3DI)
  3763. chipio_set_conn_rate(codec, 0x0F, SR_96_000);
  3764. dspio_set_uint_param(codec, 0x80, 0x00, tmp);
  3765. chipio_set_stream_control(codec, 0x03, 1);
  3766. chipio_set_stream_control(codec, 0x04, 1);
  3767. if (spec->quirk == QUIRK_SBZ) {
  3768. chipio_write(codec, 0x18B098, 0x0000000C);
  3769. chipio_write(codec, 0x18B09C, 0x0000000C);
  3770. }
  3771. ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
  3772. break;
  3773. case REAR_LINE_IN:
  3774. ca0132_mic_boost_set(codec, 0);
  3775. switch (spec->quirk) {
  3776. case QUIRK_SBZ:
  3777. case QUIRK_R3D:
  3778. ca0132_mmio_gpio_set(codec, 0, false);
  3779. break;
  3780. case QUIRK_R3DI:
  3781. r3di_gpio_mic_set(codec, R3DI_REAR_MIC);
  3782. break;
  3783. }
  3784. chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
  3785. chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
  3786. if (spec->quirk == QUIRK_R3DI)
  3787. chipio_set_conn_rate(codec, 0x0F, SR_96_000);
  3788. tmp = FLOAT_ZERO;
  3789. dspio_set_uint_param(codec, 0x80, 0x00, tmp);
  3790. if (spec->quirk == QUIRK_SBZ) {
  3791. chipio_write(codec, 0x18B098, 0x00000000);
  3792. chipio_write(codec, 0x18B09C, 0x00000000);
  3793. }
  3794. chipio_set_stream_control(codec, 0x03, 1);
  3795. chipio_set_stream_control(codec, 0x04, 1);
  3796. break;
  3797. case FRONT_MIC:
  3798. switch (spec->quirk) {
  3799. case QUIRK_SBZ:
  3800. case QUIRK_R3D:
  3801. ca0132_mmio_gpio_set(codec, 0, true);
  3802. ca0132_mmio_gpio_set(codec, 5, false);
  3803. tmp = FLOAT_THREE;
  3804. break;
  3805. case QUIRK_R3DI:
  3806. r3di_gpio_mic_set(codec, R3DI_FRONT_MIC);
  3807. tmp = FLOAT_ONE;
  3808. break;
  3809. default:
  3810. tmp = FLOAT_ONE;
  3811. break;
  3812. }
  3813. chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
  3814. chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
  3815. if (spec->quirk == QUIRK_R3DI)
  3816. chipio_set_conn_rate(codec, 0x0F, SR_96_000);
  3817. dspio_set_uint_param(codec, 0x80, 0x00, tmp);
  3818. chipio_set_stream_control(codec, 0x03, 1);
  3819. chipio_set_stream_control(codec, 0x04, 1);
  3820. if (spec->quirk == QUIRK_SBZ) {
  3821. chipio_write(codec, 0x18B098, 0x0000000C);
  3822. chipio_write(codec, 0x18B09C, 0x000000CC);
  3823. }
  3824. ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
  3825. break;
  3826. }
  3827. ca0132_cvoice_switch_set(codec);
  3828. snd_hda_power_down_pm(codec);
  3829. return 0;
  3830. }
  3831. /*
  3832. * Check if VNODE settings take effect immediately.
  3833. */
  3834. static bool ca0132_is_vnode_effective(struct hda_codec *codec,
  3835. hda_nid_t vnid,
  3836. hda_nid_t *shared_nid)
  3837. {
  3838. struct ca0132_spec *spec = codec->spec;
  3839. hda_nid_t nid;
  3840. switch (vnid) {
  3841. case VNID_SPK:
  3842. nid = spec->shared_out_nid;
  3843. break;
  3844. case VNID_MIC:
  3845. nid = spec->shared_mic_nid;
  3846. break;
  3847. default:
  3848. return false;
  3849. }
  3850. if (shared_nid)
  3851. *shared_nid = nid;
  3852. return true;
  3853. }
  3854. /*
  3855. * The following functions are control change helpers.
  3856. * They return 0 if no changed. Return 1 if changed.
  3857. */
  3858. static int ca0132_voicefx_set(struct hda_codec *codec, int enable)
  3859. {
  3860. struct ca0132_spec *spec = codec->spec;
  3861. unsigned int tmp;
  3862. /* based on CrystalVoice state to enable VoiceFX. */
  3863. if (enable) {
  3864. tmp = spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ?
  3865. FLOAT_ONE : FLOAT_ZERO;
  3866. } else {
  3867. tmp = FLOAT_ZERO;
  3868. }
  3869. dspio_set_uint_param(codec, ca0132_voicefx.mid,
  3870. ca0132_voicefx.reqs[0], tmp);
  3871. return 1;
  3872. }
  3873. /*
  3874. * Set the effects parameters
  3875. */
  3876. static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val)
  3877. {
  3878. struct ca0132_spec *spec = codec->spec;
  3879. unsigned int on, tmp;
  3880. int num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
  3881. int err = 0;
  3882. int idx = nid - EFFECT_START_NID;
  3883. if ((idx < 0) || (idx >= num_fx))
  3884. return 0; /* no changed */
  3885. /* for out effect, qualify with PE */
  3886. if ((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) {
  3887. /* if PE if off, turn off out effects. */
  3888. if (!spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
  3889. val = 0;
  3890. }
  3891. /* for in effect, qualify with CrystalVoice */
  3892. if ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID)) {
  3893. /* if CrystalVoice if off, turn off in effects. */
  3894. if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
  3895. val = 0;
  3896. /* Voice Focus applies to 2-ch Mic, Digital Mic */
  3897. if ((nid == VOICE_FOCUS) && (spec->cur_mic_type != DIGITAL_MIC))
  3898. val = 0;
  3899. /* If Voice Focus on SBZ, set to two channel. */
  3900. if ((nid == VOICE_FOCUS) && (spec->quirk == QUIRK_SBZ)
  3901. && (spec->cur_mic_type != REAR_LINE_IN)) {
  3902. if (spec->effects_switch[CRYSTAL_VOICE -
  3903. EFFECT_START_NID]) {
  3904. if (spec->effects_switch[VOICE_FOCUS -
  3905. EFFECT_START_NID]) {
  3906. tmp = FLOAT_TWO;
  3907. val = 1;
  3908. } else
  3909. tmp = FLOAT_ONE;
  3910. dspio_set_uint_param(codec, 0x80, 0x00, tmp);
  3911. }
  3912. }
  3913. /*
  3914. * For SBZ noise reduction, there's an extra command
  3915. * to module ID 0x47. No clue why.
  3916. */
  3917. if ((nid == NOISE_REDUCTION) && (spec->quirk == QUIRK_SBZ)
  3918. && (spec->cur_mic_type != REAR_LINE_IN)) {
  3919. if (spec->effects_switch[CRYSTAL_VOICE -
  3920. EFFECT_START_NID]) {
  3921. if (spec->effects_switch[NOISE_REDUCTION -
  3922. EFFECT_START_NID])
  3923. tmp = FLOAT_ONE;
  3924. else
  3925. tmp = FLOAT_ZERO;
  3926. } else
  3927. tmp = FLOAT_ZERO;
  3928. dspio_set_uint_param(codec, 0x47, 0x00, tmp);
  3929. }
  3930. /* If rear line in disable effects. */
  3931. if (spec->use_alt_functions &&
  3932. spec->in_enum_val == REAR_LINE_IN)
  3933. val = 0;
  3934. }
  3935. codec_dbg(codec, "ca0132_effect_set: nid=0x%x, val=%ld\n",
  3936. nid, val);
  3937. on = (val == 0) ? FLOAT_ZERO : FLOAT_ONE;
  3938. err = dspio_set_uint_param(codec, ca0132_effects[idx].mid,
  3939. ca0132_effects[idx].reqs[0], on);
  3940. if (err < 0)
  3941. return 0; /* no changed */
  3942. return 1;
  3943. }
  3944. /*
  3945. * Turn on/off Playback Enhancements
  3946. */
  3947. static int ca0132_pe_switch_set(struct hda_codec *codec)
  3948. {
  3949. struct ca0132_spec *spec = codec->spec;
  3950. hda_nid_t nid;
  3951. int i, ret = 0;
  3952. codec_dbg(codec, "ca0132_pe_switch_set: val=%ld\n",
  3953. spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]);
  3954. if (spec->use_alt_functions)
  3955. ca0132_alt_select_out(codec);
  3956. i = OUT_EFFECT_START_NID - EFFECT_START_NID;
  3957. nid = OUT_EFFECT_START_NID;
  3958. /* PE affects all out effects */
  3959. for (; nid < OUT_EFFECT_END_NID; nid++, i++)
  3960. ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
  3961. return ret;
  3962. }
  3963. /* Check if Mic1 is streaming, if so, stop streaming */
  3964. static int stop_mic1(struct hda_codec *codec)
  3965. {
  3966. struct ca0132_spec *spec = codec->spec;
  3967. unsigned int oldval = snd_hda_codec_read(codec, spec->adcs[0], 0,
  3968. AC_VERB_GET_CONV, 0);
  3969. if (oldval != 0)
  3970. snd_hda_codec_write(codec, spec->adcs[0], 0,
  3971. AC_VERB_SET_CHANNEL_STREAMID,
  3972. 0);
  3973. return oldval;
  3974. }
  3975. /* Resume Mic1 streaming if it was stopped. */
  3976. static void resume_mic1(struct hda_codec *codec, unsigned int oldval)
  3977. {
  3978. struct ca0132_spec *spec = codec->spec;
  3979. /* Restore the previous stream and channel */
  3980. if (oldval != 0)
  3981. snd_hda_codec_write(codec, spec->adcs[0], 0,
  3982. AC_VERB_SET_CHANNEL_STREAMID,
  3983. oldval);
  3984. }
  3985. /*
  3986. * Turn on/off CrystalVoice
  3987. */
  3988. static int ca0132_cvoice_switch_set(struct hda_codec *codec)
  3989. {
  3990. struct ca0132_spec *spec = codec->spec;
  3991. hda_nid_t nid;
  3992. int i, ret = 0;
  3993. unsigned int oldval;
  3994. codec_dbg(codec, "ca0132_cvoice_switch_set: val=%ld\n",
  3995. spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]);
  3996. i = IN_EFFECT_START_NID - EFFECT_START_NID;
  3997. nid = IN_EFFECT_START_NID;
  3998. /* CrystalVoice affects all in effects */
  3999. for (; nid < IN_EFFECT_END_NID; nid++, i++)
  4000. ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
  4001. /* including VoiceFX */
  4002. ret |= ca0132_voicefx_set(codec, (spec->voicefx_val ? 1 : 0));
  4003. /* set correct vipsource */
  4004. oldval = stop_mic1(codec);
  4005. if (spec->use_alt_functions)
  4006. ret |= ca0132_alt_set_vipsource(codec, 1);
  4007. else
  4008. ret |= ca0132_set_vipsource(codec, 1);
  4009. resume_mic1(codec, oldval);
  4010. return ret;
  4011. }
  4012. static int ca0132_mic_boost_set(struct hda_codec *codec, long val)
  4013. {
  4014. struct ca0132_spec *spec = codec->spec;
  4015. int ret = 0;
  4016. if (val) /* on */
  4017. ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
  4018. HDA_INPUT, 0, HDA_AMP_VOLMASK, 3);
  4019. else /* off */
  4020. ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
  4021. HDA_INPUT, 0, HDA_AMP_VOLMASK, 0);
  4022. return ret;
  4023. }
  4024. static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val)
  4025. {
  4026. struct ca0132_spec *spec = codec->spec;
  4027. int ret = 0;
  4028. ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
  4029. HDA_INPUT, 0, HDA_AMP_VOLMASK, val);
  4030. return ret;
  4031. }
  4032. static int ca0132_vnode_switch_set(struct snd_kcontrol *kcontrol,
  4033. struct snd_ctl_elem_value *ucontrol)
  4034. {
  4035. struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
  4036. hda_nid_t nid = get_amp_nid(kcontrol);
  4037. hda_nid_t shared_nid = 0;
  4038. bool effective;
  4039. int ret = 0;
  4040. struct ca0132_spec *spec = codec->spec;
  4041. int auto_jack;
  4042. if (nid == VNID_HP_SEL) {
  4043. auto_jack =
  4044. spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
  4045. if (!auto_jack) {
  4046. if (spec->use_alt_functions)
  4047. ca0132_alt_select_out(codec);
  4048. else
  4049. ca0132_select_out(codec);
  4050. }
  4051. return 1;
  4052. }
  4053. if (nid == VNID_AMIC1_SEL) {
  4054. auto_jack =
  4055. spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
  4056. if (!auto_jack)
  4057. ca0132_select_mic(codec);
  4058. return 1;
  4059. }
  4060. if (nid == VNID_HP_ASEL) {
  4061. if (spec->use_alt_functions)
  4062. ca0132_alt_select_out(codec);
  4063. else
  4064. ca0132_select_out(codec);
  4065. return 1;
  4066. }
  4067. if (nid == VNID_AMIC1_ASEL) {
  4068. ca0132_select_mic(codec);
  4069. return 1;
  4070. }
  4071. /* if effective conditions, then update hw immediately. */
  4072. effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
  4073. if (effective) {
  4074. int dir = get_amp_direction(kcontrol);
  4075. int ch = get_amp_channels(kcontrol);
  4076. unsigned long pval;
  4077. mutex_lock(&codec->control_mutex);
  4078. pval = kcontrol->private_value;
  4079. kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
  4080. 0, dir);
  4081. ret = snd_hda_mixer_amp_switch_put(kcontrol, ucontrol);
  4082. kcontrol->private_value = pval;
  4083. mutex_unlock(&codec->control_mutex);
  4084. }
  4085. return ret;
  4086. }
  4087. /* End of control change helpers. */
  4088. /*
  4089. * Below I've added controls to mess with the effect levels, I've only enabled
  4090. * them on the Sound Blaster Z, but they would probably also work on the
  4091. * Chromebook. I figured they were probably tuned specifically for it, and left
  4092. * out for a reason.
  4093. */
  4094. /* Sets DSP effect level from the sliders above the controls */
  4095. static int ca0132_alt_slider_ctl_set(struct hda_codec *codec, hda_nid_t nid,
  4096. const unsigned int *lookup, int idx)
  4097. {
  4098. int i = 0;
  4099. unsigned int y;
  4100. /*
  4101. * For X_BASS, req 2 is actually crossover freq instead of
  4102. * effect level
  4103. */
  4104. if (nid == X_BASS)
  4105. y = 2;
  4106. else
  4107. y = 1;
  4108. snd_hda_power_up(codec);
  4109. if (nid == XBASS_XOVER) {
  4110. for (i = 0; i < OUT_EFFECTS_COUNT; i++)
  4111. if (ca0132_effects[i].nid == X_BASS)
  4112. break;
  4113. dspio_set_param(codec, ca0132_effects[i].mid, 0x20,
  4114. ca0132_effects[i].reqs[1],
  4115. &(lookup[idx - 1]), sizeof(unsigned int));
  4116. } else {
  4117. /* Find the actual effect structure */
  4118. for (i = 0; i < OUT_EFFECTS_COUNT; i++)
  4119. if (nid == ca0132_effects[i].nid)
  4120. break;
  4121. dspio_set_param(codec, ca0132_effects[i].mid, 0x20,
  4122. ca0132_effects[i].reqs[y],
  4123. &(lookup[idx]), sizeof(unsigned int));
  4124. }
  4125. snd_hda_power_down(codec);
  4126. return 0;
  4127. }
  4128. static int ca0132_alt_xbass_xover_slider_ctl_get(struct snd_kcontrol *kcontrol,
  4129. struct snd_ctl_elem_value *ucontrol)
  4130. {
  4131. struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
  4132. struct ca0132_spec *spec = codec->spec;
  4133. long *valp = ucontrol->value.integer.value;
  4134. *valp = spec->xbass_xover_freq;
  4135. return 0;
  4136. }
  4137. static int ca0132_alt_slider_ctl_get(struct snd_kcontrol *kcontrol,
  4138. struct snd_ctl_elem_value *ucontrol)
  4139. {
  4140. struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
  4141. struct ca0132_spec *spec = codec->spec;
  4142. hda_nid_t nid = get_amp_nid(kcontrol);
  4143. long *valp = ucontrol->value.integer.value;
  4144. int idx = nid - OUT_EFFECT_START_NID;
  4145. *valp = spec->fx_ctl_val[idx];
  4146. return 0;
  4147. }
  4148. /*
  4149. * The X-bass crossover starts at 10hz, so the min is 1. The
  4150. * frequency is set in multiples of 10.
  4151. */
  4152. static int ca0132_alt_xbass_xover_slider_info(struct snd_kcontrol *kcontrol,
  4153. struct snd_ctl_elem_info *uinfo)
  4154. {
  4155. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  4156. uinfo->count = 1;
  4157. uinfo->value.integer.min = 1;
  4158. uinfo->value.integer.max = 100;
  4159. uinfo->value.integer.step = 1;
  4160. return 0;
  4161. }
  4162. static int ca0132_alt_effect_slider_info(struct snd_kcontrol *kcontrol,
  4163. struct snd_ctl_elem_info *uinfo)
  4164. {
  4165. int chs = get_amp_channels(kcontrol);
  4166. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  4167. uinfo->count = chs == 3 ? 2 : 1;
  4168. uinfo->value.integer.min = 0;
  4169. uinfo->value.integer.max = 100;
  4170. uinfo->value.integer.step = 1;
  4171. return 0;
  4172. }
  4173. static int ca0132_alt_xbass_xover_slider_put(struct snd_kcontrol *kcontrol,
  4174. struct snd_ctl_elem_value *ucontrol)
  4175. {
  4176. struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
  4177. struct ca0132_spec *spec = codec->spec;
  4178. hda_nid_t nid = get_amp_nid(kcontrol);
  4179. long *valp = ucontrol->value.integer.value;
  4180. int idx;
  4181. /* any change? */
  4182. if (spec->xbass_xover_freq == *valp)
  4183. return 0;
  4184. spec->xbass_xover_freq = *valp;
  4185. idx = *valp;
  4186. ca0132_alt_slider_ctl_set(codec, nid, float_xbass_xover_lookup, idx);
  4187. return 0;
  4188. }
  4189. static int ca0132_alt_effect_slider_put(struct snd_kcontrol *kcontrol,
  4190. struct snd_ctl_elem_value *ucontrol)
  4191. {
  4192. struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
  4193. struct ca0132_spec *spec = codec->spec;
  4194. hda_nid_t nid = get_amp_nid(kcontrol);
  4195. long *valp = ucontrol->value.integer.value;
  4196. int idx;
  4197. idx = nid - EFFECT_START_NID;
  4198. /* any change? */
  4199. if (spec->fx_ctl_val[idx] == *valp)
  4200. return 0;
  4201. spec->fx_ctl_val[idx] = *valp;
  4202. idx = *valp;
  4203. ca0132_alt_slider_ctl_set(codec, nid, float_zero_to_one_lookup, idx);
  4204. return 0;
  4205. }
  4206. /*
  4207. * Mic Boost Enum for alternative ca0132 codecs. I didn't like that the original
  4208. * only has off or full 30 dB, and didn't like making a volume slider that has
  4209. * traditional 0-100 in alsamixer that goes in big steps. I like enum better.
  4210. */
  4211. #define MIC_BOOST_NUM_OF_STEPS 4
  4212. #define MIC_BOOST_ENUM_MAX_STRLEN 10
  4213. static int ca0132_alt_mic_boost_info(struct snd_kcontrol *kcontrol,
  4214. struct snd_ctl_elem_info *uinfo)
  4215. {
  4216. char *sfx = "dB";
  4217. char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
  4218. uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
  4219. uinfo->count = 1;
  4220. uinfo->value.enumerated.items = MIC_BOOST_NUM_OF_STEPS;
  4221. if (uinfo->value.enumerated.item >= MIC_BOOST_NUM_OF_STEPS)
  4222. uinfo->value.enumerated.item = MIC_BOOST_NUM_OF_STEPS - 1;
  4223. sprintf(namestr, "%d %s", (uinfo->value.enumerated.item * 10), sfx);
  4224. strcpy(uinfo->value.enumerated.name, namestr);
  4225. return 0;
  4226. }
  4227. static int ca0132_alt_mic_boost_get(struct snd_kcontrol *kcontrol,
  4228. struct snd_ctl_elem_value *ucontrol)
  4229. {
  4230. struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
  4231. struct ca0132_spec *spec = codec->spec;
  4232. ucontrol->value.enumerated.item[0] = spec->mic_boost_enum_val;
  4233. return 0;
  4234. }
  4235. static int ca0132_alt_mic_boost_put(struct snd_kcontrol *kcontrol,
  4236. struct snd_ctl_elem_value *ucontrol)
  4237. {
  4238. struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
  4239. struct ca0132_spec *spec = codec->spec;
  4240. int sel = ucontrol->value.enumerated.item[0];
  4241. unsigned int items = MIC_BOOST_NUM_OF_STEPS;
  4242. if (sel >= items)
  4243. return 0;
  4244. codec_dbg(codec, "ca0132_alt_mic_boost: boost=%d\n",
  4245. sel);
  4246. spec->mic_boost_enum_val = sel;
  4247. if (spec->in_enum_val != REAR_LINE_IN)
  4248. ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
  4249. return 1;
  4250. }
  4251. /*
  4252. * Input Select Control for alternative ca0132 codecs. This exists because
  4253. * front microphone has no auto-detect, and we need a way to set the rear
  4254. * as line-in
  4255. */
  4256. static int ca0132_alt_input_source_info(struct snd_kcontrol *kcontrol,
  4257. struct snd_ctl_elem_info *uinfo)
  4258. {
  4259. uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
  4260. uinfo->count = 1;
  4261. uinfo->value.enumerated.items = IN_SRC_NUM_OF_INPUTS;
  4262. if (uinfo->value.enumerated.item >= IN_SRC_NUM_OF_INPUTS)
  4263. uinfo->value.enumerated.item = IN_SRC_NUM_OF_INPUTS - 1;
  4264. strcpy(uinfo->value.enumerated.name,
  4265. in_src_str[uinfo->value.enumerated.item]);
  4266. return 0;
  4267. }
  4268. static int ca0132_alt_input_source_get(struct snd_kcontrol *kcontrol,
  4269. struct snd_ctl_elem_value *ucontrol)
  4270. {
  4271. struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
  4272. struct ca0132_spec *spec = codec->spec;
  4273. ucontrol->value.enumerated.item[0] = spec->in_enum_val;
  4274. return 0;
  4275. }
  4276. static int ca0132_alt_input_source_put(struct snd_kcontrol *kcontrol,
  4277. struct snd_ctl_elem_value *ucontrol)
  4278. {
  4279. struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
  4280. struct ca0132_spec *spec = codec->spec;
  4281. int sel = ucontrol->value.enumerated.item[0];
  4282. unsigned int items = IN_SRC_NUM_OF_INPUTS;
  4283. if (sel >= items)
  4284. return 0;
  4285. codec_dbg(codec, "ca0132_alt_input_select: sel=%d, preset=%s\n",
  4286. sel, in_src_str[sel]);
  4287. spec->in_enum_val = sel;
  4288. ca0132_alt_select_in(codec);
  4289. return 1;
  4290. }
  4291. /* Sound Blaster Z Output Select Control */
  4292. static int ca0132_alt_output_select_get_info(struct snd_kcontrol *kcontrol,
  4293. struct snd_ctl_elem_info *uinfo)
  4294. {
  4295. uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
  4296. uinfo->count = 1;
  4297. uinfo->value.enumerated.items = NUM_OF_OUTPUTS;
  4298. if (uinfo->value.enumerated.item >= NUM_OF_OUTPUTS)
  4299. uinfo->value.enumerated.item = NUM_OF_OUTPUTS - 1;
  4300. strcpy(uinfo->value.enumerated.name,
  4301. alt_out_presets[uinfo->value.enumerated.item].name);
  4302. return 0;
  4303. }
  4304. static int ca0132_alt_output_select_get(struct snd_kcontrol *kcontrol,
  4305. struct snd_ctl_elem_value *ucontrol)
  4306. {
  4307. struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
  4308. struct ca0132_spec *spec = codec->spec;
  4309. ucontrol->value.enumerated.item[0] = spec->out_enum_val;
  4310. return 0;
  4311. }
  4312. static int ca0132_alt_output_select_put(struct snd_kcontrol *kcontrol,
  4313. struct snd_ctl_elem_value *ucontrol)
  4314. {
  4315. struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
  4316. struct ca0132_spec *spec = codec->spec;
  4317. int sel = ucontrol->value.enumerated.item[0];
  4318. unsigned int items = NUM_OF_OUTPUTS;
  4319. unsigned int auto_jack;
  4320. if (sel >= items)
  4321. return 0;
  4322. codec_dbg(codec, "ca0132_alt_output_select: sel=%d, preset=%s\n",
  4323. sel, alt_out_presets[sel].name);
  4324. spec->out_enum_val = sel;
  4325. auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
  4326. if (!auto_jack)
  4327. ca0132_alt_select_out(codec);
  4328. return 1;
  4329. }
  4330. /*
  4331. * Smart Volume output setting control. Three different settings, Normal,
  4332. * which takes the value from the smart volume slider. The two others, loud
  4333. * and night, disregard the slider value and have uneditable values.
  4334. */
  4335. #define NUM_OF_SVM_SETTINGS 3
  4336. static const char *const out_svm_set_enum_str[3] = {"Normal", "Loud", "Night" };
  4337. static int ca0132_alt_svm_setting_info(struct snd_kcontrol *kcontrol,
  4338. struct snd_ctl_elem_info *uinfo)
  4339. {
  4340. uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
  4341. uinfo->count = 1;
  4342. uinfo->value.enumerated.items = NUM_OF_SVM_SETTINGS;
  4343. if (uinfo->value.enumerated.item >= NUM_OF_SVM_SETTINGS)
  4344. uinfo->value.enumerated.item = NUM_OF_SVM_SETTINGS - 1;
  4345. strcpy(uinfo->value.enumerated.name,
  4346. out_svm_set_enum_str[uinfo->value.enumerated.item]);
  4347. return 0;
  4348. }
  4349. static int ca0132_alt_svm_setting_get(struct snd_kcontrol *kcontrol,
  4350. struct snd_ctl_elem_value *ucontrol)
  4351. {
  4352. struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
  4353. struct ca0132_spec *spec = codec->spec;
  4354. ucontrol->value.enumerated.item[0] = spec->smart_volume_setting;
  4355. return 0;
  4356. }
  4357. static int ca0132_alt_svm_setting_put(struct snd_kcontrol *kcontrol,
  4358. struct snd_ctl_elem_value *ucontrol)
  4359. {
  4360. struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
  4361. struct ca0132_spec *spec = codec->spec;
  4362. int sel = ucontrol->value.enumerated.item[0];
  4363. unsigned int items = NUM_OF_SVM_SETTINGS;
  4364. unsigned int idx = SMART_VOLUME - EFFECT_START_NID;
  4365. unsigned int tmp;
  4366. if (sel >= items)
  4367. return 0;
  4368. codec_dbg(codec, "ca0132_alt_svm_setting: sel=%d, preset=%s\n",
  4369. sel, out_svm_set_enum_str[sel]);
  4370. spec->smart_volume_setting = sel;
  4371. switch (sel) {
  4372. case 0:
  4373. tmp = FLOAT_ZERO;
  4374. break;
  4375. case 1:
  4376. tmp = FLOAT_ONE;
  4377. break;
  4378. case 2:
  4379. tmp = FLOAT_TWO;
  4380. break;
  4381. default:
  4382. tmp = FLOAT_ZERO;
  4383. break;
  4384. }
  4385. /* Req 2 is the Smart Volume Setting req. */
  4386. dspio_set_uint_param(codec, ca0132_effects[idx].mid,
  4387. ca0132_effects[idx].reqs[2], tmp);
  4388. return 1;
  4389. }
  4390. /* Sound Blaster Z EQ preset controls */
  4391. static int ca0132_alt_eq_preset_info(struct snd_kcontrol *kcontrol,
  4392. struct snd_ctl_elem_info *uinfo)
  4393. {
  4394. unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets);
  4395. uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
  4396. uinfo->count = 1;
  4397. uinfo->value.enumerated.items = items;
  4398. if (uinfo->value.enumerated.item >= items)
  4399. uinfo->value.enumerated.item = items - 1;
  4400. strcpy(uinfo->value.enumerated.name,
  4401. ca0132_alt_eq_presets[uinfo->value.enumerated.item].name);
  4402. return 0;
  4403. }
  4404. static int ca0132_alt_eq_preset_get(struct snd_kcontrol *kcontrol,
  4405. struct snd_ctl_elem_value *ucontrol)
  4406. {
  4407. struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
  4408. struct ca0132_spec *spec = codec->spec;
  4409. ucontrol->value.enumerated.item[0] = spec->eq_preset_val;
  4410. return 0;
  4411. }
  4412. static int ca0132_alt_eq_preset_put(struct snd_kcontrol *kcontrol,
  4413. struct snd_ctl_elem_value *ucontrol)
  4414. {
  4415. struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
  4416. struct ca0132_spec *spec = codec->spec;
  4417. int i, err = 0;
  4418. int sel = ucontrol->value.enumerated.item[0];
  4419. unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets);
  4420. if (sel >= items)
  4421. return 0;
  4422. codec_dbg(codec, "%s: sel=%d, preset=%s\n", __func__, sel,
  4423. ca0132_alt_eq_presets[sel].name);
  4424. /*
  4425. * Idx 0 is default.
  4426. * Default needs to qualify with CrystalVoice state.
  4427. */
  4428. for (i = 0; i < EQ_PRESET_MAX_PARAM_COUNT; i++) {
  4429. err = dspio_set_uint_param(codec, ca0132_alt_eq_enum.mid,
  4430. ca0132_alt_eq_enum.reqs[i],
  4431. ca0132_alt_eq_presets[sel].vals[i]);
  4432. if (err < 0)
  4433. break;
  4434. }
  4435. if (err >= 0)
  4436. spec->eq_preset_val = sel;
  4437. return 1;
  4438. }
  4439. static int ca0132_voicefx_info(struct snd_kcontrol *kcontrol,
  4440. struct snd_ctl_elem_info *uinfo)
  4441. {
  4442. unsigned int items = ARRAY_SIZE(ca0132_voicefx_presets);
  4443. uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
  4444. uinfo->count = 1;
  4445. uinfo->value.enumerated.items = items;
  4446. if (uinfo->value.enumerated.item >= items)
  4447. uinfo->value.enumerated.item = items - 1;
  4448. strcpy(uinfo->value.enumerated.name,
  4449. ca0132_voicefx_presets[uinfo->value.enumerated.item].name);
  4450. return 0;
  4451. }
  4452. static int ca0132_voicefx_get(struct snd_kcontrol *kcontrol,
  4453. struct snd_ctl_elem_value *ucontrol)
  4454. {
  4455. struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
  4456. struct ca0132_spec *spec = codec->spec;
  4457. ucontrol->value.enumerated.item[0] = spec->voicefx_val;
  4458. return 0;
  4459. }
  4460. static int ca0132_voicefx_put(struct snd_kcontrol *kcontrol,
  4461. struct snd_ctl_elem_value *ucontrol)
  4462. {
  4463. struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
  4464. struct ca0132_spec *spec = codec->spec;
  4465. int i, err = 0;
  4466. int sel = ucontrol->value.enumerated.item[0];
  4467. if (sel >= ARRAY_SIZE(ca0132_voicefx_presets))
  4468. return 0;
  4469. codec_dbg(codec, "ca0132_voicefx_put: sel=%d, preset=%s\n",
  4470. sel, ca0132_voicefx_presets[sel].name);
  4471. /*
  4472. * Idx 0 is default.
  4473. * Default needs to qualify with CrystalVoice state.
  4474. */
  4475. for (i = 0; i < VOICEFX_MAX_PARAM_COUNT; i++) {
  4476. err = dspio_set_uint_param(codec, ca0132_voicefx.mid,
  4477. ca0132_voicefx.reqs[i],
  4478. ca0132_voicefx_presets[sel].vals[i]);
  4479. if (err < 0)
  4480. break;
  4481. }
  4482. if (err >= 0) {
  4483. spec->voicefx_val = sel;
  4484. /* enable voice fx */
  4485. ca0132_voicefx_set(codec, (sel ? 1 : 0));
  4486. }
  4487. return 1;
  4488. }
  4489. static int ca0132_switch_get(struct snd_kcontrol *kcontrol,
  4490. struct snd_ctl_elem_value *ucontrol)
  4491. {
  4492. struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
  4493. struct ca0132_spec *spec = codec->spec;
  4494. hda_nid_t nid = get_amp_nid(kcontrol);
  4495. int ch = get_amp_channels(kcontrol);
  4496. long *valp = ucontrol->value.integer.value;
  4497. /* vnode */
  4498. if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
  4499. if (ch & 1) {
  4500. *valp = spec->vnode_lswitch[nid - VNODE_START_NID];
  4501. valp++;
  4502. }
  4503. if (ch & 2) {
  4504. *valp = spec->vnode_rswitch[nid - VNODE_START_NID];
  4505. valp++;
  4506. }
  4507. return 0;
  4508. }
  4509. /* effects, include PE and CrystalVoice */
  4510. if ((nid >= EFFECT_START_NID) && (nid < EFFECT_END_NID)) {
  4511. *valp = spec->effects_switch[nid - EFFECT_START_NID];
  4512. return 0;
  4513. }
  4514. /* mic boost */
  4515. if (nid == spec->input_pins[0]) {
  4516. *valp = spec->cur_mic_boost;
  4517. return 0;
  4518. }
  4519. return 0;
  4520. }
  4521. static int ca0132_switch_put(struct snd_kcontrol *kcontrol,
  4522. struct snd_ctl_elem_value *ucontrol)
  4523. {
  4524. struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
  4525. struct ca0132_spec *spec = codec->spec;
  4526. hda_nid_t nid = get_amp_nid(kcontrol);
  4527. int ch = get_amp_channels(kcontrol);
  4528. long *valp = ucontrol->value.integer.value;
  4529. int changed = 1;
  4530. codec_dbg(codec, "ca0132_switch_put: nid=0x%x, val=%ld\n",
  4531. nid, *valp);
  4532. snd_hda_power_up(codec);
  4533. /* vnode */
  4534. if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
  4535. if (ch & 1) {
  4536. spec->vnode_lswitch[nid - VNODE_START_NID] = *valp;
  4537. valp++;
  4538. }
  4539. if (ch & 2) {
  4540. spec->vnode_rswitch[nid - VNODE_START_NID] = *valp;
  4541. valp++;
  4542. }
  4543. changed = ca0132_vnode_switch_set(kcontrol, ucontrol);
  4544. goto exit;
  4545. }
  4546. /* PE */
  4547. if (nid == PLAY_ENHANCEMENT) {
  4548. spec->effects_switch[nid - EFFECT_START_NID] = *valp;
  4549. changed = ca0132_pe_switch_set(codec);
  4550. goto exit;
  4551. }
  4552. /* CrystalVoice */
  4553. if (nid == CRYSTAL_VOICE) {
  4554. spec->effects_switch[nid - EFFECT_START_NID] = *valp;
  4555. changed = ca0132_cvoice_switch_set(codec);
  4556. goto exit;
  4557. }
  4558. /* out and in effects */
  4559. if (((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) ||
  4560. ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID))) {
  4561. spec->effects_switch[nid - EFFECT_START_NID] = *valp;
  4562. changed = ca0132_effects_set(codec, nid, *valp);
  4563. goto exit;
  4564. }
  4565. /* mic boost */
  4566. if (nid == spec->input_pins[0]) {
  4567. spec->cur_mic_boost = *valp;
  4568. if (spec->use_alt_functions) {
  4569. if (spec->in_enum_val != REAR_LINE_IN)
  4570. changed = ca0132_mic_boost_set(codec, *valp);
  4571. } else {
  4572. /* Mic boost does not apply to Digital Mic */
  4573. if (spec->cur_mic_type != DIGITAL_MIC)
  4574. changed = ca0132_mic_boost_set(codec, *valp);
  4575. }
  4576. goto exit;
  4577. }
  4578. exit:
  4579. snd_hda_power_down(codec);
  4580. return changed;
  4581. }
  4582. /*
  4583. * Volume related
  4584. */
  4585. /*
  4586. * Sets the internal DSP decibel level to match the DAC for output, and the
  4587. * ADC for input. Currently only the SBZ sets dsp capture volume level, and
  4588. * all alternative codecs set DSP playback volume.
  4589. */
  4590. static void ca0132_alt_dsp_volume_put(struct hda_codec *codec, hda_nid_t nid)
  4591. {
  4592. struct ca0132_spec *spec = codec->spec;
  4593. unsigned int dsp_dir;
  4594. unsigned int lookup_val;
  4595. if (nid == VNID_SPK)
  4596. dsp_dir = DSP_VOL_OUT;
  4597. else
  4598. dsp_dir = DSP_VOL_IN;
  4599. lookup_val = spec->vnode_lvol[nid - VNODE_START_NID];
  4600. dspio_set_uint_param(codec,
  4601. ca0132_alt_vol_ctls[dsp_dir].mid,
  4602. ca0132_alt_vol_ctls[dsp_dir].reqs[0],
  4603. float_vol_db_lookup[lookup_val]);
  4604. lookup_val = spec->vnode_rvol[nid - VNODE_START_NID];
  4605. dspio_set_uint_param(codec,
  4606. ca0132_alt_vol_ctls[dsp_dir].mid,
  4607. ca0132_alt_vol_ctls[dsp_dir].reqs[1],
  4608. float_vol_db_lookup[lookup_val]);
  4609. dspio_set_uint_param(codec,
  4610. ca0132_alt_vol_ctls[dsp_dir].mid,
  4611. ca0132_alt_vol_ctls[dsp_dir].reqs[2], FLOAT_ZERO);
  4612. }
  4613. static int ca0132_volume_info(struct snd_kcontrol *kcontrol,
  4614. struct snd_ctl_elem_info *uinfo)
  4615. {
  4616. struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
  4617. struct ca0132_spec *spec = codec->spec;
  4618. hda_nid_t nid = get_amp_nid(kcontrol);
  4619. int ch = get_amp_channels(kcontrol);
  4620. int dir = get_amp_direction(kcontrol);
  4621. unsigned long pval;
  4622. int err;
  4623. switch (nid) {
  4624. case VNID_SPK:
  4625. /* follow shared_out info */
  4626. nid = spec->shared_out_nid;
  4627. mutex_lock(&codec->control_mutex);
  4628. pval = kcontrol->private_value;
  4629. kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
  4630. err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
  4631. kcontrol->private_value = pval;
  4632. mutex_unlock(&codec->control_mutex);
  4633. break;
  4634. case VNID_MIC:
  4635. /* follow shared_mic info */
  4636. nid = spec->shared_mic_nid;
  4637. mutex_lock(&codec->control_mutex);
  4638. pval = kcontrol->private_value;
  4639. kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
  4640. err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
  4641. kcontrol->private_value = pval;
  4642. mutex_unlock(&codec->control_mutex);
  4643. break;
  4644. default:
  4645. err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
  4646. }
  4647. return err;
  4648. }
  4649. static int ca0132_volume_get(struct snd_kcontrol *kcontrol,
  4650. struct snd_ctl_elem_value *ucontrol)
  4651. {
  4652. struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
  4653. struct ca0132_spec *spec = codec->spec;
  4654. hda_nid_t nid = get_amp_nid(kcontrol);
  4655. int ch = get_amp_channels(kcontrol);
  4656. long *valp = ucontrol->value.integer.value;
  4657. /* store the left and right volume */
  4658. if (ch & 1) {
  4659. *valp = spec->vnode_lvol[nid - VNODE_START_NID];
  4660. valp++;
  4661. }
  4662. if (ch & 2) {
  4663. *valp = spec->vnode_rvol[nid - VNODE_START_NID];
  4664. valp++;
  4665. }
  4666. return 0;
  4667. }
  4668. static int ca0132_volume_put(struct snd_kcontrol *kcontrol,
  4669. struct snd_ctl_elem_value *ucontrol)
  4670. {
  4671. struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
  4672. struct ca0132_spec *spec = codec->spec;
  4673. hda_nid_t nid = get_amp_nid(kcontrol);
  4674. int ch = get_amp_channels(kcontrol);
  4675. long *valp = ucontrol->value.integer.value;
  4676. hda_nid_t shared_nid = 0;
  4677. bool effective;
  4678. int changed = 1;
  4679. /* store the left and right volume */
  4680. if (ch & 1) {
  4681. spec->vnode_lvol[nid - VNODE_START_NID] = *valp;
  4682. valp++;
  4683. }
  4684. if (ch & 2) {
  4685. spec->vnode_rvol[nid - VNODE_START_NID] = *valp;
  4686. valp++;
  4687. }
  4688. /* if effective conditions, then update hw immediately. */
  4689. effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
  4690. if (effective) {
  4691. int dir = get_amp_direction(kcontrol);
  4692. unsigned long pval;
  4693. snd_hda_power_up(codec);
  4694. mutex_lock(&codec->control_mutex);
  4695. pval = kcontrol->private_value;
  4696. kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
  4697. 0, dir);
  4698. changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol);
  4699. kcontrol->private_value = pval;
  4700. mutex_unlock(&codec->control_mutex);
  4701. snd_hda_power_down(codec);
  4702. }
  4703. return changed;
  4704. }
  4705. /*
  4706. * This function is the same as the one above, because using an if statement
  4707. * inside of the above volume control for the DSP volume would cause too much
  4708. * lag. This is a lot more smooth.
  4709. */
  4710. static int ca0132_alt_volume_put(struct snd_kcontrol *kcontrol,
  4711. struct snd_ctl_elem_value *ucontrol)
  4712. {
  4713. struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
  4714. struct ca0132_spec *spec = codec->spec;
  4715. hda_nid_t nid = get_amp_nid(kcontrol);
  4716. int ch = get_amp_channels(kcontrol);
  4717. long *valp = ucontrol->value.integer.value;
  4718. hda_nid_t vnid = 0;
  4719. int changed = 1;
  4720. switch (nid) {
  4721. case 0x02:
  4722. vnid = VNID_SPK;
  4723. break;
  4724. case 0x07:
  4725. vnid = VNID_MIC;
  4726. break;
  4727. }
  4728. /* store the left and right volume */
  4729. if (ch & 1) {
  4730. spec->vnode_lvol[vnid - VNODE_START_NID] = *valp;
  4731. valp++;
  4732. }
  4733. if (ch & 2) {
  4734. spec->vnode_rvol[vnid - VNODE_START_NID] = *valp;
  4735. valp++;
  4736. }
  4737. snd_hda_power_up(codec);
  4738. ca0132_alt_dsp_volume_put(codec, vnid);
  4739. mutex_lock(&codec->control_mutex);
  4740. changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol);
  4741. mutex_unlock(&codec->control_mutex);
  4742. snd_hda_power_down(codec);
  4743. return changed;
  4744. }
  4745. static int ca0132_volume_tlv(struct snd_kcontrol *kcontrol, int op_flag,
  4746. unsigned int size, unsigned int __user *tlv)
  4747. {
  4748. struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
  4749. struct ca0132_spec *spec = codec->spec;
  4750. hda_nid_t nid = get_amp_nid(kcontrol);
  4751. int ch = get_amp_channels(kcontrol);
  4752. int dir = get_amp_direction(kcontrol);
  4753. unsigned long pval;
  4754. int err;
  4755. switch (nid) {
  4756. case VNID_SPK:
  4757. /* follow shared_out tlv */
  4758. nid = spec->shared_out_nid;
  4759. mutex_lock(&codec->control_mutex);
  4760. pval = kcontrol->private_value;
  4761. kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
  4762. err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
  4763. kcontrol->private_value = pval;
  4764. mutex_unlock(&codec->control_mutex);
  4765. break;
  4766. case VNID_MIC:
  4767. /* follow shared_mic tlv */
  4768. nid = spec->shared_mic_nid;
  4769. mutex_lock(&codec->control_mutex);
  4770. pval = kcontrol->private_value;
  4771. kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
  4772. err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
  4773. kcontrol->private_value = pval;
  4774. mutex_unlock(&codec->control_mutex);
  4775. break;
  4776. default:
  4777. err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
  4778. }
  4779. return err;
  4780. }
  4781. /* Add volume slider control for effect level */
  4782. static int ca0132_alt_add_effect_slider(struct hda_codec *codec, hda_nid_t nid,
  4783. const char *pfx, int dir)
  4784. {
  4785. char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
  4786. int type = dir ? HDA_INPUT : HDA_OUTPUT;
  4787. struct snd_kcontrol_new knew =
  4788. HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
  4789. sprintf(namestr, "FX: %s %s Volume", pfx, dirstr[dir]);
  4790. knew.tlv.c = NULL;
  4791. switch (nid) {
  4792. case XBASS_XOVER:
  4793. knew.info = ca0132_alt_xbass_xover_slider_info;
  4794. knew.get = ca0132_alt_xbass_xover_slider_ctl_get;
  4795. knew.put = ca0132_alt_xbass_xover_slider_put;
  4796. break;
  4797. default:
  4798. knew.info = ca0132_alt_effect_slider_info;
  4799. knew.get = ca0132_alt_slider_ctl_get;
  4800. knew.put = ca0132_alt_effect_slider_put;
  4801. knew.private_value =
  4802. HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
  4803. break;
  4804. }
  4805. return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
  4806. }
  4807. /*
  4808. * Added FX: prefix for the alternative codecs, because otherwise the surround
  4809. * effect would conflict with the Surround sound volume control. Also seems more
  4810. * clear as to what the switches do. Left alone for others.
  4811. */
  4812. static int add_fx_switch(struct hda_codec *codec, hda_nid_t nid,
  4813. const char *pfx, int dir)
  4814. {
  4815. struct ca0132_spec *spec = codec->spec;
  4816. char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
  4817. int type = dir ? HDA_INPUT : HDA_OUTPUT;
  4818. struct snd_kcontrol_new knew =
  4819. CA0132_CODEC_MUTE_MONO(namestr, nid, 1, type);
  4820. /* If using alt_controls, add FX: prefix. But, don't add FX:
  4821. * prefix to OutFX or InFX enable controls.
  4822. */
  4823. if ((spec->use_alt_controls) && (nid <= IN_EFFECT_END_NID))
  4824. sprintf(namestr, "FX: %s %s Switch", pfx, dirstr[dir]);
  4825. else
  4826. sprintf(namestr, "%s %s Switch", pfx, dirstr[dir]);
  4827. return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
  4828. }
  4829. static int add_voicefx(struct hda_codec *codec)
  4830. {
  4831. struct snd_kcontrol_new knew =
  4832. HDA_CODEC_MUTE_MONO(ca0132_voicefx.name,
  4833. VOICEFX, 1, 0, HDA_INPUT);
  4834. knew.info = ca0132_voicefx_info;
  4835. knew.get = ca0132_voicefx_get;
  4836. knew.put = ca0132_voicefx_put;
  4837. return snd_hda_ctl_add(codec, VOICEFX, snd_ctl_new1(&knew, codec));
  4838. }
  4839. /* Create the EQ Preset control */
  4840. static int add_ca0132_alt_eq_presets(struct hda_codec *codec)
  4841. {
  4842. struct snd_kcontrol_new knew =
  4843. HDA_CODEC_MUTE_MONO(ca0132_alt_eq_enum.name,
  4844. EQ_PRESET_ENUM, 1, 0, HDA_OUTPUT);
  4845. knew.info = ca0132_alt_eq_preset_info;
  4846. knew.get = ca0132_alt_eq_preset_get;
  4847. knew.put = ca0132_alt_eq_preset_put;
  4848. return snd_hda_ctl_add(codec, EQ_PRESET_ENUM,
  4849. snd_ctl_new1(&knew, codec));
  4850. }
  4851. /*
  4852. * Add enumerated control for the three different settings of the smart volume
  4853. * output effect. Normal just uses the slider value, and loud and night are
  4854. * their own things that ignore that value.
  4855. */
  4856. static int ca0132_alt_add_svm_enum(struct hda_codec *codec)
  4857. {
  4858. struct snd_kcontrol_new knew =
  4859. HDA_CODEC_MUTE_MONO("FX: Smart Volume Setting",
  4860. SMART_VOLUME_ENUM, 1, 0, HDA_OUTPUT);
  4861. knew.info = ca0132_alt_svm_setting_info;
  4862. knew.get = ca0132_alt_svm_setting_get;
  4863. knew.put = ca0132_alt_svm_setting_put;
  4864. return snd_hda_ctl_add(codec, SMART_VOLUME_ENUM,
  4865. snd_ctl_new1(&knew, codec));
  4866. }
  4867. /*
  4868. * Create an Output Select enumerated control for codecs with surround
  4869. * out capabilities.
  4870. */
  4871. static int ca0132_alt_add_output_enum(struct hda_codec *codec)
  4872. {
  4873. struct snd_kcontrol_new knew =
  4874. HDA_CODEC_MUTE_MONO("Output Select",
  4875. OUTPUT_SOURCE_ENUM, 1, 0, HDA_OUTPUT);
  4876. knew.info = ca0132_alt_output_select_get_info;
  4877. knew.get = ca0132_alt_output_select_get;
  4878. knew.put = ca0132_alt_output_select_put;
  4879. return snd_hda_ctl_add(codec, OUTPUT_SOURCE_ENUM,
  4880. snd_ctl_new1(&knew, codec));
  4881. }
  4882. /*
  4883. * Create an Input Source enumerated control for the alternate ca0132 codecs
  4884. * because the front microphone has no auto-detect, and Line-in has to be set
  4885. * somehow.
  4886. */
  4887. static int ca0132_alt_add_input_enum(struct hda_codec *codec)
  4888. {
  4889. struct snd_kcontrol_new knew =
  4890. HDA_CODEC_MUTE_MONO("Input Source",
  4891. INPUT_SOURCE_ENUM, 1, 0, HDA_INPUT);
  4892. knew.info = ca0132_alt_input_source_info;
  4893. knew.get = ca0132_alt_input_source_get;
  4894. knew.put = ca0132_alt_input_source_put;
  4895. return snd_hda_ctl_add(codec, INPUT_SOURCE_ENUM,
  4896. snd_ctl_new1(&knew, codec));
  4897. }
  4898. /*
  4899. * Add mic boost enumerated control. Switches through 0dB to 30dB. This adds
  4900. * more control than the original mic boost, which is either full 30dB or off.
  4901. */
  4902. static int ca0132_alt_add_mic_boost_enum(struct hda_codec *codec)
  4903. {
  4904. struct snd_kcontrol_new knew =
  4905. HDA_CODEC_MUTE_MONO("Mic Boost Capture Switch",
  4906. MIC_BOOST_ENUM, 1, 0, HDA_INPUT);
  4907. knew.info = ca0132_alt_mic_boost_info;
  4908. knew.get = ca0132_alt_mic_boost_get;
  4909. knew.put = ca0132_alt_mic_boost_put;
  4910. return snd_hda_ctl_add(codec, MIC_BOOST_ENUM,
  4911. snd_ctl_new1(&knew, codec));
  4912. }
  4913. /*
  4914. * Need to create slave controls for the alternate codecs that have surround
  4915. * capabilities.
  4916. */
  4917. static const char * const ca0132_alt_slave_pfxs[] = {
  4918. "Front", "Surround", "Center", "LFE", NULL,
  4919. };
  4920. /*
  4921. * Also need special channel map, because the default one is incorrect.
  4922. * I think this has to do with the pin for rear surround being 0x11,
  4923. * and the center/lfe being 0x10. Usually the pin order is the opposite.
  4924. */
  4925. static const struct snd_pcm_chmap_elem ca0132_alt_chmaps[] = {
  4926. { .channels = 2,
  4927. .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR } },
  4928. { .channels = 4,
  4929. .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR,
  4930. SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
  4931. { .channels = 6,
  4932. .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR,
  4933. SNDRV_CHMAP_FC, SNDRV_CHMAP_LFE,
  4934. SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
  4935. { }
  4936. };
  4937. /* Add the correct chmap for streams with 6 channels. */
  4938. static void ca0132_alt_add_chmap_ctls(struct hda_codec *codec)
  4939. {
  4940. int err = 0;
  4941. struct hda_pcm *pcm;
  4942. list_for_each_entry(pcm, &codec->pcm_list_head, list) {
  4943. struct hda_pcm_stream *hinfo =
  4944. &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
  4945. struct snd_pcm_chmap *chmap;
  4946. const struct snd_pcm_chmap_elem *elem;
  4947. elem = ca0132_alt_chmaps;
  4948. if (hinfo->channels_max == 6) {
  4949. err = snd_pcm_add_chmap_ctls(pcm->pcm,
  4950. SNDRV_PCM_STREAM_PLAYBACK,
  4951. elem, hinfo->channels_max, 0, &chmap);
  4952. if (err < 0)
  4953. codec_dbg(codec, "snd_pcm_add_chmap_ctls failed!");
  4954. }
  4955. }
  4956. }
  4957. /*
  4958. * When changing Node IDs for Mixer Controls below, make sure to update
  4959. * Node IDs in ca0132_config() as well.
  4960. */
  4961. static const struct snd_kcontrol_new ca0132_mixer[] = {
  4962. CA0132_CODEC_VOL("Master Playback Volume", VNID_SPK, HDA_OUTPUT),
  4963. CA0132_CODEC_MUTE("Master Playback Switch", VNID_SPK, HDA_OUTPUT),
  4964. CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT),
  4965. CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
  4966. HDA_CODEC_VOLUME("Analog-Mic2 Capture Volume", 0x08, 0, HDA_INPUT),
  4967. HDA_CODEC_MUTE("Analog-Mic2 Capture Switch", 0x08, 0, HDA_INPUT),
  4968. HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
  4969. HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
  4970. CA0132_CODEC_MUTE_MONO("Mic1-Boost (30dB) Capture Switch",
  4971. 0x12, 1, HDA_INPUT),
  4972. CA0132_CODEC_MUTE_MONO("HP/Speaker Playback Switch",
  4973. VNID_HP_SEL, 1, HDA_OUTPUT),
  4974. CA0132_CODEC_MUTE_MONO("AMic1/DMic Capture Switch",
  4975. VNID_AMIC1_SEL, 1, HDA_INPUT),
  4976. CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
  4977. VNID_HP_ASEL, 1, HDA_OUTPUT),
  4978. CA0132_CODEC_MUTE_MONO("AMic1/DMic Auto Detect Capture Switch",
  4979. VNID_AMIC1_ASEL, 1, HDA_INPUT),
  4980. { } /* end */
  4981. };
  4982. /*
  4983. * Desktop specific control mixer. Removes auto-detect for mic, and adds
  4984. * surround controls. Also sets both the Front Playback and Capture Volume
  4985. * controls to alt so they set the DSP's decibel level.
  4986. */
  4987. static const struct snd_kcontrol_new desktop_mixer[] = {
  4988. CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT),
  4989. CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT),
  4990. HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT),
  4991. HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT),
  4992. HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT),
  4993. HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT),
  4994. HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT),
  4995. HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT),
  4996. CA0132_ALT_CODEC_VOL("Capture Volume", 0x07, HDA_INPUT),
  4997. CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
  4998. HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
  4999. HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
  5000. CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
  5001. VNID_HP_ASEL, 1, HDA_OUTPUT),
  5002. { } /* end */
  5003. };
  5004. /*
  5005. * Same as the Sound Blaster Z, except doesn't use the alt volume for capture
  5006. * because it doesn't set decibel levels for the DSP for capture.
  5007. */
  5008. static const struct snd_kcontrol_new r3di_mixer[] = {
  5009. CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT),
  5010. CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT),
  5011. HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT),
  5012. HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT),
  5013. HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT),
  5014. HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT),
  5015. HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT),
  5016. HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT),
  5017. CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT),
  5018. CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
  5019. HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
  5020. HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
  5021. CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
  5022. VNID_HP_ASEL, 1, HDA_OUTPUT),
  5023. { } /* end */
  5024. };
  5025. static int ca0132_build_controls(struct hda_codec *codec)
  5026. {
  5027. struct ca0132_spec *spec = codec->spec;
  5028. int i, num_fx, num_sliders;
  5029. int err = 0;
  5030. /* Add Mixer controls */
  5031. for (i = 0; i < spec->num_mixers; i++) {
  5032. err = snd_hda_add_new_ctls(codec, spec->mixers[i]);
  5033. if (err < 0)
  5034. return err;
  5035. }
  5036. /* Setup vmaster with surround slaves for desktop ca0132 devices */
  5037. if (spec->use_alt_functions) {
  5038. snd_hda_set_vmaster_tlv(codec, spec->dacs[0], HDA_OUTPUT,
  5039. spec->tlv);
  5040. snd_hda_add_vmaster(codec, "Master Playback Volume",
  5041. spec->tlv, ca0132_alt_slave_pfxs,
  5042. "Playback Volume");
  5043. err = __snd_hda_add_vmaster(codec, "Master Playback Switch",
  5044. NULL, ca0132_alt_slave_pfxs,
  5045. "Playback Switch",
  5046. true, &spec->vmaster_mute.sw_kctl);
  5047. }
  5048. /* Add in and out effects controls.
  5049. * VoiceFX, PE and CrystalVoice are added separately.
  5050. */
  5051. num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
  5052. for (i = 0; i < num_fx; i++) {
  5053. /* SBZ and R3D break if Echo Cancellation is used. */
  5054. if (spec->quirk == QUIRK_SBZ || spec->quirk == QUIRK_R3D) {
  5055. if (i == (ECHO_CANCELLATION - IN_EFFECT_START_NID +
  5056. OUT_EFFECTS_COUNT))
  5057. continue;
  5058. }
  5059. err = add_fx_switch(codec, ca0132_effects[i].nid,
  5060. ca0132_effects[i].name,
  5061. ca0132_effects[i].direct);
  5062. if (err < 0)
  5063. return err;
  5064. }
  5065. /*
  5066. * If codec has use_alt_controls set to true, add effect level sliders,
  5067. * EQ presets, and Smart Volume presets. Also, change names to add FX
  5068. * prefix, and change PlayEnhancement and CrystalVoice to match.
  5069. */
  5070. if (spec->use_alt_controls) {
  5071. ca0132_alt_add_svm_enum(codec);
  5072. add_ca0132_alt_eq_presets(codec);
  5073. err = add_fx_switch(codec, PLAY_ENHANCEMENT,
  5074. "Enable OutFX", 0);
  5075. if (err < 0)
  5076. return err;
  5077. err = add_fx_switch(codec, CRYSTAL_VOICE,
  5078. "Enable InFX", 1);
  5079. if (err < 0)
  5080. return err;
  5081. num_sliders = OUT_EFFECTS_COUNT - 1;
  5082. for (i = 0; i < num_sliders; i++) {
  5083. err = ca0132_alt_add_effect_slider(codec,
  5084. ca0132_effects[i].nid,
  5085. ca0132_effects[i].name,
  5086. ca0132_effects[i].direct);
  5087. if (err < 0)
  5088. return err;
  5089. }
  5090. err = ca0132_alt_add_effect_slider(codec, XBASS_XOVER,
  5091. "X-Bass Crossover", EFX_DIR_OUT);
  5092. if (err < 0)
  5093. return err;
  5094. } else {
  5095. err = add_fx_switch(codec, PLAY_ENHANCEMENT,
  5096. "PlayEnhancement", 0);
  5097. if (err < 0)
  5098. return err;
  5099. err = add_fx_switch(codec, CRYSTAL_VOICE,
  5100. "CrystalVoice", 1);
  5101. if (err < 0)
  5102. return err;
  5103. }
  5104. add_voicefx(codec);
  5105. /*
  5106. * If the codec uses alt_functions, you need the enumerated controls
  5107. * to select the new outputs and inputs, plus add the new mic boost
  5108. * setting control.
  5109. */
  5110. if (spec->use_alt_functions) {
  5111. ca0132_alt_add_output_enum(codec);
  5112. ca0132_alt_add_input_enum(codec);
  5113. ca0132_alt_add_mic_boost_enum(codec);
  5114. }
  5115. #ifdef ENABLE_TUNING_CONTROLS
  5116. add_tuning_ctls(codec);
  5117. #endif
  5118. err = snd_hda_jack_add_kctls(codec, &spec->autocfg);
  5119. if (err < 0)
  5120. return err;
  5121. if (spec->dig_out) {
  5122. err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out,
  5123. spec->dig_out);
  5124. if (err < 0)
  5125. return err;
  5126. err = snd_hda_create_spdif_share_sw(codec, &spec->multiout);
  5127. if (err < 0)
  5128. return err;
  5129. /* spec->multiout.share_spdif = 1; */
  5130. }
  5131. if (spec->dig_in) {
  5132. err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in);
  5133. if (err < 0)
  5134. return err;
  5135. }
  5136. if (spec->use_alt_functions)
  5137. ca0132_alt_add_chmap_ctls(codec);
  5138. return 0;
  5139. }
  5140. /*
  5141. * PCM
  5142. */
  5143. static const struct hda_pcm_stream ca0132_pcm_analog_playback = {
  5144. .substreams = 1,
  5145. .channels_min = 2,
  5146. .channels_max = 6,
  5147. .ops = {
  5148. .prepare = ca0132_playback_pcm_prepare,
  5149. .cleanup = ca0132_playback_pcm_cleanup,
  5150. .get_delay = ca0132_playback_pcm_delay,
  5151. },
  5152. };
  5153. static const struct hda_pcm_stream ca0132_pcm_analog_capture = {
  5154. .substreams = 1,
  5155. .channels_min = 2,
  5156. .channels_max = 2,
  5157. .ops = {
  5158. .prepare = ca0132_capture_pcm_prepare,
  5159. .cleanup = ca0132_capture_pcm_cleanup,
  5160. .get_delay = ca0132_capture_pcm_delay,
  5161. },
  5162. };
  5163. static const struct hda_pcm_stream ca0132_pcm_digital_playback = {
  5164. .substreams = 1,
  5165. .channels_min = 2,
  5166. .channels_max = 2,
  5167. .ops = {
  5168. .open = ca0132_dig_playback_pcm_open,
  5169. .close = ca0132_dig_playback_pcm_close,
  5170. .prepare = ca0132_dig_playback_pcm_prepare,
  5171. .cleanup = ca0132_dig_playback_pcm_cleanup
  5172. },
  5173. };
  5174. static const struct hda_pcm_stream ca0132_pcm_digital_capture = {
  5175. .substreams = 1,
  5176. .channels_min = 2,
  5177. .channels_max = 2,
  5178. };
  5179. static int ca0132_build_pcms(struct hda_codec *codec)
  5180. {
  5181. struct ca0132_spec *spec = codec->spec;
  5182. struct hda_pcm *info;
  5183. info = snd_hda_codec_pcm_new(codec, "CA0132 Analog");
  5184. if (!info)
  5185. return -ENOMEM;
  5186. if (spec->use_alt_functions) {
  5187. info->own_chmap = true;
  5188. info->stream[SNDRV_PCM_STREAM_PLAYBACK].chmap
  5189. = ca0132_alt_chmaps;
  5190. }
  5191. info->stream[SNDRV_PCM_STREAM_PLAYBACK] = ca0132_pcm_analog_playback;
  5192. info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dacs[0];
  5193. info->stream[SNDRV_PCM_STREAM_PLAYBACK].channels_max =
  5194. spec->multiout.max_channels;
  5195. info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
  5196. info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
  5197. info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0];
  5198. /* With the DSP enabled, desktops don't use this ADC. */
  5199. if (!spec->use_alt_functions) {
  5200. info = snd_hda_codec_pcm_new(codec, "CA0132 Analog Mic-In2");
  5201. if (!info)
  5202. return -ENOMEM;
  5203. info->stream[SNDRV_PCM_STREAM_CAPTURE] =
  5204. ca0132_pcm_analog_capture;
  5205. info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
  5206. info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[1];
  5207. }
  5208. info = snd_hda_codec_pcm_new(codec, "CA0132 What U Hear");
  5209. if (!info)
  5210. return -ENOMEM;
  5211. info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
  5212. info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
  5213. info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[2];
  5214. if (!spec->dig_out && !spec->dig_in)
  5215. return 0;
  5216. info = snd_hda_codec_pcm_new(codec, "CA0132 Digital");
  5217. if (!info)
  5218. return -ENOMEM;
  5219. info->pcm_type = HDA_PCM_TYPE_SPDIF;
  5220. if (spec->dig_out) {
  5221. info->stream[SNDRV_PCM_STREAM_PLAYBACK] =
  5222. ca0132_pcm_digital_playback;
  5223. info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out;
  5224. }
  5225. if (spec->dig_in) {
  5226. info->stream[SNDRV_PCM_STREAM_CAPTURE] =
  5227. ca0132_pcm_digital_capture;
  5228. info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in;
  5229. }
  5230. return 0;
  5231. }
  5232. static void init_output(struct hda_codec *codec, hda_nid_t pin, hda_nid_t dac)
  5233. {
  5234. if (pin) {
  5235. snd_hda_set_pin_ctl(codec, pin, PIN_HP);
  5236. if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
  5237. snd_hda_codec_write(codec, pin, 0,
  5238. AC_VERB_SET_AMP_GAIN_MUTE,
  5239. AMP_OUT_UNMUTE);
  5240. }
  5241. if (dac && (get_wcaps(codec, dac) & AC_WCAP_OUT_AMP))
  5242. snd_hda_codec_write(codec, dac, 0,
  5243. AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_ZERO);
  5244. }
  5245. static void init_input(struct hda_codec *codec, hda_nid_t pin, hda_nid_t adc)
  5246. {
  5247. if (pin) {
  5248. snd_hda_set_pin_ctl(codec, pin, PIN_VREF80);
  5249. if (get_wcaps(codec, pin) & AC_WCAP_IN_AMP)
  5250. snd_hda_codec_write(codec, pin, 0,
  5251. AC_VERB_SET_AMP_GAIN_MUTE,
  5252. AMP_IN_UNMUTE(0));
  5253. }
  5254. if (adc && (get_wcaps(codec, adc) & AC_WCAP_IN_AMP)) {
  5255. snd_hda_codec_write(codec, adc, 0, AC_VERB_SET_AMP_GAIN_MUTE,
  5256. AMP_IN_UNMUTE(0));
  5257. /* init to 0 dB and unmute. */
  5258. snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
  5259. HDA_AMP_VOLMASK, 0x5a);
  5260. snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
  5261. HDA_AMP_MUTE, 0);
  5262. }
  5263. }
  5264. static void refresh_amp_caps(struct hda_codec *codec, hda_nid_t nid, int dir)
  5265. {
  5266. unsigned int caps;
  5267. caps = snd_hda_param_read(codec, nid, dir == HDA_OUTPUT ?
  5268. AC_PAR_AMP_OUT_CAP : AC_PAR_AMP_IN_CAP);
  5269. snd_hda_override_amp_caps(codec, nid, dir, caps);
  5270. }
  5271. /*
  5272. * Switch between Digital built-in mic and analog mic.
  5273. */
  5274. static void ca0132_set_dmic(struct hda_codec *codec, int enable)
  5275. {
  5276. struct ca0132_spec *spec = codec->spec;
  5277. unsigned int tmp;
  5278. u8 val;
  5279. unsigned int oldval;
  5280. codec_dbg(codec, "ca0132_set_dmic: enable=%d\n", enable);
  5281. oldval = stop_mic1(codec);
  5282. ca0132_set_vipsource(codec, 0);
  5283. if (enable) {
  5284. /* set DMic input as 2-ch */
  5285. tmp = FLOAT_TWO;
  5286. dspio_set_uint_param(codec, 0x80, 0x00, tmp);
  5287. val = spec->dmic_ctl;
  5288. val |= 0x80;
  5289. snd_hda_codec_write(codec, spec->input_pins[0], 0,
  5290. VENDOR_CHIPIO_DMIC_CTL_SET, val);
  5291. if (!(spec->dmic_ctl & 0x20))
  5292. chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 1);
  5293. } else {
  5294. /* set AMic input as mono */
  5295. tmp = FLOAT_ONE;
  5296. dspio_set_uint_param(codec, 0x80, 0x00, tmp);
  5297. val = spec->dmic_ctl;
  5298. /* clear bit7 and bit5 to disable dmic */
  5299. val &= 0x5f;
  5300. snd_hda_codec_write(codec, spec->input_pins[0], 0,
  5301. VENDOR_CHIPIO_DMIC_CTL_SET, val);
  5302. if (!(spec->dmic_ctl & 0x20))
  5303. chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 0);
  5304. }
  5305. ca0132_set_vipsource(codec, 1);
  5306. resume_mic1(codec, oldval);
  5307. }
  5308. /*
  5309. * Initialization for Digital Mic.
  5310. */
  5311. static void ca0132_init_dmic(struct hda_codec *codec)
  5312. {
  5313. struct ca0132_spec *spec = codec->spec;
  5314. u8 val;
  5315. /* Setup Digital Mic here, but don't enable.
  5316. * Enable based on jack detect.
  5317. */
  5318. /* MCLK uses MPIO1, set to enable.
  5319. * Bit 2-0: MPIO select
  5320. * Bit 3: set to disable
  5321. * Bit 7-4: reserved
  5322. */
  5323. val = 0x01;
  5324. snd_hda_codec_write(codec, spec->input_pins[0], 0,
  5325. VENDOR_CHIPIO_DMIC_MCLK_SET, val);
  5326. /* Data1 uses MPIO3. Data2 not use
  5327. * Bit 2-0: Data1 MPIO select
  5328. * Bit 3: set disable Data1
  5329. * Bit 6-4: Data2 MPIO select
  5330. * Bit 7: set disable Data2
  5331. */
  5332. val = 0x83;
  5333. snd_hda_codec_write(codec, spec->input_pins[0], 0,
  5334. VENDOR_CHIPIO_DMIC_PIN_SET, val);
  5335. /* Use Ch-0 and Ch-1. Rate is 48K, mode 1. Disable DMic first.
  5336. * Bit 3-0: Channel mask
  5337. * Bit 4: set for 48KHz, clear for 32KHz
  5338. * Bit 5: mode
  5339. * Bit 6: set to select Data2, clear for Data1
  5340. * Bit 7: set to enable DMic, clear for AMic
  5341. */
  5342. if (spec->quirk == QUIRK_ALIENWARE_M17XR4)
  5343. val = 0x33;
  5344. else
  5345. val = 0x23;
  5346. /* keep a copy of dmic ctl val for enable/disable dmic purpuse */
  5347. spec->dmic_ctl = val;
  5348. snd_hda_codec_write(codec, spec->input_pins[0], 0,
  5349. VENDOR_CHIPIO_DMIC_CTL_SET, val);
  5350. }
  5351. /*
  5352. * Initialization for Analog Mic 2
  5353. */
  5354. static void ca0132_init_analog_mic2(struct hda_codec *codec)
  5355. {
  5356. struct ca0132_spec *spec = codec->spec;
  5357. mutex_lock(&spec->chipio_mutex);
  5358. snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
  5359. VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20);
  5360. snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
  5361. VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
  5362. snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
  5363. VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
  5364. snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
  5365. VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x2D);
  5366. snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
  5367. VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
  5368. snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
  5369. VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
  5370. mutex_unlock(&spec->chipio_mutex);
  5371. }
  5372. static void ca0132_refresh_widget_caps(struct hda_codec *codec)
  5373. {
  5374. struct ca0132_spec *spec = codec->spec;
  5375. int i;
  5376. codec_dbg(codec, "ca0132_refresh_widget_caps.\n");
  5377. snd_hda_codec_update_widgets(codec);
  5378. for (i = 0; i < spec->multiout.num_dacs; i++)
  5379. refresh_amp_caps(codec, spec->dacs[i], HDA_OUTPUT);
  5380. for (i = 0; i < spec->num_outputs; i++)
  5381. refresh_amp_caps(codec, spec->out_pins[i], HDA_OUTPUT);
  5382. for (i = 0; i < spec->num_inputs; i++) {
  5383. refresh_amp_caps(codec, spec->adcs[i], HDA_INPUT);
  5384. refresh_amp_caps(codec, spec->input_pins[i], HDA_INPUT);
  5385. }
  5386. }
  5387. /*
  5388. * Recon3D r3d_setup_defaults sub functions.
  5389. */
  5390. static void r3d_dsp_scp_startup(struct hda_codec *codec)
  5391. {
  5392. unsigned int tmp;
  5393. tmp = 0x00000000;
  5394. dspio_set_uint_param_no_source(codec, 0x80, 0x0A, tmp);
  5395. tmp = 0x00000001;
  5396. dspio_set_uint_param_no_source(codec, 0x80, 0x0B, tmp);
  5397. tmp = 0x00000004;
  5398. dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
  5399. tmp = 0x00000005;
  5400. dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
  5401. tmp = 0x00000000;
  5402. dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
  5403. }
  5404. static void r3d_dsp_initial_mic_setup(struct hda_codec *codec)
  5405. {
  5406. unsigned int tmp;
  5407. /* Mic 1 Setup */
  5408. chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
  5409. chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
  5410. /* This ConnPointID is unique to Recon3Di. Haven't seen it elsewhere */
  5411. chipio_set_conn_rate(codec, 0x0F, SR_96_000);
  5412. tmp = FLOAT_ONE;
  5413. dspio_set_uint_param(codec, 0x80, 0x00, tmp);
  5414. /* Mic 2 Setup, even though it isn't connected on SBZ */
  5415. chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, SR_96_000);
  5416. chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, SR_96_000);
  5417. chipio_set_conn_rate(codec, 0x0F, SR_96_000);
  5418. tmp = FLOAT_ZERO;
  5419. dspio_set_uint_param(codec, 0x80, 0x01, tmp);
  5420. }
  5421. /*
  5422. * Initialize Sound Blaster Z analog microphones.
  5423. */
  5424. static void sbz_init_analog_mics(struct hda_codec *codec)
  5425. {
  5426. unsigned int tmp;
  5427. /* Mic 1 Setup */
  5428. chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
  5429. chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
  5430. tmp = FLOAT_THREE;
  5431. dspio_set_uint_param(codec, 0x80, 0x00, tmp);
  5432. /* Mic 2 Setup, even though it isn't connected on SBZ */
  5433. chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, SR_96_000);
  5434. chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, SR_96_000);
  5435. tmp = FLOAT_ZERO;
  5436. dspio_set_uint_param(codec, 0x80, 0x01, tmp);
  5437. }
  5438. /*
  5439. * Sets the source of stream 0x14 to connpointID 0x48, and the destination
  5440. * connpointID to 0x91. If this isn't done, the destination is 0x71, and
  5441. * you get no sound. I'm guessing this has to do with the Sound Blaster Z
  5442. * having an updated DAC, which changes the destination to that DAC.
  5443. */
  5444. static void sbz_connect_streams(struct hda_codec *codec)
  5445. {
  5446. struct ca0132_spec *spec = codec->spec;
  5447. mutex_lock(&spec->chipio_mutex);
  5448. codec_dbg(codec, "Connect Streams entered, mutex locked and loaded.\n");
  5449. chipio_set_stream_channels(codec, 0x0C, 6);
  5450. chipio_set_stream_control(codec, 0x0C, 1);
  5451. /* This value is 0x43 for 96khz, and 0x83 for 192khz. */
  5452. chipio_write_no_mutex(codec, 0x18a020, 0x00000043);
  5453. /* Setup stream 0x14 with it's source and destination points */
  5454. chipio_set_stream_source_dest(codec, 0x14, 0x48, 0x91);
  5455. chipio_set_conn_rate_no_mutex(codec, 0x48, SR_96_000);
  5456. chipio_set_conn_rate_no_mutex(codec, 0x91, SR_96_000);
  5457. chipio_set_stream_channels(codec, 0x14, 2);
  5458. chipio_set_stream_control(codec, 0x14, 1);
  5459. codec_dbg(codec, "Connect Streams exited, mutex released.\n");
  5460. mutex_unlock(&spec->chipio_mutex);
  5461. }
  5462. /*
  5463. * Write data through ChipIO to setup proper stream destinations.
  5464. * Not sure how it exactly works, but it seems to direct data
  5465. * to different destinations. Example is f8 to c0, e0 to c0.
  5466. * All I know is, if you don't set these, you get no sound.
  5467. */
  5468. static void sbz_chipio_startup_data(struct hda_codec *codec)
  5469. {
  5470. struct ca0132_spec *spec = codec->spec;
  5471. mutex_lock(&spec->chipio_mutex);
  5472. codec_dbg(codec, "Startup Data entered, mutex locked and loaded.\n");
  5473. /* These control audio output */
  5474. chipio_write_no_mutex(codec, 0x190060, 0x0001f8c0);
  5475. chipio_write_no_mutex(codec, 0x190064, 0x0001f9c1);
  5476. chipio_write_no_mutex(codec, 0x190068, 0x0001fac6);
  5477. chipio_write_no_mutex(codec, 0x19006c, 0x0001fbc7);
  5478. /* Signal to update I think */
  5479. chipio_write_no_mutex(codec, 0x19042c, 0x00000001);
  5480. chipio_set_stream_channels(codec, 0x0C, 6);
  5481. chipio_set_stream_control(codec, 0x0C, 1);
  5482. /* No clue what these control */
  5483. chipio_write_no_mutex(codec, 0x190030, 0x0001e0c0);
  5484. chipio_write_no_mutex(codec, 0x190034, 0x0001e1c1);
  5485. chipio_write_no_mutex(codec, 0x190038, 0x0001e4c2);
  5486. chipio_write_no_mutex(codec, 0x19003c, 0x0001e5c3);
  5487. chipio_write_no_mutex(codec, 0x190040, 0x0001e2c4);
  5488. chipio_write_no_mutex(codec, 0x190044, 0x0001e3c5);
  5489. chipio_write_no_mutex(codec, 0x190048, 0x0001e8c6);
  5490. chipio_write_no_mutex(codec, 0x19004c, 0x0001e9c7);
  5491. chipio_write_no_mutex(codec, 0x190050, 0x0001ecc8);
  5492. chipio_write_no_mutex(codec, 0x190054, 0x0001edc9);
  5493. chipio_write_no_mutex(codec, 0x190058, 0x0001eaca);
  5494. chipio_write_no_mutex(codec, 0x19005c, 0x0001ebcb);
  5495. chipio_write_no_mutex(codec, 0x19042c, 0x00000001);
  5496. codec_dbg(codec, "Startup Data exited, mutex released.\n");
  5497. mutex_unlock(&spec->chipio_mutex);
  5498. }
  5499. /*
  5500. * Sound Blaster Z uses these after DSP is loaded. Weird SCP commands
  5501. * without a 0x20 source like normal.
  5502. */
  5503. static void sbz_dsp_scp_startup(struct hda_codec *codec)
  5504. {
  5505. unsigned int tmp;
  5506. tmp = 0x00000003;
  5507. dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
  5508. tmp = 0x00000000;
  5509. dspio_set_uint_param_no_source(codec, 0x80, 0x0A, tmp);
  5510. tmp = 0x00000001;
  5511. dspio_set_uint_param_no_source(codec, 0x80, 0x0B, tmp);
  5512. tmp = 0x00000004;
  5513. dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
  5514. tmp = 0x00000005;
  5515. dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
  5516. tmp = 0x00000000;
  5517. dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
  5518. }
  5519. static void sbz_dsp_initial_mic_setup(struct hda_codec *codec)
  5520. {
  5521. unsigned int tmp;
  5522. chipio_set_stream_control(codec, 0x03, 0);
  5523. chipio_set_stream_control(codec, 0x04, 0);
  5524. chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
  5525. chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
  5526. tmp = FLOAT_THREE;
  5527. dspio_set_uint_param(codec, 0x80, 0x00, tmp);
  5528. chipio_set_stream_control(codec, 0x03, 1);
  5529. chipio_set_stream_control(codec, 0x04, 1);
  5530. chipio_write(codec, 0x18b098, 0x0000000c);
  5531. chipio_write(codec, 0x18b09C, 0x0000000c);
  5532. }
  5533. /*
  5534. * Setup default parameters for DSP
  5535. */
  5536. static void ca0132_setup_defaults(struct hda_codec *codec)
  5537. {
  5538. struct ca0132_spec *spec = codec->spec;
  5539. unsigned int tmp;
  5540. int num_fx;
  5541. int idx, i;
  5542. if (spec->dsp_state != DSP_DOWNLOADED)
  5543. return;
  5544. /* out, in effects + voicefx */
  5545. num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
  5546. for (idx = 0; idx < num_fx; idx++) {
  5547. for (i = 0; i <= ca0132_effects[idx].params; i++) {
  5548. dspio_set_uint_param(codec, ca0132_effects[idx].mid,
  5549. ca0132_effects[idx].reqs[i],
  5550. ca0132_effects[idx].def_vals[i]);
  5551. }
  5552. }
  5553. /*remove DSP headroom*/
  5554. tmp = FLOAT_ZERO;
  5555. dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
  5556. /*set speaker EQ bypass attenuation*/
  5557. dspio_set_uint_param(codec, 0x8f, 0x01, tmp);
  5558. /* set AMic1 and AMic2 as mono mic */
  5559. tmp = FLOAT_ONE;
  5560. dspio_set_uint_param(codec, 0x80, 0x00, tmp);
  5561. dspio_set_uint_param(codec, 0x80, 0x01, tmp);
  5562. /* set AMic1 as CrystalVoice input */
  5563. tmp = FLOAT_ONE;
  5564. dspio_set_uint_param(codec, 0x80, 0x05, tmp);
  5565. /* set WUH source */
  5566. tmp = FLOAT_TWO;
  5567. dspio_set_uint_param(codec, 0x31, 0x00, tmp);
  5568. }
  5569. /*
  5570. * Setup default parameters for Recon3D/Recon3Di DSP.
  5571. */
  5572. static void r3d_setup_defaults(struct hda_codec *codec)
  5573. {
  5574. struct ca0132_spec *spec = codec->spec;
  5575. unsigned int tmp;
  5576. int num_fx;
  5577. int idx, i;
  5578. if (spec->dsp_state != DSP_DOWNLOADED)
  5579. return;
  5580. r3d_dsp_scp_startup(codec);
  5581. r3d_dsp_initial_mic_setup(codec);
  5582. /*remove DSP headroom*/
  5583. tmp = FLOAT_ZERO;
  5584. dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
  5585. /* set WUH source */
  5586. tmp = FLOAT_TWO;
  5587. dspio_set_uint_param(codec, 0x31, 0x00, tmp);
  5588. chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
  5589. /* Set speaker source? */
  5590. dspio_set_uint_param(codec, 0x32, 0x00, tmp);
  5591. if (spec->quirk == QUIRK_R3DI)
  5592. r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADED);
  5593. /* Setup effect defaults */
  5594. num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
  5595. for (idx = 0; idx < num_fx; idx++) {
  5596. for (i = 0; i <= ca0132_effects[idx].params; i++) {
  5597. dspio_set_uint_param(codec,
  5598. ca0132_effects[idx].mid,
  5599. ca0132_effects[idx].reqs[i],
  5600. ca0132_effects[idx].def_vals[i]);
  5601. }
  5602. }
  5603. }
  5604. /*
  5605. * Setup default parameters for the Sound Blaster Z DSP. A lot more going on
  5606. * than the Chromebook setup.
  5607. */
  5608. static void sbz_setup_defaults(struct hda_codec *codec)
  5609. {
  5610. struct ca0132_spec *spec = codec->spec;
  5611. unsigned int tmp, stream_format;
  5612. int num_fx;
  5613. int idx, i;
  5614. if (spec->dsp_state != DSP_DOWNLOADED)
  5615. return;
  5616. sbz_dsp_scp_startup(codec);
  5617. sbz_init_analog_mics(codec);
  5618. sbz_connect_streams(codec);
  5619. sbz_chipio_startup_data(codec);
  5620. chipio_set_stream_control(codec, 0x03, 1);
  5621. chipio_set_stream_control(codec, 0x04, 1);
  5622. /*
  5623. * Sets internal input loopback to off, used to have a switch to
  5624. * enable input loopback, but turned out to be way too buggy.
  5625. */
  5626. tmp = FLOAT_ONE;
  5627. dspio_set_uint_param(codec, 0x37, 0x08, tmp);
  5628. dspio_set_uint_param(codec, 0x37, 0x10, tmp);
  5629. /*remove DSP headroom*/
  5630. tmp = FLOAT_ZERO;
  5631. dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
  5632. /* set WUH source */
  5633. tmp = FLOAT_TWO;
  5634. dspio_set_uint_param(codec, 0x31, 0x00, tmp);
  5635. chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
  5636. /* Set speaker source? */
  5637. dspio_set_uint_param(codec, 0x32, 0x00, tmp);
  5638. sbz_dsp_initial_mic_setup(codec);
  5639. /* out, in effects + voicefx */
  5640. num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
  5641. for (idx = 0; idx < num_fx; idx++) {
  5642. for (i = 0; i <= ca0132_effects[idx].params; i++) {
  5643. dspio_set_uint_param(codec,
  5644. ca0132_effects[idx].mid,
  5645. ca0132_effects[idx].reqs[i],
  5646. ca0132_effects[idx].def_vals[i]);
  5647. }
  5648. }
  5649. /*
  5650. * Have to make a stream to bind the sound output to, otherwise
  5651. * you'll get dead audio. Before I did this, it would bind to an
  5652. * audio input, and would never work
  5653. */
  5654. stream_format = snd_hdac_calc_stream_format(48000, 2,
  5655. SNDRV_PCM_FORMAT_S32_LE, 32, 0);
  5656. snd_hda_codec_setup_stream(codec, spec->dacs[0], spec->dsp_stream_id,
  5657. 0, stream_format);
  5658. snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
  5659. snd_hda_codec_setup_stream(codec, spec->dacs[0], spec->dsp_stream_id,
  5660. 0, stream_format);
  5661. snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
  5662. }
  5663. /*
  5664. * Initialization of flags in chip
  5665. */
  5666. static void ca0132_init_flags(struct hda_codec *codec)
  5667. {
  5668. struct ca0132_spec *spec = codec->spec;
  5669. if (spec->use_alt_functions) {
  5670. chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, 1);
  5671. chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, 1);
  5672. chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, 1);
  5673. chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, 1);
  5674. chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, 1);
  5675. chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
  5676. chipio_set_control_flag(codec, CONTROL_FLAG_SPDIF2OUT, 0);
  5677. chipio_set_control_flag(codec,
  5678. CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
  5679. chipio_set_control_flag(codec,
  5680. CONTROL_FLAG_PORT_A_10KOHM_LOAD, 1);
  5681. } else {
  5682. chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
  5683. chipio_set_control_flag(codec,
  5684. CONTROL_FLAG_PORT_A_COMMON_MODE, 0);
  5685. chipio_set_control_flag(codec,
  5686. CONTROL_FLAG_PORT_D_COMMON_MODE, 0);
  5687. chipio_set_control_flag(codec,
  5688. CONTROL_FLAG_PORT_A_10KOHM_LOAD, 0);
  5689. chipio_set_control_flag(codec,
  5690. CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
  5691. chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_HIGH_PASS, 1);
  5692. }
  5693. }
  5694. /*
  5695. * Initialization of parameters in chip
  5696. */
  5697. static void ca0132_init_params(struct hda_codec *codec)
  5698. {
  5699. struct ca0132_spec *spec = codec->spec;
  5700. if (spec->use_alt_functions) {
  5701. chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
  5702. chipio_set_conn_rate(codec, 0x0B, SR_48_000);
  5703. chipio_set_control_param(codec, CONTROL_PARAM_SPDIF1_SOURCE, 0);
  5704. chipio_set_control_param(codec, 0, 0);
  5705. chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
  5706. }
  5707. chipio_set_control_param(codec, CONTROL_PARAM_PORTA_160OHM_GAIN, 6);
  5708. chipio_set_control_param(codec, CONTROL_PARAM_PORTD_160OHM_GAIN, 6);
  5709. }
  5710. static void ca0132_set_dsp_msr(struct hda_codec *codec, bool is96k)
  5711. {
  5712. chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, is96k);
  5713. chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, is96k);
  5714. chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, is96k);
  5715. chipio_set_control_flag(codec, CONTROL_FLAG_SRC_CLOCK_196MHZ, is96k);
  5716. chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, is96k);
  5717. chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, is96k);
  5718. chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
  5719. chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
  5720. chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
  5721. }
  5722. static bool ca0132_download_dsp_images(struct hda_codec *codec)
  5723. {
  5724. bool dsp_loaded = false;
  5725. struct ca0132_spec *spec = codec->spec;
  5726. const struct dsp_image_seg *dsp_os_image;
  5727. const struct firmware *fw_entry;
  5728. /*
  5729. * Alternate firmwares for different variants. The Recon3Di apparently
  5730. * can use the default firmware, but I'll leave the option in case
  5731. * it needs it again.
  5732. */
  5733. switch (spec->quirk) {
  5734. case QUIRK_SBZ:
  5735. if (request_firmware(&fw_entry, SBZ_EFX_FILE,
  5736. codec->card->dev) != 0) {
  5737. codec_dbg(codec, "SBZ alt firmware not detected. ");
  5738. spec->alt_firmware_present = false;
  5739. } else {
  5740. codec_dbg(codec, "Sound Blaster Z firmware selected.");
  5741. spec->alt_firmware_present = true;
  5742. }
  5743. break;
  5744. case QUIRK_R3DI:
  5745. if (request_firmware(&fw_entry, R3DI_EFX_FILE,
  5746. codec->card->dev) != 0) {
  5747. codec_dbg(codec, "Recon3Di alt firmware not detected.");
  5748. spec->alt_firmware_present = false;
  5749. } else {
  5750. codec_dbg(codec, "Recon3Di firmware selected.");
  5751. spec->alt_firmware_present = true;
  5752. }
  5753. break;
  5754. default:
  5755. spec->alt_firmware_present = false;
  5756. break;
  5757. }
  5758. /*
  5759. * Use default ctefx.bin if no alt firmware is detected, or if none
  5760. * exists for your particular codec.
  5761. */
  5762. if (!spec->alt_firmware_present) {
  5763. codec_dbg(codec, "Default firmware selected.");
  5764. if (request_firmware(&fw_entry, EFX_FILE,
  5765. codec->card->dev) != 0)
  5766. return false;
  5767. }
  5768. dsp_os_image = (struct dsp_image_seg *)(fw_entry->data);
  5769. if (dspload_image(codec, dsp_os_image, 0, 0, true, 0)) {
  5770. codec_err(codec, "ca0132 DSP load image failed\n");
  5771. goto exit_download;
  5772. }
  5773. dsp_loaded = dspload_wait_loaded(codec);
  5774. exit_download:
  5775. release_firmware(fw_entry);
  5776. return dsp_loaded;
  5777. }
  5778. static void ca0132_download_dsp(struct hda_codec *codec)
  5779. {
  5780. struct ca0132_spec *spec = codec->spec;
  5781. #ifndef CONFIG_SND_HDA_CODEC_CA0132_DSP
  5782. return; /* NOP */
  5783. #endif
  5784. if (spec->dsp_state == DSP_DOWNLOAD_FAILED)
  5785. return; /* don't retry failures */
  5786. chipio_enable_clocks(codec);
  5787. if (spec->dsp_state != DSP_DOWNLOADED) {
  5788. spec->dsp_state = DSP_DOWNLOADING;
  5789. if (!ca0132_download_dsp_images(codec))
  5790. spec->dsp_state = DSP_DOWNLOAD_FAILED;
  5791. else
  5792. spec->dsp_state = DSP_DOWNLOADED;
  5793. }
  5794. /* For codecs using alt functions, this is already done earlier */
  5795. if (spec->dsp_state == DSP_DOWNLOADED && (!spec->use_alt_functions))
  5796. ca0132_set_dsp_msr(codec, true);
  5797. }
  5798. static void ca0132_process_dsp_response(struct hda_codec *codec,
  5799. struct hda_jack_callback *callback)
  5800. {
  5801. struct ca0132_spec *spec = codec->spec;
  5802. codec_dbg(codec, "ca0132_process_dsp_response\n");
  5803. if (spec->wait_scp) {
  5804. if (dspio_get_response_data(codec) >= 0)
  5805. spec->wait_scp = 0;
  5806. }
  5807. dspio_clear_response_queue(codec);
  5808. }
  5809. static void hp_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
  5810. {
  5811. struct ca0132_spec *spec = codec->spec;
  5812. struct hda_jack_tbl *tbl;
  5813. /* Delay enabling the HP amp, to let the mic-detection
  5814. * state machine run.
  5815. */
  5816. cancel_delayed_work_sync(&spec->unsol_hp_work);
  5817. schedule_delayed_work(&spec->unsol_hp_work, msecs_to_jiffies(500));
  5818. tbl = snd_hda_jack_tbl_get(codec, cb->nid);
  5819. if (tbl)
  5820. tbl->block_report = 1;
  5821. }
  5822. static void amic_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
  5823. {
  5824. struct ca0132_spec *spec = codec->spec;
  5825. if (spec->use_alt_functions)
  5826. ca0132_alt_select_in(codec);
  5827. else
  5828. ca0132_select_mic(codec);
  5829. }
  5830. static void ca0132_init_unsol(struct hda_codec *codec)
  5831. {
  5832. struct ca0132_spec *spec = codec->spec;
  5833. snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_hp, hp_callback);
  5834. snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_amic1,
  5835. amic_callback);
  5836. snd_hda_jack_detect_enable_callback(codec, UNSOL_TAG_DSP,
  5837. ca0132_process_dsp_response);
  5838. /* Front headphone jack detection */
  5839. if (spec->use_alt_functions)
  5840. snd_hda_jack_detect_enable_callback(codec,
  5841. spec->unsol_tag_front_hp, hp_callback);
  5842. }
  5843. /*
  5844. * Verbs tables.
  5845. */
  5846. /* Sends before DSP download. */
  5847. static struct hda_verb ca0132_base_init_verbs[] = {
  5848. /*enable ct extension*/
  5849. {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x1},
  5850. {}
  5851. };
  5852. /* Send at exit. */
  5853. static struct hda_verb ca0132_base_exit_verbs[] = {
  5854. /*set afg to D3*/
  5855. {0x01, AC_VERB_SET_POWER_STATE, 0x03},
  5856. /*disable ct extension*/
  5857. {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0},
  5858. {}
  5859. };
  5860. /* Other verbs tables. Sends after DSP download. */
  5861. static struct hda_verb ca0132_init_verbs0[] = {
  5862. /* chip init verbs */
  5863. {0x15, 0x70D, 0xF0},
  5864. {0x15, 0x70E, 0xFE},
  5865. {0x15, 0x707, 0x75},
  5866. {0x15, 0x707, 0xD3},
  5867. {0x15, 0x707, 0x09},
  5868. {0x15, 0x707, 0x53},
  5869. {0x15, 0x707, 0xD4},
  5870. {0x15, 0x707, 0xEF},
  5871. {0x15, 0x707, 0x75},
  5872. {0x15, 0x707, 0xD3},
  5873. {0x15, 0x707, 0x09},
  5874. {0x15, 0x707, 0x02},
  5875. {0x15, 0x707, 0x37},
  5876. {0x15, 0x707, 0x78},
  5877. {0x15, 0x53C, 0xCE},
  5878. {0x15, 0x575, 0xC9},
  5879. {0x15, 0x53D, 0xCE},
  5880. {0x15, 0x5B7, 0xC9},
  5881. {0x15, 0x70D, 0xE8},
  5882. {0x15, 0x70E, 0xFE},
  5883. {0x15, 0x707, 0x02},
  5884. {0x15, 0x707, 0x68},
  5885. {0x15, 0x707, 0x62},
  5886. {0x15, 0x53A, 0xCE},
  5887. {0x15, 0x546, 0xC9},
  5888. {0x15, 0x53B, 0xCE},
  5889. {0x15, 0x5E8, 0xC9},
  5890. {}
  5891. };
  5892. /* Extra init verbs for desktop cards. */
  5893. static struct hda_verb ca0132_init_verbs1[] = {
  5894. {0x15, 0x70D, 0x20},
  5895. {0x15, 0x70E, 0x19},
  5896. {0x15, 0x707, 0x00},
  5897. {0x15, 0x539, 0xCE},
  5898. {0x15, 0x546, 0xC9},
  5899. {0x15, 0x70D, 0xB7},
  5900. {0x15, 0x70E, 0x09},
  5901. {0x15, 0x707, 0x10},
  5902. {0x15, 0x70D, 0xAF},
  5903. {0x15, 0x70E, 0x09},
  5904. {0x15, 0x707, 0x01},
  5905. {0x15, 0x707, 0x05},
  5906. {0x15, 0x70D, 0x73},
  5907. {0x15, 0x70E, 0x09},
  5908. {0x15, 0x707, 0x14},
  5909. {0x15, 0x6FF, 0xC4},
  5910. {}
  5911. };
  5912. static void ca0132_init_chip(struct hda_codec *codec)
  5913. {
  5914. struct ca0132_spec *spec = codec->spec;
  5915. int num_fx;
  5916. int i;
  5917. unsigned int on;
  5918. mutex_init(&spec->chipio_mutex);
  5919. spec->cur_out_type = SPEAKER_OUT;
  5920. if (!spec->use_alt_functions)
  5921. spec->cur_mic_type = DIGITAL_MIC;
  5922. else
  5923. spec->cur_mic_type = REAR_MIC;
  5924. spec->cur_mic_boost = 0;
  5925. for (i = 0; i < VNODES_COUNT; i++) {
  5926. spec->vnode_lvol[i] = 0x5a;
  5927. spec->vnode_rvol[i] = 0x5a;
  5928. spec->vnode_lswitch[i] = 0;
  5929. spec->vnode_rswitch[i] = 0;
  5930. }
  5931. /*
  5932. * Default states for effects are in ca0132_effects[].
  5933. */
  5934. num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
  5935. for (i = 0; i < num_fx; i++) {
  5936. on = (unsigned int)ca0132_effects[i].reqs[0];
  5937. spec->effects_switch[i] = on ? 1 : 0;
  5938. }
  5939. /*
  5940. * Sets defaults for the effect slider controls, only for alternative
  5941. * ca0132 codecs. Also sets x-bass crossover frequency to 80hz.
  5942. */
  5943. if (spec->use_alt_controls) {
  5944. spec->xbass_xover_freq = 8;
  5945. for (i = 0; i < EFFECT_LEVEL_SLIDERS; i++)
  5946. spec->fx_ctl_val[i] = effect_slider_defaults[i];
  5947. }
  5948. spec->voicefx_val = 0;
  5949. spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID] = 1;
  5950. spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] = 0;
  5951. #ifdef ENABLE_TUNING_CONTROLS
  5952. ca0132_init_tuning_defaults(codec);
  5953. #endif
  5954. }
  5955. /*
  5956. * Recon3Di exit specific commands.
  5957. */
  5958. /* prevents popping noise on shutdown */
  5959. static void r3di_gpio_shutdown(struct hda_codec *codec)
  5960. {
  5961. snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_DATA, 0x00);
  5962. }
  5963. /*
  5964. * Sound Blaster Z exit specific commands.
  5965. */
  5966. static void sbz_region2_exit(struct hda_codec *codec)
  5967. {
  5968. struct ca0132_spec *spec = codec->spec;
  5969. unsigned int i;
  5970. for (i = 0; i < 4; i++)
  5971. writeb(0x0, spec->mem_base + 0x100);
  5972. for (i = 0; i < 8; i++)
  5973. writeb(0xb3, spec->mem_base + 0x304);
  5974. ca0132_mmio_gpio_set(codec, 0, false);
  5975. ca0132_mmio_gpio_set(codec, 1, false);
  5976. ca0132_mmio_gpio_set(codec, 4, true);
  5977. ca0132_mmio_gpio_set(codec, 5, false);
  5978. ca0132_mmio_gpio_set(codec, 7, false);
  5979. }
  5980. static void sbz_set_pin_ctl_default(struct hda_codec *codec)
  5981. {
  5982. hda_nid_t pins[5] = {0x0B, 0x0C, 0x0E, 0x12, 0x13};
  5983. unsigned int i;
  5984. snd_hda_codec_write(codec, 0x11, 0,
  5985. AC_VERB_SET_PIN_WIDGET_CONTROL, 0x40);
  5986. for (i = 0; i < 5; i++)
  5987. snd_hda_codec_write(codec, pins[i], 0,
  5988. AC_VERB_SET_PIN_WIDGET_CONTROL, 0x00);
  5989. }
  5990. static void ca0132_clear_unsolicited(struct hda_codec *codec)
  5991. {
  5992. hda_nid_t pins[7] = {0x0B, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13};
  5993. unsigned int i;
  5994. for (i = 0; i < 7; i++) {
  5995. snd_hda_codec_write(codec, pins[i], 0,
  5996. AC_VERB_SET_UNSOLICITED_ENABLE, 0x00);
  5997. }
  5998. }
  5999. /* On shutdown, sends commands in sets of three */
  6000. static void sbz_gpio_shutdown_commands(struct hda_codec *codec, int dir,
  6001. int mask, int data)
  6002. {
  6003. if (dir >= 0)
  6004. snd_hda_codec_write(codec, 0x01, 0,
  6005. AC_VERB_SET_GPIO_DIRECTION, dir);
  6006. if (mask >= 0)
  6007. snd_hda_codec_write(codec, 0x01, 0,
  6008. AC_VERB_SET_GPIO_MASK, mask);
  6009. if (data >= 0)
  6010. snd_hda_codec_write(codec, 0x01, 0,
  6011. AC_VERB_SET_GPIO_DATA, data);
  6012. }
  6013. static void sbz_exit_chip(struct hda_codec *codec)
  6014. {
  6015. chipio_set_stream_control(codec, 0x03, 0);
  6016. chipio_set_stream_control(codec, 0x04, 0);
  6017. /* Mess with GPIO */
  6018. sbz_gpio_shutdown_commands(codec, 0x07, 0x07, -1);
  6019. sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x05);
  6020. sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x01);
  6021. chipio_set_stream_control(codec, 0x14, 0);
  6022. chipio_set_stream_control(codec, 0x0C, 0);
  6023. chipio_set_conn_rate(codec, 0x41, SR_192_000);
  6024. chipio_set_conn_rate(codec, 0x91, SR_192_000);
  6025. chipio_write(codec, 0x18a020, 0x00000083);
  6026. sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x03);
  6027. sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x07);
  6028. sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x06);
  6029. chipio_set_stream_control(codec, 0x0C, 0);
  6030. chipio_set_control_param(codec, 0x0D, 0x24);
  6031. ca0132_clear_unsolicited(codec);
  6032. sbz_set_pin_ctl_default(codec);
  6033. snd_hda_codec_write(codec, 0x0B, 0,
  6034. AC_VERB_SET_EAPD_BTLENABLE, 0x00);
  6035. sbz_region2_exit(codec);
  6036. }
  6037. static void r3d_exit_chip(struct hda_codec *codec)
  6038. {
  6039. ca0132_clear_unsolicited(codec);
  6040. snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
  6041. snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5b);
  6042. }
  6043. static void ca0132_exit_chip(struct hda_codec *codec)
  6044. {
  6045. /* put any chip cleanup stuffs here. */
  6046. if (dspload_is_loaded(codec))
  6047. dsp_reset(codec);
  6048. }
  6049. /*
  6050. * This fixes a problem that was hard to reproduce. Very rarely, I would
  6051. * boot up, and there would be no sound, but the DSP indicated it had loaded
  6052. * properly. I did a few memory dumps to see if anything was different, and
  6053. * there were a few areas of memory uninitialized with a1a2a3a4. This function
  6054. * checks if those areas are uninitialized, and if they are, it'll attempt to
  6055. * reload the card 3 times. Usually it fixes by the second.
  6056. */
  6057. static void sbz_dsp_startup_check(struct hda_codec *codec)
  6058. {
  6059. struct ca0132_spec *spec = codec->spec;
  6060. unsigned int dsp_data_check[4];
  6061. unsigned int cur_address = 0x390;
  6062. unsigned int i;
  6063. unsigned int failure = 0;
  6064. unsigned int reload = 3;
  6065. if (spec->startup_check_entered)
  6066. return;
  6067. spec->startup_check_entered = true;
  6068. for (i = 0; i < 4; i++) {
  6069. chipio_read(codec, cur_address, &dsp_data_check[i]);
  6070. cur_address += 0x4;
  6071. }
  6072. for (i = 0; i < 4; i++) {
  6073. if (dsp_data_check[i] == 0xa1a2a3a4)
  6074. failure = 1;
  6075. }
  6076. codec_dbg(codec, "Startup Check: %d ", failure);
  6077. if (failure)
  6078. codec_info(codec, "DSP not initialized properly. Attempting to fix.");
  6079. /*
  6080. * While the failure condition is true, and we haven't reached our
  6081. * three reload limit, continue trying to reload the driver and
  6082. * fix the issue.
  6083. */
  6084. while (failure && (reload != 0)) {
  6085. codec_info(codec, "Reloading... Tries left: %d", reload);
  6086. sbz_exit_chip(codec);
  6087. spec->dsp_state = DSP_DOWNLOAD_INIT;
  6088. codec->patch_ops.init(codec);
  6089. failure = 0;
  6090. for (i = 0; i < 4; i++) {
  6091. chipio_read(codec, cur_address, &dsp_data_check[i]);
  6092. cur_address += 0x4;
  6093. }
  6094. for (i = 0; i < 4; i++) {
  6095. if (dsp_data_check[i] == 0xa1a2a3a4)
  6096. failure = 1;
  6097. }
  6098. reload--;
  6099. }
  6100. if (!failure && reload < 3)
  6101. codec_info(codec, "DSP fixed.");
  6102. if (!failure)
  6103. return;
  6104. codec_info(codec, "DSP failed to initialize properly. Either try a full shutdown or a suspend to clear the internal memory.");
  6105. }
  6106. /*
  6107. * This is for the extra volume verbs 0x797 (left) and 0x798 (right). These add
  6108. * extra precision for decibel values. If you had the dB value in floating point
  6109. * you would take the value after the decimal point, multiply by 64, and divide
  6110. * by 2. So for 8.59, it's (59 * 64) / 100. Useful if someone wanted to
  6111. * implement fixed point or floating point dB volumes. For now, I'll set them
  6112. * to 0 just incase a value has lingered from a boot into Windows.
  6113. */
  6114. static void ca0132_alt_vol_setup(struct hda_codec *codec)
  6115. {
  6116. snd_hda_codec_write(codec, 0x02, 0, 0x797, 0x00);
  6117. snd_hda_codec_write(codec, 0x02, 0, 0x798, 0x00);
  6118. snd_hda_codec_write(codec, 0x03, 0, 0x797, 0x00);
  6119. snd_hda_codec_write(codec, 0x03, 0, 0x798, 0x00);
  6120. snd_hda_codec_write(codec, 0x04, 0, 0x797, 0x00);
  6121. snd_hda_codec_write(codec, 0x04, 0, 0x798, 0x00);
  6122. snd_hda_codec_write(codec, 0x07, 0, 0x797, 0x00);
  6123. snd_hda_codec_write(codec, 0x07, 0, 0x798, 0x00);
  6124. }
  6125. /*
  6126. * Extra commands that don't really fit anywhere else.
  6127. */
  6128. static void sbz_pre_dsp_setup(struct hda_codec *codec)
  6129. {
  6130. struct ca0132_spec *spec = codec->spec;
  6131. writel(0x00820680, spec->mem_base + 0x01C);
  6132. writel(0x00820680, spec->mem_base + 0x01C);
  6133. snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xfc);
  6134. snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xfd);
  6135. snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xfe);
  6136. snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xff);
  6137. chipio_write(codec, 0x18b0a4, 0x000000c2);
  6138. snd_hda_codec_write(codec, 0x11, 0,
  6139. AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44);
  6140. }
  6141. static void r3d_pre_dsp_setup(struct hda_codec *codec)
  6142. {
  6143. snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xfc);
  6144. snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xfd);
  6145. snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xfe);
  6146. snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xff);
  6147. chipio_write(codec, 0x18b0a4, 0x000000c2);
  6148. snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
  6149. VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x1E);
  6150. snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
  6151. VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x1C);
  6152. snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
  6153. VENDOR_CHIPIO_8051_DATA_WRITE, 0x5B);
  6154. snd_hda_codec_write(codec, 0x11, 0,
  6155. AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44);
  6156. }
  6157. static void r3di_pre_dsp_setup(struct hda_codec *codec)
  6158. {
  6159. chipio_write(codec, 0x18b0a4, 0x000000c2);
  6160. snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
  6161. VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x1E);
  6162. snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
  6163. VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x1C);
  6164. snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
  6165. VENDOR_CHIPIO_8051_DATA_WRITE, 0x5B);
  6166. snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
  6167. VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20);
  6168. snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
  6169. VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
  6170. snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
  6171. VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
  6172. snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
  6173. VENDOR_CHIPIO_8051_DATA_WRITE, 0x40);
  6174. snd_hda_codec_write(codec, 0x11, 0,
  6175. AC_VERB_SET_PIN_WIDGET_CONTROL, 0x04);
  6176. }
  6177. /*
  6178. * These are sent before the DSP is downloaded. Not sure
  6179. * what they do, or if they're necessary. Could possibly
  6180. * be removed. Figure they're better to leave in.
  6181. */
  6182. static void ca0132_mmio_init(struct hda_codec *codec)
  6183. {
  6184. struct ca0132_spec *spec = codec->spec;
  6185. writel(0x00000000, spec->mem_base + 0x400);
  6186. writel(0x00000000, spec->mem_base + 0x408);
  6187. writel(0x00000000, spec->mem_base + 0x40C);
  6188. writel(0x00880680, spec->mem_base + 0x01C);
  6189. writel(0x00000083, spec->mem_base + 0xC0C);
  6190. writel(0x00000030, spec->mem_base + 0xC00);
  6191. writel(0x00000000, spec->mem_base + 0xC04);
  6192. writel(0x00000003, spec->mem_base + 0xC0C);
  6193. writel(0x00000003, spec->mem_base + 0xC0C);
  6194. writel(0x00000003, spec->mem_base + 0xC0C);
  6195. writel(0x00000003, spec->mem_base + 0xC0C);
  6196. writel(0x000000C1, spec->mem_base + 0xC08);
  6197. writel(0x000000F1, spec->mem_base + 0xC08);
  6198. writel(0x00000001, spec->mem_base + 0xC08);
  6199. writel(0x000000C7, spec->mem_base + 0xC08);
  6200. writel(0x000000C1, spec->mem_base + 0xC08);
  6201. writel(0x00000080, spec->mem_base + 0xC04);
  6202. }
  6203. /*
  6204. * Extra init functions for alternative ca0132 codecs. Done
  6205. * here so they don't clutter up the main ca0132_init function
  6206. * anymore than they have to.
  6207. */
  6208. static void ca0132_alt_init(struct hda_codec *codec)
  6209. {
  6210. struct ca0132_spec *spec = codec->spec;
  6211. ca0132_alt_vol_setup(codec);
  6212. switch (spec->quirk) {
  6213. case QUIRK_SBZ:
  6214. codec_dbg(codec, "SBZ alt_init");
  6215. ca0132_gpio_init(codec);
  6216. sbz_pre_dsp_setup(codec);
  6217. snd_hda_sequence_write(codec, spec->chip_init_verbs);
  6218. snd_hda_sequence_write(codec, spec->desktop_init_verbs);
  6219. break;
  6220. case QUIRK_R3DI:
  6221. codec_dbg(codec, "R3DI alt_init");
  6222. ca0132_gpio_init(codec);
  6223. ca0132_gpio_setup(codec);
  6224. r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADING);
  6225. r3di_pre_dsp_setup(codec);
  6226. snd_hda_sequence_write(codec, spec->chip_init_verbs);
  6227. snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x6FF, 0xC4);
  6228. break;
  6229. case QUIRK_R3D:
  6230. r3d_pre_dsp_setup(codec);
  6231. snd_hda_sequence_write(codec, spec->chip_init_verbs);
  6232. snd_hda_sequence_write(codec, spec->desktop_init_verbs);
  6233. break;
  6234. }
  6235. }
  6236. static int ca0132_init(struct hda_codec *codec)
  6237. {
  6238. struct ca0132_spec *spec = codec->spec;
  6239. struct auto_pin_cfg *cfg = &spec->autocfg;
  6240. int i;
  6241. bool dsp_loaded;
  6242. /*
  6243. * If the DSP is already downloaded, and init has been entered again,
  6244. * there's only two reasons for it. One, the codec has awaken from a
  6245. * suspended state, and in that case dspload_is_loaded will return
  6246. * false, and the init will be ran again. The other reason it gets
  6247. * re entered is on startup for some reason it triggers a suspend and
  6248. * resume state. In this case, it will check if the DSP is downloaded,
  6249. * and not run the init function again. For codecs using alt_functions,
  6250. * it will check if the DSP is loaded properly.
  6251. */
  6252. if (spec->dsp_state == DSP_DOWNLOADED) {
  6253. dsp_loaded = dspload_is_loaded(codec);
  6254. if (!dsp_loaded) {
  6255. spec->dsp_reload = true;
  6256. spec->dsp_state = DSP_DOWNLOAD_INIT;
  6257. } else {
  6258. if (spec->quirk == QUIRK_SBZ)
  6259. sbz_dsp_startup_check(codec);
  6260. return 0;
  6261. }
  6262. }
  6263. if (spec->dsp_state != DSP_DOWNLOAD_FAILED)
  6264. spec->dsp_state = DSP_DOWNLOAD_INIT;
  6265. spec->curr_chip_addx = INVALID_CHIP_ADDRESS;
  6266. if (spec->use_pci_mmio)
  6267. ca0132_mmio_init(codec);
  6268. snd_hda_power_up_pm(codec);
  6269. ca0132_init_unsol(codec);
  6270. ca0132_init_params(codec);
  6271. ca0132_init_flags(codec);
  6272. snd_hda_sequence_write(codec, spec->base_init_verbs);
  6273. if (spec->use_alt_functions)
  6274. ca0132_alt_init(codec);
  6275. ca0132_download_dsp(codec);
  6276. ca0132_refresh_widget_caps(codec);
  6277. switch (spec->quirk) {
  6278. case QUIRK_R3DI:
  6279. case QUIRK_R3D:
  6280. r3d_setup_defaults(codec);
  6281. break;
  6282. case QUIRK_SBZ:
  6283. sbz_setup_defaults(codec);
  6284. break;
  6285. default:
  6286. ca0132_setup_defaults(codec);
  6287. ca0132_init_analog_mic2(codec);
  6288. ca0132_init_dmic(codec);
  6289. break;
  6290. }
  6291. for (i = 0; i < spec->num_outputs; i++)
  6292. init_output(codec, spec->out_pins[i], spec->dacs[0]);
  6293. init_output(codec, cfg->dig_out_pins[0], spec->dig_out);
  6294. for (i = 0; i < spec->num_inputs; i++)
  6295. init_input(codec, spec->input_pins[i], spec->adcs[i]);
  6296. init_input(codec, cfg->dig_in_pin, spec->dig_in);
  6297. if (!spec->use_alt_functions) {
  6298. snd_hda_sequence_write(codec, spec->chip_init_verbs);
  6299. snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
  6300. VENDOR_CHIPIO_PARAM_EX_ID_SET, 0x0D);
  6301. snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
  6302. VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 0x20);
  6303. }
  6304. if (spec->quirk == QUIRK_SBZ)
  6305. ca0132_gpio_setup(codec);
  6306. snd_hda_sequence_write(codec, spec->spec_init_verbs);
  6307. if (spec->use_alt_functions) {
  6308. ca0132_alt_select_out(codec);
  6309. ca0132_alt_select_in(codec);
  6310. } else {
  6311. ca0132_select_out(codec);
  6312. ca0132_select_mic(codec);
  6313. }
  6314. snd_hda_jack_report_sync(codec);
  6315. /*
  6316. * Re set the PlayEnhancement switch on a resume event, because the
  6317. * controls will not be reloaded.
  6318. */
  6319. if (spec->dsp_reload) {
  6320. spec->dsp_reload = false;
  6321. ca0132_pe_switch_set(codec);
  6322. }
  6323. snd_hda_power_down_pm(codec);
  6324. return 0;
  6325. }
  6326. static void ca0132_free(struct hda_codec *codec)
  6327. {
  6328. struct ca0132_spec *spec = codec->spec;
  6329. cancel_delayed_work_sync(&spec->unsol_hp_work);
  6330. snd_hda_power_up(codec);
  6331. switch (spec->quirk) {
  6332. case QUIRK_SBZ:
  6333. sbz_exit_chip(codec);
  6334. break;
  6335. case QUIRK_R3D:
  6336. r3d_exit_chip(codec);
  6337. break;
  6338. case QUIRK_R3DI:
  6339. r3di_gpio_shutdown(codec);
  6340. break;
  6341. }
  6342. snd_hda_sequence_write(codec, spec->base_exit_verbs);
  6343. ca0132_exit_chip(codec);
  6344. snd_hda_power_down(codec);
  6345. if (spec->mem_base)
  6346. iounmap(spec->mem_base);
  6347. kfree(spec->spec_init_verbs);
  6348. kfree(codec->spec);
  6349. }
  6350. static void ca0132_reboot_notify(struct hda_codec *codec)
  6351. {
  6352. codec->patch_ops.free(codec);
  6353. }
  6354. static const struct hda_codec_ops ca0132_patch_ops = {
  6355. .build_controls = ca0132_build_controls,
  6356. .build_pcms = ca0132_build_pcms,
  6357. .init = ca0132_init,
  6358. .free = ca0132_free,
  6359. .unsol_event = snd_hda_jack_unsol_event,
  6360. .reboot_notify = ca0132_reboot_notify,
  6361. };
  6362. static void ca0132_config(struct hda_codec *codec)
  6363. {
  6364. struct ca0132_spec *spec = codec->spec;
  6365. spec->dacs[0] = 0x2;
  6366. spec->dacs[1] = 0x3;
  6367. spec->dacs[2] = 0x4;
  6368. spec->multiout.dac_nids = spec->dacs;
  6369. spec->multiout.num_dacs = 3;
  6370. if (!spec->use_alt_functions)
  6371. spec->multiout.max_channels = 2;
  6372. else
  6373. spec->multiout.max_channels = 6;
  6374. switch (spec->quirk) {
  6375. case QUIRK_ALIENWARE:
  6376. codec_dbg(codec, "ca0132_config: QUIRK_ALIENWARE applied.\n");
  6377. snd_hda_apply_pincfgs(codec, alienware_pincfgs);
  6378. spec->num_outputs = 2;
  6379. spec->out_pins[0] = 0x0b; /* speaker out */
  6380. spec->out_pins[1] = 0x0f;
  6381. spec->shared_out_nid = 0x2;
  6382. spec->unsol_tag_hp = 0x0f;
  6383. spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
  6384. spec->adcs[1] = 0x8; /* analog mic2 */
  6385. spec->adcs[2] = 0xa; /* what u hear */
  6386. spec->num_inputs = 3;
  6387. spec->input_pins[0] = 0x12;
  6388. spec->input_pins[1] = 0x11;
  6389. spec->input_pins[2] = 0x13;
  6390. spec->shared_mic_nid = 0x7;
  6391. spec->unsol_tag_amic1 = 0x11;
  6392. break;
  6393. case QUIRK_SBZ:
  6394. case QUIRK_R3D:
  6395. if (spec->quirk == QUIRK_SBZ) {
  6396. codec_dbg(codec, "%s: QUIRK_SBZ applied.\n", __func__);
  6397. snd_hda_apply_pincfgs(codec, sbz_pincfgs);
  6398. }
  6399. if (spec->quirk == QUIRK_R3D) {
  6400. codec_dbg(codec, "%s: QUIRK_R3D applied.\n", __func__);
  6401. snd_hda_apply_pincfgs(codec, r3d_pincfgs);
  6402. }
  6403. spec->num_outputs = 2;
  6404. spec->out_pins[0] = 0x0B; /* Line out */
  6405. spec->out_pins[1] = 0x0F; /* Rear headphone out */
  6406. spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
  6407. spec->out_pins[3] = 0x11; /* Rear surround */
  6408. spec->shared_out_nid = 0x2;
  6409. spec->unsol_tag_hp = spec->out_pins[1];
  6410. spec->unsol_tag_front_hp = spec->out_pins[2];
  6411. spec->adcs[0] = 0x7; /* Rear Mic / Line-in */
  6412. spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */
  6413. spec->adcs[2] = 0xa; /* what u hear */
  6414. spec->num_inputs = 2;
  6415. spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
  6416. spec->input_pins[1] = 0x13; /* What U Hear */
  6417. spec->shared_mic_nid = 0x7;
  6418. spec->unsol_tag_amic1 = spec->input_pins[0];
  6419. /* SPDIF I/O */
  6420. spec->dig_out = 0x05;
  6421. spec->multiout.dig_out_nid = spec->dig_out;
  6422. spec->dig_in = 0x09;
  6423. break;
  6424. case QUIRK_R3DI:
  6425. codec_dbg(codec, "%s: QUIRK_R3DI applied.\n", __func__);
  6426. snd_hda_apply_pincfgs(codec, r3di_pincfgs);
  6427. spec->num_outputs = 2;
  6428. spec->out_pins[0] = 0x0B; /* Line out */
  6429. spec->out_pins[1] = 0x0F; /* Rear headphone out */
  6430. spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
  6431. spec->out_pins[3] = 0x11; /* Rear surround */
  6432. spec->shared_out_nid = 0x2;
  6433. spec->unsol_tag_hp = spec->out_pins[1];
  6434. spec->unsol_tag_front_hp = spec->out_pins[2];
  6435. spec->adcs[0] = 0x07; /* Rear Mic / Line-in */
  6436. spec->adcs[1] = 0x08; /* Front Mic, but only if no DSP */
  6437. spec->adcs[2] = 0x0a; /* what u hear */
  6438. spec->num_inputs = 2;
  6439. spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
  6440. spec->input_pins[1] = 0x13; /* What U Hear */
  6441. spec->shared_mic_nid = 0x7;
  6442. spec->unsol_tag_amic1 = spec->input_pins[0];
  6443. /* SPDIF I/O */
  6444. spec->dig_out = 0x05;
  6445. spec->multiout.dig_out_nid = spec->dig_out;
  6446. break;
  6447. default:
  6448. spec->num_outputs = 2;
  6449. spec->out_pins[0] = 0x0b; /* speaker out */
  6450. spec->out_pins[1] = 0x10; /* headphone out */
  6451. spec->shared_out_nid = 0x2;
  6452. spec->unsol_tag_hp = spec->out_pins[1];
  6453. spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
  6454. spec->adcs[1] = 0x8; /* analog mic2 */
  6455. spec->adcs[2] = 0xa; /* what u hear */
  6456. spec->num_inputs = 3;
  6457. spec->input_pins[0] = 0x12;
  6458. spec->input_pins[1] = 0x11;
  6459. spec->input_pins[2] = 0x13;
  6460. spec->shared_mic_nid = 0x7;
  6461. spec->unsol_tag_amic1 = spec->input_pins[0];
  6462. /* SPDIF I/O */
  6463. spec->dig_out = 0x05;
  6464. spec->multiout.dig_out_nid = spec->dig_out;
  6465. spec->dig_in = 0x09;
  6466. break;
  6467. }
  6468. }
  6469. static int ca0132_prepare_verbs(struct hda_codec *codec)
  6470. {
  6471. /* Verbs + terminator (an empty element) */
  6472. #define NUM_SPEC_VERBS 2
  6473. struct ca0132_spec *spec = codec->spec;
  6474. spec->chip_init_verbs = ca0132_init_verbs0;
  6475. if (spec->quirk == QUIRK_SBZ || spec->quirk == QUIRK_R3D)
  6476. spec->desktop_init_verbs = ca0132_init_verbs1;
  6477. spec->spec_init_verbs = kcalloc(NUM_SPEC_VERBS,
  6478. sizeof(struct hda_verb),
  6479. GFP_KERNEL);
  6480. if (!spec->spec_init_verbs)
  6481. return -ENOMEM;
  6482. /* config EAPD */
  6483. spec->spec_init_verbs[0].nid = 0x0b;
  6484. spec->spec_init_verbs[0].param = 0x78D;
  6485. spec->spec_init_verbs[0].verb = 0x00;
  6486. /* Previously commented configuration */
  6487. /*
  6488. spec->spec_init_verbs[2].nid = 0x0b;
  6489. spec->spec_init_verbs[2].param = AC_VERB_SET_EAPD_BTLENABLE;
  6490. spec->spec_init_verbs[2].verb = 0x02;
  6491. spec->spec_init_verbs[3].nid = 0x10;
  6492. spec->spec_init_verbs[3].param = 0x78D;
  6493. spec->spec_init_verbs[3].verb = 0x02;
  6494. spec->spec_init_verbs[4].nid = 0x10;
  6495. spec->spec_init_verbs[4].param = AC_VERB_SET_EAPD_BTLENABLE;
  6496. spec->spec_init_verbs[4].verb = 0x02;
  6497. */
  6498. /* Terminator: spec->spec_init_verbs[NUM_SPEC_VERBS-1] */
  6499. return 0;
  6500. }
  6501. static int patch_ca0132(struct hda_codec *codec)
  6502. {
  6503. struct ca0132_spec *spec;
  6504. int err;
  6505. const struct snd_pci_quirk *quirk;
  6506. codec_dbg(codec, "patch_ca0132\n");
  6507. spec = kzalloc(sizeof(*spec), GFP_KERNEL);
  6508. if (!spec)
  6509. return -ENOMEM;
  6510. codec->spec = spec;
  6511. spec->codec = codec;
  6512. codec->patch_ops = ca0132_patch_ops;
  6513. codec->pcm_format_first = 1;
  6514. codec->no_sticky_stream = 1;
  6515. /* Detect codec quirk */
  6516. quirk = snd_pci_quirk_lookup(codec->bus->pci, ca0132_quirks);
  6517. if (quirk)
  6518. spec->quirk = quirk->value;
  6519. else
  6520. spec->quirk = QUIRK_NONE;
  6521. spec->dsp_state = DSP_DOWNLOAD_INIT;
  6522. spec->num_mixers = 1;
  6523. /* Set which mixers each quirk uses. */
  6524. switch (spec->quirk) {
  6525. case QUIRK_SBZ:
  6526. spec->mixers[0] = desktop_mixer;
  6527. snd_hda_codec_set_name(codec, "Sound Blaster Z");
  6528. break;
  6529. case QUIRK_R3D:
  6530. spec->mixers[0] = desktop_mixer;
  6531. snd_hda_codec_set_name(codec, "Recon3D");
  6532. break;
  6533. case QUIRK_R3DI:
  6534. spec->mixers[0] = r3di_mixer;
  6535. snd_hda_codec_set_name(codec, "Recon3Di");
  6536. break;
  6537. default:
  6538. spec->mixers[0] = ca0132_mixer;
  6539. break;
  6540. }
  6541. /* Setup whether or not to use alt functions/controls/pci_mmio */
  6542. switch (spec->quirk) {
  6543. case QUIRK_SBZ:
  6544. case QUIRK_R3D:
  6545. spec->use_alt_controls = true;
  6546. spec->use_alt_functions = true;
  6547. spec->use_pci_mmio = true;
  6548. break;
  6549. case QUIRK_R3DI:
  6550. spec->use_alt_controls = true;
  6551. spec->use_alt_functions = true;
  6552. spec->use_pci_mmio = false;
  6553. break;
  6554. default:
  6555. spec->use_alt_controls = false;
  6556. spec->use_alt_functions = false;
  6557. spec->use_pci_mmio = false;
  6558. break;
  6559. }
  6560. if (spec->use_pci_mmio) {
  6561. spec->mem_base = pci_iomap(codec->bus->pci, 2, 0xC20);
  6562. if (spec->mem_base == NULL) {
  6563. codec_warn(codec, "pci_iomap failed! Setting quirk to QUIRK_NONE.");
  6564. spec->quirk = QUIRK_NONE;
  6565. }
  6566. }
  6567. spec->base_init_verbs = ca0132_base_init_verbs;
  6568. spec->base_exit_verbs = ca0132_base_exit_verbs;
  6569. INIT_DELAYED_WORK(&spec->unsol_hp_work, ca0132_unsol_hp_delayed);
  6570. ca0132_init_chip(codec);
  6571. ca0132_config(codec);
  6572. err = ca0132_prepare_verbs(codec);
  6573. if (err < 0)
  6574. goto error;
  6575. err = snd_hda_parse_pin_def_config(codec, &spec->autocfg, NULL);
  6576. if (err < 0)
  6577. goto error;
  6578. return 0;
  6579. error:
  6580. ca0132_free(codec);
  6581. return err;
  6582. }
  6583. /*
  6584. * patch entries
  6585. */
  6586. static struct hda_device_id snd_hda_id_ca0132[] = {
  6587. HDA_CODEC_ENTRY(0x11020011, "CA0132", patch_ca0132),
  6588. {} /* terminator */
  6589. };
  6590. MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_ca0132);
  6591. MODULE_LICENSE("GPL");
  6592. MODULE_DESCRIPTION("Creative Sound Core3D codec");
  6593. static struct hda_codec_driver ca0132_driver = {
  6594. .id = snd_hda_id_ca0132,
  6595. };
  6596. module_hda_codec_driver(ca0132_driver);