smc_wr.c 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Shared Memory Communications over RDMA (SMC-R) and RoCE
  4. *
  5. * Work Requests exploiting Infiniband API
  6. *
  7. * Work requests (WR) of type ib_post_send or ib_post_recv respectively
  8. * are submitted to either RC SQ or RC RQ respectively
  9. * (reliably connected send/receive queue)
  10. * and become work queue entries (WQEs).
  11. * While an SQ WR/WQE is pending, we track it until transmission completion.
  12. * Through a send or receive completion queue (CQ) respectively,
  13. * we get completion queue entries (CQEs) [aka work completions (WCs)].
  14. * Since the CQ callback is called from IRQ context, we split work by using
  15. * bottom halves implemented by tasklets.
  16. *
  17. * SMC uses this to exchange LLC (link layer control)
  18. * and CDC (connection data control) messages.
  19. *
  20. * Copyright IBM Corp. 2016
  21. *
  22. * Author(s): Steffen Maier <maier@linux.vnet.ibm.com>
  23. */
  24. #include <linux/atomic.h>
  25. #include <linux/hashtable.h>
  26. #include <linux/wait.h>
  27. #include <rdma/ib_verbs.h>
  28. #include <asm/div64.h>
  29. #include "smc.h"
  30. #include "smc_wr.h"
  31. #define SMC_WR_MAX_POLL_CQE 10 /* max. # of compl. queue elements in 1 poll */
  32. #define SMC_WR_RX_HASH_BITS 4
  33. static DEFINE_HASHTABLE(smc_wr_rx_hash, SMC_WR_RX_HASH_BITS);
  34. static DEFINE_SPINLOCK(smc_wr_rx_hash_lock);
  35. struct smc_wr_tx_pend { /* control data for a pending send request */
  36. u64 wr_id; /* work request id sent */
  37. smc_wr_tx_handler handler;
  38. enum ib_wc_status wc_status; /* CQE status */
  39. struct smc_link *link;
  40. u32 idx;
  41. struct smc_wr_tx_pend_priv priv;
  42. };
  43. /******************************** send queue *********************************/
  44. /*------------------------------- completion --------------------------------*/
  45. static inline int smc_wr_tx_find_pending_index(struct smc_link *link, u64 wr_id)
  46. {
  47. u32 i;
  48. for (i = 0; i < link->wr_tx_cnt; i++) {
  49. if (link->wr_tx_pends[i].wr_id == wr_id)
  50. return i;
  51. }
  52. return link->wr_tx_cnt;
  53. }
  54. static inline void smc_wr_tx_process_cqe(struct ib_wc *wc)
  55. {
  56. struct smc_wr_tx_pend pnd_snd;
  57. struct smc_link *link;
  58. u32 pnd_snd_idx;
  59. int i;
  60. link = wc->qp->qp_context;
  61. if (wc->opcode == IB_WC_REG_MR) {
  62. if (wc->status)
  63. link->wr_reg_state = FAILED;
  64. else
  65. link->wr_reg_state = CONFIRMED;
  66. wake_up(&link->wr_reg_wait);
  67. return;
  68. }
  69. pnd_snd_idx = smc_wr_tx_find_pending_index(link, wc->wr_id);
  70. if (pnd_snd_idx == link->wr_tx_cnt)
  71. return;
  72. link->wr_tx_pends[pnd_snd_idx].wc_status = wc->status;
  73. memcpy(&pnd_snd, &link->wr_tx_pends[pnd_snd_idx], sizeof(pnd_snd));
  74. /* clear the full struct smc_wr_tx_pend including .priv */
  75. memset(&link->wr_tx_pends[pnd_snd_idx], 0,
  76. sizeof(link->wr_tx_pends[pnd_snd_idx]));
  77. memset(&link->wr_tx_bufs[pnd_snd_idx], 0,
  78. sizeof(link->wr_tx_bufs[pnd_snd_idx]));
  79. if (!test_and_clear_bit(pnd_snd_idx, link->wr_tx_mask))
  80. return;
  81. if (wc->status) {
  82. for_each_set_bit(i, link->wr_tx_mask, link->wr_tx_cnt) {
  83. /* clear full struct smc_wr_tx_pend including .priv */
  84. memset(&link->wr_tx_pends[i], 0,
  85. sizeof(link->wr_tx_pends[i]));
  86. memset(&link->wr_tx_bufs[i], 0,
  87. sizeof(link->wr_tx_bufs[i]));
  88. clear_bit(i, link->wr_tx_mask);
  89. }
  90. /* terminate connections of this link group abnormally */
  91. smc_lgr_terminate(smc_get_lgr(link));
  92. }
  93. if (pnd_snd.handler)
  94. pnd_snd.handler(&pnd_snd.priv, link, wc->status);
  95. wake_up(&link->wr_tx_wait);
  96. }
  97. static void smc_wr_tx_tasklet_fn(unsigned long data)
  98. {
  99. struct smc_ib_device *dev = (struct smc_ib_device *)data;
  100. struct ib_wc wc[SMC_WR_MAX_POLL_CQE];
  101. int i = 0, rc;
  102. int polled = 0;
  103. again:
  104. polled++;
  105. do {
  106. memset(&wc, 0, sizeof(wc));
  107. rc = ib_poll_cq(dev->roce_cq_send, SMC_WR_MAX_POLL_CQE, wc);
  108. if (polled == 1) {
  109. ib_req_notify_cq(dev->roce_cq_send,
  110. IB_CQ_NEXT_COMP |
  111. IB_CQ_REPORT_MISSED_EVENTS);
  112. }
  113. if (!rc)
  114. break;
  115. for (i = 0; i < rc; i++)
  116. smc_wr_tx_process_cqe(&wc[i]);
  117. } while (rc > 0);
  118. if (polled == 1)
  119. goto again;
  120. }
  121. void smc_wr_tx_cq_handler(struct ib_cq *ib_cq, void *cq_context)
  122. {
  123. struct smc_ib_device *dev = (struct smc_ib_device *)cq_context;
  124. tasklet_schedule(&dev->send_tasklet);
  125. }
  126. /*---------------------------- request submission ---------------------------*/
  127. static inline int smc_wr_tx_get_free_slot_index(struct smc_link *link, u32 *idx)
  128. {
  129. *idx = link->wr_tx_cnt;
  130. for_each_clear_bit(*idx, link->wr_tx_mask, link->wr_tx_cnt) {
  131. if (!test_and_set_bit(*idx, link->wr_tx_mask))
  132. return 0;
  133. }
  134. *idx = link->wr_tx_cnt;
  135. return -EBUSY;
  136. }
  137. /**
  138. * smc_wr_tx_get_free_slot() - returns buffer for message assembly,
  139. * and sets info for pending transmit tracking
  140. * @link: Pointer to smc_link used to later send the message.
  141. * @handler: Send completion handler function pointer.
  142. * @wr_buf: Out value returns pointer to message buffer.
  143. * @wr_pend_priv: Out value returns pointer serving as handler context.
  144. *
  145. * Return: 0 on success, or -errno on error.
  146. */
  147. int smc_wr_tx_get_free_slot(struct smc_link *link,
  148. smc_wr_tx_handler handler,
  149. struct smc_wr_buf **wr_buf,
  150. struct smc_wr_tx_pend_priv **wr_pend_priv)
  151. {
  152. struct smc_wr_tx_pend *wr_pend;
  153. u32 idx = link->wr_tx_cnt;
  154. struct ib_send_wr *wr_ib;
  155. u64 wr_id;
  156. int rc;
  157. *wr_buf = NULL;
  158. *wr_pend_priv = NULL;
  159. if (in_softirq()) {
  160. rc = smc_wr_tx_get_free_slot_index(link, &idx);
  161. if (rc)
  162. return rc;
  163. } else {
  164. rc = wait_event_timeout(
  165. link->wr_tx_wait,
  166. link->state == SMC_LNK_INACTIVE ||
  167. (smc_wr_tx_get_free_slot_index(link, &idx) != -EBUSY),
  168. SMC_WR_TX_WAIT_FREE_SLOT_TIME);
  169. if (!rc) {
  170. /* timeout - terminate connections */
  171. smc_lgr_terminate(smc_get_lgr(link));
  172. return -EPIPE;
  173. }
  174. if (idx == link->wr_tx_cnt)
  175. return -EPIPE;
  176. }
  177. wr_id = smc_wr_tx_get_next_wr_id(link);
  178. wr_pend = &link->wr_tx_pends[idx];
  179. wr_pend->wr_id = wr_id;
  180. wr_pend->handler = handler;
  181. wr_pend->link = link;
  182. wr_pend->idx = idx;
  183. wr_ib = &link->wr_tx_ibs[idx];
  184. wr_ib->wr_id = wr_id;
  185. *wr_buf = &link->wr_tx_bufs[idx];
  186. *wr_pend_priv = &wr_pend->priv;
  187. return 0;
  188. }
  189. int smc_wr_tx_put_slot(struct smc_link *link,
  190. struct smc_wr_tx_pend_priv *wr_pend_priv)
  191. {
  192. struct smc_wr_tx_pend *pend;
  193. pend = container_of(wr_pend_priv, struct smc_wr_tx_pend, priv);
  194. if (pend->idx < link->wr_tx_cnt) {
  195. /* clear the full struct smc_wr_tx_pend including .priv */
  196. memset(&link->wr_tx_pends[pend->idx], 0,
  197. sizeof(link->wr_tx_pends[pend->idx]));
  198. memset(&link->wr_tx_bufs[pend->idx], 0,
  199. sizeof(link->wr_tx_bufs[pend->idx]));
  200. test_and_clear_bit(pend->idx, link->wr_tx_mask);
  201. return 1;
  202. }
  203. return 0;
  204. }
  205. /* Send prepared WR slot via ib_post_send.
  206. * @priv: pointer to smc_wr_tx_pend_priv identifying prepared message buffer
  207. */
  208. int smc_wr_tx_send(struct smc_link *link, struct smc_wr_tx_pend_priv *priv)
  209. {
  210. struct smc_wr_tx_pend *pend;
  211. int rc;
  212. ib_req_notify_cq(link->smcibdev->roce_cq_send,
  213. IB_CQ_NEXT_COMP | IB_CQ_REPORT_MISSED_EVENTS);
  214. pend = container_of(priv, struct smc_wr_tx_pend, priv);
  215. rc = ib_post_send(link->roce_qp, &link->wr_tx_ibs[pend->idx], NULL);
  216. if (rc) {
  217. smc_wr_tx_put_slot(link, priv);
  218. smc_lgr_terminate(smc_get_lgr(link));
  219. }
  220. return rc;
  221. }
  222. /* Register a memory region and wait for result. */
  223. int smc_wr_reg_send(struct smc_link *link, struct ib_mr *mr)
  224. {
  225. int rc;
  226. ib_req_notify_cq(link->smcibdev->roce_cq_send,
  227. IB_CQ_NEXT_COMP | IB_CQ_REPORT_MISSED_EVENTS);
  228. link->wr_reg_state = POSTED;
  229. link->wr_reg.wr.wr_id = (u64)(uintptr_t)mr;
  230. link->wr_reg.mr = mr;
  231. link->wr_reg.key = mr->rkey;
  232. rc = ib_post_send(link->roce_qp, &link->wr_reg.wr, NULL);
  233. if (rc)
  234. return rc;
  235. rc = wait_event_interruptible_timeout(link->wr_reg_wait,
  236. (link->wr_reg_state != POSTED),
  237. SMC_WR_REG_MR_WAIT_TIME);
  238. if (!rc) {
  239. /* timeout - terminate connections */
  240. smc_lgr_terminate(smc_get_lgr(link));
  241. return -EPIPE;
  242. }
  243. if (rc == -ERESTARTSYS)
  244. return -EINTR;
  245. switch (link->wr_reg_state) {
  246. case CONFIRMED:
  247. rc = 0;
  248. break;
  249. case FAILED:
  250. rc = -EIO;
  251. break;
  252. case POSTED:
  253. rc = -EPIPE;
  254. break;
  255. }
  256. return rc;
  257. }
  258. void smc_wr_tx_dismiss_slots(struct smc_link *link, u8 wr_tx_hdr_type,
  259. smc_wr_tx_filter filter,
  260. smc_wr_tx_dismisser dismisser,
  261. unsigned long data)
  262. {
  263. struct smc_wr_tx_pend_priv *tx_pend;
  264. struct smc_wr_rx_hdr *wr_tx;
  265. int i;
  266. for_each_set_bit(i, link->wr_tx_mask, link->wr_tx_cnt) {
  267. wr_tx = (struct smc_wr_rx_hdr *)&link->wr_tx_bufs[i];
  268. if (wr_tx->type != wr_tx_hdr_type)
  269. continue;
  270. tx_pend = &link->wr_tx_pends[i].priv;
  271. if (filter(tx_pend, data))
  272. dismisser(tx_pend);
  273. }
  274. }
  275. /****************************** receive queue ********************************/
  276. int smc_wr_rx_register_handler(struct smc_wr_rx_handler *handler)
  277. {
  278. struct smc_wr_rx_handler *h_iter;
  279. int rc = 0;
  280. spin_lock(&smc_wr_rx_hash_lock);
  281. hash_for_each_possible(smc_wr_rx_hash, h_iter, list, handler->type) {
  282. if (h_iter->type == handler->type) {
  283. rc = -EEXIST;
  284. goto out_unlock;
  285. }
  286. }
  287. hash_add(smc_wr_rx_hash, &handler->list, handler->type);
  288. out_unlock:
  289. spin_unlock(&smc_wr_rx_hash_lock);
  290. return rc;
  291. }
  292. /* Demultiplex a received work request based on the message type to its handler.
  293. * Relies on smc_wr_rx_hash having been completely filled before any IB WRs,
  294. * and not being modified any more afterwards so we don't need to lock it.
  295. */
  296. static inline void smc_wr_rx_demultiplex(struct ib_wc *wc)
  297. {
  298. struct smc_link *link = (struct smc_link *)wc->qp->qp_context;
  299. struct smc_wr_rx_handler *handler;
  300. struct smc_wr_rx_hdr *wr_rx;
  301. u64 temp_wr_id;
  302. u32 index;
  303. if (wc->byte_len < sizeof(*wr_rx))
  304. return; /* short message */
  305. temp_wr_id = wc->wr_id;
  306. index = do_div(temp_wr_id, link->wr_rx_cnt);
  307. wr_rx = (struct smc_wr_rx_hdr *)&link->wr_rx_bufs[index];
  308. hash_for_each_possible(smc_wr_rx_hash, handler, list, wr_rx->type) {
  309. if (handler->type == wr_rx->type)
  310. handler->handler(wc, wr_rx);
  311. }
  312. }
  313. static inline void smc_wr_rx_process_cqes(struct ib_wc wc[], int num)
  314. {
  315. struct smc_link *link;
  316. int i;
  317. for (i = 0; i < num; i++) {
  318. link = wc[i].qp->qp_context;
  319. if (wc[i].status == IB_WC_SUCCESS) {
  320. link->wr_rx_tstamp = jiffies;
  321. smc_wr_rx_demultiplex(&wc[i]);
  322. smc_wr_rx_post(link); /* refill WR RX */
  323. } else {
  324. /* handle status errors */
  325. switch (wc[i].status) {
  326. case IB_WC_RETRY_EXC_ERR:
  327. case IB_WC_RNR_RETRY_EXC_ERR:
  328. case IB_WC_WR_FLUSH_ERR:
  329. /* terminate connections of this link group
  330. * abnormally
  331. */
  332. smc_lgr_terminate(smc_get_lgr(link));
  333. break;
  334. default:
  335. smc_wr_rx_post(link); /* refill WR RX */
  336. break;
  337. }
  338. }
  339. }
  340. }
  341. static void smc_wr_rx_tasklet_fn(unsigned long data)
  342. {
  343. struct smc_ib_device *dev = (struct smc_ib_device *)data;
  344. struct ib_wc wc[SMC_WR_MAX_POLL_CQE];
  345. int polled = 0;
  346. int rc;
  347. again:
  348. polled++;
  349. do {
  350. memset(&wc, 0, sizeof(wc));
  351. rc = ib_poll_cq(dev->roce_cq_recv, SMC_WR_MAX_POLL_CQE, wc);
  352. if (polled == 1) {
  353. ib_req_notify_cq(dev->roce_cq_recv,
  354. IB_CQ_SOLICITED_MASK
  355. | IB_CQ_REPORT_MISSED_EVENTS);
  356. }
  357. if (!rc)
  358. break;
  359. smc_wr_rx_process_cqes(&wc[0], rc);
  360. } while (rc > 0);
  361. if (polled == 1)
  362. goto again;
  363. }
  364. void smc_wr_rx_cq_handler(struct ib_cq *ib_cq, void *cq_context)
  365. {
  366. struct smc_ib_device *dev = (struct smc_ib_device *)cq_context;
  367. tasklet_schedule(&dev->recv_tasklet);
  368. }
  369. int smc_wr_rx_post_init(struct smc_link *link)
  370. {
  371. u32 i;
  372. int rc = 0;
  373. for (i = 0; i < link->wr_rx_cnt; i++)
  374. rc = smc_wr_rx_post(link);
  375. return rc;
  376. }
  377. /***************************** init, exit, misc ******************************/
  378. void smc_wr_remember_qp_attr(struct smc_link *lnk)
  379. {
  380. struct ib_qp_attr *attr = &lnk->qp_attr;
  381. struct ib_qp_init_attr init_attr;
  382. memset(attr, 0, sizeof(*attr));
  383. memset(&init_attr, 0, sizeof(init_attr));
  384. ib_query_qp(lnk->roce_qp, attr,
  385. IB_QP_STATE |
  386. IB_QP_CUR_STATE |
  387. IB_QP_PKEY_INDEX |
  388. IB_QP_PORT |
  389. IB_QP_QKEY |
  390. IB_QP_AV |
  391. IB_QP_PATH_MTU |
  392. IB_QP_TIMEOUT |
  393. IB_QP_RETRY_CNT |
  394. IB_QP_RNR_RETRY |
  395. IB_QP_RQ_PSN |
  396. IB_QP_ALT_PATH |
  397. IB_QP_MIN_RNR_TIMER |
  398. IB_QP_SQ_PSN |
  399. IB_QP_PATH_MIG_STATE |
  400. IB_QP_CAP |
  401. IB_QP_DEST_QPN,
  402. &init_attr);
  403. lnk->wr_tx_cnt = min_t(size_t, SMC_WR_BUF_CNT,
  404. lnk->qp_attr.cap.max_send_wr);
  405. lnk->wr_rx_cnt = min_t(size_t, SMC_WR_BUF_CNT * 3,
  406. lnk->qp_attr.cap.max_recv_wr);
  407. }
  408. static void smc_wr_init_sge(struct smc_link *lnk)
  409. {
  410. u32 i;
  411. for (i = 0; i < lnk->wr_tx_cnt; i++) {
  412. lnk->wr_tx_sges[i].addr =
  413. lnk->wr_tx_dma_addr + i * SMC_WR_BUF_SIZE;
  414. lnk->wr_tx_sges[i].length = SMC_WR_TX_SIZE;
  415. lnk->wr_tx_sges[i].lkey = lnk->roce_pd->local_dma_lkey;
  416. lnk->wr_tx_ibs[i].next = NULL;
  417. lnk->wr_tx_ibs[i].sg_list = &lnk->wr_tx_sges[i];
  418. lnk->wr_tx_ibs[i].num_sge = 1;
  419. lnk->wr_tx_ibs[i].opcode = IB_WR_SEND;
  420. lnk->wr_tx_ibs[i].send_flags =
  421. IB_SEND_SIGNALED | IB_SEND_SOLICITED;
  422. }
  423. for (i = 0; i < lnk->wr_rx_cnt; i++) {
  424. lnk->wr_rx_sges[i].addr =
  425. lnk->wr_rx_dma_addr + i * SMC_WR_BUF_SIZE;
  426. lnk->wr_rx_sges[i].length = SMC_WR_BUF_SIZE;
  427. lnk->wr_rx_sges[i].lkey = lnk->roce_pd->local_dma_lkey;
  428. lnk->wr_rx_ibs[i].next = NULL;
  429. lnk->wr_rx_ibs[i].sg_list = &lnk->wr_rx_sges[i];
  430. lnk->wr_rx_ibs[i].num_sge = 1;
  431. }
  432. lnk->wr_reg.wr.next = NULL;
  433. lnk->wr_reg.wr.num_sge = 0;
  434. lnk->wr_reg.wr.send_flags = IB_SEND_SIGNALED;
  435. lnk->wr_reg.wr.opcode = IB_WR_REG_MR;
  436. lnk->wr_reg.access = IB_ACCESS_LOCAL_WRITE | IB_ACCESS_REMOTE_WRITE;
  437. }
  438. void smc_wr_free_link(struct smc_link *lnk)
  439. {
  440. struct ib_device *ibdev;
  441. memset(lnk->wr_tx_mask, 0,
  442. BITS_TO_LONGS(SMC_WR_BUF_CNT) * sizeof(*lnk->wr_tx_mask));
  443. if (!lnk->smcibdev)
  444. return;
  445. ibdev = lnk->smcibdev->ibdev;
  446. if (lnk->wr_rx_dma_addr) {
  447. ib_dma_unmap_single(ibdev, lnk->wr_rx_dma_addr,
  448. SMC_WR_BUF_SIZE * lnk->wr_rx_cnt,
  449. DMA_FROM_DEVICE);
  450. lnk->wr_rx_dma_addr = 0;
  451. }
  452. if (lnk->wr_tx_dma_addr) {
  453. ib_dma_unmap_single(ibdev, lnk->wr_tx_dma_addr,
  454. SMC_WR_BUF_SIZE * lnk->wr_tx_cnt,
  455. DMA_TO_DEVICE);
  456. lnk->wr_tx_dma_addr = 0;
  457. }
  458. }
  459. void smc_wr_free_link_mem(struct smc_link *lnk)
  460. {
  461. kfree(lnk->wr_tx_pends);
  462. lnk->wr_tx_pends = NULL;
  463. kfree(lnk->wr_tx_mask);
  464. lnk->wr_tx_mask = NULL;
  465. kfree(lnk->wr_tx_sges);
  466. lnk->wr_tx_sges = NULL;
  467. kfree(lnk->wr_rx_sges);
  468. lnk->wr_rx_sges = NULL;
  469. kfree(lnk->wr_rx_ibs);
  470. lnk->wr_rx_ibs = NULL;
  471. kfree(lnk->wr_tx_ibs);
  472. lnk->wr_tx_ibs = NULL;
  473. kfree(lnk->wr_tx_bufs);
  474. lnk->wr_tx_bufs = NULL;
  475. kfree(lnk->wr_rx_bufs);
  476. lnk->wr_rx_bufs = NULL;
  477. }
  478. int smc_wr_alloc_link_mem(struct smc_link *link)
  479. {
  480. /* allocate link related memory */
  481. link->wr_tx_bufs = kcalloc(SMC_WR_BUF_CNT, SMC_WR_BUF_SIZE, GFP_KERNEL);
  482. if (!link->wr_tx_bufs)
  483. goto no_mem;
  484. link->wr_rx_bufs = kcalloc(SMC_WR_BUF_CNT * 3, SMC_WR_BUF_SIZE,
  485. GFP_KERNEL);
  486. if (!link->wr_rx_bufs)
  487. goto no_mem_wr_tx_bufs;
  488. link->wr_tx_ibs = kcalloc(SMC_WR_BUF_CNT, sizeof(link->wr_tx_ibs[0]),
  489. GFP_KERNEL);
  490. if (!link->wr_tx_ibs)
  491. goto no_mem_wr_rx_bufs;
  492. link->wr_rx_ibs = kcalloc(SMC_WR_BUF_CNT * 3,
  493. sizeof(link->wr_rx_ibs[0]),
  494. GFP_KERNEL);
  495. if (!link->wr_rx_ibs)
  496. goto no_mem_wr_tx_ibs;
  497. link->wr_tx_sges = kcalloc(SMC_WR_BUF_CNT, sizeof(link->wr_tx_sges[0]),
  498. GFP_KERNEL);
  499. if (!link->wr_tx_sges)
  500. goto no_mem_wr_rx_ibs;
  501. link->wr_rx_sges = kcalloc(SMC_WR_BUF_CNT * 3,
  502. sizeof(link->wr_rx_sges[0]),
  503. GFP_KERNEL);
  504. if (!link->wr_rx_sges)
  505. goto no_mem_wr_tx_sges;
  506. link->wr_tx_mask = kcalloc(BITS_TO_LONGS(SMC_WR_BUF_CNT),
  507. sizeof(*link->wr_tx_mask),
  508. GFP_KERNEL);
  509. if (!link->wr_tx_mask)
  510. goto no_mem_wr_rx_sges;
  511. link->wr_tx_pends = kcalloc(SMC_WR_BUF_CNT,
  512. sizeof(link->wr_tx_pends[0]),
  513. GFP_KERNEL);
  514. if (!link->wr_tx_pends)
  515. goto no_mem_wr_tx_mask;
  516. return 0;
  517. no_mem_wr_tx_mask:
  518. kfree(link->wr_tx_mask);
  519. no_mem_wr_rx_sges:
  520. kfree(link->wr_rx_sges);
  521. no_mem_wr_tx_sges:
  522. kfree(link->wr_tx_sges);
  523. no_mem_wr_rx_ibs:
  524. kfree(link->wr_rx_ibs);
  525. no_mem_wr_tx_ibs:
  526. kfree(link->wr_tx_ibs);
  527. no_mem_wr_rx_bufs:
  528. kfree(link->wr_rx_bufs);
  529. no_mem_wr_tx_bufs:
  530. kfree(link->wr_tx_bufs);
  531. no_mem:
  532. return -ENOMEM;
  533. }
  534. void smc_wr_remove_dev(struct smc_ib_device *smcibdev)
  535. {
  536. tasklet_kill(&smcibdev->recv_tasklet);
  537. tasklet_kill(&smcibdev->send_tasklet);
  538. }
  539. void smc_wr_add_dev(struct smc_ib_device *smcibdev)
  540. {
  541. tasklet_init(&smcibdev->recv_tasklet, smc_wr_rx_tasklet_fn,
  542. (unsigned long)smcibdev);
  543. tasklet_init(&smcibdev->send_tasklet, smc_wr_tx_tasklet_fn,
  544. (unsigned long)smcibdev);
  545. }
  546. int smc_wr_create_link(struct smc_link *lnk)
  547. {
  548. struct ib_device *ibdev = lnk->smcibdev->ibdev;
  549. int rc = 0;
  550. smc_wr_tx_set_wr_id(&lnk->wr_tx_id, 0);
  551. lnk->wr_rx_id = 0;
  552. lnk->wr_rx_dma_addr = ib_dma_map_single(
  553. ibdev, lnk->wr_rx_bufs, SMC_WR_BUF_SIZE * lnk->wr_rx_cnt,
  554. DMA_FROM_DEVICE);
  555. if (ib_dma_mapping_error(ibdev, lnk->wr_rx_dma_addr)) {
  556. lnk->wr_rx_dma_addr = 0;
  557. rc = -EIO;
  558. goto out;
  559. }
  560. lnk->wr_tx_dma_addr = ib_dma_map_single(
  561. ibdev, lnk->wr_tx_bufs, SMC_WR_BUF_SIZE * lnk->wr_tx_cnt,
  562. DMA_TO_DEVICE);
  563. if (ib_dma_mapping_error(ibdev, lnk->wr_tx_dma_addr)) {
  564. rc = -EIO;
  565. goto dma_unmap;
  566. }
  567. smc_wr_init_sge(lnk);
  568. memset(lnk->wr_tx_mask, 0,
  569. BITS_TO_LONGS(SMC_WR_BUF_CNT) * sizeof(*lnk->wr_tx_mask));
  570. init_waitqueue_head(&lnk->wr_tx_wait);
  571. init_waitqueue_head(&lnk->wr_reg_wait);
  572. return rc;
  573. dma_unmap:
  574. ib_dma_unmap_single(ibdev, lnk->wr_rx_dma_addr,
  575. SMC_WR_BUF_SIZE * lnk->wr_rx_cnt,
  576. DMA_FROM_DEVICE);
  577. lnk->wr_rx_dma_addr = 0;
  578. out:
  579. return rc;
  580. }