ocrdma_verbs.c 80 KB

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  1. /* This file is part of the Emulex RoCE Device Driver for
  2. * RoCE (RDMA over Converged Ethernet) adapters.
  3. * Copyright (C) 2012-2015 Emulex. All rights reserved.
  4. * EMULEX and SLI are trademarks of Emulex.
  5. * www.emulex.com
  6. *
  7. * This software is available to you under a choice of one of two licenses.
  8. * You may choose to be licensed under the terms of the GNU General Public
  9. * License (GPL) Version 2, available from the file COPYING in the main
  10. * directory of this source tree, or the BSD license below:
  11. *
  12. * Redistribution and use in source and binary forms, with or without
  13. * modification, are permitted provided that the following conditions
  14. * are met:
  15. *
  16. * - Redistributions of source code must retain the above copyright notice,
  17. * this list of conditions and the following disclaimer.
  18. *
  19. * - Redistributions in binary form must reproduce the above copyright
  20. * notice, this list of conditions and the following disclaimer in
  21. * the documentation and/or other materials provided with the distribution.
  22. *
  23. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  24. * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,THE
  25. * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  26. * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
  27. * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  28. * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  29. * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  30. * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  31. * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
  32. * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
  33. * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34. *
  35. * Contact Information:
  36. * linux-drivers@emulex.com
  37. *
  38. * Emulex
  39. * 3333 Susan Street
  40. * Costa Mesa, CA 92626
  41. */
  42. #include <linux/dma-mapping.h>
  43. #include <rdma/ib_verbs.h>
  44. #include <rdma/ib_user_verbs.h>
  45. #include <rdma/iw_cm.h>
  46. #include <rdma/ib_umem.h>
  47. #include <rdma/ib_addr.h>
  48. #include <rdma/ib_cache.h>
  49. #include "ocrdma.h"
  50. #include "ocrdma_hw.h"
  51. #include "ocrdma_verbs.h"
  52. #include <rdma/ocrdma-abi.h>
  53. int ocrdma_query_pkey(struct ib_device *ibdev, u8 port, u16 index, u16 *pkey)
  54. {
  55. if (index > 1)
  56. return -EINVAL;
  57. *pkey = 0xffff;
  58. return 0;
  59. }
  60. int ocrdma_query_device(struct ib_device *ibdev, struct ib_device_attr *attr,
  61. struct ib_udata *uhw)
  62. {
  63. struct ocrdma_dev *dev = get_ocrdma_dev(ibdev);
  64. if (uhw->inlen || uhw->outlen)
  65. return -EINVAL;
  66. memset(attr, 0, sizeof *attr);
  67. memcpy(&attr->fw_ver, &dev->attr.fw_ver[0],
  68. min(sizeof(dev->attr.fw_ver), sizeof(attr->fw_ver)));
  69. ocrdma_get_guid(dev, (u8 *)&attr->sys_image_guid);
  70. attr->max_mr_size = dev->attr.max_mr_size;
  71. attr->page_size_cap = 0xffff000;
  72. attr->vendor_id = dev->nic_info.pdev->vendor;
  73. attr->vendor_part_id = dev->nic_info.pdev->device;
  74. attr->hw_ver = dev->asic_id;
  75. attr->max_qp = dev->attr.max_qp;
  76. attr->max_ah = OCRDMA_MAX_AH;
  77. attr->max_qp_wr = dev->attr.max_wqe;
  78. attr->device_cap_flags = IB_DEVICE_CURR_QP_STATE_MOD |
  79. IB_DEVICE_RC_RNR_NAK_GEN |
  80. IB_DEVICE_SHUTDOWN_PORT |
  81. IB_DEVICE_SYS_IMAGE_GUID |
  82. IB_DEVICE_LOCAL_DMA_LKEY |
  83. IB_DEVICE_MEM_MGT_EXTENSIONS;
  84. attr->max_sge = min(dev->attr.max_send_sge, dev->attr.max_recv_sge);
  85. attr->max_sge_rd = dev->attr.max_rdma_sge;
  86. attr->max_cq = dev->attr.max_cq;
  87. attr->max_cqe = dev->attr.max_cqe;
  88. attr->max_mr = dev->attr.max_mr;
  89. attr->max_mw = dev->attr.max_mw;
  90. attr->max_pd = dev->attr.max_pd;
  91. attr->atomic_cap = 0;
  92. attr->max_fmr = 0;
  93. attr->max_map_per_fmr = 0;
  94. attr->max_qp_rd_atom =
  95. min(dev->attr.max_ord_per_qp, dev->attr.max_ird_per_qp);
  96. attr->max_qp_init_rd_atom = dev->attr.max_ord_per_qp;
  97. attr->max_srq = dev->attr.max_srq;
  98. attr->max_srq_sge = dev->attr.max_srq_sge;
  99. attr->max_srq_wr = dev->attr.max_rqe;
  100. attr->local_ca_ack_delay = dev->attr.local_ca_ack_delay;
  101. attr->max_fast_reg_page_list_len = dev->attr.max_pages_per_frmr;
  102. attr->max_pkeys = 1;
  103. return 0;
  104. }
  105. struct net_device *ocrdma_get_netdev(struct ib_device *ibdev, u8 port_num)
  106. {
  107. struct ocrdma_dev *dev;
  108. struct net_device *ndev = NULL;
  109. rcu_read_lock();
  110. dev = get_ocrdma_dev(ibdev);
  111. if (dev)
  112. ndev = dev->nic_info.netdev;
  113. if (ndev)
  114. dev_hold(ndev);
  115. rcu_read_unlock();
  116. return ndev;
  117. }
  118. static inline void get_link_speed_and_width(struct ocrdma_dev *dev,
  119. u8 *ib_speed, u8 *ib_width)
  120. {
  121. int status;
  122. u8 speed;
  123. status = ocrdma_mbx_get_link_speed(dev, &speed, NULL);
  124. if (status)
  125. speed = OCRDMA_PHYS_LINK_SPEED_ZERO;
  126. switch (speed) {
  127. case OCRDMA_PHYS_LINK_SPEED_1GBPS:
  128. *ib_speed = IB_SPEED_SDR;
  129. *ib_width = IB_WIDTH_1X;
  130. break;
  131. case OCRDMA_PHYS_LINK_SPEED_10GBPS:
  132. *ib_speed = IB_SPEED_QDR;
  133. *ib_width = IB_WIDTH_1X;
  134. break;
  135. case OCRDMA_PHYS_LINK_SPEED_20GBPS:
  136. *ib_speed = IB_SPEED_DDR;
  137. *ib_width = IB_WIDTH_4X;
  138. break;
  139. case OCRDMA_PHYS_LINK_SPEED_40GBPS:
  140. *ib_speed = IB_SPEED_QDR;
  141. *ib_width = IB_WIDTH_4X;
  142. break;
  143. default:
  144. /* Unsupported */
  145. *ib_speed = IB_SPEED_SDR;
  146. *ib_width = IB_WIDTH_1X;
  147. }
  148. }
  149. int ocrdma_query_port(struct ib_device *ibdev,
  150. u8 port, struct ib_port_attr *props)
  151. {
  152. enum ib_port_state port_state;
  153. struct ocrdma_dev *dev;
  154. struct net_device *netdev;
  155. /* props being zeroed by the caller, avoid zeroing it here */
  156. dev = get_ocrdma_dev(ibdev);
  157. if (port > 1) {
  158. pr_err("%s(%d) invalid_port=0x%x\n", __func__,
  159. dev->id, port);
  160. return -EINVAL;
  161. }
  162. netdev = dev->nic_info.netdev;
  163. if (netif_running(netdev) && netif_oper_up(netdev)) {
  164. port_state = IB_PORT_ACTIVE;
  165. props->phys_state = 5;
  166. } else {
  167. port_state = IB_PORT_DOWN;
  168. props->phys_state = 3;
  169. }
  170. props->max_mtu = IB_MTU_4096;
  171. props->active_mtu = iboe_get_mtu(netdev->mtu);
  172. props->lid = 0;
  173. props->lmc = 0;
  174. props->sm_lid = 0;
  175. props->sm_sl = 0;
  176. props->state = port_state;
  177. props->port_cap_flags =
  178. IB_PORT_CM_SUP |
  179. IB_PORT_REINIT_SUP |
  180. IB_PORT_DEVICE_MGMT_SUP | IB_PORT_VENDOR_CLASS_SUP |
  181. IB_PORT_IP_BASED_GIDS;
  182. props->gid_tbl_len = OCRDMA_MAX_SGID;
  183. props->pkey_tbl_len = 1;
  184. props->bad_pkey_cntr = 0;
  185. props->qkey_viol_cntr = 0;
  186. get_link_speed_and_width(dev, &props->active_speed,
  187. &props->active_width);
  188. props->max_msg_sz = 0x80000000;
  189. props->max_vl_num = 4;
  190. return 0;
  191. }
  192. int ocrdma_modify_port(struct ib_device *ibdev, u8 port, int mask,
  193. struct ib_port_modify *props)
  194. {
  195. struct ocrdma_dev *dev;
  196. dev = get_ocrdma_dev(ibdev);
  197. if (port > 1) {
  198. pr_err("%s(%d) invalid_port=0x%x\n", __func__, dev->id, port);
  199. return -EINVAL;
  200. }
  201. return 0;
  202. }
  203. static int ocrdma_add_mmap(struct ocrdma_ucontext *uctx, u64 phy_addr,
  204. unsigned long len)
  205. {
  206. struct ocrdma_mm *mm;
  207. mm = kzalloc(sizeof(*mm), GFP_KERNEL);
  208. if (mm == NULL)
  209. return -ENOMEM;
  210. mm->key.phy_addr = phy_addr;
  211. mm->key.len = len;
  212. INIT_LIST_HEAD(&mm->entry);
  213. mutex_lock(&uctx->mm_list_lock);
  214. list_add_tail(&mm->entry, &uctx->mm_head);
  215. mutex_unlock(&uctx->mm_list_lock);
  216. return 0;
  217. }
  218. static void ocrdma_del_mmap(struct ocrdma_ucontext *uctx, u64 phy_addr,
  219. unsigned long len)
  220. {
  221. struct ocrdma_mm *mm, *tmp;
  222. mutex_lock(&uctx->mm_list_lock);
  223. list_for_each_entry_safe(mm, tmp, &uctx->mm_head, entry) {
  224. if (len != mm->key.len && phy_addr != mm->key.phy_addr)
  225. continue;
  226. list_del(&mm->entry);
  227. kfree(mm);
  228. break;
  229. }
  230. mutex_unlock(&uctx->mm_list_lock);
  231. }
  232. static bool ocrdma_search_mmap(struct ocrdma_ucontext *uctx, u64 phy_addr,
  233. unsigned long len)
  234. {
  235. bool found = false;
  236. struct ocrdma_mm *mm;
  237. mutex_lock(&uctx->mm_list_lock);
  238. list_for_each_entry(mm, &uctx->mm_head, entry) {
  239. if (len != mm->key.len && phy_addr != mm->key.phy_addr)
  240. continue;
  241. found = true;
  242. break;
  243. }
  244. mutex_unlock(&uctx->mm_list_lock);
  245. return found;
  246. }
  247. static u16 _ocrdma_pd_mgr_get_bitmap(struct ocrdma_dev *dev, bool dpp_pool)
  248. {
  249. u16 pd_bitmap_idx = 0;
  250. const unsigned long *pd_bitmap;
  251. if (dpp_pool) {
  252. pd_bitmap = dev->pd_mgr->pd_dpp_bitmap;
  253. pd_bitmap_idx = find_first_zero_bit(pd_bitmap,
  254. dev->pd_mgr->max_dpp_pd);
  255. __set_bit(pd_bitmap_idx, dev->pd_mgr->pd_dpp_bitmap);
  256. dev->pd_mgr->pd_dpp_count++;
  257. if (dev->pd_mgr->pd_dpp_count > dev->pd_mgr->pd_dpp_thrsh)
  258. dev->pd_mgr->pd_dpp_thrsh = dev->pd_mgr->pd_dpp_count;
  259. } else {
  260. pd_bitmap = dev->pd_mgr->pd_norm_bitmap;
  261. pd_bitmap_idx = find_first_zero_bit(pd_bitmap,
  262. dev->pd_mgr->max_normal_pd);
  263. __set_bit(pd_bitmap_idx, dev->pd_mgr->pd_norm_bitmap);
  264. dev->pd_mgr->pd_norm_count++;
  265. if (dev->pd_mgr->pd_norm_count > dev->pd_mgr->pd_norm_thrsh)
  266. dev->pd_mgr->pd_norm_thrsh = dev->pd_mgr->pd_norm_count;
  267. }
  268. return pd_bitmap_idx;
  269. }
  270. static int _ocrdma_pd_mgr_put_bitmap(struct ocrdma_dev *dev, u16 pd_id,
  271. bool dpp_pool)
  272. {
  273. u16 pd_count;
  274. u16 pd_bit_index;
  275. pd_count = dpp_pool ? dev->pd_mgr->pd_dpp_count :
  276. dev->pd_mgr->pd_norm_count;
  277. if (pd_count == 0)
  278. return -EINVAL;
  279. if (dpp_pool) {
  280. pd_bit_index = pd_id - dev->pd_mgr->pd_dpp_start;
  281. if (pd_bit_index >= dev->pd_mgr->max_dpp_pd) {
  282. return -EINVAL;
  283. } else {
  284. __clear_bit(pd_bit_index, dev->pd_mgr->pd_dpp_bitmap);
  285. dev->pd_mgr->pd_dpp_count--;
  286. }
  287. } else {
  288. pd_bit_index = pd_id - dev->pd_mgr->pd_norm_start;
  289. if (pd_bit_index >= dev->pd_mgr->max_normal_pd) {
  290. return -EINVAL;
  291. } else {
  292. __clear_bit(pd_bit_index, dev->pd_mgr->pd_norm_bitmap);
  293. dev->pd_mgr->pd_norm_count--;
  294. }
  295. }
  296. return 0;
  297. }
  298. static int ocrdma_put_pd_num(struct ocrdma_dev *dev, u16 pd_id,
  299. bool dpp_pool)
  300. {
  301. int status;
  302. mutex_lock(&dev->dev_lock);
  303. status = _ocrdma_pd_mgr_put_bitmap(dev, pd_id, dpp_pool);
  304. mutex_unlock(&dev->dev_lock);
  305. return status;
  306. }
  307. static int ocrdma_get_pd_num(struct ocrdma_dev *dev, struct ocrdma_pd *pd)
  308. {
  309. u16 pd_idx = 0;
  310. int status = 0;
  311. mutex_lock(&dev->dev_lock);
  312. if (pd->dpp_enabled) {
  313. /* try allocating DPP PD, if not available then normal PD */
  314. if (dev->pd_mgr->pd_dpp_count < dev->pd_mgr->max_dpp_pd) {
  315. pd_idx = _ocrdma_pd_mgr_get_bitmap(dev, true);
  316. pd->id = dev->pd_mgr->pd_dpp_start + pd_idx;
  317. pd->dpp_page = dev->pd_mgr->dpp_page_index + pd_idx;
  318. } else if (dev->pd_mgr->pd_norm_count <
  319. dev->pd_mgr->max_normal_pd) {
  320. pd_idx = _ocrdma_pd_mgr_get_bitmap(dev, false);
  321. pd->id = dev->pd_mgr->pd_norm_start + pd_idx;
  322. pd->dpp_enabled = false;
  323. } else {
  324. status = -EINVAL;
  325. }
  326. } else {
  327. if (dev->pd_mgr->pd_norm_count < dev->pd_mgr->max_normal_pd) {
  328. pd_idx = _ocrdma_pd_mgr_get_bitmap(dev, false);
  329. pd->id = dev->pd_mgr->pd_norm_start + pd_idx;
  330. } else {
  331. status = -EINVAL;
  332. }
  333. }
  334. mutex_unlock(&dev->dev_lock);
  335. return status;
  336. }
  337. static struct ocrdma_pd *_ocrdma_alloc_pd(struct ocrdma_dev *dev,
  338. struct ocrdma_ucontext *uctx,
  339. struct ib_udata *udata)
  340. {
  341. struct ocrdma_pd *pd = NULL;
  342. int status;
  343. pd = kzalloc(sizeof(*pd), GFP_KERNEL);
  344. if (!pd)
  345. return ERR_PTR(-ENOMEM);
  346. if (udata && uctx && dev->attr.max_dpp_pds) {
  347. pd->dpp_enabled =
  348. ocrdma_get_asic_type(dev) == OCRDMA_ASIC_GEN_SKH_R;
  349. pd->num_dpp_qp =
  350. pd->dpp_enabled ? (dev->nic_info.db_page_size /
  351. dev->attr.wqe_size) : 0;
  352. }
  353. if (dev->pd_mgr->pd_prealloc_valid) {
  354. status = ocrdma_get_pd_num(dev, pd);
  355. if (status == 0) {
  356. return pd;
  357. } else {
  358. kfree(pd);
  359. return ERR_PTR(status);
  360. }
  361. }
  362. retry:
  363. status = ocrdma_mbx_alloc_pd(dev, pd);
  364. if (status) {
  365. if (pd->dpp_enabled) {
  366. pd->dpp_enabled = false;
  367. pd->num_dpp_qp = 0;
  368. goto retry;
  369. } else {
  370. kfree(pd);
  371. return ERR_PTR(status);
  372. }
  373. }
  374. return pd;
  375. }
  376. static inline int is_ucontext_pd(struct ocrdma_ucontext *uctx,
  377. struct ocrdma_pd *pd)
  378. {
  379. return (uctx->cntxt_pd == pd);
  380. }
  381. static int _ocrdma_dealloc_pd(struct ocrdma_dev *dev,
  382. struct ocrdma_pd *pd)
  383. {
  384. int status;
  385. if (dev->pd_mgr->pd_prealloc_valid)
  386. status = ocrdma_put_pd_num(dev, pd->id, pd->dpp_enabled);
  387. else
  388. status = ocrdma_mbx_dealloc_pd(dev, pd);
  389. kfree(pd);
  390. return status;
  391. }
  392. static int ocrdma_alloc_ucontext_pd(struct ocrdma_dev *dev,
  393. struct ocrdma_ucontext *uctx,
  394. struct ib_udata *udata)
  395. {
  396. int status = 0;
  397. uctx->cntxt_pd = _ocrdma_alloc_pd(dev, uctx, udata);
  398. if (IS_ERR(uctx->cntxt_pd)) {
  399. status = PTR_ERR(uctx->cntxt_pd);
  400. uctx->cntxt_pd = NULL;
  401. goto err;
  402. }
  403. uctx->cntxt_pd->uctx = uctx;
  404. uctx->cntxt_pd->ibpd.device = &dev->ibdev;
  405. err:
  406. return status;
  407. }
  408. static int ocrdma_dealloc_ucontext_pd(struct ocrdma_ucontext *uctx)
  409. {
  410. struct ocrdma_pd *pd = uctx->cntxt_pd;
  411. struct ocrdma_dev *dev = get_ocrdma_dev(pd->ibpd.device);
  412. if (uctx->pd_in_use) {
  413. pr_err("%s(%d) Freeing in use pdid=0x%x.\n",
  414. __func__, dev->id, pd->id);
  415. }
  416. uctx->cntxt_pd = NULL;
  417. (void)_ocrdma_dealloc_pd(dev, pd);
  418. return 0;
  419. }
  420. static struct ocrdma_pd *ocrdma_get_ucontext_pd(struct ocrdma_ucontext *uctx)
  421. {
  422. struct ocrdma_pd *pd = NULL;
  423. mutex_lock(&uctx->mm_list_lock);
  424. if (!uctx->pd_in_use) {
  425. uctx->pd_in_use = true;
  426. pd = uctx->cntxt_pd;
  427. }
  428. mutex_unlock(&uctx->mm_list_lock);
  429. return pd;
  430. }
  431. static void ocrdma_release_ucontext_pd(struct ocrdma_ucontext *uctx)
  432. {
  433. mutex_lock(&uctx->mm_list_lock);
  434. uctx->pd_in_use = false;
  435. mutex_unlock(&uctx->mm_list_lock);
  436. }
  437. struct ib_ucontext *ocrdma_alloc_ucontext(struct ib_device *ibdev,
  438. struct ib_udata *udata)
  439. {
  440. int status;
  441. struct ocrdma_ucontext *ctx;
  442. struct ocrdma_alloc_ucontext_resp resp;
  443. struct ocrdma_dev *dev = get_ocrdma_dev(ibdev);
  444. struct pci_dev *pdev = dev->nic_info.pdev;
  445. u32 map_len = roundup(sizeof(u32) * 2048, PAGE_SIZE);
  446. if (!udata)
  447. return ERR_PTR(-EFAULT);
  448. ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
  449. if (!ctx)
  450. return ERR_PTR(-ENOMEM);
  451. INIT_LIST_HEAD(&ctx->mm_head);
  452. mutex_init(&ctx->mm_list_lock);
  453. ctx->ah_tbl.va = dma_zalloc_coherent(&pdev->dev, map_len,
  454. &ctx->ah_tbl.pa, GFP_KERNEL);
  455. if (!ctx->ah_tbl.va) {
  456. kfree(ctx);
  457. return ERR_PTR(-ENOMEM);
  458. }
  459. ctx->ah_tbl.len = map_len;
  460. memset(&resp, 0, sizeof(resp));
  461. resp.ah_tbl_len = ctx->ah_tbl.len;
  462. resp.ah_tbl_page = virt_to_phys(ctx->ah_tbl.va);
  463. status = ocrdma_add_mmap(ctx, resp.ah_tbl_page, resp.ah_tbl_len);
  464. if (status)
  465. goto map_err;
  466. status = ocrdma_alloc_ucontext_pd(dev, ctx, udata);
  467. if (status)
  468. goto pd_err;
  469. resp.dev_id = dev->id;
  470. resp.max_inline_data = dev->attr.max_inline_data;
  471. resp.wqe_size = dev->attr.wqe_size;
  472. resp.rqe_size = dev->attr.rqe_size;
  473. resp.dpp_wqe_size = dev->attr.wqe_size;
  474. memcpy(resp.fw_ver, dev->attr.fw_ver, sizeof(resp.fw_ver));
  475. status = ib_copy_to_udata(udata, &resp, sizeof(resp));
  476. if (status)
  477. goto cpy_err;
  478. return &ctx->ibucontext;
  479. cpy_err:
  480. pd_err:
  481. ocrdma_del_mmap(ctx, ctx->ah_tbl.pa, ctx->ah_tbl.len);
  482. map_err:
  483. dma_free_coherent(&pdev->dev, ctx->ah_tbl.len, ctx->ah_tbl.va,
  484. ctx->ah_tbl.pa);
  485. kfree(ctx);
  486. return ERR_PTR(status);
  487. }
  488. int ocrdma_dealloc_ucontext(struct ib_ucontext *ibctx)
  489. {
  490. int status;
  491. struct ocrdma_mm *mm, *tmp;
  492. struct ocrdma_ucontext *uctx = get_ocrdma_ucontext(ibctx);
  493. struct ocrdma_dev *dev = get_ocrdma_dev(ibctx->device);
  494. struct pci_dev *pdev = dev->nic_info.pdev;
  495. status = ocrdma_dealloc_ucontext_pd(uctx);
  496. ocrdma_del_mmap(uctx, uctx->ah_tbl.pa, uctx->ah_tbl.len);
  497. dma_free_coherent(&pdev->dev, uctx->ah_tbl.len, uctx->ah_tbl.va,
  498. uctx->ah_tbl.pa);
  499. list_for_each_entry_safe(mm, tmp, &uctx->mm_head, entry) {
  500. list_del(&mm->entry);
  501. kfree(mm);
  502. }
  503. kfree(uctx);
  504. return status;
  505. }
  506. int ocrdma_mmap(struct ib_ucontext *context, struct vm_area_struct *vma)
  507. {
  508. struct ocrdma_ucontext *ucontext = get_ocrdma_ucontext(context);
  509. struct ocrdma_dev *dev = get_ocrdma_dev(context->device);
  510. unsigned long vm_page = vma->vm_pgoff << PAGE_SHIFT;
  511. u64 unmapped_db = (u64) dev->nic_info.unmapped_db;
  512. unsigned long len = (vma->vm_end - vma->vm_start);
  513. int status;
  514. bool found;
  515. if (vma->vm_start & (PAGE_SIZE - 1))
  516. return -EINVAL;
  517. found = ocrdma_search_mmap(ucontext, vma->vm_pgoff << PAGE_SHIFT, len);
  518. if (!found)
  519. return -EINVAL;
  520. if ((vm_page >= unmapped_db) && (vm_page <= (unmapped_db +
  521. dev->nic_info.db_total_size)) &&
  522. (len <= dev->nic_info.db_page_size)) {
  523. if (vma->vm_flags & VM_READ)
  524. return -EPERM;
  525. vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
  526. status = io_remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
  527. len, vma->vm_page_prot);
  528. } else if (dev->nic_info.dpp_unmapped_len &&
  529. (vm_page >= (u64) dev->nic_info.dpp_unmapped_addr) &&
  530. (vm_page <= (u64) (dev->nic_info.dpp_unmapped_addr +
  531. dev->nic_info.dpp_unmapped_len)) &&
  532. (len <= dev->nic_info.dpp_unmapped_len)) {
  533. if (vma->vm_flags & VM_READ)
  534. return -EPERM;
  535. vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
  536. status = io_remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
  537. len, vma->vm_page_prot);
  538. } else {
  539. status = remap_pfn_range(vma, vma->vm_start,
  540. vma->vm_pgoff, len, vma->vm_page_prot);
  541. }
  542. return status;
  543. }
  544. static int ocrdma_copy_pd_uresp(struct ocrdma_dev *dev, struct ocrdma_pd *pd,
  545. struct ib_ucontext *ib_ctx,
  546. struct ib_udata *udata)
  547. {
  548. int status;
  549. u64 db_page_addr;
  550. u64 dpp_page_addr = 0;
  551. u32 db_page_size;
  552. struct ocrdma_alloc_pd_uresp rsp;
  553. struct ocrdma_ucontext *uctx = get_ocrdma_ucontext(ib_ctx);
  554. memset(&rsp, 0, sizeof(rsp));
  555. rsp.id = pd->id;
  556. rsp.dpp_enabled = pd->dpp_enabled;
  557. db_page_addr = ocrdma_get_db_addr(dev, pd->id);
  558. db_page_size = dev->nic_info.db_page_size;
  559. status = ocrdma_add_mmap(uctx, db_page_addr, db_page_size);
  560. if (status)
  561. return status;
  562. if (pd->dpp_enabled) {
  563. dpp_page_addr = dev->nic_info.dpp_unmapped_addr +
  564. (pd->id * PAGE_SIZE);
  565. status = ocrdma_add_mmap(uctx, dpp_page_addr,
  566. PAGE_SIZE);
  567. if (status)
  568. goto dpp_map_err;
  569. rsp.dpp_page_addr_hi = upper_32_bits(dpp_page_addr);
  570. rsp.dpp_page_addr_lo = dpp_page_addr;
  571. }
  572. status = ib_copy_to_udata(udata, &rsp, sizeof(rsp));
  573. if (status)
  574. goto ucopy_err;
  575. pd->uctx = uctx;
  576. return 0;
  577. ucopy_err:
  578. if (pd->dpp_enabled)
  579. ocrdma_del_mmap(pd->uctx, dpp_page_addr, PAGE_SIZE);
  580. dpp_map_err:
  581. ocrdma_del_mmap(pd->uctx, db_page_addr, db_page_size);
  582. return status;
  583. }
  584. struct ib_pd *ocrdma_alloc_pd(struct ib_device *ibdev,
  585. struct ib_ucontext *context,
  586. struct ib_udata *udata)
  587. {
  588. struct ocrdma_dev *dev = get_ocrdma_dev(ibdev);
  589. struct ocrdma_pd *pd;
  590. struct ocrdma_ucontext *uctx = NULL;
  591. int status;
  592. u8 is_uctx_pd = false;
  593. if (udata && context) {
  594. uctx = get_ocrdma_ucontext(context);
  595. pd = ocrdma_get_ucontext_pd(uctx);
  596. if (pd) {
  597. is_uctx_pd = true;
  598. goto pd_mapping;
  599. }
  600. }
  601. pd = _ocrdma_alloc_pd(dev, uctx, udata);
  602. if (IS_ERR(pd)) {
  603. status = PTR_ERR(pd);
  604. goto exit;
  605. }
  606. pd_mapping:
  607. if (udata && context) {
  608. status = ocrdma_copy_pd_uresp(dev, pd, context, udata);
  609. if (status)
  610. goto err;
  611. }
  612. return &pd->ibpd;
  613. err:
  614. if (is_uctx_pd) {
  615. ocrdma_release_ucontext_pd(uctx);
  616. } else {
  617. if (_ocrdma_dealloc_pd(dev, pd))
  618. pr_err("%s: _ocrdma_dealloc_pd() failed\n", __func__);
  619. }
  620. exit:
  621. return ERR_PTR(status);
  622. }
  623. int ocrdma_dealloc_pd(struct ib_pd *ibpd)
  624. {
  625. struct ocrdma_pd *pd = get_ocrdma_pd(ibpd);
  626. struct ocrdma_dev *dev = get_ocrdma_dev(ibpd->device);
  627. struct ocrdma_ucontext *uctx = NULL;
  628. int status = 0;
  629. u64 usr_db;
  630. uctx = pd->uctx;
  631. if (uctx) {
  632. u64 dpp_db = dev->nic_info.dpp_unmapped_addr +
  633. (pd->id * PAGE_SIZE);
  634. if (pd->dpp_enabled)
  635. ocrdma_del_mmap(pd->uctx, dpp_db, PAGE_SIZE);
  636. usr_db = ocrdma_get_db_addr(dev, pd->id);
  637. ocrdma_del_mmap(pd->uctx, usr_db, dev->nic_info.db_page_size);
  638. if (is_ucontext_pd(uctx, pd)) {
  639. ocrdma_release_ucontext_pd(uctx);
  640. return status;
  641. }
  642. }
  643. status = _ocrdma_dealloc_pd(dev, pd);
  644. return status;
  645. }
  646. static int ocrdma_alloc_lkey(struct ocrdma_dev *dev, struct ocrdma_mr *mr,
  647. u32 pdid, int acc, u32 num_pbls, u32 addr_check)
  648. {
  649. int status;
  650. mr->hwmr.fr_mr = 0;
  651. mr->hwmr.local_rd = 1;
  652. mr->hwmr.remote_rd = (acc & IB_ACCESS_REMOTE_READ) ? 1 : 0;
  653. mr->hwmr.remote_wr = (acc & IB_ACCESS_REMOTE_WRITE) ? 1 : 0;
  654. mr->hwmr.local_wr = (acc & IB_ACCESS_LOCAL_WRITE) ? 1 : 0;
  655. mr->hwmr.mw_bind = (acc & IB_ACCESS_MW_BIND) ? 1 : 0;
  656. mr->hwmr.remote_atomic = (acc & IB_ACCESS_REMOTE_ATOMIC) ? 1 : 0;
  657. mr->hwmr.num_pbls = num_pbls;
  658. status = ocrdma_mbx_alloc_lkey(dev, &mr->hwmr, pdid, addr_check);
  659. if (status)
  660. return status;
  661. mr->ibmr.lkey = mr->hwmr.lkey;
  662. if (mr->hwmr.remote_wr || mr->hwmr.remote_rd)
  663. mr->ibmr.rkey = mr->hwmr.lkey;
  664. return 0;
  665. }
  666. struct ib_mr *ocrdma_get_dma_mr(struct ib_pd *ibpd, int acc)
  667. {
  668. int status;
  669. struct ocrdma_mr *mr;
  670. struct ocrdma_pd *pd = get_ocrdma_pd(ibpd);
  671. struct ocrdma_dev *dev = get_ocrdma_dev(ibpd->device);
  672. if (acc & IB_ACCESS_REMOTE_WRITE && !(acc & IB_ACCESS_LOCAL_WRITE)) {
  673. pr_err("%s err, invalid access rights\n", __func__);
  674. return ERR_PTR(-EINVAL);
  675. }
  676. mr = kzalloc(sizeof(*mr), GFP_KERNEL);
  677. if (!mr)
  678. return ERR_PTR(-ENOMEM);
  679. status = ocrdma_alloc_lkey(dev, mr, pd->id, acc, 0,
  680. OCRDMA_ADDR_CHECK_DISABLE);
  681. if (status) {
  682. kfree(mr);
  683. return ERR_PTR(status);
  684. }
  685. return &mr->ibmr;
  686. }
  687. static void ocrdma_free_mr_pbl_tbl(struct ocrdma_dev *dev,
  688. struct ocrdma_hw_mr *mr)
  689. {
  690. struct pci_dev *pdev = dev->nic_info.pdev;
  691. int i = 0;
  692. if (mr->pbl_table) {
  693. for (i = 0; i < mr->num_pbls; i++) {
  694. if (!mr->pbl_table[i].va)
  695. continue;
  696. dma_free_coherent(&pdev->dev, mr->pbl_size,
  697. mr->pbl_table[i].va,
  698. mr->pbl_table[i].pa);
  699. }
  700. kfree(mr->pbl_table);
  701. mr->pbl_table = NULL;
  702. }
  703. }
  704. static int ocrdma_get_pbl_info(struct ocrdma_dev *dev, struct ocrdma_mr *mr,
  705. u32 num_pbes)
  706. {
  707. u32 num_pbls = 0;
  708. u32 idx = 0;
  709. int status = 0;
  710. u32 pbl_size;
  711. do {
  712. pbl_size = OCRDMA_MIN_HPAGE_SIZE * (1 << idx);
  713. if (pbl_size > MAX_OCRDMA_PBL_SIZE) {
  714. status = -EFAULT;
  715. break;
  716. }
  717. num_pbls = roundup(num_pbes, (pbl_size / sizeof(u64)));
  718. num_pbls = num_pbls / (pbl_size / sizeof(u64));
  719. idx++;
  720. } while (num_pbls >= dev->attr.max_num_mr_pbl);
  721. mr->hwmr.num_pbes = num_pbes;
  722. mr->hwmr.num_pbls = num_pbls;
  723. mr->hwmr.pbl_size = pbl_size;
  724. return status;
  725. }
  726. static int ocrdma_build_pbl_tbl(struct ocrdma_dev *dev, struct ocrdma_hw_mr *mr)
  727. {
  728. int status = 0;
  729. int i;
  730. u32 dma_len = mr->pbl_size;
  731. struct pci_dev *pdev = dev->nic_info.pdev;
  732. void *va;
  733. dma_addr_t pa;
  734. mr->pbl_table = kzalloc(sizeof(struct ocrdma_pbl) *
  735. mr->num_pbls, GFP_KERNEL);
  736. if (!mr->pbl_table)
  737. return -ENOMEM;
  738. for (i = 0; i < mr->num_pbls; i++) {
  739. va = dma_zalloc_coherent(&pdev->dev, dma_len, &pa, GFP_KERNEL);
  740. if (!va) {
  741. ocrdma_free_mr_pbl_tbl(dev, mr);
  742. status = -ENOMEM;
  743. break;
  744. }
  745. mr->pbl_table[i].va = va;
  746. mr->pbl_table[i].pa = pa;
  747. }
  748. return status;
  749. }
  750. static void build_user_pbes(struct ocrdma_dev *dev, struct ocrdma_mr *mr,
  751. u32 num_pbes)
  752. {
  753. struct ocrdma_pbe *pbe;
  754. struct scatterlist *sg;
  755. struct ocrdma_pbl *pbl_tbl = mr->hwmr.pbl_table;
  756. struct ib_umem *umem = mr->umem;
  757. int shift, pg_cnt, pages, pbe_cnt, entry, total_num_pbes = 0;
  758. if (!mr->hwmr.num_pbes)
  759. return;
  760. pbe = (struct ocrdma_pbe *)pbl_tbl->va;
  761. pbe_cnt = 0;
  762. shift = umem->page_shift;
  763. for_each_sg(umem->sg_head.sgl, sg, umem->nmap, entry) {
  764. pages = sg_dma_len(sg) >> shift;
  765. for (pg_cnt = 0; pg_cnt < pages; pg_cnt++) {
  766. /* store the page address in pbe */
  767. pbe->pa_lo =
  768. cpu_to_le32(sg_dma_address(sg) +
  769. (pg_cnt << shift));
  770. pbe->pa_hi =
  771. cpu_to_le32(upper_32_bits(sg_dma_address(sg) +
  772. (pg_cnt << shift)));
  773. pbe_cnt += 1;
  774. total_num_pbes += 1;
  775. pbe++;
  776. /* if done building pbes, issue the mbx cmd. */
  777. if (total_num_pbes == num_pbes)
  778. return;
  779. /* if the given pbl is full storing the pbes,
  780. * move to next pbl.
  781. */
  782. if (pbe_cnt ==
  783. (mr->hwmr.pbl_size / sizeof(u64))) {
  784. pbl_tbl++;
  785. pbe = (struct ocrdma_pbe *)pbl_tbl->va;
  786. pbe_cnt = 0;
  787. }
  788. }
  789. }
  790. }
  791. struct ib_mr *ocrdma_reg_user_mr(struct ib_pd *ibpd, u64 start, u64 len,
  792. u64 usr_addr, int acc, struct ib_udata *udata)
  793. {
  794. int status = -ENOMEM;
  795. struct ocrdma_dev *dev = get_ocrdma_dev(ibpd->device);
  796. struct ocrdma_mr *mr;
  797. struct ocrdma_pd *pd;
  798. u32 num_pbes;
  799. pd = get_ocrdma_pd(ibpd);
  800. if (acc & IB_ACCESS_REMOTE_WRITE && !(acc & IB_ACCESS_LOCAL_WRITE))
  801. return ERR_PTR(-EINVAL);
  802. mr = kzalloc(sizeof(*mr), GFP_KERNEL);
  803. if (!mr)
  804. return ERR_PTR(status);
  805. mr->umem = ib_umem_get(ibpd->uobject->context, start, len, acc, 0);
  806. if (IS_ERR(mr->umem)) {
  807. status = -EFAULT;
  808. goto umem_err;
  809. }
  810. num_pbes = ib_umem_page_count(mr->umem);
  811. status = ocrdma_get_pbl_info(dev, mr, num_pbes);
  812. if (status)
  813. goto umem_err;
  814. mr->hwmr.pbe_size = BIT(mr->umem->page_shift);
  815. mr->hwmr.fbo = ib_umem_offset(mr->umem);
  816. mr->hwmr.va = usr_addr;
  817. mr->hwmr.len = len;
  818. mr->hwmr.remote_wr = (acc & IB_ACCESS_REMOTE_WRITE) ? 1 : 0;
  819. mr->hwmr.remote_rd = (acc & IB_ACCESS_REMOTE_READ) ? 1 : 0;
  820. mr->hwmr.local_wr = (acc & IB_ACCESS_LOCAL_WRITE) ? 1 : 0;
  821. mr->hwmr.local_rd = 1;
  822. mr->hwmr.remote_atomic = (acc & IB_ACCESS_REMOTE_ATOMIC) ? 1 : 0;
  823. status = ocrdma_build_pbl_tbl(dev, &mr->hwmr);
  824. if (status)
  825. goto umem_err;
  826. build_user_pbes(dev, mr, num_pbes);
  827. status = ocrdma_reg_mr(dev, &mr->hwmr, pd->id, acc);
  828. if (status)
  829. goto mbx_err;
  830. mr->ibmr.lkey = mr->hwmr.lkey;
  831. if (mr->hwmr.remote_wr || mr->hwmr.remote_rd)
  832. mr->ibmr.rkey = mr->hwmr.lkey;
  833. return &mr->ibmr;
  834. mbx_err:
  835. ocrdma_free_mr_pbl_tbl(dev, &mr->hwmr);
  836. umem_err:
  837. kfree(mr);
  838. return ERR_PTR(status);
  839. }
  840. int ocrdma_dereg_mr(struct ib_mr *ib_mr)
  841. {
  842. struct ocrdma_mr *mr = get_ocrdma_mr(ib_mr);
  843. struct ocrdma_dev *dev = get_ocrdma_dev(ib_mr->device);
  844. (void) ocrdma_mbx_dealloc_lkey(dev, mr->hwmr.fr_mr, mr->hwmr.lkey);
  845. kfree(mr->pages);
  846. ocrdma_free_mr_pbl_tbl(dev, &mr->hwmr);
  847. /* it could be user registered memory. */
  848. if (mr->umem)
  849. ib_umem_release(mr->umem);
  850. kfree(mr);
  851. /* Don't stop cleanup, in case FW is unresponsive */
  852. if (dev->mqe_ctx.fw_error_state) {
  853. pr_err("%s(%d) fw not responding.\n",
  854. __func__, dev->id);
  855. }
  856. return 0;
  857. }
  858. static int ocrdma_copy_cq_uresp(struct ocrdma_dev *dev, struct ocrdma_cq *cq,
  859. struct ib_udata *udata,
  860. struct ib_ucontext *ib_ctx)
  861. {
  862. int status;
  863. struct ocrdma_ucontext *uctx = get_ocrdma_ucontext(ib_ctx);
  864. struct ocrdma_create_cq_uresp uresp;
  865. memset(&uresp, 0, sizeof(uresp));
  866. uresp.cq_id = cq->id;
  867. uresp.page_size = PAGE_ALIGN(cq->len);
  868. uresp.num_pages = 1;
  869. uresp.max_hw_cqe = cq->max_hw_cqe;
  870. uresp.page_addr[0] = virt_to_phys(cq->va);
  871. uresp.db_page_addr = ocrdma_get_db_addr(dev, uctx->cntxt_pd->id);
  872. uresp.db_page_size = dev->nic_info.db_page_size;
  873. uresp.phase_change = cq->phase_change ? 1 : 0;
  874. status = ib_copy_to_udata(udata, &uresp, sizeof(uresp));
  875. if (status) {
  876. pr_err("%s(%d) copy error cqid=0x%x.\n",
  877. __func__, dev->id, cq->id);
  878. goto err;
  879. }
  880. status = ocrdma_add_mmap(uctx, uresp.db_page_addr, uresp.db_page_size);
  881. if (status)
  882. goto err;
  883. status = ocrdma_add_mmap(uctx, uresp.page_addr[0], uresp.page_size);
  884. if (status) {
  885. ocrdma_del_mmap(uctx, uresp.db_page_addr, uresp.db_page_size);
  886. goto err;
  887. }
  888. cq->ucontext = uctx;
  889. err:
  890. return status;
  891. }
  892. struct ib_cq *ocrdma_create_cq(struct ib_device *ibdev,
  893. const struct ib_cq_init_attr *attr,
  894. struct ib_ucontext *ib_ctx,
  895. struct ib_udata *udata)
  896. {
  897. int entries = attr->cqe;
  898. struct ocrdma_cq *cq;
  899. struct ocrdma_dev *dev = get_ocrdma_dev(ibdev);
  900. struct ocrdma_ucontext *uctx = NULL;
  901. u16 pd_id = 0;
  902. int status;
  903. struct ocrdma_create_cq_ureq ureq;
  904. if (attr->flags)
  905. return ERR_PTR(-EINVAL);
  906. if (udata) {
  907. if (ib_copy_from_udata(&ureq, udata, sizeof(ureq)))
  908. return ERR_PTR(-EFAULT);
  909. } else
  910. ureq.dpp_cq = 0;
  911. cq = kzalloc(sizeof(*cq), GFP_KERNEL);
  912. if (!cq)
  913. return ERR_PTR(-ENOMEM);
  914. spin_lock_init(&cq->cq_lock);
  915. spin_lock_init(&cq->comp_handler_lock);
  916. INIT_LIST_HEAD(&cq->sq_head);
  917. INIT_LIST_HEAD(&cq->rq_head);
  918. if (ib_ctx) {
  919. uctx = get_ocrdma_ucontext(ib_ctx);
  920. pd_id = uctx->cntxt_pd->id;
  921. }
  922. status = ocrdma_mbx_create_cq(dev, cq, entries, ureq.dpp_cq, pd_id);
  923. if (status) {
  924. kfree(cq);
  925. return ERR_PTR(status);
  926. }
  927. if (ib_ctx) {
  928. status = ocrdma_copy_cq_uresp(dev, cq, udata, ib_ctx);
  929. if (status)
  930. goto ctx_err;
  931. }
  932. cq->phase = OCRDMA_CQE_VALID;
  933. dev->cq_tbl[cq->id] = cq;
  934. return &cq->ibcq;
  935. ctx_err:
  936. ocrdma_mbx_destroy_cq(dev, cq);
  937. kfree(cq);
  938. return ERR_PTR(status);
  939. }
  940. int ocrdma_resize_cq(struct ib_cq *ibcq, int new_cnt,
  941. struct ib_udata *udata)
  942. {
  943. int status = 0;
  944. struct ocrdma_cq *cq = get_ocrdma_cq(ibcq);
  945. if (new_cnt < 1 || new_cnt > cq->max_hw_cqe) {
  946. status = -EINVAL;
  947. return status;
  948. }
  949. ibcq->cqe = new_cnt;
  950. return status;
  951. }
  952. static void ocrdma_flush_cq(struct ocrdma_cq *cq)
  953. {
  954. int cqe_cnt;
  955. int valid_count = 0;
  956. unsigned long flags;
  957. struct ocrdma_dev *dev = get_ocrdma_dev(cq->ibcq.device);
  958. struct ocrdma_cqe *cqe = NULL;
  959. cqe = cq->va;
  960. cqe_cnt = cq->cqe_cnt;
  961. /* Last irq might have scheduled a polling thread
  962. * sync-up with it before hard flushing.
  963. */
  964. spin_lock_irqsave(&cq->cq_lock, flags);
  965. while (cqe_cnt) {
  966. if (is_cqe_valid(cq, cqe))
  967. valid_count++;
  968. cqe++;
  969. cqe_cnt--;
  970. }
  971. ocrdma_ring_cq_db(dev, cq->id, false, false, valid_count);
  972. spin_unlock_irqrestore(&cq->cq_lock, flags);
  973. }
  974. int ocrdma_destroy_cq(struct ib_cq *ibcq)
  975. {
  976. struct ocrdma_cq *cq = get_ocrdma_cq(ibcq);
  977. struct ocrdma_eq *eq = NULL;
  978. struct ocrdma_dev *dev = get_ocrdma_dev(ibcq->device);
  979. int pdid = 0;
  980. u32 irq, indx;
  981. dev->cq_tbl[cq->id] = NULL;
  982. indx = ocrdma_get_eq_table_index(dev, cq->eqn);
  983. BUG_ON(indx == -EINVAL);
  984. eq = &dev->eq_tbl[indx];
  985. irq = ocrdma_get_irq(dev, eq);
  986. synchronize_irq(irq);
  987. ocrdma_flush_cq(cq);
  988. (void)ocrdma_mbx_destroy_cq(dev, cq);
  989. if (cq->ucontext) {
  990. pdid = cq->ucontext->cntxt_pd->id;
  991. ocrdma_del_mmap(cq->ucontext, (u64) cq->pa,
  992. PAGE_ALIGN(cq->len));
  993. ocrdma_del_mmap(cq->ucontext,
  994. ocrdma_get_db_addr(dev, pdid),
  995. dev->nic_info.db_page_size);
  996. }
  997. kfree(cq);
  998. return 0;
  999. }
  1000. static int ocrdma_add_qpn_map(struct ocrdma_dev *dev, struct ocrdma_qp *qp)
  1001. {
  1002. int status = -EINVAL;
  1003. if (qp->id < OCRDMA_MAX_QP && dev->qp_tbl[qp->id] == NULL) {
  1004. dev->qp_tbl[qp->id] = qp;
  1005. status = 0;
  1006. }
  1007. return status;
  1008. }
  1009. static void ocrdma_del_qpn_map(struct ocrdma_dev *dev, struct ocrdma_qp *qp)
  1010. {
  1011. dev->qp_tbl[qp->id] = NULL;
  1012. }
  1013. static int ocrdma_check_qp_params(struct ib_pd *ibpd, struct ocrdma_dev *dev,
  1014. struct ib_qp_init_attr *attrs)
  1015. {
  1016. if ((attrs->qp_type != IB_QPT_GSI) &&
  1017. (attrs->qp_type != IB_QPT_RC) &&
  1018. (attrs->qp_type != IB_QPT_UC) &&
  1019. (attrs->qp_type != IB_QPT_UD)) {
  1020. pr_err("%s(%d) unsupported qp type=0x%x requested\n",
  1021. __func__, dev->id, attrs->qp_type);
  1022. return -EINVAL;
  1023. }
  1024. /* Skip the check for QP1 to support CM size of 128 */
  1025. if ((attrs->qp_type != IB_QPT_GSI) &&
  1026. (attrs->cap.max_send_wr > dev->attr.max_wqe)) {
  1027. pr_err("%s(%d) unsupported send_wr=0x%x requested\n",
  1028. __func__, dev->id, attrs->cap.max_send_wr);
  1029. pr_err("%s(%d) supported send_wr=0x%x\n",
  1030. __func__, dev->id, dev->attr.max_wqe);
  1031. return -EINVAL;
  1032. }
  1033. if (!attrs->srq && (attrs->cap.max_recv_wr > dev->attr.max_rqe)) {
  1034. pr_err("%s(%d) unsupported recv_wr=0x%x requested\n",
  1035. __func__, dev->id, attrs->cap.max_recv_wr);
  1036. pr_err("%s(%d) supported recv_wr=0x%x\n",
  1037. __func__, dev->id, dev->attr.max_rqe);
  1038. return -EINVAL;
  1039. }
  1040. if (attrs->cap.max_inline_data > dev->attr.max_inline_data) {
  1041. pr_err("%s(%d) unsupported inline data size=0x%x requested\n",
  1042. __func__, dev->id, attrs->cap.max_inline_data);
  1043. pr_err("%s(%d) supported inline data size=0x%x\n",
  1044. __func__, dev->id, dev->attr.max_inline_data);
  1045. return -EINVAL;
  1046. }
  1047. if (attrs->cap.max_send_sge > dev->attr.max_send_sge) {
  1048. pr_err("%s(%d) unsupported send_sge=0x%x requested\n",
  1049. __func__, dev->id, attrs->cap.max_send_sge);
  1050. pr_err("%s(%d) supported send_sge=0x%x\n",
  1051. __func__, dev->id, dev->attr.max_send_sge);
  1052. return -EINVAL;
  1053. }
  1054. if (attrs->cap.max_recv_sge > dev->attr.max_recv_sge) {
  1055. pr_err("%s(%d) unsupported recv_sge=0x%x requested\n",
  1056. __func__, dev->id, attrs->cap.max_recv_sge);
  1057. pr_err("%s(%d) supported recv_sge=0x%x\n",
  1058. __func__, dev->id, dev->attr.max_recv_sge);
  1059. return -EINVAL;
  1060. }
  1061. /* unprivileged user space cannot create special QP */
  1062. if (ibpd->uobject && attrs->qp_type == IB_QPT_GSI) {
  1063. pr_err
  1064. ("%s(%d) Userspace can't create special QPs of type=0x%x\n",
  1065. __func__, dev->id, attrs->qp_type);
  1066. return -EINVAL;
  1067. }
  1068. /* allow creating only one GSI type of QP */
  1069. if (attrs->qp_type == IB_QPT_GSI && dev->gsi_qp_created) {
  1070. pr_err("%s(%d) GSI special QPs already created.\n",
  1071. __func__, dev->id);
  1072. return -EINVAL;
  1073. }
  1074. /* verify consumer QPs are not trying to use GSI QP's CQ */
  1075. if ((attrs->qp_type != IB_QPT_GSI) && (dev->gsi_qp_created)) {
  1076. if ((dev->gsi_sqcq == get_ocrdma_cq(attrs->send_cq)) ||
  1077. (dev->gsi_rqcq == get_ocrdma_cq(attrs->recv_cq))) {
  1078. pr_err("%s(%d) Consumer QP cannot use GSI CQs.\n",
  1079. __func__, dev->id);
  1080. return -EINVAL;
  1081. }
  1082. }
  1083. return 0;
  1084. }
  1085. static int ocrdma_copy_qp_uresp(struct ocrdma_qp *qp,
  1086. struct ib_udata *udata, int dpp_offset,
  1087. int dpp_credit_lmt, int srq)
  1088. {
  1089. int status;
  1090. u64 usr_db;
  1091. struct ocrdma_create_qp_uresp uresp;
  1092. struct ocrdma_pd *pd = qp->pd;
  1093. struct ocrdma_dev *dev = get_ocrdma_dev(pd->ibpd.device);
  1094. memset(&uresp, 0, sizeof(uresp));
  1095. usr_db = dev->nic_info.unmapped_db +
  1096. (pd->id * dev->nic_info.db_page_size);
  1097. uresp.qp_id = qp->id;
  1098. uresp.sq_dbid = qp->sq.dbid;
  1099. uresp.num_sq_pages = 1;
  1100. uresp.sq_page_size = PAGE_ALIGN(qp->sq.len);
  1101. uresp.sq_page_addr[0] = virt_to_phys(qp->sq.va);
  1102. uresp.num_wqe_allocated = qp->sq.max_cnt;
  1103. if (!srq) {
  1104. uresp.rq_dbid = qp->rq.dbid;
  1105. uresp.num_rq_pages = 1;
  1106. uresp.rq_page_size = PAGE_ALIGN(qp->rq.len);
  1107. uresp.rq_page_addr[0] = virt_to_phys(qp->rq.va);
  1108. uresp.num_rqe_allocated = qp->rq.max_cnt;
  1109. }
  1110. uresp.db_page_addr = usr_db;
  1111. uresp.db_page_size = dev->nic_info.db_page_size;
  1112. uresp.db_sq_offset = OCRDMA_DB_GEN2_SQ_OFFSET;
  1113. uresp.db_rq_offset = OCRDMA_DB_GEN2_RQ_OFFSET;
  1114. uresp.db_shift = OCRDMA_DB_RQ_SHIFT;
  1115. if (qp->dpp_enabled) {
  1116. uresp.dpp_credit = dpp_credit_lmt;
  1117. uresp.dpp_offset = dpp_offset;
  1118. }
  1119. status = ib_copy_to_udata(udata, &uresp, sizeof(uresp));
  1120. if (status) {
  1121. pr_err("%s(%d) user copy error.\n", __func__, dev->id);
  1122. goto err;
  1123. }
  1124. status = ocrdma_add_mmap(pd->uctx, uresp.sq_page_addr[0],
  1125. uresp.sq_page_size);
  1126. if (status)
  1127. goto err;
  1128. if (!srq) {
  1129. status = ocrdma_add_mmap(pd->uctx, uresp.rq_page_addr[0],
  1130. uresp.rq_page_size);
  1131. if (status)
  1132. goto rq_map_err;
  1133. }
  1134. return status;
  1135. rq_map_err:
  1136. ocrdma_del_mmap(pd->uctx, uresp.sq_page_addr[0], uresp.sq_page_size);
  1137. err:
  1138. return status;
  1139. }
  1140. static void ocrdma_set_qp_db(struct ocrdma_dev *dev, struct ocrdma_qp *qp,
  1141. struct ocrdma_pd *pd)
  1142. {
  1143. if (ocrdma_get_asic_type(dev) == OCRDMA_ASIC_GEN_SKH_R) {
  1144. qp->sq_db = dev->nic_info.db +
  1145. (pd->id * dev->nic_info.db_page_size) +
  1146. OCRDMA_DB_GEN2_SQ_OFFSET;
  1147. qp->rq_db = dev->nic_info.db +
  1148. (pd->id * dev->nic_info.db_page_size) +
  1149. OCRDMA_DB_GEN2_RQ_OFFSET;
  1150. } else {
  1151. qp->sq_db = dev->nic_info.db +
  1152. (pd->id * dev->nic_info.db_page_size) +
  1153. OCRDMA_DB_SQ_OFFSET;
  1154. qp->rq_db = dev->nic_info.db +
  1155. (pd->id * dev->nic_info.db_page_size) +
  1156. OCRDMA_DB_RQ_OFFSET;
  1157. }
  1158. }
  1159. static int ocrdma_alloc_wr_id_tbl(struct ocrdma_qp *qp)
  1160. {
  1161. qp->wqe_wr_id_tbl =
  1162. kzalloc(sizeof(*(qp->wqe_wr_id_tbl)) * qp->sq.max_cnt,
  1163. GFP_KERNEL);
  1164. if (qp->wqe_wr_id_tbl == NULL)
  1165. return -ENOMEM;
  1166. qp->rqe_wr_id_tbl =
  1167. kzalloc(sizeof(u64) * qp->rq.max_cnt, GFP_KERNEL);
  1168. if (qp->rqe_wr_id_tbl == NULL)
  1169. return -ENOMEM;
  1170. return 0;
  1171. }
  1172. static void ocrdma_set_qp_init_params(struct ocrdma_qp *qp,
  1173. struct ocrdma_pd *pd,
  1174. struct ib_qp_init_attr *attrs)
  1175. {
  1176. qp->pd = pd;
  1177. spin_lock_init(&qp->q_lock);
  1178. INIT_LIST_HEAD(&qp->sq_entry);
  1179. INIT_LIST_HEAD(&qp->rq_entry);
  1180. qp->qp_type = attrs->qp_type;
  1181. qp->cap_flags = OCRDMA_QP_INB_RD | OCRDMA_QP_INB_WR;
  1182. qp->max_inline_data = attrs->cap.max_inline_data;
  1183. qp->sq.max_sges = attrs->cap.max_send_sge;
  1184. qp->rq.max_sges = attrs->cap.max_recv_sge;
  1185. qp->state = OCRDMA_QPS_RST;
  1186. qp->signaled = (attrs->sq_sig_type == IB_SIGNAL_ALL_WR) ? true : false;
  1187. }
  1188. static void ocrdma_store_gsi_qp_cq(struct ocrdma_dev *dev,
  1189. struct ib_qp_init_attr *attrs)
  1190. {
  1191. if (attrs->qp_type == IB_QPT_GSI) {
  1192. dev->gsi_qp_created = 1;
  1193. dev->gsi_sqcq = get_ocrdma_cq(attrs->send_cq);
  1194. dev->gsi_rqcq = get_ocrdma_cq(attrs->recv_cq);
  1195. }
  1196. }
  1197. struct ib_qp *ocrdma_create_qp(struct ib_pd *ibpd,
  1198. struct ib_qp_init_attr *attrs,
  1199. struct ib_udata *udata)
  1200. {
  1201. int status;
  1202. struct ocrdma_pd *pd = get_ocrdma_pd(ibpd);
  1203. struct ocrdma_qp *qp;
  1204. struct ocrdma_dev *dev = get_ocrdma_dev(ibpd->device);
  1205. struct ocrdma_create_qp_ureq ureq;
  1206. u16 dpp_credit_lmt, dpp_offset;
  1207. status = ocrdma_check_qp_params(ibpd, dev, attrs);
  1208. if (status)
  1209. goto gen_err;
  1210. memset(&ureq, 0, sizeof(ureq));
  1211. if (udata) {
  1212. if (ib_copy_from_udata(&ureq, udata, sizeof(ureq)))
  1213. return ERR_PTR(-EFAULT);
  1214. }
  1215. qp = kzalloc(sizeof(*qp), GFP_KERNEL);
  1216. if (!qp) {
  1217. status = -ENOMEM;
  1218. goto gen_err;
  1219. }
  1220. ocrdma_set_qp_init_params(qp, pd, attrs);
  1221. if (udata == NULL)
  1222. qp->cap_flags |= (OCRDMA_QP_MW_BIND | OCRDMA_QP_LKEY0 |
  1223. OCRDMA_QP_FAST_REG);
  1224. mutex_lock(&dev->dev_lock);
  1225. status = ocrdma_mbx_create_qp(qp, attrs, ureq.enable_dpp_cq,
  1226. ureq.dpp_cq_id,
  1227. &dpp_offset, &dpp_credit_lmt);
  1228. if (status)
  1229. goto mbx_err;
  1230. /* user space QP's wr_id table are managed in library */
  1231. if (udata == NULL) {
  1232. status = ocrdma_alloc_wr_id_tbl(qp);
  1233. if (status)
  1234. goto map_err;
  1235. }
  1236. status = ocrdma_add_qpn_map(dev, qp);
  1237. if (status)
  1238. goto map_err;
  1239. ocrdma_set_qp_db(dev, qp, pd);
  1240. if (udata) {
  1241. status = ocrdma_copy_qp_uresp(qp, udata, dpp_offset,
  1242. dpp_credit_lmt,
  1243. (attrs->srq != NULL));
  1244. if (status)
  1245. goto cpy_err;
  1246. }
  1247. ocrdma_store_gsi_qp_cq(dev, attrs);
  1248. qp->ibqp.qp_num = qp->id;
  1249. mutex_unlock(&dev->dev_lock);
  1250. return &qp->ibqp;
  1251. cpy_err:
  1252. ocrdma_del_qpn_map(dev, qp);
  1253. map_err:
  1254. ocrdma_mbx_destroy_qp(dev, qp);
  1255. mbx_err:
  1256. mutex_unlock(&dev->dev_lock);
  1257. kfree(qp->wqe_wr_id_tbl);
  1258. kfree(qp->rqe_wr_id_tbl);
  1259. kfree(qp);
  1260. pr_err("%s(%d) error=%d\n", __func__, dev->id, status);
  1261. gen_err:
  1262. return ERR_PTR(status);
  1263. }
  1264. int _ocrdma_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
  1265. int attr_mask)
  1266. {
  1267. int status = 0;
  1268. struct ocrdma_qp *qp;
  1269. struct ocrdma_dev *dev;
  1270. enum ib_qp_state old_qps;
  1271. qp = get_ocrdma_qp(ibqp);
  1272. dev = get_ocrdma_dev(ibqp->device);
  1273. if (attr_mask & IB_QP_STATE)
  1274. status = ocrdma_qp_state_change(qp, attr->qp_state, &old_qps);
  1275. /* if new and previous states are same hw doesn't need to
  1276. * know about it.
  1277. */
  1278. if (status < 0)
  1279. return status;
  1280. return ocrdma_mbx_modify_qp(dev, qp, attr, attr_mask);
  1281. }
  1282. int ocrdma_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
  1283. int attr_mask, struct ib_udata *udata)
  1284. {
  1285. unsigned long flags;
  1286. int status = -EINVAL;
  1287. struct ocrdma_qp *qp;
  1288. struct ocrdma_dev *dev;
  1289. enum ib_qp_state old_qps, new_qps;
  1290. qp = get_ocrdma_qp(ibqp);
  1291. dev = get_ocrdma_dev(ibqp->device);
  1292. /* syncronize with multiple context trying to change, retrive qps */
  1293. mutex_lock(&dev->dev_lock);
  1294. /* syncronize with wqe, rqe posting and cqe processing contexts */
  1295. spin_lock_irqsave(&qp->q_lock, flags);
  1296. old_qps = get_ibqp_state(qp->state);
  1297. if (attr_mask & IB_QP_STATE)
  1298. new_qps = attr->qp_state;
  1299. else
  1300. new_qps = old_qps;
  1301. spin_unlock_irqrestore(&qp->q_lock, flags);
  1302. if (!ib_modify_qp_is_ok(old_qps, new_qps, ibqp->qp_type, attr_mask,
  1303. IB_LINK_LAYER_ETHERNET)) {
  1304. pr_err("%s(%d) invalid attribute mask=0x%x specified for\n"
  1305. "qpn=0x%x of type=0x%x old_qps=0x%x, new_qps=0x%x\n",
  1306. __func__, dev->id, attr_mask, qp->id, ibqp->qp_type,
  1307. old_qps, new_qps);
  1308. goto param_err;
  1309. }
  1310. status = _ocrdma_modify_qp(ibqp, attr, attr_mask);
  1311. if (status > 0)
  1312. status = 0;
  1313. param_err:
  1314. mutex_unlock(&dev->dev_lock);
  1315. return status;
  1316. }
  1317. static enum ib_mtu ocrdma_mtu_int_to_enum(u16 mtu)
  1318. {
  1319. switch (mtu) {
  1320. case 256:
  1321. return IB_MTU_256;
  1322. case 512:
  1323. return IB_MTU_512;
  1324. case 1024:
  1325. return IB_MTU_1024;
  1326. case 2048:
  1327. return IB_MTU_2048;
  1328. case 4096:
  1329. return IB_MTU_4096;
  1330. default:
  1331. return IB_MTU_1024;
  1332. }
  1333. }
  1334. static int ocrdma_to_ib_qp_acc_flags(int qp_cap_flags)
  1335. {
  1336. int ib_qp_acc_flags = 0;
  1337. if (qp_cap_flags & OCRDMA_QP_INB_WR)
  1338. ib_qp_acc_flags |= IB_ACCESS_REMOTE_WRITE;
  1339. if (qp_cap_flags & OCRDMA_QP_INB_RD)
  1340. ib_qp_acc_flags |= IB_ACCESS_LOCAL_WRITE;
  1341. return ib_qp_acc_flags;
  1342. }
  1343. int ocrdma_query_qp(struct ib_qp *ibqp,
  1344. struct ib_qp_attr *qp_attr,
  1345. int attr_mask, struct ib_qp_init_attr *qp_init_attr)
  1346. {
  1347. int status;
  1348. u32 qp_state;
  1349. struct ocrdma_qp_params params;
  1350. struct ocrdma_qp *qp = get_ocrdma_qp(ibqp);
  1351. struct ocrdma_dev *dev = get_ocrdma_dev(ibqp->device);
  1352. memset(&params, 0, sizeof(params));
  1353. mutex_lock(&dev->dev_lock);
  1354. status = ocrdma_mbx_query_qp(dev, qp, &params);
  1355. mutex_unlock(&dev->dev_lock);
  1356. if (status)
  1357. goto mbx_err;
  1358. if (qp->qp_type == IB_QPT_UD)
  1359. qp_attr->qkey = params.qkey;
  1360. qp_attr->path_mtu =
  1361. ocrdma_mtu_int_to_enum(params.path_mtu_pkey_indx &
  1362. OCRDMA_QP_PARAMS_PATH_MTU_MASK) >>
  1363. OCRDMA_QP_PARAMS_PATH_MTU_SHIFT;
  1364. qp_attr->path_mig_state = IB_MIG_MIGRATED;
  1365. qp_attr->rq_psn = params.hop_lmt_rq_psn & OCRDMA_QP_PARAMS_RQ_PSN_MASK;
  1366. qp_attr->sq_psn = params.tclass_sq_psn & OCRDMA_QP_PARAMS_SQ_PSN_MASK;
  1367. qp_attr->dest_qp_num =
  1368. params.ack_to_rnr_rtc_dest_qpn & OCRDMA_QP_PARAMS_DEST_QPN_MASK;
  1369. qp_attr->qp_access_flags = ocrdma_to_ib_qp_acc_flags(qp->cap_flags);
  1370. qp_attr->cap.max_send_wr = qp->sq.max_cnt - 1;
  1371. qp_attr->cap.max_recv_wr = qp->rq.max_cnt - 1;
  1372. qp_attr->cap.max_send_sge = qp->sq.max_sges;
  1373. qp_attr->cap.max_recv_sge = qp->rq.max_sges;
  1374. qp_attr->cap.max_inline_data = qp->max_inline_data;
  1375. qp_init_attr->cap = qp_attr->cap;
  1376. qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE;
  1377. rdma_ah_set_grh(&qp_attr->ah_attr, NULL,
  1378. params.rnt_rc_sl_fl &
  1379. OCRDMA_QP_PARAMS_FLOW_LABEL_MASK,
  1380. qp->sgid_idx,
  1381. (params.hop_lmt_rq_psn &
  1382. OCRDMA_QP_PARAMS_HOP_LMT_MASK) >>
  1383. OCRDMA_QP_PARAMS_HOP_LMT_SHIFT,
  1384. (params.tclass_sq_psn &
  1385. OCRDMA_QP_PARAMS_TCLASS_MASK) >>
  1386. OCRDMA_QP_PARAMS_TCLASS_SHIFT);
  1387. rdma_ah_set_dgid_raw(&qp_attr->ah_attr, &params.dgid[0]);
  1388. rdma_ah_set_port_num(&qp_attr->ah_attr, 1);
  1389. rdma_ah_set_sl(&qp_attr->ah_attr, (params.rnt_rc_sl_fl &
  1390. OCRDMA_QP_PARAMS_SL_MASK) >>
  1391. OCRDMA_QP_PARAMS_SL_SHIFT);
  1392. qp_attr->timeout = (params.ack_to_rnr_rtc_dest_qpn &
  1393. OCRDMA_QP_PARAMS_ACK_TIMEOUT_MASK) >>
  1394. OCRDMA_QP_PARAMS_ACK_TIMEOUT_SHIFT;
  1395. qp_attr->rnr_retry = (params.ack_to_rnr_rtc_dest_qpn &
  1396. OCRDMA_QP_PARAMS_RNR_RETRY_CNT_MASK) >>
  1397. OCRDMA_QP_PARAMS_RNR_RETRY_CNT_SHIFT;
  1398. qp_attr->retry_cnt =
  1399. (params.rnt_rc_sl_fl & OCRDMA_QP_PARAMS_RETRY_CNT_MASK) >>
  1400. OCRDMA_QP_PARAMS_RETRY_CNT_SHIFT;
  1401. qp_attr->min_rnr_timer = 0;
  1402. qp_attr->pkey_index = 0;
  1403. qp_attr->port_num = 1;
  1404. rdma_ah_set_path_bits(&qp_attr->ah_attr, 0);
  1405. rdma_ah_set_static_rate(&qp_attr->ah_attr, 0);
  1406. qp_attr->alt_pkey_index = 0;
  1407. qp_attr->alt_port_num = 0;
  1408. qp_attr->alt_timeout = 0;
  1409. memset(&qp_attr->alt_ah_attr, 0, sizeof(qp_attr->alt_ah_attr));
  1410. qp_state = (params.max_sge_recv_flags & OCRDMA_QP_PARAMS_STATE_MASK) >>
  1411. OCRDMA_QP_PARAMS_STATE_SHIFT;
  1412. qp_attr->qp_state = get_ibqp_state(qp_state);
  1413. qp_attr->cur_qp_state = qp_attr->qp_state;
  1414. qp_attr->sq_draining = (qp_state == OCRDMA_QPS_SQ_DRAINING) ? 1 : 0;
  1415. qp_attr->max_dest_rd_atomic =
  1416. params.max_ord_ird >> OCRDMA_QP_PARAMS_MAX_ORD_SHIFT;
  1417. qp_attr->max_rd_atomic =
  1418. params.max_ord_ird & OCRDMA_QP_PARAMS_MAX_IRD_MASK;
  1419. qp_attr->en_sqd_async_notify = (params.max_sge_recv_flags &
  1420. OCRDMA_QP_PARAMS_FLAGS_SQD_ASYNC) ? 1 : 0;
  1421. /* Sync driver QP state with FW */
  1422. ocrdma_qp_state_change(qp, qp_attr->qp_state, NULL);
  1423. mbx_err:
  1424. return status;
  1425. }
  1426. static void ocrdma_srq_toggle_bit(struct ocrdma_srq *srq, unsigned int idx)
  1427. {
  1428. unsigned int i = idx / 32;
  1429. u32 mask = (1U << (idx % 32));
  1430. srq->idx_bit_fields[i] ^= mask;
  1431. }
  1432. static int ocrdma_hwq_free_cnt(struct ocrdma_qp_hwq_info *q)
  1433. {
  1434. return ((q->max_wqe_idx - q->head) + q->tail) % q->max_cnt;
  1435. }
  1436. static int is_hw_sq_empty(struct ocrdma_qp *qp)
  1437. {
  1438. return (qp->sq.tail == qp->sq.head);
  1439. }
  1440. static int is_hw_rq_empty(struct ocrdma_qp *qp)
  1441. {
  1442. return (qp->rq.tail == qp->rq.head);
  1443. }
  1444. static void *ocrdma_hwq_head(struct ocrdma_qp_hwq_info *q)
  1445. {
  1446. return q->va + (q->head * q->entry_size);
  1447. }
  1448. static void *ocrdma_hwq_head_from_idx(struct ocrdma_qp_hwq_info *q,
  1449. u32 idx)
  1450. {
  1451. return q->va + (idx * q->entry_size);
  1452. }
  1453. static void ocrdma_hwq_inc_head(struct ocrdma_qp_hwq_info *q)
  1454. {
  1455. q->head = (q->head + 1) & q->max_wqe_idx;
  1456. }
  1457. static void ocrdma_hwq_inc_tail(struct ocrdma_qp_hwq_info *q)
  1458. {
  1459. q->tail = (q->tail + 1) & q->max_wqe_idx;
  1460. }
  1461. /* discard the cqe for a given QP */
  1462. static void ocrdma_discard_cqes(struct ocrdma_qp *qp, struct ocrdma_cq *cq)
  1463. {
  1464. unsigned long cq_flags;
  1465. unsigned long flags;
  1466. int discard_cnt = 0;
  1467. u32 cur_getp, stop_getp;
  1468. struct ocrdma_cqe *cqe;
  1469. u32 qpn = 0, wqe_idx = 0;
  1470. spin_lock_irqsave(&cq->cq_lock, cq_flags);
  1471. /* traverse through the CQEs in the hw CQ,
  1472. * find the matching CQE for a given qp,
  1473. * mark the matching one discarded by clearing qpn.
  1474. * ring the doorbell in the poll_cq() as
  1475. * we don't complete out of order cqe.
  1476. */
  1477. cur_getp = cq->getp;
  1478. /* find upto when do we reap the cq. */
  1479. stop_getp = cur_getp;
  1480. do {
  1481. if (is_hw_sq_empty(qp) && (!qp->srq && is_hw_rq_empty(qp)))
  1482. break;
  1483. cqe = cq->va + cur_getp;
  1484. /* if (a) done reaping whole hw cq, or
  1485. * (b) qp_xq becomes empty.
  1486. * then exit
  1487. */
  1488. qpn = cqe->cmn.qpn & OCRDMA_CQE_QPN_MASK;
  1489. /* if previously discarded cqe found, skip that too. */
  1490. /* check for matching qp */
  1491. if (qpn == 0 || qpn != qp->id)
  1492. goto skip_cqe;
  1493. if (is_cqe_for_sq(cqe)) {
  1494. ocrdma_hwq_inc_tail(&qp->sq);
  1495. } else {
  1496. if (qp->srq) {
  1497. wqe_idx = (le32_to_cpu(cqe->rq.buftag_qpn) >>
  1498. OCRDMA_CQE_BUFTAG_SHIFT) &
  1499. qp->srq->rq.max_wqe_idx;
  1500. BUG_ON(wqe_idx < 1);
  1501. spin_lock_irqsave(&qp->srq->q_lock, flags);
  1502. ocrdma_hwq_inc_tail(&qp->srq->rq);
  1503. ocrdma_srq_toggle_bit(qp->srq, wqe_idx - 1);
  1504. spin_unlock_irqrestore(&qp->srq->q_lock, flags);
  1505. } else {
  1506. ocrdma_hwq_inc_tail(&qp->rq);
  1507. }
  1508. }
  1509. /* mark cqe discarded so that it is not picked up later
  1510. * in the poll_cq().
  1511. */
  1512. discard_cnt += 1;
  1513. cqe->cmn.qpn = 0;
  1514. skip_cqe:
  1515. cur_getp = (cur_getp + 1) % cq->max_hw_cqe;
  1516. } while (cur_getp != stop_getp);
  1517. spin_unlock_irqrestore(&cq->cq_lock, cq_flags);
  1518. }
  1519. void ocrdma_del_flush_qp(struct ocrdma_qp *qp)
  1520. {
  1521. int found = false;
  1522. unsigned long flags;
  1523. struct ocrdma_dev *dev = get_ocrdma_dev(qp->ibqp.device);
  1524. /* sync with any active CQ poll */
  1525. spin_lock_irqsave(&dev->flush_q_lock, flags);
  1526. found = ocrdma_is_qp_in_sq_flushlist(qp->sq_cq, qp);
  1527. if (found)
  1528. list_del(&qp->sq_entry);
  1529. if (!qp->srq) {
  1530. found = ocrdma_is_qp_in_rq_flushlist(qp->rq_cq, qp);
  1531. if (found)
  1532. list_del(&qp->rq_entry);
  1533. }
  1534. spin_unlock_irqrestore(&dev->flush_q_lock, flags);
  1535. }
  1536. int ocrdma_destroy_qp(struct ib_qp *ibqp)
  1537. {
  1538. struct ocrdma_pd *pd;
  1539. struct ocrdma_qp *qp;
  1540. struct ocrdma_dev *dev;
  1541. struct ib_qp_attr attrs;
  1542. int attr_mask;
  1543. unsigned long flags;
  1544. qp = get_ocrdma_qp(ibqp);
  1545. dev = get_ocrdma_dev(ibqp->device);
  1546. pd = qp->pd;
  1547. /* change the QP state to ERROR */
  1548. if (qp->state != OCRDMA_QPS_RST) {
  1549. attrs.qp_state = IB_QPS_ERR;
  1550. attr_mask = IB_QP_STATE;
  1551. _ocrdma_modify_qp(ibqp, &attrs, attr_mask);
  1552. }
  1553. /* ensure that CQEs for newly created QP (whose id may be same with
  1554. * one which just getting destroyed are same), dont get
  1555. * discarded until the old CQEs are discarded.
  1556. */
  1557. mutex_lock(&dev->dev_lock);
  1558. (void) ocrdma_mbx_destroy_qp(dev, qp);
  1559. /*
  1560. * acquire CQ lock while destroy is in progress, in order to
  1561. * protect against proessing in-flight CQEs for this QP.
  1562. */
  1563. spin_lock_irqsave(&qp->sq_cq->cq_lock, flags);
  1564. if (qp->rq_cq && (qp->rq_cq != qp->sq_cq))
  1565. spin_lock(&qp->rq_cq->cq_lock);
  1566. ocrdma_del_qpn_map(dev, qp);
  1567. if (qp->rq_cq && (qp->rq_cq != qp->sq_cq))
  1568. spin_unlock(&qp->rq_cq->cq_lock);
  1569. spin_unlock_irqrestore(&qp->sq_cq->cq_lock, flags);
  1570. if (!pd->uctx) {
  1571. ocrdma_discard_cqes(qp, qp->sq_cq);
  1572. ocrdma_discard_cqes(qp, qp->rq_cq);
  1573. }
  1574. mutex_unlock(&dev->dev_lock);
  1575. if (pd->uctx) {
  1576. ocrdma_del_mmap(pd->uctx, (u64) qp->sq.pa,
  1577. PAGE_ALIGN(qp->sq.len));
  1578. if (!qp->srq)
  1579. ocrdma_del_mmap(pd->uctx, (u64) qp->rq.pa,
  1580. PAGE_ALIGN(qp->rq.len));
  1581. }
  1582. ocrdma_del_flush_qp(qp);
  1583. kfree(qp->wqe_wr_id_tbl);
  1584. kfree(qp->rqe_wr_id_tbl);
  1585. kfree(qp);
  1586. return 0;
  1587. }
  1588. static int ocrdma_copy_srq_uresp(struct ocrdma_dev *dev, struct ocrdma_srq *srq,
  1589. struct ib_udata *udata)
  1590. {
  1591. int status;
  1592. struct ocrdma_create_srq_uresp uresp;
  1593. memset(&uresp, 0, sizeof(uresp));
  1594. uresp.rq_dbid = srq->rq.dbid;
  1595. uresp.num_rq_pages = 1;
  1596. uresp.rq_page_addr[0] = virt_to_phys(srq->rq.va);
  1597. uresp.rq_page_size = srq->rq.len;
  1598. uresp.db_page_addr = dev->nic_info.unmapped_db +
  1599. (srq->pd->id * dev->nic_info.db_page_size);
  1600. uresp.db_page_size = dev->nic_info.db_page_size;
  1601. uresp.num_rqe_allocated = srq->rq.max_cnt;
  1602. if (ocrdma_get_asic_type(dev) == OCRDMA_ASIC_GEN_SKH_R) {
  1603. uresp.db_rq_offset = OCRDMA_DB_GEN2_RQ_OFFSET;
  1604. uresp.db_shift = 24;
  1605. } else {
  1606. uresp.db_rq_offset = OCRDMA_DB_RQ_OFFSET;
  1607. uresp.db_shift = 16;
  1608. }
  1609. status = ib_copy_to_udata(udata, &uresp, sizeof(uresp));
  1610. if (status)
  1611. return status;
  1612. status = ocrdma_add_mmap(srq->pd->uctx, uresp.rq_page_addr[0],
  1613. uresp.rq_page_size);
  1614. if (status)
  1615. return status;
  1616. return status;
  1617. }
  1618. struct ib_srq *ocrdma_create_srq(struct ib_pd *ibpd,
  1619. struct ib_srq_init_attr *init_attr,
  1620. struct ib_udata *udata)
  1621. {
  1622. int status = -ENOMEM;
  1623. struct ocrdma_pd *pd = get_ocrdma_pd(ibpd);
  1624. struct ocrdma_dev *dev = get_ocrdma_dev(ibpd->device);
  1625. struct ocrdma_srq *srq;
  1626. if (init_attr->attr.max_sge > dev->attr.max_recv_sge)
  1627. return ERR_PTR(-EINVAL);
  1628. if (init_attr->attr.max_wr > dev->attr.max_rqe)
  1629. return ERR_PTR(-EINVAL);
  1630. srq = kzalloc(sizeof(*srq), GFP_KERNEL);
  1631. if (!srq)
  1632. return ERR_PTR(status);
  1633. spin_lock_init(&srq->q_lock);
  1634. srq->pd = pd;
  1635. srq->db = dev->nic_info.db + (pd->id * dev->nic_info.db_page_size);
  1636. status = ocrdma_mbx_create_srq(dev, srq, init_attr, pd);
  1637. if (status)
  1638. goto err;
  1639. if (udata == NULL) {
  1640. status = -ENOMEM;
  1641. srq->rqe_wr_id_tbl = kzalloc(sizeof(u64) * srq->rq.max_cnt,
  1642. GFP_KERNEL);
  1643. if (srq->rqe_wr_id_tbl == NULL)
  1644. goto arm_err;
  1645. srq->bit_fields_len = (srq->rq.max_cnt / 32) +
  1646. (srq->rq.max_cnt % 32 ? 1 : 0);
  1647. srq->idx_bit_fields =
  1648. kmalloc(srq->bit_fields_len * sizeof(u32), GFP_KERNEL);
  1649. if (srq->idx_bit_fields == NULL)
  1650. goto arm_err;
  1651. memset(srq->idx_bit_fields, 0xff,
  1652. srq->bit_fields_len * sizeof(u32));
  1653. }
  1654. if (init_attr->attr.srq_limit) {
  1655. status = ocrdma_mbx_modify_srq(srq, &init_attr->attr);
  1656. if (status)
  1657. goto arm_err;
  1658. }
  1659. if (udata) {
  1660. status = ocrdma_copy_srq_uresp(dev, srq, udata);
  1661. if (status)
  1662. goto arm_err;
  1663. }
  1664. return &srq->ibsrq;
  1665. arm_err:
  1666. ocrdma_mbx_destroy_srq(dev, srq);
  1667. err:
  1668. kfree(srq->rqe_wr_id_tbl);
  1669. kfree(srq->idx_bit_fields);
  1670. kfree(srq);
  1671. return ERR_PTR(status);
  1672. }
  1673. int ocrdma_modify_srq(struct ib_srq *ibsrq,
  1674. struct ib_srq_attr *srq_attr,
  1675. enum ib_srq_attr_mask srq_attr_mask,
  1676. struct ib_udata *udata)
  1677. {
  1678. int status;
  1679. struct ocrdma_srq *srq;
  1680. srq = get_ocrdma_srq(ibsrq);
  1681. if (srq_attr_mask & IB_SRQ_MAX_WR)
  1682. status = -EINVAL;
  1683. else
  1684. status = ocrdma_mbx_modify_srq(srq, srq_attr);
  1685. return status;
  1686. }
  1687. int ocrdma_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr)
  1688. {
  1689. int status;
  1690. struct ocrdma_srq *srq;
  1691. srq = get_ocrdma_srq(ibsrq);
  1692. status = ocrdma_mbx_query_srq(srq, srq_attr);
  1693. return status;
  1694. }
  1695. int ocrdma_destroy_srq(struct ib_srq *ibsrq)
  1696. {
  1697. int status;
  1698. struct ocrdma_srq *srq;
  1699. struct ocrdma_dev *dev = get_ocrdma_dev(ibsrq->device);
  1700. srq = get_ocrdma_srq(ibsrq);
  1701. status = ocrdma_mbx_destroy_srq(dev, srq);
  1702. if (srq->pd->uctx)
  1703. ocrdma_del_mmap(srq->pd->uctx, (u64) srq->rq.pa,
  1704. PAGE_ALIGN(srq->rq.len));
  1705. kfree(srq->idx_bit_fields);
  1706. kfree(srq->rqe_wr_id_tbl);
  1707. kfree(srq);
  1708. return status;
  1709. }
  1710. /* unprivileged verbs and their support functions. */
  1711. static void ocrdma_build_ud_hdr(struct ocrdma_qp *qp,
  1712. struct ocrdma_hdr_wqe *hdr,
  1713. struct ib_send_wr *wr)
  1714. {
  1715. struct ocrdma_ewqe_ud_hdr *ud_hdr =
  1716. (struct ocrdma_ewqe_ud_hdr *)(hdr + 1);
  1717. struct ocrdma_ah *ah = get_ocrdma_ah(ud_wr(wr)->ah);
  1718. ud_hdr->rsvd_dest_qpn = ud_wr(wr)->remote_qpn;
  1719. if (qp->qp_type == IB_QPT_GSI)
  1720. ud_hdr->qkey = qp->qkey;
  1721. else
  1722. ud_hdr->qkey = ud_wr(wr)->remote_qkey;
  1723. ud_hdr->rsvd_ahid = ah->id;
  1724. ud_hdr->hdr_type = ah->hdr_type;
  1725. if (ah->av->valid & OCRDMA_AV_VLAN_VALID)
  1726. hdr->cw |= (OCRDMA_FLAG_AH_VLAN_PR << OCRDMA_WQE_FLAGS_SHIFT);
  1727. }
  1728. static void ocrdma_build_sges(struct ocrdma_hdr_wqe *hdr,
  1729. struct ocrdma_sge *sge, int num_sge,
  1730. struct ib_sge *sg_list)
  1731. {
  1732. int i;
  1733. for (i = 0; i < num_sge; i++) {
  1734. sge[i].lrkey = sg_list[i].lkey;
  1735. sge[i].addr_lo = sg_list[i].addr;
  1736. sge[i].addr_hi = upper_32_bits(sg_list[i].addr);
  1737. sge[i].len = sg_list[i].length;
  1738. hdr->total_len += sg_list[i].length;
  1739. }
  1740. if (num_sge == 0)
  1741. memset(sge, 0, sizeof(*sge));
  1742. }
  1743. static inline uint32_t ocrdma_sglist_len(struct ib_sge *sg_list, int num_sge)
  1744. {
  1745. uint32_t total_len = 0, i;
  1746. for (i = 0; i < num_sge; i++)
  1747. total_len += sg_list[i].length;
  1748. return total_len;
  1749. }
  1750. static int ocrdma_build_inline_sges(struct ocrdma_qp *qp,
  1751. struct ocrdma_hdr_wqe *hdr,
  1752. struct ocrdma_sge *sge,
  1753. struct ib_send_wr *wr, u32 wqe_size)
  1754. {
  1755. int i;
  1756. char *dpp_addr;
  1757. if (wr->send_flags & IB_SEND_INLINE && qp->qp_type != IB_QPT_UD) {
  1758. hdr->total_len = ocrdma_sglist_len(wr->sg_list, wr->num_sge);
  1759. if (unlikely(hdr->total_len > qp->max_inline_data)) {
  1760. pr_err("%s() supported_len=0x%x,\n"
  1761. " unsupported len req=0x%x\n", __func__,
  1762. qp->max_inline_data, hdr->total_len);
  1763. return -EINVAL;
  1764. }
  1765. dpp_addr = (char *)sge;
  1766. for (i = 0; i < wr->num_sge; i++) {
  1767. memcpy(dpp_addr,
  1768. (void *)(unsigned long)wr->sg_list[i].addr,
  1769. wr->sg_list[i].length);
  1770. dpp_addr += wr->sg_list[i].length;
  1771. }
  1772. wqe_size += roundup(hdr->total_len, OCRDMA_WQE_ALIGN_BYTES);
  1773. if (0 == hdr->total_len)
  1774. wqe_size += sizeof(struct ocrdma_sge);
  1775. hdr->cw |= (OCRDMA_TYPE_INLINE << OCRDMA_WQE_TYPE_SHIFT);
  1776. } else {
  1777. ocrdma_build_sges(hdr, sge, wr->num_sge, wr->sg_list);
  1778. if (wr->num_sge)
  1779. wqe_size += (wr->num_sge * sizeof(struct ocrdma_sge));
  1780. else
  1781. wqe_size += sizeof(struct ocrdma_sge);
  1782. hdr->cw |= (OCRDMA_TYPE_LKEY << OCRDMA_WQE_TYPE_SHIFT);
  1783. }
  1784. hdr->cw |= ((wqe_size / OCRDMA_WQE_STRIDE) << OCRDMA_WQE_SIZE_SHIFT);
  1785. return 0;
  1786. }
  1787. static int ocrdma_build_send(struct ocrdma_qp *qp, struct ocrdma_hdr_wqe *hdr,
  1788. struct ib_send_wr *wr)
  1789. {
  1790. int status;
  1791. struct ocrdma_sge *sge;
  1792. u32 wqe_size = sizeof(*hdr);
  1793. if (qp->qp_type == IB_QPT_UD || qp->qp_type == IB_QPT_GSI) {
  1794. ocrdma_build_ud_hdr(qp, hdr, wr);
  1795. sge = (struct ocrdma_sge *)(hdr + 2);
  1796. wqe_size += sizeof(struct ocrdma_ewqe_ud_hdr);
  1797. } else {
  1798. sge = (struct ocrdma_sge *)(hdr + 1);
  1799. }
  1800. status = ocrdma_build_inline_sges(qp, hdr, sge, wr, wqe_size);
  1801. return status;
  1802. }
  1803. static int ocrdma_build_write(struct ocrdma_qp *qp, struct ocrdma_hdr_wqe *hdr,
  1804. struct ib_send_wr *wr)
  1805. {
  1806. int status;
  1807. struct ocrdma_sge *ext_rw = (struct ocrdma_sge *)(hdr + 1);
  1808. struct ocrdma_sge *sge = ext_rw + 1;
  1809. u32 wqe_size = sizeof(*hdr) + sizeof(*ext_rw);
  1810. status = ocrdma_build_inline_sges(qp, hdr, sge, wr, wqe_size);
  1811. if (status)
  1812. return status;
  1813. ext_rw->addr_lo = rdma_wr(wr)->remote_addr;
  1814. ext_rw->addr_hi = upper_32_bits(rdma_wr(wr)->remote_addr);
  1815. ext_rw->lrkey = rdma_wr(wr)->rkey;
  1816. ext_rw->len = hdr->total_len;
  1817. return 0;
  1818. }
  1819. static void ocrdma_build_read(struct ocrdma_qp *qp, struct ocrdma_hdr_wqe *hdr,
  1820. struct ib_send_wr *wr)
  1821. {
  1822. struct ocrdma_sge *ext_rw = (struct ocrdma_sge *)(hdr + 1);
  1823. struct ocrdma_sge *sge = ext_rw + 1;
  1824. u32 wqe_size = ((wr->num_sge + 1) * sizeof(struct ocrdma_sge)) +
  1825. sizeof(struct ocrdma_hdr_wqe);
  1826. ocrdma_build_sges(hdr, sge, wr->num_sge, wr->sg_list);
  1827. hdr->cw |= ((wqe_size / OCRDMA_WQE_STRIDE) << OCRDMA_WQE_SIZE_SHIFT);
  1828. hdr->cw |= (OCRDMA_READ << OCRDMA_WQE_OPCODE_SHIFT);
  1829. hdr->cw |= (OCRDMA_TYPE_LKEY << OCRDMA_WQE_TYPE_SHIFT);
  1830. ext_rw->addr_lo = rdma_wr(wr)->remote_addr;
  1831. ext_rw->addr_hi = upper_32_bits(rdma_wr(wr)->remote_addr);
  1832. ext_rw->lrkey = rdma_wr(wr)->rkey;
  1833. ext_rw->len = hdr->total_len;
  1834. }
  1835. static int get_encoded_page_size(int pg_sz)
  1836. {
  1837. /* Max size is 256M 4096 << 16 */
  1838. int i = 0;
  1839. for (; i < 17; i++)
  1840. if (pg_sz == (4096 << i))
  1841. break;
  1842. return i;
  1843. }
  1844. static int ocrdma_build_reg(struct ocrdma_qp *qp,
  1845. struct ocrdma_hdr_wqe *hdr,
  1846. struct ib_reg_wr *wr)
  1847. {
  1848. u64 fbo;
  1849. struct ocrdma_ewqe_fr *fast_reg = (struct ocrdma_ewqe_fr *)(hdr + 1);
  1850. struct ocrdma_mr *mr = get_ocrdma_mr(wr->mr);
  1851. struct ocrdma_pbl *pbl_tbl = mr->hwmr.pbl_table;
  1852. struct ocrdma_pbe *pbe;
  1853. u32 wqe_size = sizeof(*fast_reg) + sizeof(*hdr);
  1854. int num_pbes = 0, i;
  1855. wqe_size = roundup(wqe_size, OCRDMA_WQE_ALIGN_BYTES);
  1856. hdr->cw |= (OCRDMA_FR_MR << OCRDMA_WQE_OPCODE_SHIFT);
  1857. hdr->cw |= ((wqe_size / OCRDMA_WQE_STRIDE) << OCRDMA_WQE_SIZE_SHIFT);
  1858. if (wr->access & IB_ACCESS_LOCAL_WRITE)
  1859. hdr->rsvd_lkey_flags |= OCRDMA_LKEY_FLAG_LOCAL_WR;
  1860. if (wr->access & IB_ACCESS_REMOTE_WRITE)
  1861. hdr->rsvd_lkey_flags |= OCRDMA_LKEY_FLAG_REMOTE_WR;
  1862. if (wr->access & IB_ACCESS_REMOTE_READ)
  1863. hdr->rsvd_lkey_flags |= OCRDMA_LKEY_FLAG_REMOTE_RD;
  1864. hdr->lkey = wr->key;
  1865. hdr->total_len = mr->ibmr.length;
  1866. fbo = mr->ibmr.iova - mr->pages[0];
  1867. fast_reg->va_hi = upper_32_bits(mr->ibmr.iova);
  1868. fast_reg->va_lo = (u32) (mr->ibmr.iova & 0xffffffff);
  1869. fast_reg->fbo_hi = upper_32_bits(fbo);
  1870. fast_reg->fbo_lo = (u32) fbo & 0xffffffff;
  1871. fast_reg->num_sges = mr->npages;
  1872. fast_reg->size_sge = get_encoded_page_size(mr->ibmr.page_size);
  1873. pbe = pbl_tbl->va;
  1874. for (i = 0; i < mr->npages; i++) {
  1875. u64 buf_addr = mr->pages[i];
  1876. pbe->pa_lo = cpu_to_le32((u32) (buf_addr & PAGE_MASK));
  1877. pbe->pa_hi = cpu_to_le32((u32) upper_32_bits(buf_addr));
  1878. num_pbes += 1;
  1879. pbe++;
  1880. /* if the pbl is full storing the pbes,
  1881. * move to next pbl.
  1882. */
  1883. if (num_pbes == (mr->hwmr.pbl_size/sizeof(u64))) {
  1884. pbl_tbl++;
  1885. pbe = (struct ocrdma_pbe *)pbl_tbl->va;
  1886. }
  1887. }
  1888. return 0;
  1889. }
  1890. static void ocrdma_ring_sq_db(struct ocrdma_qp *qp)
  1891. {
  1892. u32 val = qp->sq.dbid | (1 << OCRDMA_DB_SQ_SHIFT);
  1893. iowrite32(val, qp->sq_db);
  1894. }
  1895. int ocrdma_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
  1896. struct ib_send_wr **bad_wr)
  1897. {
  1898. int status = 0;
  1899. struct ocrdma_qp *qp = get_ocrdma_qp(ibqp);
  1900. struct ocrdma_hdr_wqe *hdr;
  1901. unsigned long flags;
  1902. spin_lock_irqsave(&qp->q_lock, flags);
  1903. if (qp->state != OCRDMA_QPS_RTS && qp->state != OCRDMA_QPS_SQD) {
  1904. spin_unlock_irqrestore(&qp->q_lock, flags);
  1905. *bad_wr = wr;
  1906. return -EINVAL;
  1907. }
  1908. while (wr) {
  1909. if (qp->qp_type == IB_QPT_UD &&
  1910. (wr->opcode != IB_WR_SEND &&
  1911. wr->opcode != IB_WR_SEND_WITH_IMM)) {
  1912. *bad_wr = wr;
  1913. status = -EINVAL;
  1914. break;
  1915. }
  1916. if (ocrdma_hwq_free_cnt(&qp->sq) == 0 ||
  1917. wr->num_sge > qp->sq.max_sges) {
  1918. *bad_wr = wr;
  1919. status = -ENOMEM;
  1920. break;
  1921. }
  1922. hdr = ocrdma_hwq_head(&qp->sq);
  1923. hdr->cw = 0;
  1924. if (wr->send_flags & IB_SEND_SIGNALED || qp->signaled)
  1925. hdr->cw |= (OCRDMA_FLAG_SIG << OCRDMA_WQE_FLAGS_SHIFT);
  1926. if (wr->send_flags & IB_SEND_FENCE)
  1927. hdr->cw |=
  1928. (OCRDMA_FLAG_FENCE_L << OCRDMA_WQE_FLAGS_SHIFT);
  1929. if (wr->send_flags & IB_SEND_SOLICITED)
  1930. hdr->cw |=
  1931. (OCRDMA_FLAG_SOLICIT << OCRDMA_WQE_FLAGS_SHIFT);
  1932. hdr->total_len = 0;
  1933. switch (wr->opcode) {
  1934. case IB_WR_SEND_WITH_IMM:
  1935. hdr->cw |= (OCRDMA_FLAG_IMM << OCRDMA_WQE_FLAGS_SHIFT);
  1936. hdr->immdt = ntohl(wr->ex.imm_data);
  1937. /* fall through */
  1938. case IB_WR_SEND:
  1939. hdr->cw |= (OCRDMA_SEND << OCRDMA_WQE_OPCODE_SHIFT);
  1940. ocrdma_build_send(qp, hdr, wr);
  1941. break;
  1942. case IB_WR_SEND_WITH_INV:
  1943. hdr->cw |= (OCRDMA_FLAG_INV << OCRDMA_WQE_FLAGS_SHIFT);
  1944. hdr->cw |= (OCRDMA_SEND << OCRDMA_WQE_OPCODE_SHIFT);
  1945. hdr->lkey = wr->ex.invalidate_rkey;
  1946. status = ocrdma_build_send(qp, hdr, wr);
  1947. break;
  1948. case IB_WR_RDMA_WRITE_WITH_IMM:
  1949. hdr->cw |= (OCRDMA_FLAG_IMM << OCRDMA_WQE_FLAGS_SHIFT);
  1950. hdr->immdt = ntohl(wr->ex.imm_data);
  1951. /* fall through */
  1952. case IB_WR_RDMA_WRITE:
  1953. hdr->cw |= (OCRDMA_WRITE << OCRDMA_WQE_OPCODE_SHIFT);
  1954. status = ocrdma_build_write(qp, hdr, wr);
  1955. break;
  1956. case IB_WR_RDMA_READ:
  1957. ocrdma_build_read(qp, hdr, wr);
  1958. break;
  1959. case IB_WR_LOCAL_INV:
  1960. hdr->cw |=
  1961. (OCRDMA_LKEY_INV << OCRDMA_WQE_OPCODE_SHIFT);
  1962. hdr->cw |= ((sizeof(struct ocrdma_hdr_wqe) +
  1963. sizeof(struct ocrdma_sge)) /
  1964. OCRDMA_WQE_STRIDE) << OCRDMA_WQE_SIZE_SHIFT;
  1965. hdr->lkey = wr->ex.invalidate_rkey;
  1966. break;
  1967. case IB_WR_REG_MR:
  1968. status = ocrdma_build_reg(qp, hdr, reg_wr(wr));
  1969. break;
  1970. default:
  1971. status = -EINVAL;
  1972. break;
  1973. }
  1974. if (status) {
  1975. *bad_wr = wr;
  1976. break;
  1977. }
  1978. if (wr->send_flags & IB_SEND_SIGNALED || qp->signaled)
  1979. qp->wqe_wr_id_tbl[qp->sq.head].signaled = 1;
  1980. else
  1981. qp->wqe_wr_id_tbl[qp->sq.head].signaled = 0;
  1982. qp->wqe_wr_id_tbl[qp->sq.head].wrid = wr->wr_id;
  1983. ocrdma_cpu_to_le32(hdr, ((hdr->cw >> OCRDMA_WQE_SIZE_SHIFT) &
  1984. OCRDMA_WQE_SIZE_MASK) * OCRDMA_WQE_STRIDE);
  1985. /* make sure wqe is written before adapter can access it */
  1986. wmb();
  1987. /* inform hw to start processing it */
  1988. ocrdma_ring_sq_db(qp);
  1989. /* update pointer, counter for next wr */
  1990. ocrdma_hwq_inc_head(&qp->sq);
  1991. wr = wr->next;
  1992. }
  1993. spin_unlock_irqrestore(&qp->q_lock, flags);
  1994. return status;
  1995. }
  1996. static void ocrdma_ring_rq_db(struct ocrdma_qp *qp)
  1997. {
  1998. u32 val = qp->rq.dbid | (1 << OCRDMA_DB_RQ_SHIFT);
  1999. iowrite32(val, qp->rq_db);
  2000. }
  2001. static void ocrdma_build_rqe(struct ocrdma_hdr_wqe *rqe, struct ib_recv_wr *wr,
  2002. u16 tag)
  2003. {
  2004. u32 wqe_size = 0;
  2005. struct ocrdma_sge *sge;
  2006. if (wr->num_sge)
  2007. wqe_size = (wr->num_sge * sizeof(*sge)) + sizeof(*rqe);
  2008. else
  2009. wqe_size = sizeof(*sge) + sizeof(*rqe);
  2010. rqe->cw = ((wqe_size / OCRDMA_WQE_STRIDE) <<
  2011. OCRDMA_WQE_SIZE_SHIFT);
  2012. rqe->cw |= (OCRDMA_FLAG_SIG << OCRDMA_WQE_FLAGS_SHIFT);
  2013. rqe->cw |= (OCRDMA_TYPE_LKEY << OCRDMA_WQE_TYPE_SHIFT);
  2014. rqe->total_len = 0;
  2015. rqe->rsvd_tag = tag;
  2016. sge = (struct ocrdma_sge *)(rqe + 1);
  2017. ocrdma_build_sges(rqe, sge, wr->num_sge, wr->sg_list);
  2018. ocrdma_cpu_to_le32(rqe, wqe_size);
  2019. }
  2020. int ocrdma_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
  2021. struct ib_recv_wr **bad_wr)
  2022. {
  2023. int status = 0;
  2024. unsigned long flags;
  2025. struct ocrdma_qp *qp = get_ocrdma_qp(ibqp);
  2026. struct ocrdma_hdr_wqe *rqe;
  2027. spin_lock_irqsave(&qp->q_lock, flags);
  2028. if (qp->state == OCRDMA_QPS_RST || qp->state == OCRDMA_QPS_ERR) {
  2029. spin_unlock_irqrestore(&qp->q_lock, flags);
  2030. *bad_wr = wr;
  2031. return -EINVAL;
  2032. }
  2033. while (wr) {
  2034. if (ocrdma_hwq_free_cnt(&qp->rq) == 0 ||
  2035. wr->num_sge > qp->rq.max_sges) {
  2036. *bad_wr = wr;
  2037. status = -ENOMEM;
  2038. break;
  2039. }
  2040. rqe = ocrdma_hwq_head(&qp->rq);
  2041. ocrdma_build_rqe(rqe, wr, 0);
  2042. qp->rqe_wr_id_tbl[qp->rq.head] = wr->wr_id;
  2043. /* make sure rqe is written before adapter can access it */
  2044. wmb();
  2045. /* inform hw to start processing it */
  2046. ocrdma_ring_rq_db(qp);
  2047. /* update pointer, counter for next wr */
  2048. ocrdma_hwq_inc_head(&qp->rq);
  2049. wr = wr->next;
  2050. }
  2051. spin_unlock_irqrestore(&qp->q_lock, flags);
  2052. return status;
  2053. }
  2054. /* cqe for srq's rqe can potentially arrive out of order.
  2055. * index gives the entry in the shadow table where to store
  2056. * the wr_id. tag/index is returned in cqe to reference back
  2057. * for a given rqe.
  2058. */
  2059. static int ocrdma_srq_get_idx(struct ocrdma_srq *srq)
  2060. {
  2061. int row = 0;
  2062. int indx = 0;
  2063. for (row = 0; row < srq->bit_fields_len; row++) {
  2064. if (srq->idx_bit_fields[row]) {
  2065. indx = ffs(srq->idx_bit_fields[row]);
  2066. indx = (row * 32) + (indx - 1);
  2067. BUG_ON(indx >= srq->rq.max_cnt);
  2068. ocrdma_srq_toggle_bit(srq, indx);
  2069. break;
  2070. }
  2071. }
  2072. BUG_ON(row == srq->bit_fields_len);
  2073. return indx + 1; /* Use from index 1 */
  2074. }
  2075. static void ocrdma_ring_srq_db(struct ocrdma_srq *srq)
  2076. {
  2077. u32 val = srq->rq.dbid | (1 << 16);
  2078. iowrite32(val, srq->db + OCRDMA_DB_GEN2_SRQ_OFFSET);
  2079. }
  2080. int ocrdma_post_srq_recv(struct ib_srq *ibsrq, struct ib_recv_wr *wr,
  2081. struct ib_recv_wr **bad_wr)
  2082. {
  2083. int status = 0;
  2084. unsigned long flags;
  2085. struct ocrdma_srq *srq;
  2086. struct ocrdma_hdr_wqe *rqe;
  2087. u16 tag;
  2088. srq = get_ocrdma_srq(ibsrq);
  2089. spin_lock_irqsave(&srq->q_lock, flags);
  2090. while (wr) {
  2091. if (ocrdma_hwq_free_cnt(&srq->rq) == 0 ||
  2092. wr->num_sge > srq->rq.max_sges) {
  2093. status = -ENOMEM;
  2094. *bad_wr = wr;
  2095. break;
  2096. }
  2097. tag = ocrdma_srq_get_idx(srq);
  2098. rqe = ocrdma_hwq_head(&srq->rq);
  2099. ocrdma_build_rqe(rqe, wr, tag);
  2100. srq->rqe_wr_id_tbl[tag] = wr->wr_id;
  2101. /* make sure rqe is written before adapter can perform DMA */
  2102. wmb();
  2103. /* inform hw to start processing it */
  2104. ocrdma_ring_srq_db(srq);
  2105. /* update pointer, counter for next wr */
  2106. ocrdma_hwq_inc_head(&srq->rq);
  2107. wr = wr->next;
  2108. }
  2109. spin_unlock_irqrestore(&srq->q_lock, flags);
  2110. return status;
  2111. }
  2112. static enum ib_wc_status ocrdma_to_ibwc_err(u16 status)
  2113. {
  2114. enum ib_wc_status ibwc_status;
  2115. switch (status) {
  2116. case OCRDMA_CQE_GENERAL_ERR:
  2117. ibwc_status = IB_WC_GENERAL_ERR;
  2118. break;
  2119. case OCRDMA_CQE_LOC_LEN_ERR:
  2120. ibwc_status = IB_WC_LOC_LEN_ERR;
  2121. break;
  2122. case OCRDMA_CQE_LOC_QP_OP_ERR:
  2123. ibwc_status = IB_WC_LOC_QP_OP_ERR;
  2124. break;
  2125. case OCRDMA_CQE_LOC_EEC_OP_ERR:
  2126. ibwc_status = IB_WC_LOC_EEC_OP_ERR;
  2127. break;
  2128. case OCRDMA_CQE_LOC_PROT_ERR:
  2129. ibwc_status = IB_WC_LOC_PROT_ERR;
  2130. break;
  2131. case OCRDMA_CQE_WR_FLUSH_ERR:
  2132. ibwc_status = IB_WC_WR_FLUSH_ERR;
  2133. break;
  2134. case OCRDMA_CQE_MW_BIND_ERR:
  2135. ibwc_status = IB_WC_MW_BIND_ERR;
  2136. break;
  2137. case OCRDMA_CQE_BAD_RESP_ERR:
  2138. ibwc_status = IB_WC_BAD_RESP_ERR;
  2139. break;
  2140. case OCRDMA_CQE_LOC_ACCESS_ERR:
  2141. ibwc_status = IB_WC_LOC_ACCESS_ERR;
  2142. break;
  2143. case OCRDMA_CQE_REM_INV_REQ_ERR:
  2144. ibwc_status = IB_WC_REM_INV_REQ_ERR;
  2145. break;
  2146. case OCRDMA_CQE_REM_ACCESS_ERR:
  2147. ibwc_status = IB_WC_REM_ACCESS_ERR;
  2148. break;
  2149. case OCRDMA_CQE_REM_OP_ERR:
  2150. ibwc_status = IB_WC_REM_OP_ERR;
  2151. break;
  2152. case OCRDMA_CQE_RETRY_EXC_ERR:
  2153. ibwc_status = IB_WC_RETRY_EXC_ERR;
  2154. break;
  2155. case OCRDMA_CQE_RNR_RETRY_EXC_ERR:
  2156. ibwc_status = IB_WC_RNR_RETRY_EXC_ERR;
  2157. break;
  2158. case OCRDMA_CQE_LOC_RDD_VIOL_ERR:
  2159. ibwc_status = IB_WC_LOC_RDD_VIOL_ERR;
  2160. break;
  2161. case OCRDMA_CQE_REM_INV_RD_REQ_ERR:
  2162. ibwc_status = IB_WC_REM_INV_RD_REQ_ERR;
  2163. break;
  2164. case OCRDMA_CQE_REM_ABORT_ERR:
  2165. ibwc_status = IB_WC_REM_ABORT_ERR;
  2166. break;
  2167. case OCRDMA_CQE_INV_EECN_ERR:
  2168. ibwc_status = IB_WC_INV_EECN_ERR;
  2169. break;
  2170. case OCRDMA_CQE_INV_EEC_STATE_ERR:
  2171. ibwc_status = IB_WC_INV_EEC_STATE_ERR;
  2172. break;
  2173. case OCRDMA_CQE_FATAL_ERR:
  2174. ibwc_status = IB_WC_FATAL_ERR;
  2175. break;
  2176. case OCRDMA_CQE_RESP_TIMEOUT_ERR:
  2177. ibwc_status = IB_WC_RESP_TIMEOUT_ERR;
  2178. break;
  2179. default:
  2180. ibwc_status = IB_WC_GENERAL_ERR;
  2181. break;
  2182. }
  2183. return ibwc_status;
  2184. }
  2185. static void ocrdma_update_wc(struct ocrdma_qp *qp, struct ib_wc *ibwc,
  2186. u32 wqe_idx)
  2187. {
  2188. struct ocrdma_hdr_wqe *hdr;
  2189. struct ocrdma_sge *rw;
  2190. int opcode;
  2191. hdr = ocrdma_hwq_head_from_idx(&qp->sq, wqe_idx);
  2192. ibwc->wr_id = qp->wqe_wr_id_tbl[wqe_idx].wrid;
  2193. /* Undo the hdr->cw swap */
  2194. opcode = le32_to_cpu(hdr->cw) & OCRDMA_WQE_OPCODE_MASK;
  2195. switch (opcode) {
  2196. case OCRDMA_WRITE:
  2197. ibwc->opcode = IB_WC_RDMA_WRITE;
  2198. break;
  2199. case OCRDMA_READ:
  2200. rw = (struct ocrdma_sge *)(hdr + 1);
  2201. ibwc->opcode = IB_WC_RDMA_READ;
  2202. ibwc->byte_len = rw->len;
  2203. break;
  2204. case OCRDMA_SEND:
  2205. ibwc->opcode = IB_WC_SEND;
  2206. break;
  2207. case OCRDMA_FR_MR:
  2208. ibwc->opcode = IB_WC_REG_MR;
  2209. break;
  2210. case OCRDMA_LKEY_INV:
  2211. ibwc->opcode = IB_WC_LOCAL_INV;
  2212. break;
  2213. default:
  2214. ibwc->status = IB_WC_GENERAL_ERR;
  2215. pr_err("%s() invalid opcode received = 0x%x\n",
  2216. __func__, hdr->cw & OCRDMA_WQE_OPCODE_MASK);
  2217. break;
  2218. }
  2219. }
  2220. static void ocrdma_set_cqe_status_flushed(struct ocrdma_qp *qp,
  2221. struct ocrdma_cqe *cqe)
  2222. {
  2223. if (is_cqe_for_sq(cqe)) {
  2224. cqe->flags_status_srcqpn = cpu_to_le32(le32_to_cpu(
  2225. cqe->flags_status_srcqpn) &
  2226. ~OCRDMA_CQE_STATUS_MASK);
  2227. cqe->flags_status_srcqpn = cpu_to_le32(le32_to_cpu(
  2228. cqe->flags_status_srcqpn) |
  2229. (OCRDMA_CQE_WR_FLUSH_ERR <<
  2230. OCRDMA_CQE_STATUS_SHIFT));
  2231. } else {
  2232. if (qp->qp_type == IB_QPT_UD || qp->qp_type == IB_QPT_GSI) {
  2233. cqe->flags_status_srcqpn = cpu_to_le32(le32_to_cpu(
  2234. cqe->flags_status_srcqpn) &
  2235. ~OCRDMA_CQE_UD_STATUS_MASK);
  2236. cqe->flags_status_srcqpn = cpu_to_le32(le32_to_cpu(
  2237. cqe->flags_status_srcqpn) |
  2238. (OCRDMA_CQE_WR_FLUSH_ERR <<
  2239. OCRDMA_CQE_UD_STATUS_SHIFT));
  2240. } else {
  2241. cqe->flags_status_srcqpn = cpu_to_le32(le32_to_cpu(
  2242. cqe->flags_status_srcqpn) &
  2243. ~OCRDMA_CQE_STATUS_MASK);
  2244. cqe->flags_status_srcqpn = cpu_to_le32(le32_to_cpu(
  2245. cqe->flags_status_srcqpn) |
  2246. (OCRDMA_CQE_WR_FLUSH_ERR <<
  2247. OCRDMA_CQE_STATUS_SHIFT));
  2248. }
  2249. }
  2250. }
  2251. static bool ocrdma_update_err_cqe(struct ib_wc *ibwc, struct ocrdma_cqe *cqe,
  2252. struct ocrdma_qp *qp, int status)
  2253. {
  2254. bool expand = false;
  2255. ibwc->byte_len = 0;
  2256. ibwc->qp = &qp->ibqp;
  2257. ibwc->status = ocrdma_to_ibwc_err(status);
  2258. ocrdma_flush_qp(qp);
  2259. ocrdma_qp_state_change(qp, IB_QPS_ERR, NULL);
  2260. /* if wqe/rqe pending for which cqe needs to be returned,
  2261. * trigger inflating it.
  2262. */
  2263. if (!is_hw_rq_empty(qp) || !is_hw_sq_empty(qp)) {
  2264. expand = true;
  2265. ocrdma_set_cqe_status_flushed(qp, cqe);
  2266. }
  2267. return expand;
  2268. }
  2269. static int ocrdma_update_err_rcqe(struct ib_wc *ibwc, struct ocrdma_cqe *cqe,
  2270. struct ocrdma_qp *qp, int status)
  2271. {
  2272. ibwc->opcode = IB_WC_RECV;
  2273. ibwc->wr_id = qp->rqe_wr_id_tbl[qp->rq.tail];
  2274. ocrdma_hwq_inc_tail(&qp->rq);
  2275. return ocrdma_update_err_cqe(ibwc, cqe, qp, status);
  2276. }
  2277. static int ocrdma_update_err_scqe(struct ib_wc *ibwc, struct ocrdma_cqe *cqe,
  2278. struct ocrdma_qp *qp, int status)
  2279. {
  2280. ocrdma_update_wc(qp, ibwc, qp->sq.tail);
  2281. ocrdma_hwq_inc_tail(&qp->sq);
  2282. return ocrdma_update_err_cqe(ibwc, cqe, qp, status);
  2283. }
  2284. static bool ocrdma_poll_err_scqe(struct ocrdma_qp *qp,
  2285. struct ocrdma_cqe *cqe, struct ib_wc *ibwc,
  2286. bool *polled, bool *stop)
  2287. {
  2288. bool expand;
  2289. struct ocrdma_dev *dev = get_ocrdma_dev(qp->ibqp.device);
  2290. int status = (le32_to_cpu(cqe->flags_status_srcqpn) &
  2291. OCRDMA_CQE_STATUS_MASK) >> OCRDMA_CQE_STATUS_SHIFT;
  2292. if (status < OCRDMA_MAX_CQE_ERR)
  2293. atomic_inc(&dev->cqe_err_stats[status]);
  2294. /* when hw sq is empty, but rq is not empty, so we continue
  2295. * to keep the cqe in order to get the cq event again.
  2296. */
  2297. if (is_hw_sq_empty(qp) && !is_hw_rq_empty(qp)) {
  2298. /* when cq for rq and sq is same, it is safe to return
  2299. * flush cqe for RQEs.
  2300. */
  2301. if (!qp->srq && (qp->sq_cq == qp->rq_cq)) {
  2302. *polled = true;
  2303. status = OCRDMA_CQE_WR_FLUSH_ERR;
  2304. expand = ocrdma_update_err_rcqe(ibwc, cqe, qp, status);
  2305. } else {
  2306. /* stop processing further cqe as this cqe is used for
  2307. * triggering cq event on buddy cq of RQ.
  2308. * When QP is destroyed, this cqe will be removed
  2309. * from the cq's hardware q.
  2310. */
  2311. *polled = false;
  2312. *stop = true;
  2313. expand = false;
  2314. }
  2315. } else if (is_hw_sq_empty(qp)) {
  2316. /* Do nothing */
  2317. expand = false;
  2318. *polled = false;
  2319. *stop = false;
  2320. } else {
  2321. *polled = true;
  2322. expand = ocrdma_update_err_scqe(ibwc, cqe, qp, status);
  2323. }
  2324. return expand;
  2325. }
  2326. static bool ocrdma_poll_success_scqe(struct ocrdma_qp *qp,
  2327. struct ocrdma_cqe *cqe,
  2328. struct ib_wc *ibwc, bool *polled)
  2329. {
  2330. bool expand = false;
  2331. int tail = qp->sq.tail;
  2332. u32 wqe_idx;
  2333. if (!qp->wqe_wr_id_tbl[tail].signaled) {
  2334. *polled = false; /* WC cannot be consumed yet */
  2335. } else {
  2336. ibwc->status = IB_WC_SUCCESS;
  2337. ibwc->wc_flags = 0;
  2338. ibwc->qp = &qp->ibqp;
  2339. ocrdma_update_wc(qp, ibwc, tail);
  2340. *polled = true;
  2341. }
  2342. wqe_idx = (le32_to_cpu(cqe->wq.wqeidx) &
  2343. OCRDMA_CQE_WQEIDX_MASK) & qp->sq.max_wqe_idx;
  2344. if (tail != wqe_idx)
  2345. expand = true; /* Coalesced CQE can't be consumed yet */
  2346. ocrdma_hwq_inc_tail(&qp->sq);
  2347. return expand;
  2348. }
  2349. static bool ocrdma_poll_scqe(struct ocrdma_qp *qp, struct ocrdma_cqe *cqe,
  2350. struct ib_wc *ibwc, bool *polled, bool *stop)
  2351. {
  2352. int status;
  2353. bool expand;
  2354. status = (le32_to_cpu(cqe->flags_status_srcqpn) &
  2355. OCRDMA_CQE_STATUS_MASK) >> OCRDMA_CQE_STATUS_SHIFT;
  2356. if (status == OCRDMA_CQE_SUCCESS)
  2357. expand = ocrdma_poll_success_scqe(qp, cqe, ibwc, polled);
  2358. else
  2359. expand = ocrdma_poll_err_scqe(qp, cqe, ibwc, polled, stop);
  2360. return expand;
  2361. }
  2362. static int ocrdma_update_ud_rcqe(struct ocrdma_dev *dev, struct ib_wc *ibwc,
  2363. struct ocrdma_cqe *cqe)
  2364. {
  2365. int status;
  2366. u16 hdr_type = 0;
  2367. status = (le32_to_cpu(cqe->flags_status_srcqpn) &
  2368. OCRDMA_CQE_UD_STATUS_MASK) >> OCRDMA_CQE_UD_STATUS_SHIFT;
  2369. ibwc->src_qp = le32_to_cpu(cqe->flags_status_srcqpn) &
  2370. OCRDMA_CQE_SRCQP_MASK;
  2371. ibwc->pkey_index = 0;
  2372. ibwc->wc_flags = IB_WC_GRH;
  2373. ibwc->byte_len = (le32_to_cpu(cqe->ud.rxlen_pkey) >>
  2374. OCRDMA_CQE_UD_XFER_LEN_SHIFT) &
  2375. OCRDMA_CQE_UD_XFER_LEN_MASK;
  2376. if (ocrdma_is_udp_encap_supported(dev)) {
  2377. hdr_type = (le32_to_cpu(cqe->ud.rxlen_pkey) >>
  2378. OCRDMA_CQE_UD_L3TYPE_SHIFT) &
  2379. OCRDMA_CQE_UD_L3TYPE_MASK;
  2380. ibwc->wc_flags |= IB_WC_WITH_NETWORK_HDR_TYPE;
  2381. ibwc->network_hdr_type = hdr_type;
  2382. }
  2383. return status;
  2384. }
  2385. static void ocrdma_update_free_srq_cqe(struct ib_wc *ibwc,
  2386. struct ocrdma_cqe *cqe,
  2387. struct ocrdma_qp *qp)
  2388. {
  2389. unsigned long flags;
  2390. struct ocrdma_srq *srq;
  2391. u32 wqe_idx;
  2392. srq = get_ocrdma_srq(qp->ibqp.srq);
  2393. wqe_idx = (le32_to_cpu(cqe->rq.buftag_qpn) >>
  2394. OCRDMA_CQE_BUFTAG_SHIFT) & srq->rq.max_wqe_idx;
  2395. BUG_ON(wqe_idx < 1);
  2396. ibwc->wr_id = srq->rqe_wr_id_tbl[wqe_idx];
  2397. spin_lock_irqsave(&srq->q_lock, flags);
  2398. ocrdma_srq_toggle_bit(srq, wqe_idx - 1);
  2399. spin_unlock_irqrestore(&srq->q_lock, flags);
  2400. ocrdma_hwq_inc_tail(&srq->rq);
  2401. }
  2402. static bool ocrdma_poll_err_rcqe(struct ocrdma_qp *qp, struct ocrdma_cqe *cqe,
  2403. struct ib_wc *ibwc, bool *polled, bool *stop,
  2404. int status)
  2405. {
  2406. bool expand;
  2407. struct ocrdma_dev *dev = get_ocrdma_dev(qp->ibqp.device);
  2408. if (status < OCRDMA_MAX_CQE_ERR)
  2409. atomic_inc(&dev->cqe_err_stats[status]);
  2410. /* when hw_rq is empty, but wq is not empty, so continue
  2411. * to keep the cqe to get the cq event again.
  2412. */
  2413. if (is_hw_rq_empty(qp) && !is_hw_sq_empty(qp)) {
  2414. if (!qp->srq && (qp->sq_cq == qp->rq_cq)) {
  2415. *polled = true;
  2416. status = OCRDMA_CQE_WR_FLUSH_ERR;
  2417. expand = ocrdma_update_err_scqe(ibwc, cqe, qp, status);
  2418. } else {
  2419. *polled = false;
  2420. *stop = true;
  2421. expand = false;
  2422. }
  2423. } else if (is_hw_rq_empty(qp)) {
  2424. /* Do nothing */
  2425. expand = false;
  2426. *polled = false;
  2427. *stop = false;
  2428. } else {
  2429. *polled = true;
  2430. expand = ocrdma_update_err_rcqe(ibwc, cqe, qp, status);
  2431. }
  2432. return expand;
  2433. }
  2434. static void ocrdma_poll_success_rcqe(struct ocrdma_qp *qp,
  2435. struct ocrdma_cqe *cqe, struct ib_wc *ibwc)
  2436. {
  2437. struct ocrdma_dev *dev;
  2438. dev = get_ocrdma_dev(qp->ibqp.device);
  2439. ibwc->opcode = IB_WC_RECV;
  2440. ibwc->qp = &qp->ibqp;
  2441. ibwc->status = IB_WC_SUCCESS;
  2442. if (qp->qp_type == IB_QPT_UD || qp->qp_type == IB_QPT_GSI)
  2443. ocrdma_update_ud_rcqe(dev, ibwc, cqe);
  2444. else
  2445. ibwc->byte_len = le32_to_cpu(cqe->rq.rxlen);
  2446. if (is_cqe_imm(cqe)) {
  2447. ibwc->ex.imm_data = htonl(le32_to_cpu(cqe->rq.lkey_immdt));
  2448. ibwc->wc_flags |= IB_WC_WITH_IMM;
  2449. } else if (is_cqe_wr_imm(cqe)) {
  2450. ibwc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
  2451. ibwc->ex.imm_data = htonl(le32_to_cpu(cqe->rq.lkey_immdt));
  2452. ibwc->wc_flags |= IB_WC_WITH_IMM;
  2453. } else if (is_cqe_invalidated(cqe)) {
  2454. ibwc->ex.invalidate_rkey = le32_to_cpu(cqe->rq.lkey_immdt);
  2455. ibwc->wc_flags |= IB_WC_WITH_INVALIDATE;
  2456. }
  2457. if (qp->ibqp.srq) {
  2458. ocrdma_update_free_srq_cqe(ibwc, cqe, qp);
  2459. } else {
  2460. ibwc->wr_id = qp->rqe_wr_id_tbl[qp->rq.tail];
  2461. ocrdma_hwq_inc_tail(&qp->rq);
  2462. }
  2463. }
  2464. static bool ocrdma_poll_rcqe(struct ocrdma_qp *qp, struct ocrdma_cqe *cqe,
  2465. struct ib_wc *ibwc, bool *polled, bool *stop)
  2466. {
  2467. int status;
  2468. bool expand = false;
  2469. ibwc->wc_flags = 0;
  2470. if (qp->qp_type == IB_QPT_UD || qp->qp_type == IB_QPT_GSI) {
  2471. status = (le32_to_cpu(cqe->flags_status_srcqpn) &
  2472. OCRDMA_CQE_UD_STATUS_MASK) >>
  2473. OCRDMA_CQE_UD_STATUS_SHIFT;
  2474. } else {
  2475. status = (le32_to_cpu(cqe->flags_status_srcqpn) &
  2476. OCRDMA_CQE_STATUS_MASK) >> OCRDMA_CQE_STATUS_SHIFT;
  2477. }
  2478. if (status == OCRDMA_CQE_SUCCESS) {
  2479. *polled = true;
  2480. ocrdma_poll_success_rcqe(qp, cqe, ibwc);
  2481. } else {
  2482. expand = ocrdma_poll_err_rcqe(qp, cqe, ibwc, polled, stop,
  2483. status);
  2484. }
  2485. return expand;
  2486. }
  2487. static void ocrdma_change_cq_phase(struct ocrdma_cq *cq, struct ocrdma_cqe *cqe,
  2488. u16 cur_getp)
  2489. {
  2490. if (cq->phase_change) {
  2491. if (cur_getp == 0)
  2492. cq->phase = (~cq->phase & OCRDMA_CQE_VALID);
  2493. } else {
  2494. /* clear valid bit */
  2495. cqe->flags_status_srcqpn = 0;
  2496. }
  2497. }
  2498. static int ocrdma_poll_hwcq(struct ocrdma_cq *cq, int num_entries,
  2499. struct ib_wc *ibwc)
  2500. {
  2501. u16 qpn = 0;
  2502. int i = 0;
  2503. bool expand = false;
  2504. int polled_hw_cqes = 0;
  2505. struct ocrdma_qp *qp = NULL;
  2506. struct ocrdma_dev *dev = get_ocrdma_dev(cq->ibcq.device);
  2507. struct ocrdma_cqe *cqe;
  2508. u16 cur_getp; bool polled = false; bool stop = false;
  2509. cur_getp = cq->getp;
  2510. while (num_entries) {
  2511. cqe = cq->va + cur_getp;
  2512. /* check whether valid cqe or not */
  2513. if (!is_cqe_valid(cq, cqe))
  2514. break;
  2515. qpn = (le32_to_cpu(cqe->cmn.qpn) & OCRDMA_CQE_QPN_MASK);
  2516. /* ignore discarded cqe */
  2517. if (qpn == 0)
  2518. goto skip_cqe;
  2519. qp = dev->qp_tbl[qpn];
  2520. BUG_ON(qp == NULL);
  2521. if (is_cqe_for_sq(cqe)) {
  2522. expand = ocrdma_poll_scqe(qp, cqe, ibwc, &polled,
  2523. &stop);
  2524. } else {
  2525. expand = ocrdma_poll_rcqe(qp, cqe, ibwc, &polled,
  2526. &stop);
  2527. }
  2528. if (expand)
  2529. goto expand_cqe;
  2530. if (stop)
  2531. goto stop_cqe;
  2532. /* clear qpn to avoid duplicate processing by discard_cqe() */
  2533. cqe->cmn.qpn = 0;
  2534. skip_cqe:
  2535. polled_hw_cqes += 1;
  2536. cur_getp = (cur_getp + 1) % cq->max_hw_cqe;
  2537. ocrdma_change_cq_phase(cq, cqe, cur_getp);
  2538. expand_cqe:
  2539. if (polled) {
  2540. num_entries -= 1;
  2541. i += 1;
  2542. ibwc = ibwc + 1;
  2543. polled = false;
  2544. }
  2545. }
  2546. stop_cqe:
  2547. cq->getp = cur_getp;
  2548. if (polled_hw_cqes)
  2549. ocrdma_ring_cq_db(dev, cq->id, false, false, polled_hw_cqes);
  2550. return i;
  2551. }
  2552. /* insert error cqe if the QP's SQ or RQ's CQ matches the CQ under poll. */
  2553. static int ocrdma_add_err_cqe(struct ocrdma_cq *cq, int num_entries,
  2554. struct ocrdma_qp *qp, struct ib_wc *ibwc)
  2555. {
  2556. int err_cqes = 0;
  2557. while (num_entries) {
  2558. if (is_hw_sq_empty(qp) && is_hw_rq_empty(qp))
  2559. break;
  2560. if (!is_hw_sq_empty(qp) && qp->sq_cq == cq) {
  2561. ocrdma_update_wc(qp, ibwc, qp->sq.tail);
  2562. ocrdma_hwq_inc_tail(&qp->sq);
  2563. } else if (!is_hw_rq_empty(qp) && qp->rq_cq == cq) {
  2564. ibwc->wr_id = qp->rqe_wr_id_tbl[qp->rq.tail];
  2565. ocrdma_hwq_inc_tail(&qp->rq);
  2566. } else {
  2567. return err_cqes;
  2568. }
  2569. ibwc->byte_len = 0;
  2570. ibwc->status = IB_WC_WR_FLUSH_ERR;
  2571. ibwc = ibwc + 1;
  2572. err_cqes += 1;
  2573. num_entries -= 1;
  2574. }
  2575. return err_cqes;
  2576. }
  2577. int ocrdma_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc)
  2578. {
  2579. int cqes_to_poll = num_entries;
  2580. struct ocrdma_cq *cq = get_ocrdma_cq(ibcq);
  2581. struct ocrdma_dev *dev = get_ocrdma_dev(ibcq->device);
  2582. int num_os_cqe = 0, err_cqes = 0;
  2583. struct ocrdma_qp *qp;
  2584. unsigned long flags;
  2585. /* poll cqes from adapter CQ */
  2586. spin_lock_irqsave(&cq->cq_lock, flags);
  2587. num_os_cqe = ocrdma_poll_hwcq(cq, cqes_to_poll, wc);
  2588. spin_unlock_irqrestore(&cq->cq_lock, flags);
  2589. cqes_to_poll -= num_os_cqe;
  2590. if (cqes_to_poll) {
  2591. wc = wc + num_os_cqe;
  2592. /* adapter returns single error cqe when qp moves to
  2593. * error state. So insert error cqes with wc_status as
  2594. * FLUSHED for pending WQEs and RQEs of QP's SQ and RQ
  2595. * respectively which uses this CQ.
  2596. */
  2597. spin_lock_irqsave(&dev->flush_q_lock, flags);
  2598. list_for_each_entry(qp, &cq->sq_head, sq_entry) {
  2599. if (cqes_to_poll == 0)
  2600. break;
  2601. err_cqes = ocrdma_add_err_cqe(cq, cqes_to_poll, qp, wc);
  2602. cqes_to_poll -= err_cqes;
  2603. num_os_cqe += err_cqes;
  2604. wc = wc + err_cqes;
  2605. }
  2606. spin_unlock_irqrestore(&dev->flush_q_lock, flags);
  2607. }
  2608. return num_os_cqe;
  2609. }
  2610. int ocrdma_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags cq_flags)
  2611. {
  2612. struct ocrdma_cq *cq = get_ocrdma_cq(ibcq);
  2613. struct ocrdma_dev *dev = get_ocrdma_dev(ibcq->device);
  2614. u16 cq_id;
  2615. unsigned long flags;
  2616. bool arm_needed = false, sol_needed = false;
  2617. cq_id = cq->id;
  2618. spin_lock_irqsave(&cq->cq_lock, flags);
  2619. if (cq_flags & IB_CQ_NEXT_COMP || cq_flags & IB_CQ_SOLICITED)
  2620. arm_needed = true;
  2621. if (cq_flags & IB_CQ_SOLICITED)
  2622. sol_needed = true;
  2623. ocrdma_ring_cq_db(dev, cq_id, arm_needed, sol_needed, 0);
  2624. spin_unlock_irqrestore(&cq->cq_lock, flags);
  2625. return 0;
  2626. }
  2627. struct ib_mr *ocrdma_alloc_mr(struct ib_pd *ibpd,
  2628. enum ib_mr_type mr_type,
  2629. u32 max_num_sg)
  2630. {
  2631. int status;
  2632. struct ocrdma_mr *mr;
  2633. struct ocrdma_pd *pd = get_ocrdma_pd(ibpd);
  2634. struct ocrdma_dev *dev = get_ocrdma_dev(ibpd->device);
  2635. if (mr_type != IB_MR_TYPE_MEM_REG)
  2636. return ERR_PTR(-EINVAL);
  2637. if (max_num_sg > dev->attr.max_pages_per_frmr)
  2638. return ERR_PTR(-EINVAL);
  2639. mr = kzalloc(sizeof(*mr), GFP_KERNEL);
  2640. if (!mr)
  2641. return ERR_PTR(-ENOMEM);
  2642. mr->pages = kcalloc(max_num_sg, sizeof(u64), GFP_KERNEL);
  2643. if (!mr->pages) {
  2644. status = -ENOMEM;
  2645. goto pl_err;
  2646. }
  2647. status = ocrdma_get_pbl_info(dev, mr, max_num_sg);
  2648. if (status)
  2649. goto pbl_err;
  2650. mr->hwmr.fr_mr = 1;
  2651. mr->hwmr.remote_rd = 0;
  2652. mr->hwmr.remote_wr = 0;
  2653. mr->hwmr.local_rd = 0;
  2654. mr->hwmr.local_wr = 0;
  2655. mr->hwmr.mw_bind = 0;
  2656. status = ocrdma_build_pbl_tbl(dev, &mr->hwmr);
  2657. if (status)
  2658. goto pbl_err;
  2659. status = ocrdma_reg_mr(dev, &mr->hwmr, pd->id, 0);
  2660. if (status)
  2661. goto mbx_err;
  2662. mr->ibmr.rkey = mr->hwmr.lkey;
  2663. mr->ibmr.lkey = mr->hwmr.lkey;
  2664. dev->stag_arr[(mr->hwmr.lkey >> 8) & (OCRDMA_MAX_STAG - 1)] =
  2665. (unsigned long) mr;
  2666. return &mr->ibmr;
  2667. mbx_err:
  2668. ocrdma_free_mr_pbl_tbl(dev, &mr->hwmr);
  2669. pbl_err:
  2670. kfree(mr->pages);
  2671. pl_err:
  2672. kfree(mr);
  2673. return ERR_PTR(-ENOMEM);
  2674. }
  2675. static int ocrdma_set_page(struct ib_mr *ibmr, u64 addr)
  2676. {
  2677. struct ocrdma_mr *mr = get_ocrdma_mr(ibmr);
  2678. if (unlikely(mr->npages == mr->hwmr.num_pbes))
  2679. return -ENOMEM;
  2680. mr->pages[mr->npages++] = addr;
  2681. return 0;
  2682. }
  2683. int ocrdma_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents,
  2684. unsigned int *sg_offset)
  2685. {
  2686. struct ocrdma_mr *mr = get_ocrdma_mr(ibmr);
  2687. mr->npages = 0;
  2688. return ib_sg_to_pages(ibmr, sg, sg_nents, sg_offset, ocrdma_set_page);
  2689. }