tilcdc_drv.c 17 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678
  1. /*
  2. * Copyright (C) 2012 Texas Instruments
  3. * Author: Rob Clark <robdclark@gmail.com>
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License version 2 as published by
  7. * the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program. If not, see <http://www.gnu.org/licenses/>.
  16. */
  17. /* LCDC DRM driver, based on da8xx-fb */
  18. #include "tilcdc_drv.h"
  19. #include "tilcdc_regs.h"
  20. #include "tilcdc_tfp410.h"
  21. #include "tilcdc_slave.h"
  22. #include "tilcdc_panel.h"
  23. #include "drm_fb_helper.h"
  24. static LIST_HEAD(module_list);
  25. static bool slave_probing;
  26. void tilcdc_module_init(struct tilcdc_module *mod, const char *name,
  27. const struct tilcdc_module_ops *funcs)
  28. {
  29. mod->name = name;
  30. mod->funcs = funcs;
  31. INIT_LIST_HEAD(&mod->list);
  32. list_add(&mod->list, &module_list);
  33. }
  34. void tilcdc_module_cleanup(struct tilcdc_module *mod)
  35. {
  36. list_del(&mod->list);
  37. }
  38. void tilcdc_slave_probedefer(bool defered)
  39. {
  40. slave_probing = defered;
  41. }
  42. static struct of_device_id tilcdc_of_match[];
  43. static struct drm_framebuffer *tilcdc_fb_create(struct drm_device *dev,
  44. struct drm_file *file_priv, struct drm_mode_fb_cmd2 *mode_cmd)
  45. {
  46. return drm_fb_cma_create(dev, file_priv, mode_cmd);
  47. }
  48. static void tilcdc_fb_output_poll_changed(struct drm_device *dev)
  49. {
  50. struct tilcdc_drm_private *priv = dev->dev_private;
  51. if (priv->fbdev)
  52. drm_fbdev_cma_hotplug_event(priv->fbdev);
  53. }
  54. static const struct drm_mode_config_funcs mode_config_funcs = {
  55. .fb_create = tilcdc_fb_create,
  56. .output_poll_changed = tilcdc_fb_output_poll_changed,
  57. };
  58. static int modeset_init(struct drm_device *dev)
  59. {
  60. struct tilcdc_drm_private *priv = dev->dev_private;
  61. struct tilcdc_module *mod;
  62. drm_mode_config_init(dev);
  63. priv->crtc = tilcdc_crtc_create(dev);
  64. list_for_each_entry(mod, &module_list, list) {
  65. DBG("loading module: %s", mod->name);
  66. mod->funcs->modeset_init(mod, dev);
  67. }
  68. if ((priv->num_encoders == 0) || (priv->num_connectors == 0)) {
  69. /* oh nos! */
  70. dev_err(dev->dev, "no encoders/connectors found\n");
  71. drm_mode_config_cleanup(dev);
  72. return -ENXIO;
  73. }
  74. dev->mode_config.min_width = 0;
  75. dev->mode_config.min_height = 0;
  76. dev->mode_config.max_width = tilcdc_crtc_max_width(priv->crtc);
  77. dev->mode_config.max_height = 2048;
  78. dev->mode_config.funcs = &mode_config_funcs;
  79. return 0;
  80. }
  81. #ifdef CONFIG_CPU_FREQ
  82. static int cpufreq_transition(struct notifier_block *nb,
  83. unsigned long val, void *data)
  84. {
  85. struct tilcdc_drm_private *priv = container_of(nb,
  86. struct tilcdc_drm_private, freq_transition);
  87. if (val == CPUFREQ_POSTCHANGE) {
  88. if (priv->lcd_fck_rate != clk_get_rate(priv->clk)) {
  89. priv->lcd_fck_rate = clk_get_rate(priv->clk);
  90. tilcdc_crtc_update_clk(priv->crtc);
  91. }
  92. }
  93. return 0;
  94. }
  95. #endif
  96. /*
  97. * DRM operations:
  98. */
  99. static int tilcdc_unload(struct drm_device *dev)
  100. {
  101. struct tilcdc_drm_private *priv = dev->dev_private;
  102. drm_fbdev_cma_fini(priv->fbdev);
  103. drm_kms_helper_poll_fini(dev);
  104. drm_mode_config_cleanup(dev);
  105. drm_vblank_cleanup(dev);
  106. pm_runtime_get_sync(dev->dev);
  107. drm_irq_uninstall(dev);
  108. pm_runtime_put_sync(dev->dev);
  109. #ifdef CONFIG_CPU_FREQ
  110. cpufreq_unregister_notifier(&priv->freq_transition,
  111. CPUFREQ_TRANSITION_NOTIFIER);
  112. #endif
  113. if (priv->clk)
  114. clk_put(priv->clk);
  115. if (priv->mmio)
  116. iounmap(priv->mmio);
  117. flush_workqueue(priv->wq);
  118. destroy_workqueue(priv->wq);
  119. dev->dev_private = NULL;
  120. pm_runtime_disable(dev->dev);
  121. kfree(priv);
  122. return 0;
  123. }
  124. static int tilcdc_load(struct drm_device *dev, unsigned long flags)
  125. {
  126. struct platform_device *pdev = dev->platformdev;
  127. struct device_node *node = pdev->dev.of_node;
  128. struct tilcdc_drm_private *priv;
  129. struct tilcdc_module *mod;
  130. struct resource *res;
  131. u32 bpp = 0;
  132. int ret;
  133. priv = kzalloc(sizeof(*priv), GFP_KERNEL);
  134. if (!priv) {
  135. dev_err(dev->dev, "failed to allocate private data\n");
  136. return -ENOMEM;
  137. }
  138. dev->dev_private = priv;
  139. priv->wq = alloc_ordered_workqueue("tilcdc", 0);
  140. if (!priv->wq) {
  141. ret = -ENOMEM;
  142. goto fail_free_priv;
  143. }
  144. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  145. if (!res) {
  146. dev_err(dev->dev, "failed to get memory resource\n");
  147. ret = -EINVAL;
  148. goto fail_free_wq;
  149. }
  150. priv->mmio = ioremap_nocache(res->start, resource_size(res));
  151. if (!priv->mmio) {
  152. dev_err(dev->dev, "failed to ioremap\n");
  153. ret = -ENOMEM;
  154. goto fail_free_wq;
  155. }
  156. priv->clk = clk_get(dev->dev, "fck");
  157. if (IS_ERR(priv->clk)) {
  158. dev_err(dev->dev, "failed to get functional clock\n");
  159. ret = -ENODEV;
  160. goto fail_iounmap;
  161. }
  162. priv->disp_clk = clk_get(dev->dev, "dpll_disp_ck");
  163. if (IS_ERR(priv->clk)) {
  164. dev_err(dev->dev, "failed to get display clock\n");
  165. ret = -ENODEV;
  166. goto fail_put_clk;
  167. }
  168. #ifdef CONFIG_CPU_FREQ
  169. priv->lcd_fck_rate = clk_get_rate(priv->clk);
  170. priv->freq_transition.notifier_call = cpufreq_transition;
  171. ret = cpufreq_register_notifier(&priv->freq_transition,
  172. CPUFREQ_TRANSITION_NOTIFIER);
  173. if (ret) {
  174. dev_err(dev->dev, "failed to register cpufreq notifier\n");
  175. goto fail_put_disp_clk;
  176. }
  177. #endif
  178. if (of_property_read_u32(node, "max-bandwidth", &priv->max_bandwidth))
  179. priv->max_bandwidth = TILCDC_DEFAULT_MAX_BANDWIDTH;
  180. DBG("Maximum Bandwidth Value %d", priv->max_bandwidth);
  181. if (of_property_read_u32(node, "ti,max-width", &priv->max_width))
  182. priv->max_width = TILCDC_DEFAULT_MAX_WIDTH;
  183. DBG("Maximum Horizontal Pixel Width Value %dpixels", priv->max_width);
  184. if (of_property_read_u32(node, "ti,max-pixelclock",
  185. &priv->max_pixelclock))
  186. priv->max_pixelclock = TILCDC_DEFAULT_MAX_PIXELCLOCK;
  187. DBG("Maximum Pixel Clock Value %dKHz", priv->max_pixelclock);
  188. pm_runtime_enable(dev->dev);
  189. /* Determine LCD IP Version */
  190. pm_runtime_get_sync(dev->dev);
  191. switch (tilcdc_read(dev, LCDC_PID_REG)) {
  192. case 0x4c100102:
  193. priv->rev = 1;
  194. break;
  195. case 0x4f200800:
  196. case 0x4f201000:
  197. priv->rev = 2;
  198. break;
  199. default:
  200. dev_warn(dev->dev, "Unknown PID Reg value 0x%08x, "
  201. "defaulting to LCD revision 1\n",
  202. tilcdc_read(dev, LCDC_PID_REG));
  203. priv->rev = 1;
  204. break;
  205. }
  206. pm_runtime_put_sync(dev->dev);
  207. ret = modeset_init(dev);
  208. if (ret < 0) {
  209. dev_err(dev->dev, "failed to initialize mode setting\n");
  210. goto fail_cpufreq_unregister;
  211. }
  212. ret = drm_vblank_init(dev, 1);
  213. if (ret < 0) {
  214. dev_err(dev->dev, "failed to initialize vblank\n");
  215. goto fail_mode_config_cleanup;
  216. }
  217. pm_runtime_get_sync(dev->dev);
  218. ret = drm_irq_install(dev, platform_get_irq(dev->platformdev, 0));
  219. pm_runtime_put_sync(dev->dev);
  220. if (ret < 0) {
  221. dev_err(dev->dev, "failed to install IRQ handler\n");
  222. goto fail_vblank_cleanup;
  223. }
  224. platform_set_drvdata(pdev, dev);
  225. list_for_each_entry(mod, &module_list, list) {
  226. DBG("%s: preferred_bpp: %d", mod->name, mod->preferred_bpp);
  227. bpp = mod->preferred_bpp;
  228. if (bpp > 0)
  229. break;
  230. }
  231. priv->fbdev = drm_fbdev_cma_init(dev, bpp,
  232. dev->mode_config.num_crtc,
  233. dev->mode_config.num_connector);
  234. if (IS_ERR(priv->fbdev)) {
  235. ret = PTR_ERR(priv->fbdev);
  236. goto fail_irq_uninstall;
  237. }
  238. drm_kms_helper_poll_init(dev);
  239. return 0;
  240. fail_irq_uninstall:
  241. pm_runtime_get_sync(dev->dev);
  242. drm_irq_uninstall(dev);
  243. pm_runtime_put_sync(dev->dev);
  244. fail_vblank_cleanup:
  245. drm_vblank_cleanup(dev);
  246. fail_mode_config_cleanup:
  247. drm_mode_config_cleanup(dev);
  248. fail_cpufreq_unregister:
  249. pm_runtime_disable(dev->dev);
  250. #ifdef CONFIG_CPU_FREQ
  251. cpufreq_unregister_notifier(&priv->freq_transition,
  252. CPUFREQ_TRANSITION_NOTIFIER);
  253. fail_put_disp_clk:
  254. clk_put(priv->disp_clk);
  255. #endif
  256. fail_put_clk:
  257. clk_put(priv->clk);
  258. fail_iounmap:
  259. iounmap(priv->mmio);
  260. fail_free_wq:
  261. flush_workqueue(priv->wq);
  262. destroy_workqueue(priv->wq);
  263. fail_free_priv:
  264. dev->dev_private = NULL;
  265. kfree(priv);
  266. return ret;
  267. }
  268. static void tilcdc_preclose(struct drm_device *dev, struct drm_file *file)
  269. {
  270. struct tilcdc_drm_private *priv = dev->dev_private;
  271. tilcdc_crtc_cancel_page_flip(priv->crtc, file);
  272. }
  273. static void tilcdc_lastclose(struct drm_device *dev)
  274. {
  275. struct tilcdc_drm_private *priv = dev->dev_private;
  276. drm_fbdev_cma_restore_mode(priv->fbdev);
  277. }
  278. static irqreturn_t tilcdc_irq(int irq, void *arg)
  279. {
  280. struct drm_device *dev = arg;
  281. struct tilcdc_drm_private *priv = dev->dev_private;
  282. return tilcdc_crtc_irq(priv->crtc);
  283. }
  284. static void tilcdc_irq_preinstall(struct drm_device *dev)
  285. {
  286. tilcdc_clear_irqstatus(dev, 0xffffffff);
  287. }
  288. static int tilcdc_irq_postinstall(struct drm_device *dev)
  289. {
  290. struct tilcdc_drm_private *priv = dev->dev_private;
  291. /* enable FIFO underflow irq: */
  292. if (priv->rev == 1)
  293. tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_V1_UNDERFLOW_INT_ENA);
  294. else
  295. tilcdc_set(dev, LCDC_INT_ENABLE_SET_REG, LCDC_V2_UNDERFLOW_INT_ENA);
  296. return 0;
  297. }
  298. static void tilcdc_irq_uninstall(struct drm_device *dev)
  299. {
  300. struct tilcdc_drm_private *priv = dev->dev_private;
  301. /* disable irqs that we might have enabled: */
  302. if (priv->rev == 1) {
  303. tilcdc_clear(dev, LCDC_RASTER_CTRL_REG,
  304. LCDC_V1_UNDERFLOW_INT_ENA | LCDC_V1_PL_INT_ENA);
  305. tilcdc_clear(dev, LCDC_DMA_CTRL_REG, LCDC_V1_END_OF_FRAME_INT_ENA);
  306. } else {
  307. tilcdc_clear(dev, LCDC_INT_ENABLE_SET_REG,
  308. LCDC_V2_UNDERFLOW_INT_ENA | LCDC_V2_PL_INT_ENA |
  309. LCDC_V2_END_OF_FRAME0_INT_ENA | LCDC_V2_END_OF_FRAME1_INT_ENA |
  310. LCDC_FRAME_DONE);
  311. }
  312. }
  313. static void enable_vblank(struct drm_device *dev, bool enable)
  314. {
  315. struct tilcdc_drm_private *priv = dev->dev_private;
  316. u32 reg, mask;
  317. if (priv->rev == 1) {
  318. reg = LCDC_DMA_CTRL_REG;
  319. mask = LCDC_V1_END_OF_FRAME_INT_ENA;
  320. } else {
  321. reg = LCDC_INT_ENABLE_SET_REG;
  322. mask = LCDC_V2_END_OF_FRAME0_INT_ENA |
  323. LCDC_V2_END_OF_FRAME1_INT_ENA | LCDC_FRAME_DONE;
  324. }
  325. if (enable)
  326. tilcdc_set(dev, reg, mask);
  327. else
  328. tilcdc_clear(dev, reg, mask);
  329. }
  330. static int tilcdc_enable_vblank(struct drm_device *dev, int crtc)
  331. {
  332. enable_vblank(dev, true);
  333. return 0;
  334. }
  335. static void tilcdc_disable_vblank(struct drm_device *dev, int crtc)
  336. {
  337. enable_vblank(dev, false);
  338. }
  339. #if defined(CONFIG_DEBUG_FS) || defined(CONFIG_PM_SLEEP)
  340. static const struct {
  341. const char *name;
  342. uint8_t rev;
  343. uint8_t save;
  344. uint32_t reg;
  345. } registers[] = {
  346. #define REG(rev, save, reg) { #reg, rev, save, reg }
  347. /* exists in revision 1: */
  348. REG(1, false, LCDC_PID_REG),
  349. REG(1, true, LCDC_CTRL_REG),
  350. REG(1, false, LCDC_STAT_REG),
  351. REG(1, true, LCDC_RASTER_CTRL_REG),
  352. REG(1, true, LCDC_RASTER_TIMING_0_REG),
  353. REG(1, true, LCDC_RASTER_TIMING_1_REG),
  354. REG(1, true, LCDC_RASTER_TIMING_2_REG),
  355. REG(1, true, LCDC_DMA_CTRL_REG),
  356. REG(1, true, LCDC_DMA_FB_BASE_ADDR_0_REG),
  357. REG(1, true, LCDC_DMA_FB_CEILING_ADDR_0_REG),
  358. REG(1, true, LCDC_DMA_FB_BASE_ADDR_1_REG),
  359. REG(1, true, LCDC_DMA_FB_CEILING_ADDR_1_REG),
  360. /* new in revision 2: */
  361. REG(2, false, LCDC_RAW_STAT_REG),
  362. REG(2, false, LCDC_MASKED_STAT_REG),
  363. REG(2, false, LCDC_INT_ENABLE_SET_REG),
  364. REG(2, false, LCDC_INT_ENABLE_CLR_REG),
  365. REG(2, false, LCDC_END_OF_INT_IND_REG),
  366. REG(2, true, LCDC_CLK_ENABLE_REG),
  367. REG(2, true, LCDC_INT_ENABLE_SET_REG),
  368. #undef REG
  369. };
  370. #endif
  371. #ifdef CONFIG_DEBUG_FS
  372. static int tilcdc_regs_show(struct seq_file *m, void *arg)
  373. {
  374. struct drm_info_node *node = (struct drm_info_node *) m->private;
  375. struct drm_device *dev = node->minor->dev;
  376. struct tilcdc_drm_private *priv = dev->dev_private;
  377. unsigned i;
  378. pm_runtime_get_sync(dev->dev);
  379. seq_printf(m, "revision: %d\n", priv->rev);
  380. for (i = 0; i < ARRAY_SIZE(registers); i++)
  381. if (priv->rev >= registers[i].rev)
  382. seq_printf(m, "%s:\t %08x\n", registers[i].name,
  383. tilcdc_read(dev, registers[i].reg));
  384. pm_runtime_put_sync(dev->dev);
  385. return 0;
  386. }
  387. static int tilcdc_mm_show(struct seq_file *m, void *arg)
  388. {
  389. struct drm_info_node *node = (struct drm_info_node *) m->private;
  390. struct drm_device *dev = node->minor->dev;
  391. return drm_mm_dump_table(m, &dev->vma_offset_manager->vm_addr_space_mm);
  392. }
  393. static struct drm_info_list tilcdc_debugfs_list[] = {
  394. { "regs", tilcdc_regs_show, 0 },
  395. { "mm", tilcdc_mm_show, 0 },
  396. { "fb", drm_fb_cma_debugfs_show, 0 },
  397. };
  398. static int tilcdc_debugfs_init(struct drm_minor *minor)
  399. {
  400. struct drm_device *dev = minor->dev;
  401. struct tilcdc_module *mod;
  402. int ret;
  403. ret = drm_debugfs_create_files(tilcdc_debugfs_list,
  404. ARRAY_SIZE(tilcdc_debugfs_list),
  405. minor->debugfs_root, minor);
  406. list_for_each_entry(mod, &module_list, list)
  407. if (mod->funcs->debugfs_init)
  408. mod->funcs->debugfs_init(mod, minor);
  409. if (ret) {
  410. dev_err(dev->dev, "could not install tilcdc_debugfs_list\n");
  411. return ret;
  412. }
  413. return ret;
  414. }
  415. static void tilcdc_debugfs_cleanup(struct drm_minor *minor)
  416. {
  417. struct tilcdc_module *mod;
  418. drm_debugfs_remove_files(tilcdc_debugfs_list,
  419. ARRAY_SIZE(tilcdc_debugfs_list), minor);
  420. list_for_each_entry(mod, &module_list, list)
  421. if (mod->funcs->debugfs_cleanup)
  422. mod->funcs->debugfs_cleanup(mod, minor);
  423. }
  424. #endif
  425. static const struct file_operations fops = {
  426. .owner = THIS_MODULE,
  427. .open = drm_open,
  428. .release = drm_release,
  429. .unlocked_ioctl = drm_ioctl,
  430. #ifdef CONFIG_COMPAT
  431. .compat_ioctl = drm_compat_ioctl,
  432. #endif
  433. .poll = drm_poll,
  434. .read = drm_read,
  435. .llseek = no_llseek,
  436. .mmap = drm_gem_cma_mmap,
  437. };
  438. static struct drm_driver tilcdc_driver = {
  439. .driver_features = DRIVER_HAVE_IRQ | DRIVER_GEM | DRIVER_MODESET,
  440. .load = tilcdc_load,
  441. .unload = tilcdc_unload,
  442. .preclose = tilcdc_preclose,
  443. .lastclose = tilcdc_lastclose,
  444. .set_busid = drm_platform_set_busid,
  445. .irq_handler = tilcdc_irq,
  446. .irq_preinstall = tilcdc_irq_preinstall,
  447. .irq_postinstall = tilcdc_irq_postinstall,
  448. .irq_uninstall = tilcdc_irq_uninstall,
  449. .get_vblank_counter = drm_vblank_count,
  450. .enable_vblank = tilcdc_enable_vblank,
  451. .disable_vblank = tilcdc_disable_vblank,
  452. .gem_free_object = drm_gem_cma_free_object,
  453. .gem_vm_ops = &drm_gem_cma_vm_ops,
  454. .dumb_create = drm_gem_cma_dumb_create,
  455. .dumb_map_offset = drm_gem_cma_dumb_map_offset,
  456. .dumb_destroy = drm_gem_dumb_destroy,
  457. #ifdef CONFIG_DEBUG_FS
  458. .debugfs_init = tilcdc_debugfs_init,
  459. .debugfs_cleanup = tilcdc_debugfs_cleanup,
  460. #endif
  461. .fops = &fops,
  462. .name = "tilcdc",
  463. .desc = "TI LCD Controller DRM",
  464. .date = "20121205",
  465. .major = 1,
  466. .minor = 0,
  467. };
  468. /*
  469. * Power management:
  470. */
  471. #ifdef CONFIG_PM_SLEEP
  472. static int tilcdc_pm_suspend(struct device *dev)
  473. {
  474. struct drm_device *ddev = dev_get_drvdata(dev);
  475. struct tilcdc_drm_private *priv = ddev->dev_private;
  476. unsigned i, n = 0;
  477. drm_kms_helper_poll_disable(ddev);
  478. /* Save register state: */
  479. for (i = 0; i < ARRAY_SIZE(registers); i++)
  480. if (registers[i].save && (priv->rev >= registers[i].rev))
  481. priv->saved_register[n++] = tilcdc_read(ddev, registers[i].reg);
  482. return 0;
  483. }
  484. static int tilcdc_pm_resume(struct device *dev)
  485. {
  486. struct drm_device *ddev = dev_get_drvdata(dev);
  487. struct tilcdc_drm_private *priv = ddev->dev_private;
  488. unsigned i, n = 0;
  489. /* Restore register state: */
  490. for (i = 0; i < ARRAY_SIZE(registers); i++)
  491. if (registers[i].save && (priv->rev >= registers[i].rev))
  492. tilcdc_write(ddev, registers[i].reg, priv->saved_register[n++]);
  493. drm_kms_helper_poll_enable(ddev);
  494. return 0;
  495. }
  496. #endif
  497. static const struct dev_pm_ops tilcdc_pm_ops = {
  498. SET_SYSTEM_SLEEP_PM_OPS(tilcdc_pm_suspend, tilcdc_pm_resume)
  499. };
  500. /*
  501. * Platform driver:
  502. */
  503. static int tilcdc_pdev_probe(struct platform_device *pdev)
  504. {
  505. /* bail out early if no DT data: */
  506. if (!pdev->dev.of_node) {
  507. dev_err(&pdev->dev, "device-tree data is missing\n");
  508. return -ENXIO;
  509. }
  510. /* defer probing if slave is in deferred probing */
  511. if (slave_probing == true)
  512. return -EPROBE_DEFER;
  513. return drm_platform_init(&tilcdc_driver, pdev);
  514. }
  515. static int tilcdc_pdev_remove(struct platform_device *pdev)
  516. {
  517. drm_put_dev(platform_get_drvdata(pdev));
  518. return 0;
  519. }
  520. static struct of_device_id tilcdc_of_match[] = {
  521. { .compatible = "ti,am33xx-tilcdc", },
  522. { },
  523. };
  524. MODULE_DEVICE_TABLE(of, tilcdc_of_match);
  525. static struct platform_driver tilcdc_platform_driver = {
  526. .probe = tilcdc_pdev_probe,
  527. .remove = tilcdc_pdev_remove,
  528. .driver = {
  529. .owner = THIS_MODULE,
  530. .name = "tilcdc",
  531. .pm = &tilcdc_pm_ops,
  532. .of_match_table = tilcdc_of_match,
  533. },
  534. };
  535. static int __init tilcdc_drm_init(void)
  536. {
  537. DBG("init");
  538. tilcdc_tfp410_init();
  539. tilcdc_slave_init();
  540. tilcdc_panel_init();
  541. return platform_driver_register(&tilcdc_platform_driver);
  542. }
  543. static void __exit tilcdc_drm_fini(void)
  544. {
  545. DBG("fini");
  546. platform_driver_unregister(&tilcdc_platform_driver);
  547. tilcdc_panel_fini();
  548. tilcdc_slave_fini();
  549. tilcdc_tfp410_fini();
  550. }
  551. module_init(tilcdc_drm_init);
  552. module_exit(tilcdc_drm_fini);
  553. MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
  554. MODULE_DESCRIPTION("TI LCD Controller DRM Driver");
  555. MODULE_LICENSE("GPL");