igc_hw.h 2.7 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /* Copyright (c) 2018 Intel Corporation */
  3. #ifndef _IGC_HW_H_
  4. #define _IGC_HW_H_
  5. #include <linux/types.h>
  6. #include <linux/if_ether.h>
  7. #include "igc_regs.h"
  8. #include "igc_defines.h"
  9. #include "igc_mac.h"
  10. #include "igc_i225.h"
  11. #include "igc_base.h"
  12. #define IGC_DEV_ID_I225_LM 0x15F2
  13. #define IGC_DEV_ID_I225_V 0x15F3
  14. /* Function pointers for the MAC. */
  15. struct igc_mac_operations {
  16. };
  17. enum igc_mac_type {
  18. igc_undefined = 0,
  19. igc_i225,
  20. igc_num_macs /* List is 1-based, so subtract 1 for true count. */
  21. };
  22. enum igc_phy_type {
  23. igc_phy_unknown = 0,
  24. igc_phy_none,
  25. igc_phy_i225,
  26. };
  27. struct igc_mac_info {
  28. struct igc_mac_operations ops;
  29. u8 addr[ETH_ALEN];
  30. u8 perm_addr[ETH_ALEN];
  31. enum igc_mac_type type;
  32. u32 collision_delta;
  33. u32 ledctl_default;
  34. u32 ledctl_mode1;
  35. u32 ledctl_mode2;
  36. u32 mc_filter_type;
  37. u32 tx_packet_delta;
  38. u32 txcw;
  39. u16 mta_reg_count;
  40. u16 uta_reg_count;
  41. u16 rar_entry_count;
  42. u8 forced_speed_duplex;
  43. bool adaptive_ifs;
  44. bool has_fwsm;
  45. bool arc_subsystem_valid;
  46. bool autoneg;
  47. bool autoneg_failed;
  48. bool get_link_status;
  49. };
  50. struct igc_bus_info {
  51. u16 func;
  52. u16 pci_cmd_word;
  53. };
  54. struct igc_hw {
  55. void *back;
  56. u8 __iomem *hw_addr;
  57. unsigned long io_base;
  58. struct igc_mac_info mac;
  59. struct igc_bus_info bus;
  60. u16 device_id;
  61. u16 subsystem_vendor_id;
  62. u16 subsystem_device_id;
  63. u16 vendor_id;
  64. u8 revision_id;
  65. };
  66. /* Statistics counters collected by the MAC */
  67. struct igc_hw_stats {
  68. u64 crcerrs;
  69. u64 algnerrc;
  70. u64 symerrs;
  71. u64 rxerrc;
  72. u64 mpc;
  73. u64 scc;
  74. u64 ecol;
  75. u64 mcc;
  76. u64 latecol;
  77. u64 colc;
  78. u64 dc;
  79. u64 tncrs;
  80. u64 sec;
  81. u64 cexterr;
  82. u64 rlec;
  83. u64 xonrxc;
  84. u64 xontxc;
  85. u64 xoffrxc;
  86. u64 xofftxc;
  87. u64 fcruc;
  88. u64 prc64;
  89. u64 prc127;
  90. u64 prc255;
  91. u64 prc511;
  92. u64 prc1023;
  93. u64 prc1522;
  94. u64 gprc;
  95. u64 bprc;
  96. u64 mprc;
  97. u64 gptc;
  98. u64 gorc;
  99. u64 gotc;
  100. u64 rnbc;
  101. u64 ruc;
  102. u64 rfc;
  103. u64 roc;
  104. u64 rjc;
  105. u64 mgprc;
  106. u64 mgpdc;
  107. u64 mgptc;
  108. u64 tor;
  109. u64 tot;
  110. u64 tpr;
  111. u64 tpt;
  112. u64 ptc64;
  113. u64 ptc127;
  114. u64 ptc255;
  115. u64 ptc511;
  116. u64 ptc1023;
  117. u64 ptc1522;
  118. u64 mptc;
  119. u64 bptc;
  120. u64 tsctc;
  121. u64 tsctfc;
  122. u64 iac;
  123. u64 icrxptc;
  124. u64 icrxatc;
  125. u64 ictxptc;
  126. u64 ictxatc;
  127. u64 ictxqec;
  128. u64 ictxqmtc;
  129. u64 icrxdmtc;
  130. u64 icrxoc;
  131. u64 cbtmpc;
  132. u64 htdpmc;
  133. u64 cbrdpc;
  134. u64 cbrmpc;
  135. u64 rpthc;
  136. u64 hgptc;
  137. u64 htcbdpc;
  138. u64 hgorc;
  139. u64 hgotc;
  140. u64 lenerrs;
  141. u64 scvpc;
  142. u64 hrmpc;
  143. u64 doosync;
  144. u64 o2bgptc;
  145. u64 o2bspc;
  146. u64 b2ospc;
  147. u64 b2ogprc;
  148. };
  149. s32 igc_read_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value);
  150. s32 igc_write_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value);
  151. void igc_read_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value);
  152. void igc_write_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value);
  153. #endif /* _IGC_HW_H_ */