i40e_common.c 167 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /* Copyright(c) 2013 - 2018 Intel Corporation. */
  3. #include "i40e_type.h"
  4. #include "i40e_adminq.h"
  5. #include "i40e_prototype.h"
  6. #include <linux/avf/virtchnl.h>
  7. /**
  8. * i40e_set_mac_type - Sets MAC type
  9. * @hw: pointer to the HW structure
  10. *
  11. * This function sets the mac type of the adapter based on the
  12. * vendor ID and device ID stored in the hw structure.
  13. **/
  14. static i40e_status i40e_set_mac_type(struct i40e_hw *hw)
  15. {
  16. i40e_status status = 0;
  17. if (hw->vendor_id == PCI_VENDOR_ID_INTEL) {
  18. switch (hw->device_id) {
  19. case I40E_DEV_ID_SFP_XL710:
  20. case I40E_DEV_ID_QEMU:
  21. case I40E_DEV_ID_KX_B:
  22. case I40E_DEV_ID_KX_C:
  23. case I40E_DEV_ID_QSFP_A:
  24. case I40E_DEV_ID_QSFP_B:
  25. case I40E_DEV_ID_QSFP_C:
  26. case I40E_DEV_ID_10G_BASE_T:
  27. case I40E_DEV_ID_10G_BASE_T4:
  28. case I40E_DEV_ID_20G_KR2:
  29. case I40E_DEV_ID_20G_KR2_A:
  30. case I40E_DEV_ID_25G_B:
  31. case I40E_DEV_ID_25G_SFP28:
  32. hw->mac.type = I40E_MAC_XL710;
  33. break;
  34. case I40E_DEV_ID_KX_X722:
  35. case I40E_DEV_ID_QSFP_X722:
  36. case I40E_DEV_ID_SFP_X722:
  37. case I40E_DEV_ID_1G_BASE_T_X722:
  38. case I40E_DEV_ID_10G_BASE_T_X722:
  39. case I40E_DEV_ID_SFP_I_X722:
  40. hw->mac.type = I40E_MAC_X722;
  41. break;
  42. default:
  43. hw->mac.type = I40E_MAC_GENERIC;
  44. break;
  45. }
  46. } else {
  47. status = I40E_ERR_DEVICE_NOT_SUPPORTED;
  48. }
  49. hw_dbg(hw, "i40e_set_mac_type found mac: %d, returns: %d\n",
  50. hw->mac.type, status);
  51. return status;
  52. }
  53. /**
  54. * i40e_aq_str - convert AQ err code to a string
  55. * @hw: pointer to the HW structure
  56. * @aq_err: the AQ error code to convert
  57. **/
  58. const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
  59. {
  60. switch (aq_err) {
  61. case I40E_AQ_RC_OK:
  62. return "OK";
  63. case I40E_AQ_RC_EPERM:
  64. return "I40E_AQ_RC_EPERM";
  65. case I40E_AQ_RC_ENOENT:
  66. return "I40E_AQ_RC_ENOENT";
  67. case I40E_AQ_RC_ESRCH:
  68. return "I40E_AQ_RC_ESRCH";
  69. case I40E_AQ_RC_EINTR:
  70. return "I40E_AQ_RC_EINTR";
  71. case I40E_AQ_RC_EIO:
  72. return "I40E_AQ_RC_EIO";
  73. case I40E_AQ_RC_ENXIO:
  74. return "I40E_AQ_RC_ENXIO";
  75. case I40E_AQ_RC_E2BIG:
  76. return "I40E_AQ_RC_E2BIG";
  77. case I40E_AQ_RC_EAGAIN:
  78. return "I40E_AQ_RC_EAGAIN";
  79. case I40E_AQ_RC_ENOMEM:
  80. return "I40E_AQ_RC_ENOMEM";
  81. case I40E_AQ_RC_EACCES:
  82. return "I40E_AQ_RC_EACCES";
  83. case I40E_AQ_RC_EFAULT:
  84. return "I40E_AQ_RC_EFAULT";
  85. case I40E_AQ_RC_EBUSY:
  86. return "I40E_AQ_RC_EBUSY";
  87. case I40E_AQ_RC_EEXIST:
  88. return "I40E_AQ_RC_EEXIST";
  89. case I40E_AQ_RC_EINVAL:
  90. return "I40E_AQ_RC_EINVAL";
  91. case I40E_AQ_RC_ENOTTY:
  92. return "I40E_AQ_RC_ENOTTY";
  93. case I40E_AQ_RC_ENOSPC:
  94. return "I40E_AQ_RC_ENOSPC";
  95. case I40E_AQ_RC_ENOSYS:
  96. return "I40E_AQ_RC_ENOSYS";
  97. case I40E_AQ_RC_ERANGE:
  98. return "I40E_AQ_RC_ERANGE";
  99. case I40E_AQ_RC_EFLUSHED:
  100. return "I40E_AQ_RC_EFLUSHED";
  101. case I40E_AQ_RC_BAD_ADDR:
  102. return "I40E_AQ_RC_BAD_ADDR";
  103. case I40E_AQ_RC_EMODE:
  104. return "I40E_AQ_RC_EMODE";
  105. case I40E_AQ_RC_EFBIG:
  106. return "I40E_AQ_RC_EFBIG";
  107. }
  108. snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
  109. return hw->err_str;
  110. }
  111. /**
  112. * i40e_stat_str - convert status err code to a string
  113. * @hw: pointer to the HW structure
  114. * @stat_err: the status error code to convert
  115. **/
  116. const char *i40e_stat_str(struct i40e_hw *hw, i40e_status stat_err)
  117. {
  118. switch (stat_err) {
  119. case 0:
  120. return "OK";
  121. case I40E_ERR_NVM:
  122. return "I40E_ERR_NVM";
  123. case I40E_ERR_NVM_CHECKSUM:
  124. return "I40E_ERR_NVM_CHECKSUM";
  125. case I40E_ERR_PHY:
  126. return "I40E_ERR_PHY";
  127. case I40E_ERR_CONFIG:
  128. return "I40E_ERR_CONFIG";
  129. case I40E_ERR_PARAM:
  130. return "I40E_ERR_PARAM";
  131. case I40E_ERR_MAC_TYPE:
  132. return "I40E_ERR_MAC_TYPE";
  133. case I40E_ERR_UNKNOWN_PHY:
  134. return "I40E_ERR_UNKNOWN_PHY";
  135. case I40E_ERR_LINK_SETUP:
  136. return "I40E_ERR_LINK_SETUP";
  137. case I40E_ERR_ADAPTER_STOPPED:
  138. return "I40E_ERR_ADAPTER_STOPPED";
  139. case I40E_ERR_INVALID_MAC_ADDR:
  140. return "I40E_ERR_INVALID_MAC_ADDR";
  141. case I40E_ERR_DEVICE_NOT_SUPPORTED:
  142. return "I40E_ERR_DEVICE_NOT_SUPPORTED";
  143. case I40E_ERR_MASTER_REQUESTS_PENDING:
  144. return "I40E_ERR_MASTER_REQUESTS_PENDING";
  145. case I40E_ERR_INVALID_LINK_SETTINGS:
  146. return "I40E_ERR_INVALID_LINK_SETTINGS";
  147. case I40E_ERR_AUTONEG_NOT_COMPLETE:
  148. return "I40E_ERR_AUTONEG_NOT_COMPLETE";
  149. case I40E_ERR_RESET_FAILED:
  150. return "I40E_ERR_RESET_FAILED";
  151. case I40E_ERR_SWFW_SYNC:
  152. return "I40E_ERR_SWFW_SYNC";
  153. case I40E_ERR_NO_AVAILABLE_VSI:
  154. return "I40E_ERR_NO_AVAILABLE_VSI";
  155. case I40E_ERR_NO_MEMORY:
  156. return "I40E_ERR_NO_MEMORY";
  157. case I40E_ERR_BAD_PTR:
  158. return "I40E_ERR_BAD_PTR";
  159. case I40E_ERR_RING_FULL:
  160. return "I40E_ERR_RING_FULL";
  161. case I40E_ERR_INVALID_PD_ID:
  162. return "I40E_ERR_INVALID_PD_ID";
  163. case I40E_ERR_INVALID_QP_ID:
  164. return "I40E_ERR_INVALID_QP_ID";
  165. case I40E_ERR_INVALID_CQ_ID:
  166. return "I40E_ERR_INVALID_CQ_ID";
  167. case I40E_ERR_INVALID_CEQ_ID:
  168. return "I40E_ERR_INVALID_CEQ_ID";
  169. case I40E_ERR_INVALID_AEQ_ID:
  170. return "I40E_ERR_INVALID_AEQ_ID";
  171. case I40E_ERR_INVALID_SIZE:
  172. return "I40E_ERR_INVALID_SIZE";
  173. case I40E_ERR_INVALID_ARP_INDEX:
  174. return "I40E_ERR_INVALID_ARP_INDEX";
  175. case I40E_ERR_INVALID_FPM_FUNC_ID:
  176. return "I40E_ERR_INVALID_FPM_FUNC_ID";
  177. case I40E_ERR_QP_INVALID_MSG_SIZE:
  178. return "I40E_ERR_QP_INVALID_MSG_SIZE";
  179. case I40E_ERR_QP_TOOMANY_WRS_POSTED:
  180. return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
  181. case I40E_ERR_INVALID_FRAG_COUNT:
  182. return "I40E_ERR_INVALID_FRAG_COUNT";
  183. case I40E_ERR_QUEUE_EMPTY:
  184. return "I40E_ERR_QUEUE_EMPTY";
  185. case I40E_ERR_INVALID_ALIGNMENT:
  186. return "I40E_ERR_INVALID_ALIGNMENT";
  187. case I40E_ERR_FLUSHED_QUEUE:
  188. return "I40E_ERR_FLUSHED_QUEUE";
  189. case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
  190. return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
  191. case I40E_ERR_INVALID_IMM_DATA_SIZE:
  192. return "I40E_ERR_INVALID_IMM_DATA_SIZE";
  193. case I40E_ERR_TIMEOUT:
  194. return "I40E_ERR_TIMEOUT";
  195. case I40E_ERR_OPCODE_MISMATCH:
  196. return "I40E_ERR_OPCODE_MISMATCH";
  197. case I40E_ERR_CQP_COMPL_ERROR:
  198. return "I40E_ERR_CQP_COMPL_ERROR";
  199. case I40E_ERR_INVALID_VF_ID:
  200. return "I40E_ERR_INVALID_VF_ID";
  201. case I40E_ERR_INVALID_HMCFN_ID:
  202. return "I40E_ERR_INVALID_HMCFN_ID";
  203. case I40E_ERR_BACKING_PAGE_ERROR:
  204. return "I40E_ERR_BACKING_PAGE_ERROR";
  205. case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
  206. return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
  207. case I40E_ERR_INVALID_PBLE_INDEX:
  208. return "I40E_ERR_INVALID_PBLE_INDEX";
  209. case I40E_ERR_INVALID_SD_INDEX:
  210. return "I40E_ERR_INVALID_SD_INDEX";
  211. case I40E_ERR_INVALID_PAGE_DESC_INDEX:
  212. return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
  213. case I40E_ERR_INVALID_SD_TYPE:
  214. return "I40E_ERR_INVALID_SD_TYPE";
  215. case I40E_ERR_MEMCPY_FAILED:
  216. return "I40E_ERR_MEMCPY_FAILED";
  217. case I40E_ERR_INVALID_HMC_OBJ_INDEX:
  218. return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
  219. case I40E_ERR_INVALID_HMC_OBJ_COUNT:
  220. return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
  221. case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
  222. return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
  223. case I40E_ERR_SRQ_ENABLED:
  224. return "I40E_ERR_SRQ_ENABLED";
  225. case I40E_ERR_ADMIN_QUEUE_ERROR:
  226. return "I40E_ERR_ADMIN_QUEUE_ERROR";
  227. case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
  228. return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
  229. case I40E_ERR_BUF_TOO_SHORT:
  230. return "I40E_ERR_BUF_TOO_SHORT";
  231. case I40E_ERR_ADMIN_QUEUE_FULL:
  232. return "I40E_ERR_ADMIN_QUEUE_FULL";
  233. case I40E_ERR_ADMIN_QUEUE_NO_WORK:
  234. return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
  235. case I40E_ERR_BAD_IWARP_CQE:
  236. return "I40E_ERR_BAD_IWARP_CQE";
  237. case I40E_ERR_NVM_BLANK_MODE:
  238. return "I40E_ERR_NVM_BLANK_MODE";
  239. case I40E_ERR_NOT_IMPLEMENTED:
  240. return "I40E_ERR_NOT_IMPLEMENTED";
  241. case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
  242. return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
  243. case I40E_ERR_DIAG_TEST_FAILED:
  244. return "I40E_ERR_DIAG_TEST_FAILED";
  245. case I40E_ERR_NOT_READY:
  246. return "I40E_ERR_NOT_READY";
  247. case I40E_NOT_SUPPORTED:
  248. return "I40E_NOT_SUPPORTED";
  249. case I40E_ERR_FIRMWARE_API_VERSION:
  250. return "I40E_ERR_FIRMWARE_API_VERSION";
  251. case I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR:
  252. return "I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR";
  253. }
  254. snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
  255. return hw->err_str;
  256. }
  257. /**
  258. * i40e_debug_aq
  259. * @hw: debug mask related to admin queue
  260. * @mask: debug mask
  261. * @desc: pointer to admin queue descriptor
  262. * @buffer: pointer to command buffer
  263. * @buf_len: max length of buffer
  264. *
  265. * Dumps debug log about adminq command with descriptor contents.
  266. **/
  267. void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
  268. void *buffer, u16 buf_len)
  269. {
  270. struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
  271. u16 len;
  272. u8 *buf = (u8 *)buffer;
  273. if ((!(mask & hw->debug_mask)) || (desc == NULL))
  274. return;
  275. len = le16_to_cpu(aq_desc->datalen);
  276. i40e_debug(hw, mask,
  277. "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
  278. le16_to_cpu(aq_desc->opcode),
  279. le16_to_cpu(aq_desc->flags),
  280. le16_to_cpu(aq_desc->datalen),
  281. le16_to_cpu(aq_desc->retval));
  282. i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
  283. le32_to_cpu(aq_desc->cookie_high),
  284. le32_to_cpu(aq_desc->cookie_low));
  285. i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
  286. le32_to_cpu(aq_desc->params.internal.param0),
  287. le32_to_cpu(aq_desc->params.internal.param1));
  288. i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
  289. le32_to_cpu(aq_desc->params.external.addr_high),
  290. le32_to_cpu(aq_desc->params.external.addr_low));
  291. if ((buffer != NULL) && (aq_desc->datalen != 0)) {
  292. i40e_debug(hw, mask, "AQ CMD Buffer:\n");
  293. if (buf_len < len)
  294. len = buf_len;
  295. /* write the full 16-byte chunks */
  296. if (hw->debug_mask & mask) {
  297. char prefix[27];
  298. snprintf(prefix, sizeof(prefix),
  299. "i40e %02x:%02x.%x: \t0x",
  300. hw->bus.bus_id,
  301. hw->bus.device,
  302. hw->bus.func);
  303. print_hex_dump(KERN_INFO, prefix, DUMP_PREFIX_OFFSET,
  304. 16, 1, buf, len, false);
  305. }
  306. }
  307. }
  308. /**
  309. * i40e_check_asq_alive
  310. * @hw: pointer to the hw struct
  311. *
  312. * Returns true if Queue is enabled else false.
  313. **/
  314. bool i40e_check_asq_alive(struct i40e_hw *hw)
  315. {
  316. if (hw->aq.asq.len)
  317. return !!(rd32(hw, hw->aq.asq.len) &
  318. I40E_PF_ATQLEN_ATQENABLE_MASK);
  319. else
  320. return false;
  321. }
  322. /**
  323. * i40e_aq_queue_shutdown
  324. * @hw: pointer to the hw struct
  325. * @unloading: is the driver unloading itself
  326. *
  327. * Tell the Firmware that we're shutting down the AdminQ and whether
  328. * or not the driver is unloading as well.
  329. **/
  330. i40e_status i40e_aq_queue_shutdown(struct i40e_hw *hw,
  331. bool unloading)
  332. {
  333. struct i40e_aq_desc desc;
  334. struct i40e_aqc_queue_shutdown *cmd =
  335. (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
  336. i40e_status status;
  337. i40e_fill_default_direct_cmd_desc(&desc,
  338. i40e_aqc_opc_queue_shutdown);
  339. if (unloading)
  340. cmd->driver_unloading = cpu_to_le32(I40E_AQ_DRIVER_UNLOADING);
  341. status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
  342. return status;
  343. }
  344. /**
  345. * i40e_aq_get_set_rss_lut
  346. * @hw: pointer to the hardware structure
  347. * @vsi_id: vsi fw index
  348. * @pf_lut: for PF table set true, for VSI table set false
  349. * @lut: pointer to the lut buffer provided by the caller
  350. * @lut_size: size of the lut buffer
  351. * @set: set true to set the table, false to get the table
  352. *
  353. * Internal function to get or set RSS look up table
  354. **/
  355. static i40e_status i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
  356. u16 vsi_id, bool pf_lut,
  357. u8 *lut, u16 lut_size,
  358. bool set)
  359. {
  360. i40e_status status;
  361. struct i40e_aq_desc desc;
  362. struct i40e_aqc_get_set_rss_lut *cmd_resp =
  363. (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
  364. if (set)
  365. i40e_fill_default_direct_cmd_desc(&desc,
  366. i40e_aqc_opc_set_rss_lut);
  367. else
  368. i40e_fill_default_direct_cmd_desc(&desc,
  369. i40e_aqc_opc_get_rss_lut);
  370. /* Indirect command */
  371. desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
  372. desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
  373. cmd_resp->vsi_id =
  374. cpu_to_le16((u16)((vsi_id <<
  375. I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
  376. I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
  377. cmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
  378. if (pf_lut)
  379. cmd_resp->flags |= cpu_to_le16((u16)
  380. ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
  381. I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
  382. I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
  383. else
  384. cmd_resp->flags |= cpu_to_le16((u16)
  385. ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
  386. I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
  387. I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
  388. status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
  389. return status;
  390. }
  391. /**
  392. * i40e_aq_get_rss_lut
  393. * @hw: pointer to the hardware structure
  394. * @vsi_id: vsi fw index
  395. * @pf_lut: for PF table set true, for VSI table set false
  396. * @lut: pointer to the lut buffer provided by the caller
  397. * @lut_size: size of the lut buffer
  398. *
  399. * get the RSS lookup table, PF or VSI type
  400. **/
  401. i40e_status i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
  402. bool pf_lut, u8 *lut, u16 lut_size)
  403. {
  404. return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
  405. false);
  406. }
  407. /**
  408. * i40e_aq_set_rss_lut
  409. * @hw: pointer to the hardware structure
  410. * @vsi_id: vsi fw index
  411. * @pf_lut: for PF table set true, for VSI table set false
  412. * @lut: pointer to the lut buffer provided by the caller
  413. * @lut_size: size of the lut buffer
  414. *
  415. * set the RSS lookup table, PF or VSI type
  416. **/
  417. i40e_status i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
  418. bool pf_lut, u8 *lut, u16 lut_size)
  419. {
  420. return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
  421. }
  422. /**
  423. * i40e_aq_get_set_rss_key
  424. * @hw: pointer to the hw struct
  425. * @vsi_id: vsi fw index
  426. * @key: pointer to key info struct
  427. * @set: set true to set the key, false to get the key
  428. *
  429. * get the RSS key per VSI
  430. **/
  431. static i40e_status i40e_aq_get_set_rss_key(struct i40e_hw *hw,
  432. u16 vsi_id,
  433. struct i40e_aqc_get_set_rss_key_data *key,
  434. bool set)
  435. {
  436. i40e_status status;
  437. struct i40e_aq_desc desc;
  438. struct i40e_aqc_get_set_rss_key *cmd_resp =
  439. (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
  440. u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
  441. if (set)
  442. i40e_fill_default_direct_cmd_desc(&desc,
  443. i40e_aqc_opc_set_rss_key);
  444. else
  445. i40e_fill_default_direct_cmd_desc(&desc,
  446. i40e_aqc_opc_get_rss_key);
  447. /* Indirect command */
  448. desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
  449. desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
  450. cmd_resp->vsi_id =
  451. cpu_to_le16((u16)((vsi_id <<
  452. I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
  453. I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
  454. cmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
  455. status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
  456. return status;
  457. }
  458. /**
  459. * i40e_aq_get_rss_key
  460. * @hw: pointer to the hw struct
  461. * @vsi_id: vsi fw index
  462. * @key: pointer to key info struct
  463. *
  464. **/
  465. i40e_status i40e_aq_get_rss_key(struct i40e_hw *hw,
  466. u16 vsi_id,
  467. struct i40e_aqc_get_set_rss_key_data *key)
  468. {
  469. return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
  470. }
  471. /**
  472. * i40e_aq_set_rss_key
  473. * @hw: pointer to the hw struct
  474. * @vsi_id: vsi fw index
  475. * @key: pointer to key info struct
  476. *
  477. * set the RSS key per VSI
  478. **/
  479. i40e_status i40e_aq_set_rss_key(struct i40e_hw *hw,
  480. u16 vsi_id,
  481. struct i40e_aqc_get_set_rss_key_data *key)
  482. {
  483. return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
  484. }
  485. /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
  486. * hardware to a bit-field that can be used by SW to more easily determine the
  487. * packet type.
  488. *
  489. * Macros are used to shorten the table lines and make this table human
  490. * readable.
  491. *
  492. * We store the PTYPE in the top byte of the bit field - this is just so that
  493. * we can check that the table doesn't have a row missing, as the index into
  494. * the table should be the PTYPE.
  495. *
  496. * Typical work flow:
  497. *
  498. * IF NOT i40e_ptype_lookup[ptype].known
  499. * THEN
  500. * Packet is unknown
  501. * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
  502. * Use the rest of the fields to look at the tunnels, inner protocols, etc
  503. * ELSE
  504. * Use the enum i40e_rx_l2_ptype to decode the packet type
  505. * ENDIF
  506. */
  507. /* macro to make the table lines short */
  508. #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
  509. { PTYPE, \
  510. 1, \
  511. I40E_RX_PTYPE_OUTER_##OUTER_IP, \
  512. I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
  513. I40E_RX_PTYPE_##OUTER_FRAG, \
  514. I40E_RX_PTYPE_TUNNEL_##T, \
  515. I40E_RX_PTYPE_TUNNEL_END_##TE, \
  516. I40E_RX_PTYPE_##TEF, \
  517. I40E_RX_PTYPE_INNER_PROT_##I, \
  518. I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
  519. #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
  520. { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
  521. /* shorter macros makes the table fit but are terse */
  522. #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
  523. #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
  524. #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
  525. /* Lookup table mapping the HW PTYPE to the bit field for decoding */
  526. struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
  527. /* L2 Packet types */
  528. I40E_PTT_UNUSED_ENTRY(0),
  529. I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
  530. I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
  531. I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
  532. I40E_PTT_UNUSED_ENTRY(4),
  533. I40E_PTT_UNUSED_ENTRY(5),
  534. I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
  535. I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
  536. I40E_PTT_UNUSED_ENTRY(8),
  537. I40E_PTT_UNUSED_ENTRY(9),
  538. I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
  539. I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
  540. I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
  541. I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
  542. I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
  543. I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
  544. I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
  545. I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
  546. I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
  547. I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
  548. I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
  549. I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
  550. /* Non Tunneled IPv4 */
  551. I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
  552. I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
  553. I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
  554. I40E_PTT_UNUSED_ENTRY(25),
  555. I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
  556. I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
  557. I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
  558. /* IPv4 --> IPv4 */
  559. I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
  560. I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
  561. I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
  562. I40E_PTT_UNUSED_ENTRY(32),
  563. I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
  564. I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
  565. I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
  566. /* IPv4 --> IPv6 */
  567. I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
  568. I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
  569. I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
  570. I40E_PTT_UNUSED_ENTRY(39),
  571. I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
  572. I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
  573. I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
  574. /* IPv4 --> GRE/NAT */
  575. I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
  576. /* IPv4 --> GRE/NAT --> IPv4 */
  577. I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
  578. I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
  579. I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
  580. I40E_PTT_UNUSED_ENTRY(47),
  581. I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
  582. I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
  583. I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
  584. /* IPv4 --> GRE/NAT --> IPv6 */
  585. I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
  586. I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
  587. I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
  588. I40E_PTT_UNUSED_ENTRY(54),
  589. I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
  590. I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
  591. I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
  592. /* IPv4 --> GRE/NAT --> MAC */
  593. I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
  594. /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
  595. I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
  596. I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
  597. I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
  598. I40E_PTT_UNUSED_ENTRY(62),
  599. I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
  600. I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
  601. I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
  602. /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
  603. I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
  604. I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
  605. I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
  606. I40E_PTT_UNUSED_ENTRY(69),
  607. I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
  608. I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
  609. I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
  610. /* IPv4 --> GRE/NAT --> MAC/VLAN */
  611. I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
  612. /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
  613. I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
  614. I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
  615. I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
  616. I40E_PTT_UNUSED_ENTRY(77),
  617. I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
  618. I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
  619. I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
  620. /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
  621. I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
  622. I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
  623. I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
  624. I40E_PTT_UNUSED_ENTRY(84),
  625. I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
  626. I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
  627. I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
  628. /* Non Tunneled IPv6 */
  629. I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
  630. I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
  631. I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY4),
  632. I40E_PTT_UNUSED_ENTRY(91),
  633. I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
  634. I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
  635. I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
  636. /* IPv6 --> IPv4 */
  637. I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
  638. I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
  639. I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
  640. I40E_PTT_UNUSED_ENTRY(98),
  641. I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
  642. I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
  643. I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
  644. /* IPv6 --> IPv6 */
  645. I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
  646. I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
  647. I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
  648. I40E_PTT_UNUSED_ENTRY(105),
  649. I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
  650. I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
  651. I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
  652. /* IPv6 --> GRE/NAT */
  653. I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
  654. /* IPv6 --> GRE/NAT -> IPv4 */
  655. I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
  656. I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
  657. I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
  658. I40E_PTT_UNUSED_ENTRY(113),
  659. I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
  660. I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
  661. I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
  662. /* IPv6 --> GRE/NAT -> IPv6 */
  663. I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
  664. I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
  665. I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
  666. I40E_PTT_UNUSED_ENTRY(120),
  667. I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
  668. I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
  669. I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
  670. /* IPv6 --> GRE/NAT -> MAC */
  671. I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
  672. /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
  673. I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
  674. I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
  675. I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
  676. I40E_PTT_UNUSED_ENTRY(128),
  677. I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
  678. I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
  679. I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
  680. /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
  681. I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
  682. I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
  683. I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
  684. I40E_PTT_UNUSED_ENTRY(135),
  685. I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
  686. I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
  687. I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
  688. /* IPv6 --> GRE/NAT -> MAC/VLAN */
  689. I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
  690. /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
  691. I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
  692. I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
  693. I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
  694. I40E_PTT_UNUSED_ENTRY(143),
  695. I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
  696. I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
  697. I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
  698. /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
  699. I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
  700. I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
  701. I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
  702. I40E_PTT_UNUSED_ENTRY(150),
  703. I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
  704. I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
  705. I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
  706. /* unused entries */
  707. I40E_PTT_UNUSED_ENTRY(154),
  708. I40E_PTT_UNUSED_ENTRY(155),
  709. I40E_PTT_UNUSED_ENTRY(156),
  710. I40E_PTT_UNUSED_ENTRY(157),
  711. I40E_PTT_UNUSED_ENTRY(158),
  712. I40E_PTT_UNUSED_ENTRY(159),
  713. I40E_PTT_UNUSED_ENTRY(160),
  714. I40E_PTT_UNUSED_ENTRY(161),
  715. I40E_PTT_UNUSED_ENTRY(162),
  716. I40E_PTT_UNUSED_ENTRY(163),
  717. I40E_PTT_UNUSED_ENTRY(164),
  718. I40E_PTT_UNUSED_ENTRY(165),
  719. I40E_PTT_UNUSED_ENTRY(166),
  720. I40E_PTT_UNUSED_ENTRY(167),
  721. I40E_PTT_UNUSED_ENTRY(168),
  722. I40E_PTT_UNUSED_ENTRY(169),
  723. I40E_PTT_UNUSED_ENTRY(170),
  724. I40E_PTT_UNUSED_ENTRY(171),
  725. I40E_PTT_UNUSED_ENTRY(172),
  726. I40E_PTT_UNUSED_ENTRY(173),
  727. I40E_PTT_UNUSED_ENTRY(174),
  728. I40E_PTT_UNUSED_ENTRY(175),
  729. I40E_PTT_UNUSED_ENTRY(176),
  730. I40E_PTT_UNUSED_ENTRY(177),
  731. I40E_PTT_UNUSED_ENTRY(178),
  732. I40E_PTT_UNUSED_ENTRY(179),
  733. I40E_PTT_UNUSED_ENTRY(180),
  734. I40E_PTT_UNUSED_ENTRY(181),
  735. I40E_PTT_UNUSED_ENTRY(182),
  736. I40E_PTT_UNUSED_ENTRY(183),
  737. I40E_PTT_UNUSED_ENTRY(184),
  738. I40E_PTT_UNUSED_ENTRY(185),
  739. I40E_PTT_UNUSED_ENTRY(186),
  740. I40E_PTT_UNUSED_ENTRY(187),
  741. I40E_PTT_UNUSED_ENTRY(188),
  742. I40E_PTT_UNUSED_ENTRY(189),
  743. I40E_PTT_UNUSED_ENTRY(190),
  744. I40E_PTT_UNUSED_ENTRY(191),
  745. I40E_PTT_UNUSED_ENTRY(192),
  746. I40E_PTT_UNUSED_ENTRY(193),
  747. I40E_PTT_UNUSED_ENTRY(194),
  748. I40E_PTT_UNUSED_ENTRY(195),
  749. I40E_PTT_UNUSED_ENTRY(196),
  750. I40E_PTT_UNUSED_ENTRY(197),
  751. I40E_PTT_UNUSED_ENTRY(198),
  752. I40E_PTT_UNUSED_ENTRY(199),
  753. I40E_PTT_UNUSED_ENTRY(200),
  754. I40E_PTT_UNUSED_ENTRY(201),
  755. I40E_PTT_UNUSED_ENTRY(202),
  756. I40E_PTT_UNUSED_ENTRY(203),
  757. I40E_PTT_UNUSED_ENTRY(204),
  758. I40E_PTT_UNUSED_ENTRY(205),
  759. I40E_PTT_UNUSED_ENTRY(206),
  760. I40E_PTT_UNUSED_ENTRY(207),
  761. I40E_PTT_UNUSED_ENTRY(208),
  762. I40E_PTT_UNUSED_ENTRY(209),
  763. I40E_PTT_UNUSED_ENTRY(210),
  764. I40E_PTT_UNUSED_ENTRY(211),
  765. I40E_PTT_UNUSED_ENTRY(212),
  766. I40E_PTT_UNUSED_ENTRY(213),
  767. I40E_PTT_UNUSED_ENTRY(214),
  768. I40E_PTT_UNUSED_ENTRY(215),
  769. I40E_PTT_UNUSED_ENTRY(216),
  770. I40E_PTT_UNUSED_ENTRY(217),
  771. I40E_PTT_UNUSED_ENTRY(218),
  772. I40E_PTT_UNUSED_ENTRY(219),
  773. I40E_PTT_UNUSED_ENTRY(220),
  774. I40E_PTT_UNUSED_ENTRY(221),
  775. I40E_PTT_UNUSED_ENTRY(222),
  776. I40E_PTT_UNUSED_ENTRY(223),
  777. I40E_PTT_UNUSED_ENTRY(224),
  778. I40E_PTT_UNUSED_ENTRY(225),
  779. I40E_PTT_UNUSED_ENTRY(226),
  780. I40E_PTT_UNUSED_ENTRY(227),
  781. I40E_PTT_UNUSED_ENTRY(228),
  782. I40E_PTT_UNUSED_ENTRY(229),
  783. I40E_PTT_UNUSED_ENTRY(230),
  784. I40E_PTT_UNUSED_ENTRY(231),
  785. I40E_PTT_UNUSED_ENTRY(232),
  786. I40E_PTT_UNUSED_ENTRY(233),
  787. I40E_PTT_UNUSED_ENTRY(234),
  788. I40E_PTT_UNUSED_ENTRY(235),
  789. I40E_PTT_UNUSED_ENTRY(236),
  790. I40E_PTT_UNUSED_ENTRY(237),
  791. I40E_PTT_UNUSED_ENTRY(238),
  792. I40E_PTT_UNUSED_ENTRY(239),
  793. I40E_PTT_UNUSED_ENTRY(240),
  794. I40E_PTT_UNUSED_ENTRY(241),
  795. I40E_PTT_UNUSED_ENTRY(242),
  796. I40E_PTT_UNUSED_ENTRY(243),
  797. I40E_PTT_UNUSED_ENTRY(244),
  798. I40E_PTT_UNUSED_ENTRY(245),
  799. I40E_PTT_UNUSED_ENTRY(246),
  800. I40E_PTT_UNUSED_ENTRY(247),
  801. I40E_PTT_UNUSED_ENTRY(248),
  802. I40E_PTT_UNUSED_ENTRY(249),
  803. I40E_PTT_UNUSED_ENTRY(250),
  804. I40E_PTT_UNUSED_ENTRY(251),
  805. I40E_PTT_UNUSED_ENTRY(252),
  806. I40E_PTT_UNUSED_ENTRY(253),
  807. I40E_PTT_UNUSED_ENTRY(254),
  808. I40E_PTT_UNUSED_ENTRY(255)
  809. };
  810. /**
  811. * i40e_init_shared_code - Initialize the shared code
  812. * @hw: pointer to hardware structure
  813. *
  814. * This assigns the MAC type and PHY code and inits the NVM.
  815. * Does not touch the hardware. This function must be called prior to any
  816. * other function in the shared code. The i40e_hw structure should be
  817. * memset to 0 prior to calling this function. The following fields in
  818. * hw structure should be filled in prior to calling this function:
  819. * hw_addr, back, device_id, vendor_id, subsystem_device_id,
  820. * subsystem_vendor_id, and revision_id
  821. **/
  822. i40e_status i40e_init_shared_code(struct i40e_hw *hw)
  823. {
  824. i40e_status status = 0;
  825. u32 port, ari, func_rid;
  826. i40e_set_mac_type(hw);
  827. switch (hw->mac.type) {
  828. case I40E_MAC_XL710:
  829. case I40E_MAC_X722:
  830. break;
  831. default:
  832. return I40E_ERR_DEVICE_NOT_SUPPORTED;
  833. }
  834. hw->phy.get_link_info = true;
  835. /* Determine port number and PF number*/
  836. port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
  837. >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
  838. hw->port = (u8)port;
  839. ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
  840. I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
  841. func_rid = rd32(hw, I40E_PF_FUNC_RID);
  842. if (ari)
  843. hw->pf_id = (u8)(func_rid & 0xff);
  844. else
  845. hw->pf_id = (u8)(func_rid & 0x7);
  846. if (hw->mac.type == I40E_MAC_X722)
  847. hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE |
  848. I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK;
  849. status = i40e_init_nvm(hw);
  850. return status;
  851. }
  852. /**
  853. * i40e_aq_mac_address_read - Retrieve the MAC addresses
  854. * @hw: pointer to the hw struct
  855. * @flags: a return indicator of what addresses were added to the addr store
  856. * @addrs: the requestor's mac addr store
  857. * @cmd_details: pointer to command details structure or NULL
  858. **/
  859. static i40e_status i40e_aq_mac_address_read(struct i40e_hw *hw,
  860. u16 *flags,
  861. struct i40e_aqc_mac_address_read_data *addrs,
  862. struct i40e_asq_cmd_details *cmd_details)
  863. {
  864. struct i40e_aq_desc desc;
  865. struct i40e_aqc_mac_address_read *cmd_data =
  866. (struct i40e_aqc_mac_address_read *)&desc.params.raw;
  867. i40e_status status;
  868. i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
  869. desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF);
  870. status = i40e_asq_send_command(hw, &desc, addrs,
  871. sizeof(*addrs), cmd_details);
  872. *flags = le16_to_cpu(cmd_data->command_flags);
  873. return status;
  874. }
  875. /**
  876. * i40e_aq_mac_address_write - Change the MAC addresses
  877. * @hw: pointer to the hw struct
  878. * @flags: indicates which MAC to be written
  879. * @mac_addr: address to write
  880. * @cmd_details: pointer to command details structure or NULL
  881. **/
  882. i40e_status i40e_aq_mac_address_write(struct i40e_hw *hw,
  883. u16 flags, u8 *mac_addr,
  884. struct i40e_asq_cmd_details *cmd_details)
  885. {
  886. struct i40e_aq_desc desc;
  887. struct i40e_aqc_mac_address_write *cmd_data =
  888. (struct i40e_aqc_mac_address_write *)&desc.params.raw;
  889. i40e_status status;
  890. i40e_fill_default_direct_cmd_desc(&desc,
  891. i40e_aqc_opc_mac_address_write);
  892. cmd_data->command_flags = cpu_to_le16(flags);
  893. cmd_data->mac_sah = cpu_to_le16((u16)mac_addr[0] << 8 | mac_addr[1]);
  894. cmd_data->mac_sal = cpu_to_le32(((u32)mac_addr[2] << 24) |
  895. ((u32)mac_addr[3] << 16) |
  896. ((u32)mac_addr[4] << 8) |
  897. mac_addr[5]);
  898. status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
  899. return status;
  900. }
  901. /**
  902. * i40e_get_mac_addr - get MAC address
  903. * @hw: pointer to the HW structure
  904. * @mac_addr: pointer to MAC address
  905. *
  906. * Reads the adapter's MAC address from register
  907. **/
  908. i40e_status i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
  909. {
  910. struct i40e_aqc_mac_address_read_data addrs;
  911. i40e_status status;
  912. u16 flags = 0;
  913. status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
  914. if (flags & I40E_AQC_LAN_ADDR_VALID)
  915. ether_addr_copy(mac_addr, addrs.pf_lan_mac);
  916. return status;
  917. }
  918. /**
  919. * i40e_get_port_mac_addr - get Port MAC address
  920. * @hw: pointer to the HW structure
  921. * @mac_addr: pointer to Port MAC address
  922. *
  923. * Reads the adapter's Port MAC address
  924. **/
  925. i40e_status i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
  926. {
  927. struct i40e_aqc_mac_address_read_data addrs;
  928. i40e_status status;
  929. u16 flags = 0;
  930. status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
  931. if (status)
  932. return status;
  933. if (flags & I40E_AQC_PORT_ADDR_VALID)
  934. ether_addr_copy(mac_addr, addrs.port_mac);
  935. else
  936. status = I40E_ERR_INVALID_MAC_ADDR;
  937. return status;
  938. }
  939. /**
  940. * i40e_pre_tx_queue_cfg - pre tx queue configure
  941. * @hw: pointer to the HW structure
  942. * @queue: target PF queue index
  943. * @enable: state change request
  944. *
  945. * Handles hw requirement to indicate intention to enable
  946. * or disable target queue.
  947. **/
  948. void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
  949. {
  950. u32 abs_queue_idx = hw->func_caps.base_queue + queue;
  951. u32 reg_block = 0;
  952. u32 reg_val;
  953. if (abs_queue_idx >= 128) {
  954. reg_block = abs_queue_idx / 128;
  955. abs_queue_idx %= 128;
  956. }
  957. reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
  958. reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
  959. reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
  960. if (enable)
  961. reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
  962. else
  963. reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
  964. wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
  965. }
  966. /**
  967. * i40e_read_pba_string - Reads part number string from EEPROM
  968. * @hw: pointer to hardware structure
  969. * @pba_num: stores the part number string from the EEPROM
  970. * @pba_num_size: part number string buffer length
  971. *
  972. * Reads the part number string from the EEPROM.
  973. **/
  974. i40e_status i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
  975. u32 pba_num_size)
  976. {
  977. i40e_status status = 0;
  978. u16 pba_word = 0;
  979. u16 pba_size = 0;
  980. u16 pba_ptr = 0;
  981. u16 i = 0;
  982. status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
  983. if (status || (pba_word != 0xFAFA)) {
  984. hw_dbg(hw, "Failed to read PBA flags or flag is invalid.\n");
  985. return status;
  986. }
  987. status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
  988. if (status) {
  989. hw_dbg(hw, "Failed to read PBA Block pointer.\n");
  990. return status;
  991. }
  992. status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
  993. if (status) {
  994. hw_dbg(hw, "Failed to read PBA Block size.\n");
  995. return status;
  996. }
  997. /* Subtract one to get PBA word count (PBA Size word is included in
  998. * total size)
  999. */
  1000. pba_size--;
  1001. if (pba_num_size < (((u32)pba_size * 2) + 1)) {
  1002. hw_dbg(hw, "Buffer to small for PBA data.\n");
  1003. return I40E_ERR_PARAM;
  1004. }
  1005. for (i = 0; i < pba_size; i++) {
  1006. status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
  1007. if (status) {
  1008. hw_dbg(hw, "Failed to read PBA Block word %d.\n", i);
  1009. return status;
  1010. }
  1011. pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
  1012. pba_num[(i * 2) + 1] = pba_word & 0xFF;
  1013. }
  1014. pba_num[(pba_size * 2)] = '\0';
  1015. return status;
  1016. }
  1017. /**
  1018. * i40e_get_media_type - Gets media type
  1019. * @hw: pointer to the hardware structure
  1020. **/
  1021. static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
  1022. {
  1023. enum i40e_media_type media;
  1024. switch (hw->phy.link_info.phy_type) {
  1025. case I40E_PHY_TYPE_10GBASE_SR:
  1026. case I40E_PHY_TYPE_10GBASE_LR:
  1027. case I40E_PHY_TYPE_1000BASE_SX:
  1028. case I40E_PHY_TYPE_1000BASE_LX:
  1029. case I40E_PHY_TYPE_40GBASE_SR4:
  1030. case I40E_PHY_TYPE_40GBASE_LR4:
  1031. case I40E_PHY_TYPE_25GBASE_LR:
  1032. case I40E_PHY_TYPE_25GBASE_SR:
  1033. media = I40E_MEDIA_TYPE_FIBER;
  1034. break;
  1035. case I40E_PHY_TYPE_100BASE_TX:
  1036. case I40E_PHY_TYPE_1000BASE_T:
  1037. case I40E_PHY_TYPE_10GBASE_T:
  1038. media = I40E_MEDIA_TYPE_BASET;
  1039. break;
  1040. case I40E_PHY_TYPE_10GBASE_CR1_CU:
  1041. case I40E_PHY_TYPE_40GBASE_CR4_CU:
  1042. case I40E_PHY_TYPE_10GBASE_CR1:
  1043. case I40E_PHY_TYPE_40GBASE_CR4:
  1044. case I40E_PHY_TYPE_10GBASE_SFPP_CU:
  1045. case I40E_PHY_TYPE_40GBASE_AOC:
  1046. case I40E_PHY_TYPE_10GBASE_AOC:
  1047. case I40E_PHY_TYPE_25GBASE_CR:
  1048. case I40E_PHY_TYPE_25GBASE_AOC:
  1049. case I40E_PHY_TYPE_25GBASE_ACC:
  1050. media = I40E_MEDIA_TYPE_DA;
  1051. break;
  1052. case I40E_PHY_TYPE_1000BASE_KX:
  1053. case I40E_PHY_TYPE_10GBASE_KX4:
  1054. case I40E_PHY_TYPE_10GBASE_KR:
  1055. case I40E_PHY_TYPE_40GBASE_KR4:
  1056. case I40E_PHY_TYPE_20GBASE_KR2:
  1057. case I40E_PHY_TYPE_25GBASE_KR:
  1058. media = I40E_MEDIA_TYPE_BACKPLANE;
  1059. break;
  1060. case I40E_PHY_TYPE_SGMII:
  1061. case I40E_PHY_TYPE_XAUI:
  1062. case I40E_PHY_TYPE_XFI:
  1063. case I40E_PHY_TYPE_XLAUI:
  1064. case I40E_PHY_TYPE_XLPPI:
  1065. default:
  1066. media = I40E_MEDIA_TYPE_UNKNOWN;
  1067. break;
  1068. }
  1069. return media;
  1070. }
  1071. /**
  1072. * i40e_poll_globr - Poll for Global Reset completion
  1073. * @hw: pointer to the hardware structure
  1074. * @retry_limit: how many times to retry before failure
  1075. **/
  1076. static i40e_status i40e_poll_globr(struct i40e_hw *hw,
  1077. u32 retry_limit)
  1078. {
  1079. u32 cnt, reg = 0;
  1080. for (cnt = 0; cnt < retry_limit; cnt++) {
  1081. reg = rd32(hw, I40E_GLGEN_RSTAT);
  1082. if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
  1083. return 0;
  1084. msleep(100);
  1085. }
  1086. hw_dbg(hw, "Global reset failed.\n");
  1087. hw_dbg(hw, "I40E_GLGEN_RSTAT = 0x%x\n", reg);
  1088. return I40E_ERR_RESET_FAILED;
  1089. }
  1090. #define I40E_PF_RESET_WAIT_COUNT_A0 200
  1091. #define I40E_PF_RESET_WAIT_COUNT 200
  1092. /**
  1093. * i40e_pf_reset - Reset the PF
  1094. * @hw: pointer to the hardware structure
  1095. *
  1096. * Assuming someone else has triggered a global reset,
  1097. * assure the global reset is complete and then reset the PF
  1098. **/
  1099. i40e_status i40e_pf_reset(struct i40e_hw *hw)
  1100. {
  1101. u32 cnt = 0;
  1102. u32 cnt1 = 0;
  1103. u32 reg = 0;
  1104. u32 grst_del;
  1105. /* Poll for Global Reset steady state in case of recent GRST.
  1106. * The grst delay value is in 100ms units, and we'll wait a
  1107. * couple counts longer to be sure we don't just miss the end.
  1108. */
  1109. grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
  1110. I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
  1111. I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
  1112. /* It can take upto 15 secs for GRST steady state.
  1113. * Bump it to 16 secs max to be safe.
  1114. */
  1115. grst_del = grst_del * 20;
  1116. for (cnt = 0; cnt < grst_del; cnt++) {
  1117. reg = rd32(hw, I40E_GLGEN_RSTAT);
  1118. if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
  1119. break;
  1120. msleep(100);
  1121. }
  1122. if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
  1123. hw_dbg(hw, "Global reset polling failed to complete.\n");
  1124. return I40E_ERR_RESET_FAILED;
  1125. }
  1126. /* Now Wait for the FW to be ready */
  1127. for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
  1128. reg = rd32(hw, I40E_GLNVM_ULD);
  1129. reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
  1130. I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
  1131. if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
  1132. I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
  1133. hw_dbg(hw, "Core and Global modules ready %d\n", cnt1);
  1134. break;
  1135. }
  1136. usleep_range(10000, 20000);
  1137. }
  1138. if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
  1139. I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
  1140. hw_dbg(hw, "wait for FW Reset complete timedout\n");
  1141. hw_dbg(hw, "I40E_GLNVM_ULD = 0x%x\n", reg);
  1142. return I40E_ERR_RESET_FAILED;
  1143. }
  1144. /* If there was a Global Reset in progress when we got here,
  1145. * we don't need to do the PF Reset
  1146. */
  1147. if (!cnt) {
  1148. u32 reg2 = 0;
  1149. if (hw->revision_id == 0)
  1150. cnt = I40E_PF_RESET_WAIT_COUNT_A0;
  1151. else
  1152. cnt = I40E_PF_RESET_WAIT_COUNT;
  1153. reg = rd32(hw, I40E_PFGEN_CTRL);
  1154. wr32(hw, I40E_PFGEN_CTRL,
  1155. (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
  1156. for (; cnt; cnt--) {
  1157. reg = rd32(hw, I40E_PFGEN_CTRL);
  1158. if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
  1159. break;
  1160. reg2 = rd32(hw, I40E_GLGEN_RSTAT);
  1161. if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK)
  1162. break;
  1163. usleep_range(1000, 2000);
  1164. }
  1165. if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
  1166. if (i40e_poll_globr(hw, grst_del))
  1167. return I40E_ERR_RESET_FAILED;
  1168. } else if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
  1169. hw_dbg(hw, "PF reset polling failed to complete.\n");
  1170. return I40E_ERR_RESET_FAILED;
  1171. }
  1172. }
  1173. i40e_clear_pxe_mode(hw);
  1174. return 0;
  1175. }
  1176. /**
  1177. * i40e_clear_hw - clear out any left over hw state
  1178. * @hw: pointer to the hw struct
  1179. *
  1180. * Clear queues and interrupts, typically called at init time,
  1181. * but after the capabilities have been found so we know how many
  1182. * queues and msix vectors have been allocated.
  1183. **/
  1184. void i40e_clear_hw(struct i40e_hw *hw)
  1185. {
  1186. u32 num_queues, base_queue;
  1187. u32 num_pf_int;
  1188. u32 num_vf_int;
  1189. u32 num_vfs;
  1190. u32 i, j;
  1191. u32 val;
  1192. u32 eol = 0x7ff;
  1193. /* get number of interrupts, queues, and VFs */
  1194. val = rd32(hw, I40E_GLPCI_CNF2);
  1195. num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
  1196. I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
  1197. num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
  1198. I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
  1199. val = rd32(hw, I40E_PFLAN_QALLOC);
  1200. base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
  1201. I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
  1202. j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
  1203. I40E_PFLAN_QALLOC_LASTQ_SHIFT;
  1204. if (val & I40E_PFLAN_QALLOC_VALID_MASK)
  1205. num_queues = (j - base_queue) + 1;
  1206. else
  1207. num_queues = 0;
  1208. val = rd32(hw, I40E_PF_VT_PFALLOC);
  1209. i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
  1210. I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
  1211. j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
  1212. I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
  1213. if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
  1214. num_vfs = (j - i) + 1;
  1215. else
  1216. num_vfs = 0;
  1217. /* stop all the interrupts */
  1218. wr32(hw, I40E_PFINT_ICR0_ENA, 0);
  1219. val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
  1220. for (i = 0; i < num_pf_int - 2; i++)
  1221. wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
  1222. /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
  1223. val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
  1224. wr32(hw, I40E_PFINT_LNKLST0, val);
  1225. for (i = 0; i < num_pf_int - 2; i++)
  1226. wr32(hw, I40E_PFINT_LNKLSTN(i), val);
  1227. val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
  1228. for (i = 0; i < num_vfs; i++)
  1229. wr32(hw, I40E_VPINT_LNKLST0(i), val);
  1230. for (i = 0; i < num_vf_int - 2; i++)
  1231. wr32(hw, I40E_VPINT_LNKLSTN(i), val);
  1232. /* warn the HW of the coming Tx disables */
  1233. for (i = 0; i < num_queues; i++) {
  1234. u32 abs_queue_idx = base_queue + i;
  1235. u32 reg_block = 0;
  1236. if (abs_queue_idx >= 128) {
  1237. reg_block = abs_queue_idx / 128;
  1238. abs_queue_idx %= 128;
  1239. }
  1240. val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
  1241. val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
  1242. val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
  1243. val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
  1244. wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
  1245. }
  1246. udelay(400);
  1247. /* stop all the queues */
  1248. for (i = 0; i < num_queues; i++) {
  1249. wr32(hw, I40E_QINT_TQCTL(i), 0);
  1250. wr32(hw, I40E_QTX_ENA(i), 0);
  1251. wr32(hw, I40E_QINT_RQCTL(i), 0);
  1252. wr32(hw, I40E_QRX_ENA(i), 0);
  1253. }
  1254. /* short wait for all queue disables to settle */
  1255. udelay(50);
  1256. }
  1257. /**
  1258. * i40e_clear_pxe_mode - clear pxe operations mode
  1259. * @hw: pointer to the hw struct
  1260. *
  1261. * Make sure all PXE mode settings are cleared, including things
  1262. * like descriptor fetch/write-back mode.
  1263. **/
  1264. void i40e_clear_pxe_mode(struct i40e_hw *hw)
  1265. {
  1266. u32 reg;
  1267. if (i40e_check_asq_alive(hw))
  1268. i40e_aq_clear_pxe_mode(hw, NULL);
  1269. /* Clear single descriptor fetch/write-back mode */
  1270. reg = rd32(hw, I40E_GLLAN_RCTL_0);
  1271. if (hw->revision_id == 0) {
  1272. /* As a work around clear PXE_MODE instead of setting it */
  1273. wr32(hw, I40E_GLLAN_RCTL_0, (reg & (~I40E_GLLAN_RCTL_0_PXE_MODE_MASK)));
  1274. } else {
  1275. wr32(hw, I40E_GLLAN_RCTL_0, (reg | I40E_GLLAN_RCTL_0_PXE_MODE_MASK));
  1276. }
  1277. }
  1278. /**
  1279. * i40e_led_is_mine - helper to find matching led
  1280. * @hw: pointer to the hw struct
  1281. * @idx: index into GPIO registers
  1282. *
  1283. * returns: 0 if no match, otherwise the value of the GPIO_CTL register
  1284. */
  1285. static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
  1286. {
  1287. u32 gpio_val = 0;
  1288. u32 port;
  1289. if (!hw->func_caps.led[idx])
  1290. return 0;
  1291. gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
  1292. port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
  1293. I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
  1294. /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
  1295. * if it is not our port then ignore
  1296. */
  1297. if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
  1298. (port != hw->port))
  1299. return 0;
  1300. return gpio_val;
  1301. }
  1302. #define I40E_COMBINED_ACTIVITY 0xA
  1303. #define I40E_FILTER_ACTIVITY 0xE
  1304. #define I40E_LINK_ACTIVITY 0xC
  1305. #define I40E_MAC_ACTIVITY 0xD
  1306. #define I40E_LED0 22
  1307. /**
  1308. * i40e_led_get - return current on/off mode
  1309. * @hw: pointer to the hw struct
  1310. *
  1311. * The value returned is the 'mode' field as defined in the
  1312. * GPIO register definitions: 0x0 = off, 0xf = on, and other
  1313. * values are variations of possible behaviors relating to
  1314. * blink, link, and wire.
  1315. **/
  1316. u32 i40e_led_get(struct i40e_hw *hw)
  1317. {
  1318. u32 current_mode = 0;
  1319. u32 mode = 0;
  1320. int i;
  1321. /* as per the documentation GPIO 22-29 are the LED
  1322. * GPIO pins named LED0..LED7
  1323. */
  1324. for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
  1325. u32 gpio_val = i40e_led_is_mine(hw, i);
  1326. if (!gpio_val)
  1327. continue;
  1328. /* ignore gpio LED src mode entries related to the activity
  1329. * LEDs
  1330. */
  1331. current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
  1332. >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
  1333. switch (current_mode) {
  1334. case I40E_COMBINED_ACTIVITY:
  1335. case I40E_FILTER_ACTIVITY:
  1336. case I40E_MAC_ACTIVITY:
  1337. case I40E_LINK_ACTIVITY:
  1338. continue;
  1339. default:
  1340. break;
  1341. }
  1342. mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
  1343. I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
  1344. break;
  1345. }
  1346. return mode;
  1347. }
  1348. /**
  1349. * i40e_led_set - set new on/off mode
  1350. * @hw: pointer to the hw struct
  1351. * @mode: 0=off, 0xf=on (else see manual for mode details)
  1352. * @blink: true if the LED should blink when on, false if steady
  1353. *
  1354. * if this function is used to turn on the blink it should
  1355. * be used to disable the blink when restoring the original state.
  1356. **/
  1357. void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
  1358. {
  1359. u32 current_mode = 0;
  1360. int i;
  1361. if (mode & 0xfffffff0)
  1362. hw_dbg(hw, "invalid mode passed in %X\n", mode);
  1363. /* as per the documentation GPIO 22-29 are the LED
  1364. * GPIO pins named LED0..LED7
  1365. */
  1366. for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
  1367. u32 gpio_val = i40e_led_is_mine(hw, i);
  1368. if (!gpio_val)
  1369. continue;
  1370. /* ignore gpio LED src mode entries related to the activity
  1371. * LEDs
  1372. */
  1373. current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
  1374. >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
  1375. switch (current_mode) {
  1376. case I40E_COMBINED_ACTIVITY:
  1377. case I40E_FILTER_ACTIVITY:
  1378. case I40E_MAC_ACTIVITY:
  1379. case I40E_LINK_ACTIVITY:
  1380. continue;
  1381. default:
  1382. break;
  1383. }
  1384. gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
  1385. /* this & is a bit of paranoia, but serves as a range check */
  1386. gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
  1387. I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
  1388. if (blink)
  1389. gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
  1390. else
  1391. gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
  1392. wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
  1393. break;
  1394. }
  1395. }
  1396. /* Admin command wrappers */
  1397. /**
  1398. * i40e_aq_get_phy_capabilities
  1399. * @hw: pointer to the hw struct
  1400. * @abilities: structure for PHY capabilities to be filled
  1401. * @qualified_modules: report Qualified Modules
  1402. * @report_init: report init capabilities (active are default)
  1403. * @cmd_details: pointer to command details structure or NULL
  1404. *
  1405. * Returns the various PHY abilities supported on the Port.
  1406. **/
  1407. i40e_status i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
  1408. bool qualified_modules, bool report_init,
  1409. struct i40e_aq_get_phy_abilities_resp *abilities,
  1410. struct i40e_asq_cmd_details *cmd_details)
  1411. {
  1412. struct i40e_aq_desc desc;
  1413. i40e_status status;
  1414. u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
  1415. u16 max_delay = I40E_MAX_PHY_TIMEOUT, total_delay = 0;
  1416. if (!abilities)
  1417. return I40E_ERR_PARAM;
  1418. do {
  1419. i40e_fill_default_direct_cmd_desc(&desc,
  1420. i40e_aqc_opc_get_phy_abilities);
  1421. desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
  1422. if (abilities_size > I40E_AQ_LARGE_BUF)
  1423. desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
  1424. if (qualified_modules)
  1425. desc.params.external.param0 |=
  1426. cpu_to_le32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
  1427. if (report_init)
  1428. desc.params.external.param0 |=
  1429. cpu_to_le32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
  1430. status = i40e_asq_send_command(hw, &desc, abilities,
  1431. abilities_size, cmd_details);
  1432. if (status)
  1433. break;
  1434. if (hw->aq.asq_last_status == I40E_AQ_RC_EIO) {
  1435. status = I40E_ERR_UNKNOWN_PHY;
  1436. break;
  1437. } else if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN) {
  1438. usleep_range(1000, 2000);
  1439. total_delay++;
  1440. status = I40E_ERR_TIMEOUT;
  1441. }
  1442. } while ((hw->aq.asq_last_status != I40E_AQ_RC_OK) &&
  1443. (total_delay < max_delay));
  1444. if (status)
  1445. return status;
  1446. if (report_init) {
  1447. if (hw->mac.type == I40E_MAC_XL710 &&
  1448. hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
  1449. hw->aq.api_min_ver >= I40E_MINOR_VER_GET_LINK_INFO_XL710) {
  1450. status = i40e_aq_get_link_info(hw, true, NULL, NULL);
  1451. } else {
  1452. hw->phy.phy_types = le32_to_cpu(abilities->phy_type);
  1453. hw->phy.phy_types |=
  1454. ((u64)abilities->phy_type_ext << 32);
  1455. }
  1456. }
  1457. return status;
  1458. }
  1459. /**
  1460. * i40e_aq_set_phy_config
  1461. * @hw: pointer to the hw struct
  1462. * @config: structure with PHY configuration to be set
  1463. * @cmd_details: pointer to command details structure or NULL
  1464. *
  1465. * Set the various PHY configuration parameters
  1466. * supported on the Port.One or more of the Set PHY config parameters may be
  1467. * ignored in an MFP mode as the PF may not have the privilege to set some
  1468. * of the PHY Config parameters. This status will be indicated by the
  1469. * command response.
  1470. **/
  1471. enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
  1472. struct i40e_aq_set_phy_config *config,
  1473. struct i40e_asq_cmd_details *cmd_details)
  1474. {
  1475. struct i40e_aq_desc desc;
  1476. struct i40e_aq_set_phy_config *cmd =
  1477. (struct i40e_aq_set_phy_config *)&desc.params.raw;
  1478. enum i40e_status_code status;
  1479. if (!config)
  1480. return I40E_ERR_PARAM;
  1481. i40e_fill_default_direct_cmd_desc(&desc,
  1482. i40e_aqc_opc_set_phy_config);
  1483. *cmd = *config;
  1484. status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
  1485. return status;
  1486. }
  1487. /**
  1488. * i40e_set_fc
  1489. * @hw: pointer to the hw struct
  1490. * @aq_failures: buffer to return AdminQ failure information
  1491. * @atomic_restart: whether to enable atomic link restart
  1492. *
  1493. * Set the requested flow control mode using set_phy_config.
  1494. **/
  1495. enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
  1496. bool atomic_restart)
  1497. {
  1498. enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
  1499. struct i40e_aq_get_phy_abilities_resp abilities;
  1500. struct i40e_aq_set_phy_config config;
  1501. enum i40e_status_code status;
  1502. u8 pause_mask = 0x0;
  1503. *aq_failures = 0x0;
  1504. switch (fc_mode) {
  1505. case I40E_FC_FULL:
  1506. pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
  1507. pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
  1508. break;
  1509. case I40E_FC_RX_PAUSE:
  1510. pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
  1511. break;
  1512. case I40E_FC_TX_PAUSE:
  1513. pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
  1514. break;
  1515. default:
  1516. break;
  1517. }
  1518. /* Get the current phy config */
  1519. status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
  1520. NULL);
  1521. if (status) {
  1522. *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
  1523. return status;
  1524. }
  1525. memset(&config, 0, sizeof(struct i40e_aq_set_phy_config));
  1526. /* clear the old pause settings */
  1527. config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
  1528. ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
  1529. /* set the new abilities */
  1530. config.abilities |= pause_mask;
  1531. /* If the abilities have changed, then set the new config */
  1532. if (config.abilities != abilities.abilities) {
  1533. /* Auto restart link so settings take effect */
  1534. if (atomic_restart)
  1535. config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
  1536. /* Copy over all the old settings */
  1537. config.phy_type = abilities.phy_type;
  1538. config.phy_type_ext = abilities.phy_type_ext;
  1539. config.link_speed = abilities.link_speed;
  1540. config.eee_capability = abilities.eee_capability;
  1541. config.eeer = abilities.eeer_val;
  1542. config.low_power_ctrl = abilities.d3_lpan;
  1543. config.fec_config = abilities.fec_cfg_curr_mod_ext_info &
  1544. I40E_AQ_PHY_FEC_CONFIG_MASK;
  1545. status = i40e_aq_set_phy_config(hw, &config, NULL);
  1546. if (status)
  1547. *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
  1548. }
  1549. /* Update the link info */
  1550. status = i40e_update_link_info(hw);
  1551. if (status) {
  1552. /* Wait a little bit (on 40G cards it sometimes takes a really
  1553. * long time for link to come back from the atomic reset)
  1554. * and try once more
  1555. */
  1556. msleep(1000);
  1557. status = i40e_update_link_info(hw);
  1558. }
  1559. if (status)
  1560. *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
  1561. return status;
  1562. }
  1563. /**
  1564. * i40e_aq_clear_pxe_mode
  1565. * @hw: pointer to the hw struct
  1566. * @cmd_details: pointer to command details structure or NULL
  1567. *
  1568. * Tell the firmware that the driver is taking over from PXE
  1569. **/
  1570. i40e_status i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
  1571. struct i40e_asq_cmd_details *cmd_details)
  1572. {
  1573. i40e_status status;
  1574. struct i40e_aq_desc desc;
  1575. struct i40e_aqc_clear_pxe *cmd =
  1576. (struct i40e_aqc_clear_pxe *)&desc.params.raw;
  1577. i40e_fill_default_direct_cmd_desc(&desc,
  1578. i40e_aqc_opc_clear_pxe_mode);
  1579. cmd->rx_cnt = 0x2;
  1580. status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
  1581. wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
  1582. return status;
  1583. }
  1584. /**
  1585. * i40e_aq_set_link_restart_an
  1586. * @hw: pointer to the hw struct
  1587. * @enable_link: if true: enable link, if false: disable link
  1588. * @cmd_details: pointer to command details structure or NULL
  1589. *
  1590. * Sets up the link and restarts the Auto-Negotiation over the link.
  1591. **/
  1592. i40e_status i40e_aq_set_link_restart_an(struct i40e_hw *hw,
  1593. bool enable_link,
  1594. struct i40e_asq_cmd_details *cmd_details)
  1595. {
  1596. struct i40e_aq_desc desc;
  1597. struct i40e_aqc_set_link_restart_an *cmd =
  1598. (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
  1599. i40e_status status;
  1600. i40e_fill_default_direct_cmd_desc(&desc,
  1601. i40e_aqc_opc_set_link_restart_an);
  1602. cmd->command = I40E_AQ_PHY_RESTART_AN;
  1603. if (enable_link)
  1604. cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
  1605. else
  1606. cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
  1607. status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
  1608. return status;
  1609. }
  1610. /**
  1611. * i40e_aq_get_link_info
  1612. * @hw: pointer to the hw struct
  1613. * @enable_lse: enable/disable LinkStatusEvent reporting
  1614. * @link: pointer to link status structure - optional
  1615. * @cmd_details: pointer to command details structure or NULL
  1616. *
  1617. * Returns the link status of the adapter.
  1618. **/
  1619. i40e_status i40e_aq_get_link_info(struct i40e_hw *hw,
  1620. bool enable_lse, struct i40e_link_status *link,
  1621. struct i40e_asq_cmd_details *cmd_details)
  1622. {
  1623. struct i40e_aq_desc desc;
  1624. struct i40e_aqc_get_link_status *resp =
  1625. (struct i40e_aqc_get_link_status *)&desc.params.raw;
  1626. struct i40e_link_status *hw_link_info = &hw->phy.link_info;
  1627. i40e_status status;
  1628. bool tx_pause, rx_pause;
  1629. u16 command_flags;
  1630. i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
  1631. if (enable_lse)
  1632. command_flags = I40E_AQ_LSE_ENABLE;
  1633. else
  1634. command_flags = I40E_AQ_LSE_DISABLE;
  1635. resp->command_flags = cpu_to_le16(command_flags);
  1636. status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
  1637. if (status)
  1638. goto aq_get_link_info_exit;
  1639. /* save off old link status information */
  1640. hw->phy.link_info_old = *hw_link_info;
  1641. /* update link status */
  1642. hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
  1643. hw->phy.media_type = i40e_get_media_type(hw);
  1644. hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
  1645. hw_link_info->link_info = resp->link_info;
  1646. hw_link_info->an_info = resp->an_info;
  1647. hw_link_info->fec_info = resp->config & (I40E_AQ_CONFIG_FEC_KR_ENA |
  1648. I40E_AQ_CONFIG_FEC_RS_ENA);
  1649. hw_link_info->ext_info = resp->ext_info;
  1650. hw_link_info->loopback = resp->loopback & I40E_AQ_LOOPBACK_MASK;
  1651. hw_link_info->max_frame_size = le16_to_cpu(resp->max_frame_size);
  1652. hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
  1653. /* update fc info */
  1654. tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
  1655. rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
  1656. if (tx_pause & rx_pause)
  1657. hw->fc.current_mode = I40E_FC_FULL;
  1658. else if (tx_pause)
  1659. hw->fc.current_mode = I40E_FC_TX_PAUSE;
  1660. else if (rx_pause)
  1661. hw->fc.current_mode = I40E_FC_RX_PAUSE;
  1662. else
  1663. hw->fc.current_mode = I40E_FC_NONE;
  1664. if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
  1665. hw_link_info->crc_enable = true;
  1666. else
  1667. hw_link_info->crc_enable = false;
  1668. if (resp->command_flags & cpu_to_le16(I40E_AQ_LSE_IS_ENABLED))
  1669. hw_link_info->lse_enable = true;
  1670. else
  1671. hw_link_info->lse_enable = false;
  1672. if ((hw->mac.type == I40E_MAC_XL710) &&
  1673. (hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
  1674. hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
  1675. hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
  1676. if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
  1677. hw->aq.api_min_ver >= 7) {
  1678. __le32 tmp;
  1679. memcpy(&tmp, resp->link_type, sizeof(tmp));
  1680. hw->phy.phy_types = le32_to_cpu(tmp);
  1681. hw->phy.phy_types |= ((u64)resp->link_type_ext << 32);
  1682. }
  1683. /* save link status information */
  1684. if (link)
  1685. *link = *hw_link_info;
  1686. /* flag cleared so helper functions don't call AQ again */
  1687. hw->phy.get_link_info = false;
  1688. aq_get_link_info_exit:
  1689. return status;
  1690. }
  1691. /**
  1692. * i40e_aq_set_phy_int_mask
  1693. * @hw: pointer to the hw struct
  1694. * @mask: interrupt mask to be set
  1695. * @cmd_details: pointer to command details structure or NULL
  1696. *
  1697. * Set link interrupt mask.
  1698. **/
  1699. i40e_status i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
  1700. u16 mask,
  1701. struct i40e_asq_cmd_details *cmd_details)
  1702. {
  1703. struct i40e_aq_desc desc;
  1704. struct i40e_aqc_set_phy_int_mask *cmd =
  1705. (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
  1706. i40e_status status;
  1707. i40e_fill_default_direct_cmd_desc(&desc,
  1708. i40e_aqc_opc_set_phy_int_mask);
  1709. cmd->event_mask = cpu_to_le16(mask);
  1710. status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
  1711. return status;
  1712. }
  1713. /**
  1714. * i40e_aq_set_phy_debug
  1715. * @hw: pointer to the hw struct
  1716. * @cmd_flags: debug command flags
  1717. * @cmd_details: pointer to command details structure or NULL
  1718. *
  1719. * Reset the external PHY.
  1720. **/
  1721. i40e_status i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
  1722. struct i40e_asq_cmd_details *cmd_details)
  1723. {
  1724. struct i40e_aq_desc desc;
  1725. struct i40e_aqc_set_phy_debug *cmd =
  1726. (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
  1727. i40e_status status;
  1728. i40e_fill_default_direct_cmd_desc(&desc,
  1729. i40e_aqc_opc_set_phy_debug);
  1730. cmd->command_flags = cmd_flags;
  1731. status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
  1732. return status;
  1733. }
  1734. /**
  1735. * i40e_aq_add_vsi
  1736. * @hw: pointer to the hw struct
  1737. * @vsi_ctx: pointer to a vsi context struct
  1738. * @cmd_details: pointer to command details structure or NULL
  1739. *
  1740. * Add a VSI context to the hardware.
  1741. **/
  1742. i40e_status i40e_aq_add_vsi(struct i40e_hw *hw,
  1743. struct i40e_vsi_context *vsi_ctx,
  1744. struct i40e_asq_cmd_details *cmd_details)
  1745. {
  1746. struct i40e_aq_desc desc;
  1747. struct i40e_aqc_add_get_update_vsi *cmd =
  1748. (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
  1749. struct i40e_aqc_add_get_update_vsi_completion *resp =
  1750. (struct i40e_aqc_add_get_update_vsi_completion *)
  1751. &desc.params.raw;
  1752. i40e_status status;
  1753. i40e_fill_default_direct_cmd_desc(&desc,
  1754. i40e_aqc_opc_add_vsi);
  1755. cmd->uplink_seid = cpu_to_le16(vsi_ctx->uplink_seid);
  1756. cmd->connection_type = vsi_ctx->connection_type;
  1757. cmd->vf_id = vsi_ctx->vf_num;
  1758. cmd->vsi_flags = cpu_to_le16(vsi_ctx->flags);
  1759. desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
  1760. status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
  1761. sizeof(vsi_ctx->info), cmd_details);
  1762. if (status)
  1763. goto aq_add_vsi_exit;
  1764. vsi_ctx->seid = le16_to_cpu(resp->seid);
  1765. vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
  1766. vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
  1767. vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
  1768. aq_add_vsi_exit:
  1769. return status;
  1770. }
  1771. /**
  1772. * i40e_aq_set_default_vsi
  1773. * @hw: pointer to the hw struct
  1774. * @seid: vsi number
  1775. * @cmd_details: pointer to command details structure or NULL
  1776. **/
  1777. i40e_status i40e_aq_set_default_vsi(struct i40e_hw *hw,
  1778. u16 seid,
  1779. struct i40e_asq_cmd_details *cmd_details)
  1780. {
  1781. struct i40e_aq_desc desc;
  1782. struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
  1783. (struct i40e_aqc_set_vsi_promiscuous_modes *)
  1784. &desc.params.raw;
  1785. i40e_status status;
  1786. i40e_fill_default_direct_cmd_desc(&desc,
  1787. i40e_aqc_opc_set_vsi_promiscuous_modes);
  1788. cmd->promiscuous_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT);
  1789. cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT);
  1790. cmd->seid = cpu_to_le16(seid);
  1791. status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
  1792. return status;
  1793. }
  1794. /**
  1795. * i40e_aq_clear_default_vsi
  1796. * @hw: pointer to the hw struct
  1797. * @seid: vsi number
  1798. * @cmd_details: pointer to command details structure or NULL
  1799. **/
  1800. i40e_status i40e_aq_clear_default_vsi(struct i40e_hw *hw,
  1801. u16 seid,
  1802. struct i40e_asq_cmd_details *cmd_details)
  1803. {
  1804. struct i40e_aq_desc desc;
  1805. struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
  1806. (struct i40e_aqc_set_vsi_promiscuous_modes *)
  1807. &desc.params.raw;
  1808. i40e_status status;
  1809. i40e_fill_default_direct_cmd_desc(&desc,
  1810. i40e_aqc_opc_set_vsi_promiscuous_modes);
  1811. cmd->promiscuous_flags = cpu_to_le16(0);
  1812. cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT);
  1813. cmd->seid = cpu_to_le16(seid);
  1814. status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
  1815. return status;
  1816. }
  1817. /**
  1818. * i40e_aq_set_vsi_unicast_promiscuous
  1819. * @hw: pointer to the hw struct
  1820. * @seid: vsi number
  1821. * @set: set unicast promiscuous enable/disable
  1822. * @cmd_details: pointer to command details structure or NULL
  1823. * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc
  1824. **/
  1825. i40e_status i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
  1826. u16 seid, bool set,
  1827. struct i40e_asq_cmd_details *cmd_details,
  1828. bool rx_only_promisc)
  1829. {
  1830. struct i40e_aq_desc desc;
  1831. struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
  1832. (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
  1833. i40e_status status;
  1834. u16 flags = 0;
  1835. i40e_fill_default_direct_cmd_desc(&desc,
  1836. i40e_aqc_opc_set_vsi_promiscuous_modes);
  1837. if (set) {
  1838. flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
  1839. if (rx_only_promisc &&
  1840. (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) ||
  1841. (hw->aq.api_maj_ver > 1)))
  1842. flags |= I40E_AQC_SET_VSI_PROMISC_TX;
  1843. }
  1844. cmd->promiscuous_flags = cpu_to_le16(flags);
  1845. cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
  1846. if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) ||
  1847. (hw->aq.api_maj_ver > 1))
  1848. cmd->valid_flags |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_TX);
  1849. cmd->seid = cpu_to_le16(seid);
  1850. status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
  1851. return status;
  1852. }
  1853. /**
  1854. * i40e_aq_set_vsi_multicast_promiscuous
  1855. * @hw: pointer to the hw struct
  1856. * @seid: vsi number
  1857. * @set: set multicast promiscuous enable/disable
  1858. * @cmd_details: pointer to command details structure or NULL
  1859. **/
  1860. i40e_status i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
  1861. u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
  1862. {
  1863. struct i40e_aq_desc desc;
  1864. struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
  1865. (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
  1866. i40e_status status;
  1867. u16 flags = 0;
  1868. i40e_fill_default_direct_cmd_desc(&desc,
  1869. i40e_aqc_opc_set_vsi_promiscuous_modes);
  1870. if (set)
  1871. flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
  1872. cmd->promiscuous_flags = cpu_to_le16(flags);
  1873. cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
  1874. cmd->seid = cpu_to_le16(seid);
  1875. status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
  1876. return status;
  1877. }
  1878. /**
  1879. * i40e_aq_set_vsi_mc_promisc_on_vlan
  1880. * @hw: pointer to the hw struct
  1881. * @seid: vsi number
  1882. * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
  1883. * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
  1884. * @cmd_details: pointer to command details structure or NULL
  1885. **/
  1886. enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
  1887. u16 seid, bool enable,
  1888. u16 vid,
  1889. struct i40e_asq_cmd_details *cmd_details)
  1890. {
  1891. struct i40e_aq_desc desc;
  1892. struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
  1893. (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
  1894. enum i40e_status_code status;
  1895. u16 flags = 0;
  1896. i40e_fill_default_direct_cmd_desc(&desc,
  1897. i40e_aqc_opc_set_vsi_promiscuous_modes);
  1898. if (enable)
  1899. flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
  1900. cmd->promiscuous_flags = cpu_to_le16(flags);
  1901. cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
  1902. cmd->seid = cpu_to_le16(seid);
  1903. cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
  1904. status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
  1905. return status;
  1906. }
  1907. /**
  1908. * i40e_aq_set_vsi_uc_promisc_on_vlan
  1909. * @hw: pointer to the hw struct
  1910. * @seid: vsi number
  1911. * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
  1912. * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
  1913. * @cmd_details: pointer to command details structure or NULL
  1914. **/
  1915. enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
  1916. u16 seid, bool enable,
  1917. u16 vid,
  1918. struct i40e_asq_cmd_details *cmd_details)
  1919. {
  1920. struct i40e_aq_desc desc;
  1921. struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
  1922. (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
  1923. enum i40e_status_code status;
  1924. u16 flags = 0;
  1925. i40e_fill_default_direct_cmd_desc(&desc,
  1926. i40e_aqc_opc_set_vsi_promiscuous_modes);
  1927. if (enable)
  1928. flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
  1929. cmd->promiscuous_flags = cpu_to_le16(flags);
  1930. cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
  1931. cmd->seid = cpu_to_le16(seid);
  1932. cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
  1933. status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
  1934. return status;
  1935. }
  1936. /**
  1937. * i40e_aq_set_vsi_bc_promisc_on_vlan
  1938. * @hw: pointer to the hw struct
  1939. * @seid: vsi number
  1940. * @enable: set broadcast promiscuous enable/disable for a given VLAN
  1941. * @vid: The VLAN tag filter - capture any broadcast packet with this VLAN tag
  1942. * @cmd_details: pointer to command details structure or NULL
  1943. **/
  1944. i40e_status i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw,
  1945. u16 seid, bool enable, u16 vid,
  1946. struct i40e_asq_cmd_details *cmd_details)
  1947. {
  1948. struct i40e_aq_desc desc;
  1949. struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
  1950. (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
  1951. i40e_status status;
  1952. u16 flags = 0;
  1953. i40e_fill_default_direct_cmd_desc(&desc,
  1954. i40e_aqc_opc_set_vsi_promiscuous_modes);
  1955. if (enable)
  1956. flags |= I40E_AQC_SET_VSI_PROMISC_BROADCAST;
  1957. cmd->promiscuous_flags = cpu_to_le16(flags);
  1958. cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
  1959. cmd->seid = cpu_to_le16(seid);
  1960. cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
  1961. status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
  1962. return status;
  1963. }
  1964. /**
  1965. * i40e_aq_set_vsi_broadcast
  1966. * @hw: pointer to the hw struct
  1967. * @seid: vsi number
  1968. * @set_filter: true to set filter, false to clear filter
  1969. * @cmd_details: pointer to command details structure or NULL
  1970. *
  1971. * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
  1972. **/
  1973. i40e_status i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
  1974. u16 seid, bool set_filter,
  1975. struct i40e_asq_cmd_details *cmd_details)
  1976. {
  1977. struct i40e_aq_desc desc;
  1978. struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
  1979. (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
  1980. i40e_status status;
  1981. i40e_fill_default_direct_cmd_desc(&desc,
  1982. i40e_aqc_opc_set_vsi_promiscuous_modes);
  1983. if (set_filter)
  1984. cmd->promiscuous_flags
  1985. |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
  1986. else
  1987. cmd->promiscuous_flags
  1988. &= cpu_to_le16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
  1989. cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
  1990. cmd->seid = cpu_to_le16(seid);
  1991. status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
  1992. return status;
  1993. }
  1994. /**
  1995. * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
  1996. * @hw: pointer to the hw struct
  1997. * @seid: vsi number
  1998. * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
  1999. * @cmd_details: pointer to command details structure or NULL
  2000. **/
  2001. i40e_status i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
  2002. u16 seid, bool enable,
  2003. struct i40e_asq_cmd_details *cmd_details)
  2004. {
  2005. struct i40e_aq_desc desc;
  2006. struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
  2007. (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
  2008. i40e_status status;
  2009. u16 flags = 0;
  2010. i40e_fill_default_direct_cmd_desc(&desc,
  2011. i40e_aqc_opc_set_vsi_promiscuous_modes);
  2012. if (enable)
  2013. flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
  2014. cmd->promiscuous_flags = cpu_to_le16(flags);
  2015. cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_VLAN);
  2016. cmd->seid = cpu_to_le16(seid);
  2017. status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
  2018. return status;
  2019. }
  2020. /**
  2021. * i40e_get_vsi_params - get VSI configuration info
  2022. * @hw: pointer to the hw struct
  2023. * @vsi_ctx: pointer to a vsi context struct
  2024. * @cmd_details: pointer to command details structure or NULL
  2025. **/
  2026. i40e_status i40e_aq_get_vsi_params(struct i40e_hw *hw,
  2027. struct i40e_vsi_context *vsi_ctx,
  2028. struct i40e_asq_cmd_details *cmd_details)
  2029. {
  2030. struct i40e_aq_desc desc;
  2031. struct i40e_aqc_add_get_update_vsi *cmd =
  2032. (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
  2033. struct i40e_aqc_add_get_update_vsi_completion *resp =
  2034. (struct i40e_aqc_add_get_update_vsi_completion *)
  2035. &desc.params.raw;
  2036. i40e_status status;
  2037. i40e_fill_default_direct_cmd_desc(&desc,
  2038. i40e_aqc_opc_get_vsi_parameters);
  2039. cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
  2040. desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
  2041. status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
  2042. sizeof(vsi_ctx->info), NULL);
  2043. if (status)
  2044. goto aq_get_vsi_params_exit;
  2045. vsi_ctx->seid = le16_to_cpu(resp->seid);
  2046. vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
  2047. vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
  2048. vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
  2049. aq_get_vsi_params_exit:
  2050. return status;
  2051. }
  2052. /**
  2053. * i40e_aq_update_vsi_params
  2054. * @hw: pointer to the hw struct
  2055. * @vsi_ctx: pointer to a vsi context struct
  2056. * @cmd_details: pointer to command details structure or NULL
  2057. *
  2058. * Update a VSI context.
  2059. **/
  2060. i40e_status i40e_aq_update_vsi_params(struct i40e_hw *hw,
  2061. struct i40e_vsi_context *vsi_ctx,
  2062. struct i40e_asq_cmd_details *cmd_details)
  2063. {
  2064. struct i40e_aq_desc desc;
  2065. struct i40e_aqc_add_get_update_vsi *cmd =
  2066. (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
  2067. struct i40e_aqc_add_get_update_vsi_completion *resp =
  2068. (struct i40e_aqc_add_get_update_vsi_completion *)
  2069. &desc.params.raw;
  2070. i40e_status status;
  2071. i40e_fill_default_direct_cmd_desc(&desc,
  2072. i40e_aqc_opc_update_vsi_parameters);
  2073. cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
  2074. desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
  2075. status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
  2076. sizeof(vsi_ctx->info), cmd_details);
  2077. vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
  2078. vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
  2079. return status;
  2080. }
  2081. /**
  2082. * i40e_aq_get_switch_config
  2083. * @hw: pointer to the hardware structure
  2084. * @buf: pointer to the result buffer
  2085. * @buf_size: length of input buffer
  2086. * @start_seid: seid to start for the report, 0 == beginning
  2087. * @cmd_details: pointer to command details structure or NULL
  2088. *
  2089. * Fill the buf with switch configuration returned from AdminQ command
  2090. **/
  2091. i40e_status i40e_aq_get_switch_config(struct i40e_hw *hw,
  2092. struct i40e_aqc_get_switch_config_resp *buf,
  2093. u16 buf_size, u16 *start_seid,
  2094. struct i40e_asq_cmd_details *cmd_details)
  2095. {
  2096. struct i40e_aq_desc desc;
  2097. struct i40e_aqc_switch_seid *scfg =
  2098. (struct i40e_aqc_switch_seid *)&desc.params.raw;
  2099. i40e_status status;
  2100. i40e_fill_default_direct_cmd_desc(&desc,
  2101. i40e_aqc_opc_get_switch_config);
  2102. desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
  2103. if (buf_size > I40E_AQ_LARGE_BUF)
  2104. desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
  2105. scfg->seid = cpu_to_le16(*start_seid);
  2106. status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
  2107. *start_seid = le16_to_cpu(scfg->seid);
  2108. return status;
  2109. }
  2110. /**
  2111. * i40e_aq_set_switch_config
  2112. * @hw: pointer to the hardware structure
  2113. * @flags: bit flag values to set
  2114. * @mode: cloud filter mode
  2115. * @valid_flags: which bit flags to set
  2116. * @mode: cloud filter mode
  2117. * @cmd_details: pointer to command details structure or NULL
  2118. *
  2119. * Set switch configuration bits
  2120. **/
  2121. enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw,
  2122. u16 flags,
  2123. u16 valid_flags, u8 mode,
  2124. struct i40e_asq_cmd_details *cmd_details)
  2125. {
  2126. struct i40e_aq_desc desc;
  2127. struct i40e_aqc_set_switch_config *scfg =
  2128. (struct i40e_aqc_set_switch_config *)&desc.params.raw;
  2129. enum i40e_status_code status;
  2130. i40e_fill_default_direct_cmd_desc(&desc,
  2131. i40e_aqc_opc_set_switch_config);
  2132. scfg->flags = cpu_to_le16(flags);
  2133. scfg->valid_flags = cpu_to_le16(valid_flags);
  2134. scfg->mode = mode;
  2135. if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
  2136. scfg->switch_tag = cpu_to_le16(hw->switch_tag);
  2137. scfg->first_tag = cpu_to_le16(hw->first_tag);
  2138. scfg->second_tag = cpu_to_le16(hw->second_tag);
  2139. }
  2140. status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
  2141. return status;
  2142. }
  2143. /**
  2144. * i40e_aq_get_firmware_version
  2145. * @hw: pointer to the hw struct
  2146. * @fw_major_version: firmware major version
  2147. * @fw_minor_version: firmware minor version
  2148. * @fw_build: firmware build number
  2149. * @api_major_version: major queue version
  2150. * @api_minor_version: minor queue version
  2151. * @cmd_details: pointer to command details structure or NULL
  2152. *
  2153. * Get the firmware version from the admin queue commands
  2154. **/
  2155. i40e_status i40e_aq_get_firmware_version(struct i40e_hw *hw,
  2156. u16 *fw_major_version, u16 *fw_minor_version,
  2157. u32 *fw_build,
  2158. u16 *api_major_version, u16 *api_minor_version,
  2159. struct i40e_asq_cmd_details *cmd_details)
  2160. {
  2161. struct i40e_aq_desc desc;
  2162. struct i40e_aqc_get_version *resp =
  2163. (struct i40e_aqc_get_version *)&desc.params.raw;
  2164. i40e_status status;
  2165. i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
  2166. status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
  2167. if (!status) {
  2168. if (fw_major_version)
  2169. *fw_major_version = le16_to_cpu(resp->fw_major);
  2170. if (fw_minor_version)
  2171. *fw_minor_version = le16_to_cpu(resp->fw_minor);
  2172. if (fw_build)
  2173. *fw_build = le32_to_cpu(resp->fw_build);
  2174. if (api_major_version)
  2175. *api_major_version = le16_to_cpu(resp->api_major);
  2176. if (api_minor_version)
  2177. *api_minor_version = le16_to_cpu(resp->api_minor);
  2178. }
  2179. return status;
  2180. }
  2181. /**
  2182. * i40e_aq_send_driver_version
  2183. * @hw: pointer to the hw struct
  2184. * @dv: driver's major, minor version
  2185. * @cmd_details: pointer to command details structure or NULL
  2186. *
  2187. * Send the driver version to the firmware
  2188. **/
  2189. i40e_status i40e_aq_send_driver_version(struct i40e_hw *hw,
  2190. struct i40e_driver_version *dv,
  2191. struct i40e_asq_cmd_details *cmd_details)
  2192. {
  2193. struct i40e_aq_desc desc;
  2194. struct i40e_aqc_driver_version *cmd =
  2195. (struct i40e_aqc_driver_version *)&desc.params.raw;
  2196. i40e_status status;
  2197. u16 len;
  2198. if (dv == NULL)
  2199. return I40E_ERR_PARAM;
  2200. i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
  2201. desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
  2202. cmd->driver_major_ver = dv->major_version;
  2203. cmd->driver_minor_ver = dv->minor_version;
  2204. cmd->driver_build_ver = dv->build_version;
  2205. cmd->driver_subbuild_ver = dv->subbuild_version;
  2206. len = 0;
  2207. while (len < sizeof(dv->driver_string) &&
  2208. (dv->driver_string[len] < 0x80) &&
  2209. dv->driver_string[len])
  2210. len++;
  2211. status = i40e_asq_send_command(hw, &desc, dv->driver_string,
  2212. len, cmd_details);
  2213. return status;
  2214. }
  2215. /**
  2216. * i40e_get_link_status - get status of the HW network link
  2217. * @hw: pointer to the hw struct
  2218. * @link_up: pointer to bool (true/false = linkup/linkdown)
  2219. *
  2220. * Variable link_up true if link is up, false if link is down.
  2221. * The variable link_up is invalid if returned value of status != 0
  2222. *
  2223. * Side effect: LinkStatusEvent reporting becomes enabled
  2224. **/
  2225. i40e_status i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
  2226. {
  2227. i40e_status status = 0;
  2228. if (hw->phy.get_link_info) {
  2229. status = i40e_update_link_info(hw);
  2230. if (status)
  2231. i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
  2232. status);
  2233. }
  2234. *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
  2235. return status;
  2236. }
  2237. /**
  2238. * i40e_updatelink_status - update status of the HW network link
  2239. * @hw: pointer to the hw struct
  2240. **/
  2241. i40e_status i40e_update_link_info(struct i40e_hw *hw)
  2242. {
  2243. struct i40e_aq_get_phy_abilities_resp abilities;
  2244. i40e_status status = 0;
  2245. status = i40e_aq_get_link_info(hw, true, NULL, NULL);
  2246. if (status)
  2247. return status;
  2248. /* extra checking needed to ensure link info to user is timely */
  2249. if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) &&
  2250. ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) ||
  2251. !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) {
  2252. status = i40e_aq_get_phy_capabilities(hw, false, false,
  2253. &abilities, NULL);
  2254. if (status)
  2255. return status;
  2256. hw->phy.link_info.req_fec_info =
  2257. abilities.fec_cfg_curr_mod_ext_info &
  2258. (I40E_AQ_REQUEST_FEC_KR | I40E_AQ_REQUEST_FEC_RS);
  2259. memcpy(hw->phy.link_info.module_type, &abilities.module_type,
  2260. sizeof(hw->phy.link_info.module_type));
  2261. }
  2262. return status;
  2263. }
  2264. /**
  2265. * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
  2266. * @hw: pointer to the hw struct
  2267. * @uplink_seid: the MAC or other gizmo SEID
  2268. * @downlink_seid: the VSI SEID
  2269. * @enabled_tc: bitmap of TCs to be enabled
  2270. * @default_port: true for default port VSI, false for control port
  2271. * @veb_seid: pointer to where to put the resulting VEB SEID
  2272. * @enable_stats: true to turn on VEB stats
  2273. * @cmd_details: pointer to command details structure or NULL
  2274. *
  2275. * This asks the FW to add a VEB between the uplink and downlink
  2276. * elements. If the uplink SEID is 0, this will be a floating VEB.
  2277. **/
  2278. i40e_status i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
  2279. u16 downlink_seid, u8 enabled_tc,
  2280. bool default_port, u16 *veb_seid,
  2281. bool enable_stats,
  2282. struct i40e_asq_cmd_details *cmd_details)
  2283. {
  2284. struct i40e_aq_desc desc;
  2285. struct i40e_aqc_add_veb *cmd =
  2286. (struct i40e_aqc_add_veb *)&desc.params.raw;
  2287. struct i40e_aqc_add_veb_completion *resp =
  2288. (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
  2289. i40e_status status;
  2290. u16 veb_flags = 0;
  2291. /* SEIDs need to either both be set or both be 0 for floating VEB */
  2292. if (!!uplink_seid != !!downlink_seid)
  2293. return I40E_ERR_PARAM;
  2294. i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
  2295. cmd->uplink_seid = cpu_to_le16(uplink_seid);
  2296. cmd->downlink_seid = cpu_to_le16(downlink_seid);
  2297. cmd->enable_tcs = enabled_tc;
  2298. if (!uplink_seid)
  2299. veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
  2300. if (default_port)
  2301. veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
  2302. else
  2303. veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
  2304. /* reverse logic here: set the bitflag to disable the stats */
  2305. if (!enable_stats)
  2306. veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
  2307. cmd->veb_flags = cpu_to_le16(veb_flags);
  2308. status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
  2309. if (!status && veb_seid)
  2310. *veb_seid = le16_to_cpu(resp->veb_seid);
  2311. return status;
  2312. }
  2313. /**
  2314. * i40e_aq_get_veb_parameters - Retrieve VEB parameters
  2315. * @hw: pointer to the hw struct
  2316. * @veb_seid: the SEID of the VEB to query
  2317. * @switch_id: the uplink switch id
  2318. * @floating: set to true if the VEB is floating
  2319. * @statistic_index: index of the stats counter block for this VEB
  2320. * @vebs_used: number of VEB's used by function
  2321. * @vebs_free: total VEB's not reserved by any function
  2322. * @cmd_details: pointer to command details structure or NULL
  2323. *
  2324. * This retrieves the parameters for a particular VEB, specified by
  2325. * uplink_seid, and returns them to the caller.
  2326. **/
  2327. i40e_status i40e_aq_get_veb_parameters(struct i40e_hw *hw,
  2328. u16 veb_seid, u16 *switch_id,
  2329. bool *floating, u16 *statistic_index,
  2330. u16 *vebs_used, u16 *vebs_free,
  2331. struct i40e_asq_cmd_details *cmd_details)
  2332. {
  2333. struct i40e_aq_desc desc;
  2334. struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
  2335. (struct i40e_aqc_get_veb_parameters_completion *)
  2336. &desc.params.raw;
  2337. i40e_status status;
  2338. if (veb_seid == 0)
  2339. return I40E_ERR_PARAM;
  2340. i40e_fill_default_direct_cmd_desc(&desc,
  2341. i40e_aqc_opc_get_veb_parameters);
  2342. cmd_resp->seid = cpu_to_le16(veb_seid);
  2343. status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
  2344. if (status)
  2345. goto get_veb_exit;
  2346. if (switch_id)
  2347. *switch_id = le16_to_cpu(cmd_resp->switch_id);
  2348. if (statistic_index)
  2349. *statistic_index = le16_to_cpu(cmd_resp->statistic_index);
  2350. if (vebs_used)
  2351. *vebs_used = le16_to_cpu(cmd_resp->vebs_used);
  2352. if (vebs_free)
  2353. *vebs_free = le16_to_cpu(cmd_resp->vebs_free);
  2354. if (floating) {
  2355. u16 flags = le16_to_cpu(cmd_resp->veb_flags);
  2356. if (flags & I40E_AQC_ADD_VEB_FLOATING)
  2357. *floating = true;
  2358. else
  2359. *floating = false;
  2360. }
  2361. get_veb_exit:
  2362. return status;
  2363. }
  2364. /**
  2365. * i40e_aq_add_macvlan
  2366. * @hw: pointer to the hw struct
  2367. * @seid: VSI for the mac address
  2368. * @mv_list: list of macvlans to be added
  2369. * @count: length of the list
  2370. * @cmd_details: pointer to command details structure or NULL
  2371. *
  2372. * Add MAC/VLAN addresses to the HW filtering
  2373. **/
  2374. i40e_status i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
  2375. struct i40e_aqc_add_macvlan_element_data *mv_list,
  2376. u16 count, struct i40e_asq_cmd_details *cmd_details)
  2377. {
  2378. struct i40e_aq_desc desc;
  2379. struct i40e_aqc_macvlan *cmd =
  2380. (struct i40e_aqc_macvlan *)&desc.params.raw;
  2381. i40e_status status;
  2382. u16 buf_size;
  2383. int i;
  2384. if (count == 0 || !mv_list || !hw)
  2385. return I40E_ERR_PARAM;
  2386. buf_size = count * sizeof(*mv_list);
  2387. /* prep the rest of the request */
  2388. i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
  2389. cmd->num_addresses = cpu_to_le16(count);
  2390. cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
  2391. cmd->seid[1] = 0;
  2392. cmd->seid[2] = 0;
  2393. for (i = 0; i < count; i++)
  2394. if (is_multicast_ether_addr(mv_list[i].mac_addr))
  2395. mv_list[i].flags |=
  2396. cpu_to_le16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
  2397. desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
  2398. if (buf_size > I40E_AQ_LARGE_BUF)
  2399. desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
  2400. status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
  2401. cmd_details);
  2402. return status;
  2403. }
  2404. /**
  2405. * i40e_aq_remove_macvlan
  2406. * @hw: pointer to the hw struct
  2407. * @seid: VSI for the mac address
  2408. * @mv_list: list of macvlans to be removed
  2409. * @count: length of the list
  2410. * @cmd_details: pointer to command details structure or NULL
  2411. *
  2412. * Remove MAC/VLAN addresses from the HW filtering
  2413. **/
  2414. i40e_status i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
  2415. struct i40e_aqc_remove_macvlan_element_data *mv_list,
  2416. u16 count, struct i40e_asq_cmd_details *cmd_details)
  2417. {
  2418. struct i40e_aq_desc desc;
  2419. struct i40e_aqc_macvlan *cmd =
  2420. (struct i40e_aqc_macvlan *)&desc.params.raw;
  2421. i40e_status status;
  2422. u16 buf_size;
  2423. if (count == 0 || !mv_list || !hw)
  2424. return I40E_ERR_PARAM;
  2425. buf_size = count * sizeof(*mv_list);
  2426. /* prep the rest of the request */
  2427. i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
  2428. cmd->num_addresses = cpu_to_le16(count);
  2429. cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
  2430. cmd->seid[1] = 0;
  2431. cmd->seid[2] = 0;
  2432. desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
  2433. if (buf_size > I40E_AQ_LARGE_BUF)
  2434. desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
  2435. status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
  2436. cmd_details);
  2437. return status;
  2438. }
  2439. /**
  2440. * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
  2441. * @hw: pointer to the hw struct
  2442. * @opcode: AQ opcode for add or delete mirror rule
  2443. * @sw_seid: Switch SEID (to which rule refers)
  2444. * @rule_type: Rule Type (ingress/egress/VLAN)
  2445. * @id: Destination VSI SEID or Rule ID
  2446. * @count: length of the list
  2447. * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
  2448. * @cmd_details: pointer to command details structure or NULL
  2449. * @rule_id: Rule ID returned from FW
  2450. * @rules_used: Number of rules used in internal switch
  2451. * @rules_free: Number of rules free in internal switch
  2452. *
  2453. * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
  2454. * VEBs/VEPA elements only
  2455. **/
  2456. static i40e_status i40e_mirrorrule_op(struct i40e_hw *hw,
  2457. u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
  2458. u16 count, __le16 *mr_list,
  2459. struct i40e_asq_cmd_details *cmd_details,
  2460. u16 *rule_id, u16 *rules_used, u16 *rules_free)
  2461. {
  2462. struct i40e_aq_desc desc;
  2463. struct i40e_aqc_add_delete_mirror_rule *cmd =
  2464. (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
  2465. struct i40e_aqc_add_delete_mirror_rule_completion *resp =
  2466. (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
  2467. i40e_status status;
  2468. u16 buf_size;
  2469. buf_size = count * sizeof(*mr_list);
  2470. /* prep the rest of the request */
  2471. i40e_fill_default_direct_cmd_desc(&desc, opcode);
  2472. cmd->seid = cpu_to_le16(sw_seid);
  2473. cmd->rule_type = cpu_to_le16(rule_type &
  2474. I40E_AQC_MIRROR_RULE_TYPE_MASK);
  2475. cmd->num_entries = cpu_to_le16(count);
  2476. /* Dest VSI for add, rule_id for delete */
  2477. cmd->destination = cpu_to_le16(id);
  2478. if (mr_list) {
  2479. desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF |
  2480. I40E_AQ_FLAG_RD));
  2481. if (buf_size > I40E_AQ_LARGE_BUF)
  2482. desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
  2483. }
  2484. status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
  2485. cmd_details);
  2486. if (!status ||
  2487. hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
  2488. if (rule_id)
  2489. *rule_id = le16_to_cpu(resp->rule_id);
  2490. if (rules_used)
  2491. *rules_used = le16_to_cpu(resp->mirror_rules_used);
  2492. if (rules_free)
  2493. *rules_free = le16_to_cpu(resp->mirror_rules_free);
  2494. }
  2495. return status;
  2496. }
  2497. /**
  2498. * i40e_aq_add_mirrorrule - add a mirror rule
  2499. * @hw: pointer to the hw struct
  2500. * @sw_seid: Switch SEID (to which rule refers)
  2501. * @rule_type: Rule Type (ingress/egress/VLAN)
  2502. * @dest_vsi: SEID of VSI to which packets will be mirrored
  2503. * @count: length of the list
  2504. * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
  2505. * @cmd_details: pointer to command details structure or NULL
  2506. * @rule_id: Rule ID returned from FW
  2507. * @rules_used: Number of rules used in internal switch
  2508. * @rules_free: Number of rules free in internal switch
  2509. *
  2510. * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only
  2511. **/
  2512. i40e_status i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
  2513. u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
  2514. struct i40e_asq_cmd_details *cmd_details,
  2515. u16 *rule_id, u16 *rules_used, u16 *rules_free)
  2516. {
  2517. if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
  2518. rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
  2519. if (count == 0 || !mr_list)
  2520. return I40E_ERR_PARAM;
  2521. }
  2522. return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
  2523. rule_type, dest_vsi, count, mr_list,
  2524. cmd_details, rule_id, rules_used, rules_free);
  2525. }
  2526. /**
  2527. * i40e_aq_delete_mirrorrule - delete a mirror rule
  2528. * @hw: pointer to the hw struct
  2529. * @sw_seid: Switch SEID (to which rule refers)
  2530. * @rule_type: Rule Type (ingress/egress/VLAN)
  2531. * @count: length of the list
  2532. * @rule_id: Rule ID that is returned in the receive desc as part of
  2533. * add_mirrorrule.
  2534. * @mr_list: list of mirrored VLAN IDs to be removed
  2535. * @cmd_details: pointer to command details structure or NULL
  2536. * @rules_used: Number of rules used in internal switch
  2537. * @rules_free: Number of rules free in internal switch
  2538. *
  2539. * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only
  2540. **/
  2541. i40e_status i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
  2542. u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
  2543. struct i40e_asq_cmd_details *cmd_details,
  2544. u16 *rules_used, u16 *rules_free)
  2545. {
  2546. /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */
  2547. if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
  2548. /* count and mr_list shall be valid for rule_type INGRESS VLAN
  2549. * mirroring. For other rule_type, count and rule_type should
  2550. * not matter.
  2551. */
  2552. if (count == 0 || !mr_list)
  2553. return I40E_ERR_PARAM;
  2554. }
  2555. return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
  2556. rule_type, rule_id, count, mr_list,
  2557. cmd_details, NULL, rules_used, rules_free);
  2558. }
  2559. /**
  2560. * i40e_aq_send_msg_to_vf
  2561. * @hw: pointer to the hardware structure
  2562. * @vfid: VF id to send msg
  2563. * @v_opcode: opcodes for VF-PF communication
  2564. * @v_retval: return error code
  2565. * @msg: pointer to the msg buffer
  2566. * @msglen: msg length
  2567. * @cmd_details: pointer to command details
  2568. *
  2569. * send msg to vf
  2570. **/
  2571. i40e_status i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
  2572. u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
  2573. struct i40e_asq_cmd_details *cmd_details)
  2574. {
  2575. struct i40e_aq_desc desc;
  2576. struct i40e_aqc_pf_vf_message *cmd =
  2577. (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
  2578. i40e_status status;
  2579. i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
  2580. cmd->id = cpu_to_le32(vfid);
  2581. desc.cookie_high = cpu_to_le32(v_opcode);
  2582. desc.cookie_low = cpu_to_le32(v_retval);
  2583. desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_SI);
  2584. if (msglen) {
  2585. desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF |
  2586. I40E_AQ_FLAG_RD));
  2587. if (msglen > I40E_AQ_LARGE_BUF)
  2588. desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
  2589. desc.datalen = cpu_to_le16(msglen);
  2590. }
  2591. status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
  2592. return status;
  2593. }
  2594. /**
  2595. * i40e_aq_debug_read_register
  2596. * @hw: pointer to the hw struct
  2597. * @reg_addr: register address
  2598. * @reg_val: register value
  2599. * @cmd_details: pointer to command details structure or NULL
  2600. *
  2601. * Read the register using the admin queue commands
  2602. **/
  2603. i40e_status i40e_aq_debug_read_register(struct i40e_hw *hw,
  2604. u32 reg_addr, u64 *reg_val,
  2605. struct i40e_asq_cmd_details *cmd_details)
  2606. {
  2607. struct i40e_aq_desc desc;
  2608. struct i40e_aqc_debug_reg_read_write *cmd_resp =
  2609. (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
  2610. i40e_status status;
  2611. if (reg_val == NULL)
  2612. return I40E_ERR_PARAM;
  2613. i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
  2614. cmd_resp->address = cpu_to_le32(reg_addr);
  2615. status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
  2616. if (!status) {
  2617. *reg_val = ((u64)le32_to_cpu(cmd_resp->value_high) << 32) |
  2618. (u64)le32_to_cpu(cmd_resp->value_low);
  2619. }
  2620. return status;
  2621. }
  2622. /**
  2623. * i40e_aq_debug_write_register
  2624. * @hw: pointer to the hw struct
  2625. * @reg_addr: register address
  2626. * @reg_val: register value
  2627. * @cmd_details: pointer to command details structure or NULL
  2628. *
  2629. * Write to a register using the admin queue commands
  2630. **/
  2631. i40e_status i40e_aq_debug_write_register(struct i40e_hw *hw,
  2632. u32 reg_addr, u64 reg_val,
  2633. struct i40e_asq_cmd_details *cmd_details)
  2634. {
  2635. struct i40e_aq_desc desc;
  2636. struct i40e_aqc_debug_reg_read_write *cmd =
  2637. (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
  2638. i40e_status status;
  2639. i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
  2640. cmd->address = cpu_to_le32(reg_addr);
  2641. cmd->value_high = cpu_to_le32((u32)(reg_val >> 32));
  2642. cmd->value_low = cpu_to_le32((u32)(reg_val & 0xFFFFFFFF));
  2643. status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
  2644. return status;
  2645. }
  2646. /**
  2647. * i40e_aq_request_resource
  2648. * @hw: pointer to the hw struct
  2649. * @resource: resource id
  2650. * @access: access type
  2651. * @sdp_number: resource number
  2652. * @timeout: the maximum time in ms that the driver may hold the resource
  2653. * @cmd_details: pointer to command details structure or NULL
  2654. *
  2655. * requests common resource using the admin queue commands
  2656. **/
  2657. i40e_status i40e_aq_request_resource(struct i40e_hw *hw,
  2658. enum i40e_aq_resources_ids resource,
  2659. enum i40e_aq_resource_access_type access,
  2660. u8 sdp_number, u64 *timeout,
  2661. struct i40e_asq_cmd_details *cmd_details)
  2662. {
  2663. struct i40e_aq_desc desc;
  2664. struct i40e_aqc_request_resource *cmd_resp =
  2665. (struct i40e_aqc_request_resource *)&desc.params.raw;
  2666. i40e_status status;
  2667. i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
  2668. cmd_resp->resource_id = cpu_to_le16(resource);
  2669. cmd_resp->access_type = cpu_to_le16(access);
  2670. cmd_resp->resource_number = cpu_to_le32(sdp_number);
  2671. status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
  2672. /* The completion specifies the maximum time in ms that the driver
  2673. * may hold the resource in the Timeout field.
  2674. * If the resource is held by someone else, the command completes with
  2675. * busy return value and the timeout field indicates the maximum time
  2676. * the current owner of the resource has to free it.
  2677. */
  2678. if (!status || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
  2679. *timeout = le32_to_cpu(cmd_resp->timeout);
  2680. return status;
  2681. }
  2682. /**
  2683. * i40e_aq_release_resource
  2684. * @hw: pointer to the hw struct
  2685. * @resource: resource id
  2686. * @sdp_number: resource number
  2687. * @cmd_details: pointer to command details structure or NULL
  2688. *
  2689. * release common resource using the admin queue commands
  2690. **/
  2691. i40e_status i40e_aq_release_resource(struct i40e_hw *hw,
  2692. enum i40e_aq_resources_ids resource,
  2693. u8 sdp_number,
  2694. struct i40e_asq_cmd_details *cmd_details)
  2695. {
  2696. struct i40e_aq_desc desc;
  2697. struct i40e_aqc_request_resource *cmd =
  2698. (struct i40e_aqc_request_resource *)&desc.params.raw;
  2699. i40e_status status;
  2700. i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
  2701. cmd->resource_id = cpu_to_le16(resource);
  2702. cmd->resource_number = cpu_to_le32(sdp_number);
  2703. status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
  2704. return status;
  2705. }
  2706. /**
  2707. * i40e_aq_read_nvm
  2708. * @hw: pointer to the hw struct
  2709. * @module_pointer: module pointer location in words from the NVM beginning
  2710. * @offset: byte offset from the module beginning
  2711. * @length: length of the section to be read (in bytes from the offset)
  2712. * @data: command buffer (size [bytes] = length)
  2713. * @last_command: tells if this is the last command in a series
  2714. * @cmd_details: pointer to command details structure or NULL
  2715. *
  2716. * Read the NVM using the admin queue commands
  2717. **/
  2718. i40e_status i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
  2719. u32 offset, u16 length, void *data,
  2720. bool last_command,
  2721. struct i40e_asq_cmd_details *cmd_details)
  2722. {
  2723. struct i40e_aq_desc desc;
  2724. struct i40e_aqc_nvm_update *cmd =
  2725. (struct i40e_aqc_nvm_update *)&desc.params.raw;
  2726. i40e_status status;
  2727. /* In offset the highest byte must be zeroed. */
  2728. if (offset & 0xFF000000) {
  2729. status = I40E_ERR_PARAM;
  2730. goto i40e_aq_read_nvm_exit;
  2731. }
  2732. i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
  2733. /* If this is the last command in a series, set the proper flag. */
  2734. if (last_command)
  2735. cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
  2736. cmd->module_pointer = module_pointer;
  2737. cmd->offset = cpu_to_le32(offset);
  2738. cmd->length = cpu_to_le16(length);
  2739. desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
  2740. if (length > I40E_AQ_LARGE_BUF)
  2741. desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
  2742. status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
  2743. i40e_aq_read_nvm_exit:
  2744. return status;
  2745. }
  2746. /**
  2747. * i40e_aq_erase_nvm
  2748. * @hw: pointer to the hw struct
  2749. * @module_pointer: module pointer location in words from the NVM beginning
  2750. * @offset: offset in the module (expressed in 4 KB from module's beginning)
  2751. * @length: length of the section to be erased (expressed in 4 KB)
  2752. * @last_command: tells if this is the last command in a series
  2753. * @cmd_details: pointer to command details structure or NULL
  2754. *
  2755. * Erase the NVM sector using the admin queue commands
  2756. **/
  2757. i40e_status i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
  2758. u32 offset, u16 length, bool last_command,
  2759. struct i40e_asq_cmd_details *cmd_details)
  2760. {
  2761. struct i40e_aq_desc desc;
  2762. struct i40e_aqc_nvm_update *cmd =
  2763. (struct i40e_aqc_nvm_update *)&desc.params.raw;
  2764. i40e_status status;
  2765. /* In offset the highest byte must be zeroed. */
  2766. if (offset & 0xFF000000) {
  2767. status = I40E_ERR_PARAM;
  2768. goto i40e_aq_erase_nvm_exit;
  2769. }
  2770. i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
  2771. /* If this is the last command in a series, set the proper flag. */
  2772. if (last_command)
  2773. cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
  2774. cmd->module_pointer = module_pointer;
  2775. cmd->offset = cpu_to_le32(offset);
  2776. cmd->length = cpu_to_le16(length);
  2777. status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
  2778. i40e_aq_erase_nvm_exit:
  2779. return status;
  2780. }
  2781. /**
  2782. * i40e_parse_discover_capabilities
  2783. * @hw: pointer to the hw struct
  2784. * @buff: pointer to a buffer containing device/function capability records
  2785. * @cap_count: number of capability records in the list
  2786. * @list_type_opc: type of capabilities list to parse
  2787. *
  2788. * Parse the device/function capabilities list.
  2789. **/
  2790. static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
  2791. u32 cap_count,
  2792. enum i40e_admin_queue_opc list_type_opc)
  2793. {
  2794. struct i40e_aqc_list_capabilities_element_resp *cap;
  2795. u32 valid_functions, num_functions;
  2796. u32 number, logical_id, phys_id;
  2797. struct i40e_hw_capabilities *p;
  2798. u16 id, ocp_cfg_word0;
  2799. i40e_status status;
  2800. u8 major_rev;
  2801. u32 i = 0;
  2802. cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
  2803. if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
  2804. p = &hw->dev_caps;
  2805. else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
  2806. p = &hw->func_caps;
  2807. else
  2808. return;
  2809. for (i = 0; i < cap_count; i++, cap++) {
  2810. id = le16_to_cpu(cap->id);
  2811. number = le32_to_cpu(cap->number);
  2812. logical_id = le32_to_cpu(cap->logical_id);
  2813. phys_id = le32_to_cpu(cap->phys_id);
  2814. major_rev = cap->major_rev;
  2815. switch (id) {
  2816. case I40E_AQ_CAP_ID_SWITCH_MODE:
  2817. p->switch_mode = number;
  2818. break;
  2819. case I40E_AQ_CAP_ID_MNG_MODE:
  2820. p->management_mode = number;
  2821. if (major_rev > 1) {
  2822. p->mng_protocols_over_mctp = logical_id;
  2823. i40e_debug(hw, I40E_DEBUG_INIT,
  2824. "HW Capability: Protocols over MCTP = %d\n",
  2825. p->mng_protocols_over_mctp);
  2826. } else {
  2827. p->mng_protocols_over_mctp = 0;
  2828. }
  2829. break;
  2830. case I40E_AQ_CAP_ID_NPAR_ACTIVE:
  2831. p->npar_enable = number;
  2832. break;
  2833. case I40E_AQ_CAP_ID_OS2BMC_CAP:
  2834. p->os2bmc = number;
  2835. break;
  2836. case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
  2837. p->valid_functions = number;
  2838. break;
  2839. case I40E_AQ_CAP_ID_SRIOV:
  2840. if (number == 1)
  2841. p->sr_iov_1_1 = true;
  2842. break;
  2843. case I40E_AQ_CAP_ID_VF:
  2844. p->num_vfs = number;
  2845. p->vf_base_id = logical_id;
  2846. break;
  2847. case I40E_AQ_CAP_ID_VMDQ:
  2848. if (number == 1)
  2849. p->vmdq = true;
  2850. break;
  2851. case I40E_AQ_CAP_ID_8021QBG:
  2852. if (number == 1)
  2853. p->evb_802_1_qbg = true;
  2854. break;
  2855. case I40E_AQ_CAP_ID_8021QBR:
  2856. if (number == 1)
  2857. p->evb_802_1_qbh = true;
  2858. break;
  2859. case I40E_AQ_CAP_ID_VSI:
  2860. p->num_vsis = number;
  2861. break;
  2862. case I40E_AQ_CAP_ID_DCB:
  2863. if (number == 1) {
  2864. p->dcb = true;
  2865. p->enabled_tcmap = logical_id;
  2866. p->maxtc = phys_id;
  2867. }
  2868. break;
  2869. case I40E_AQ_CAP_ID_FCOE:
  2870. if (number == 1)
  2871. p->fcoe = true;
  2872. break;
  2873. case I40E_AQ_CAP_ID_ISCSI:
  2874. if (number == 1)
  2875. p->iscsi = true;
  2876. break;
  2877. case I40E_AQ_CAP_ID_RSS:
  2878. p->rss = true;
  2879. p->rss_table_size = number;
  2880. p->rss_table_entry_width = logical_id;
  2881. break;
  2882. case I40E_AQ_CAP_ID_RXQ:
  2883. p->num_rx_qp = number;
  2884. p->base_queue = phys_id;
  2885. break;
  2886. case I40E_AQ_CAP_ID_TXQ:
  2887. p->num_tx_qp = number;
  2888. p->base_queue = phys_id;
  2889. break;
  2890. case I40E_AQ_CAP_ID_MSIX:
  2891. p->num_msix_vectors = number;
  2892. i40e_debug(hw, I40E_DEBUG_INIT,
  2893. "HW Capability: MSIX vector count = %d\n",
  2894. p->num_msix_vectors);
  2895. break;
  2896. case I40E_AQ_CAP_ID_VF_MSIX:
  2897. p->num_msix_vectors_vf = number;
  2898. break;
  2899. case I40E_AQ_CAP_ID_FLEX10:
  2900. if (major_rev == 1) {
  2901. if (number == 1) {
  2902. p->flex10_enable = true;
  2903. p->flex10_capable = true;
  2904. }
  2905. } else {
  2906. /* Capability revision >= 2 */
  2907. if (number & 1)
  2908. p->flex10_enable = true;
  2909. if (number & 2)
  2910. p->flex10_capable = true;
  2911. }
  2912. p->flex10_mode = logical_id;
  2913. p->flex10_status = phys_id;
  2914. break;
  2915. case I40E_AQ_CAP_ID_CEM:
  2916. if (number == 1)
  2917. p->mgmt_cem = true;
  2918. break;
  2919. case I40E_AQ_CAP_ID_IWARP:
  2920. if (number == 1)
  2921. p->iwarp = true;
  2922. break;
  2923. case I40E_AQ_CAP_ID_LED:
  2924. if (phys_id < I40E_HW_CAP_MAX_GPIO)
  2925. p->led[phys_id] = true;
  2926. break;
  2927. case I40E_AQ_CAP_ID_SDP:
  2928. if (phys_id < I40E_HW_CAP_MAX_GPIO)
  2929. p->sdp[phys_id] = true;
  2930. break;
  2931. case I40E_AQ_CAP_ID_MDIO:
  2932. if (number == 1) {
  2933. p->mdio_port_num = phys_id;
  2934. p->mdio_port_mode = logical_id;
  2935. }
  2936. break;
  2937. case I40E_AQ_CAP_ID_1588:
  2938. if (number == 1)
  2939. p->ieee_1588 = true;
  2940. break;
  2941. case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
  2942. p->fd = true;
  2943. p->fd_filters_guaranteed = number;
  2944. p->fd_filters_best_effort = logical_id;
  2945. break;
  2946. case I40E_AQ_CAP_ID_WSR_PROT:
  2947. p->wr_csr_prot = (u64)number;
  2948. p->wr_csr_prot |= (u64)logical_id << 32;
  2949. break;
  2950. case I40E_AQ_CAP_ID_NVM_MGMT:
  2951. if (number & I40E_NVM_MGMT_SEC_REV_DISABLED)
  2952. p->sec_rev_disabled = true;
  2953. if (number & I40E_NVM_MGMT_UPDATE_DISABLED)
  2954. p->update_disabled = true;
  2955. break;
  2956. default:
  2957. break;
  2958. }
  2959. }
  2960. if (p->fcoe)
  2961. i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
  2962. /* Software override ensuring FCoE is disabled if npar or mfp
  2963. * mode because it is not supported in these modes.
  2964. */
  2965. if (p->npar_enable || p->flex10_enable)
  2966. p->fcoe = false;
  2967. /* count the enabled ports (aka the "not disabled" ports) */
  2968. hw->num_ports = 0;
  2969. for (i = 0; i < 4; i++) {
  2970. u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
  2971. u64 port_cfg = 0;
  2972. /* use AQ read to get the physical register offset instead
  2973. * of the port relative offset
  2974. */
  2975. i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
  2976. if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
  2977. hw->num_ports++;
  2978. }
  2979. /* OCP cards case: if a mezz is removed the Ethernet port is at
  2980. * disabled state in PRTGEN_CNF register. Additional NVM read is
  2981. * needed in order to check if we are dealing with OCP card.
  2982. * Those cards have 4 PFs at minimum, so using PRTGEN_CNF for counting
  2983. * physical ports results in wrong partition id calculation and thus
  2984. * not supporting WoL.
  2985. */
  2986. if (hw->mac.type == I40E_MAC_X722) {
  2987. if (!i40e_acquire_nvm(hw, I40E_RESOURCE_READ)) {
  2988. status = i40e_aq_read_nvm(hw, I40E_SR_EMP_MODULE_PTR,
  2989. 2 * I40E_SR_OCP_CFG_WORD0,
  2990. sizeof(ocp_cfg_word0),
  2991. &ocp_cfg_word0, true, NULL);
  2992. if (!status &&
  2993. (ocp_cfg_word0 & I40E_SR_OCP_ENABLED))
  2994. hw->num_ports = 4;
  2995. i40e_release_nvm(hw);
  2996. }
  2997. }
  2998. valid_functions = p->valid_functions;
  2999. num_functions = 0;
  3000. while (valid_functions) {
  3001. if (valid_functions & 1)
  3002. num_functions++;
  3003. valid_functions >>= 1;
  3004. }
  3005. /* partition id is 1-based, and functions are evenly spread
  3006. * across the ports as partitions
  3007. */
  3008. if (hw->num_ports != 0) {
  3009. hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
  3010. hw->num_partitions = num_functions / hw->num_ports;
  3011. }
  3012. /* additional HW specific goodies that might
  3013. * someday be HW version specific
  3014. */
  3015. p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
  3016. }
  3017. /**
  3018. * i40e_aq_discover_capabilities
  3019. * @hw: pointer to the hw struct
  3020. * @buff: a virtual buffer to hold the capabilities
  3021. * @buff_size: Size of the virtual buffer
  3022. * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
  3023. * @list_type_opc: capabilities type to discover - pass in the command opcode
  3024. * @cmd_details: pointer to command details structure or NULL
  3025. *
  3026. * Get the device capabilities descriptions from the firmware
  3027. **/
  3028. i40e_status i40e_aq_discover_capabilities(struct i40e_hw *hw,
  3029. void *buff, u16 buff_size, u16 *data_size,
  3030. enum i40e_admin_queue_opc list_type_opc,
  3031. struct i40e_asq_cmd_details *cmd_details)
  3032. {
  3033. struct i40e_aqc_list_capabilites *cmd;
  3034. struct i40e_aq_desc desc;
  3035. i40e_status status = 0;
  3036. cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
  3037. if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
  3038. list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
  3039. status = I40E_ERR_PARAM;
  3040. goto exit;
  3041. }
  3042. i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
  3043. desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
  3044. if (buff_size > I40E_AQ_LARGE_BUF)
  3045. desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
  3046. status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
  3047. *data_size = le16_to_cpu(desc.datalen);
  3048. if (status)
  3049. goto exit;
  3050. i40e_parse_discover_capabilities(hw, buff, le32_to_cpu(cmd->count),
  3051. list_type_opc);
  3052. exit:
  3053. return status;
  3054. }
  3055. /**
  3056. * i40e_aq_update_nvm
  3057. * @hw: pointer to the hw struct
  3058. * @module_pointer: module pointer location in words from the NVM beginning
  3059. * @offset: byte offset from the module beginning
  3060. * @length: length of the section to be written (in bytes from the offset)
  3061. * @data: command buffer (size [bytes] = length)
  3062. * @last_command: tells if this is the last command in a series
  3063. * @preservation_flags: Preservation mode flags
  3064. * @cmd_details: pointer to command details structure or NULL
  3065. *
  3066. * Update the NVM using the admin queue commands
  3067. **/
  3068. i40e_status i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
  3069. u32 offset, u16 length, void *data,
  3070. bool last_command, u8 preservation_flags,
  3071. struct i40e_asq_cmd_details *cmd_details)
  3072. {
  3073. struct i40e_aq_desc desc;
  3074. struct i40e_aqc_nvm_update *cmd =
  3075. (struct i40e_aqc_nvm_update *)&desc.params.raw;
  3076. i40e_status status;
  3077. /* In offset the highest byte must be zeroed. */
  3078. if (offset & 0xFF000000) {
  3079. status = I40E_ERR_PARAM;
  3080. goto i40e_aq_update_nvm_exit;
  3081. }
  3082. i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
  3083. /* If this is the last command in a series, set the proper flag. */
  3084. if (last_command)
  3085. cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
  3086. if (hw->mac.type == I40E_MAC_X722) {
  3087. if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_SELECTED)
  3088. cmd->command_flags |=
  3089. (I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED <<
  3090. I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT);
  3091. else if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_ALL)
  3092. cmd->command_flags |=
  3093. (I40E_AQ_NVM_PRESERVATION_FLAGS_ALL <<
  3094. I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT);
  3095. }
  3096. cmd->module_pointer = module_pointer;
  3097. cmd->offset = cpu_to_le32(offset);
  3098. cmd->length = cpu_to_le16(length);
  3099. desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
  3100. if (length > I40E_AQ_LARGE_BUF)
  3101. desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
  3102. status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
  3103. i40e_aq_update_nvm_exit:
  3104. return status;
  3105. }
  3106. /**
  3107. * i40e_aq_rearrange_nvm
  3108. * @hw: pointer to the hw struct
  3109. * @rearrange_nvm: defines direction of rearrangement
  3110. * @cmd_details: pointer to command details structure or NULL
  3111. *
  3112. * Rearrange NVM structure, available only for transition FW
  3113. **/
  3114. i40e_status i40e_aq_rearrange_nvm(struct i40e_hw *hw,
  3115. u8 rearrange_nvm,
  3116. struct i40e_asq_cmd_details *cmd_details)
  3117. {
  3118. struct i40e_aqc_nvm_update *cmd;
  3119. i40e_status status;
  3120. struct i40e_aq_desc desc;
  3121. cmd = (struct i40e_aqc_nvm_update *)&desc.params.raw;
  3122. i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
  3123. rearrange_nvm &= (I40E_AQ_NVM_REARRANGE_TO_FLAT |
  3124. I40E_AQ_NVM_REARRANGE_TO_STRUCT);
  3125. if (!rearrange_nvm) {
  3126. status = I40E_ERR_PARAM;
  3127. goto i40e_aq_rearrange_nvm_exit;
  3128. }
  3129. cmd->command_flags |= rearrange_nvm;
  3130. status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
  3131. i40e_aq_rearrange_nvm_exit:
  3132. return status;
  3133. }
  3134. /**
  3135. * i40e_aq_get_lldp_mib
  3136. * @hw: pointer to the hw struct
  3137. * @bridge_type: type of bridge requested
  3138. * @mib_type: Local, Remote or both Local and Remote MIBs
  3139. * @buff: pointer to a user supplied buffer to store the MIB block
  3140. * @buff_size: size of the buffer (in bytes)
  3141. * @local_len : length of the returned Local LLDP MIB
  3142. * @remote_len: length of the returned Remote LLDP MIB
  3143. * @cmd_details: pointer to command details structure or NULL
  3144. *
  3145. * Requests the complete LLDP MIB (entire packet).
  3146. **/
  3147. i40e_status i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
  3148. u8 mib_type, void *buff, u16 buff_size,
  3149. u16 *local_len, u16 *remote_len,
  3150. struct i40e_asq_cmd_details *cmd_details)
  3151. {
  3152. struct i40e_aq_desc desc;
  3153. struct i40e_aqc_lldp_get_mib *cmd =
  3154. (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
  3155. struct i40e_aqc_lldp_get_mib *resp =
  3156. (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
  3157. i40e_status status;
  3158. if (buff_size == 0 || !buff)
  3159. return I40E_ERR_PARAM;
  3160. i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
  3161. /* Indirect Command */
  3162. desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
  3163. cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
  3164. cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
  3165. I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
  3166. desc.datalen = cpu_to_le16(buff_size);
  3167. desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
  3168. if (buff_size > I40E_AQ_LARGE_BUF)
  3169. desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
  3170. status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
  3171. if (!status) {
  3172. if (local_len != NULL)
  3173. *local_len = le16_to_cpu(resp->local_len);
  3174. if (remote_len != NULL)
  3175. *remote_len = le16_to_cpu(resp->remote_len);
  3176. }
  3177. return status;
  3178. }
  3179. /**
  3180. * i40e_aq_cfg_lldp_mib_change_event
  3181. * @hw: pointer to the hw struct
  3182. * @enable_update: Enable or Disable event posting
  3183. * @cmd_details: pointer to command details structure or NULL
  3184. *
  3185. * Enable or Disable posting of an event on ARQ when LLDP MIB
  3186. * associated with the interface changes
  3187. **/
  3188. i40e_status i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
  3189. bool enable_update,
  3190. struct i40e_asq_cmd_details *cmd_details)
  3191. {
  3192. struct i40e_aq_desc desc;
  3193. struct i40e_aqc_lldp_update_mib *cmd =
  3194. (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
  3195. i40e_status status;
  3196. i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
  3197. if (!enable_update)
  3198. cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
  3199. status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
  3200. return status;
  3201. }
  3202. /**
  3203. * i40e_aq_stop_lldp
  3204. * @hw: pointer to the hw struct
  3205. * @shutdown_agent: True if LLDP Agent needs to be Shutdown
  3206. * @cmd_details: pointer to command details structure or NULL
  3207. *
  3208. * Stop or Shutdown the embedded LLDP Agent
  3209. **/
  3210. i40e_status i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
  3211. struct i40e_asq_cmd_details *cmd_details)
  3212. {
  3213. struct i40e_aq_desc desc;
  3214. struct i40e_aqc_lldp_stop *cmd =
  3215. (struct i40e_aqc_lldp_stop *)&desc.params.raw;
  3216. i40e_status status;
  3217. i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
  3218. if (shutdown_agent)
  3219. cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
  3220. status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
  3221. return status;
  3222. }
  3223. /**
  3224. * i40e_aq_start_lldp
  3225. * @hw: pointer to the hw struct
  3226. * @buff: buffer for result
  3227. * @buff_size: buffer size
  3228. * @cmd_details: pointer to command details structure or NULL
  3229. *
  3230. * Start the embedded LLDP Agent on all ports.
  3231. **/
  3232. i40e_status i40e_aq_start_lldp(struct i40e_hw *hw,
  3233. struct i40e_asq_cmd_details *cmd_details)
  3234. {
  3235. struct i40e_aq_desc desc;
  3236. struct i40e_aqc_lldp_start *cmd =
  3237. (struct i40e_aqc_lldp_start *)&desc.params.raw;
  3238. i40e_status status;
  3239. i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
  3240. cmd->command = I40E_AQ_LLDP_AGENT_START;
  3241. status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
  3242. return status;
  3243. }
  3244. /**
  3245. * i40e_aq_set_dcb_parameters
  3246. * @hw: pointer to the hw struct
  3247. * @cmd_details: pointer to command details structure or NULL
  3248. * @dcb_enable: True if DCB configuration needs to be applied
  3249. *
  3250. **/
  3251. enum i40e_status_code
  3252. i40e_aq_set_dcb_parameters(struct i40e_hw *hw, bool dcb_enable,
  3253. struct i40e_asq_cmd_details *cmd_details)
  3254. {
  3255. struct i40e_aq_desc desc;
  3256. struct i40e_aqc_set_dcb_parameters *cmd =
  3257. (struct i40e_aqc_set_dcb_parameters *)&desc.params.raw;
  3258. i40e_status status;
  3259. i40e_fill_default_direct_cmd_desc(&desc,
  3260. i40e_aqc_opc_set_dcb_parameters);
  3261. if (dcb_enable) {
  3262. cmd->valid_flags = I40E_DCB_VALID;
  3263. cmd->command = I40E_AQ_DCB_SET_AGENT;
  3264. }
  3265. status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
  3266. return status;
  3267. }
  3268. /**
  3269. * i40e_aq_get_cee_dcb_config
  3270. * @hw: pointer to the hw struct
  3271. * @buff: response buffer that stores CEE operational configuration
  3272. * @buff_size: size of the buffer passed
  3273. * @cmd_details: pointer to command details structure or NULL
  3274. *
  3275. * Get CEE DCBX mode operational configuration from firmware
  3276. **/
  3277. i40e_status i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
  3278. void *buff, u16 buff_size,
  3279. struct i40e_asq_cmd_details *cmd_details)
  3280. {
  3281. struct i40e_aq_desc desc;
  3282. i40e_status status;
  3283. if (buff_size == 0 || !buff)
  3284. return I40E_ERR_PARAM;
  3285. i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
  3286. desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
  3287. status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
  3288. cmd_details);
  3289. return status;
  3290. }
  3291. /**
  3292. * i40e_aq_add_udp_tunnel
  3293. * @hw: pointer to the hw struct
  3294. * @udp_port: the UDP port to add in Host byte order
  3295. * @protocol_index: protocol index type
  3296. * @filter_index: pointer to filter index
  3297. * @cmd_details: pointer to command details structure or NULL
  3298. *
  3299. * Note: Firmware expects the udp_port value to be in Little Endian format,
  3300. * and this function will call cpu_to_le16 to convert from Host byte order to
  3301. * Little Endian order.
  3302. **/
  3303. i40e_status i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
  3304. u16 udp_port, u8 protocol_index,
  3305. u8 *filter_index,
  3306. struct i40e_asq_cmd_details *cmd_details)
  3307. {
  3308. struct i40e_aq_desc desc;
  3309. struct i40e_aqc_add_udp_tunnel *cmd =
  3310. (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
  3311. struct i40e_aqc_del_udp_tunnel_completion *resp =
  3312. (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
  3313. i40e_status status;
  3314. i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
  3315. cmd->udp_port = cpu_to_le16(udp_port);
  3316. cmd->protocol_type = protocol_index;
  3317. status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
  3318. if (!status && filter_index)
  3319. *filter_index = resp->index;
  3320. return status;
  3321. }
  3322. /**
  3323. * i40e_aq_del_udp_tunnel
  3324. * @hw: pointer to the hw struct
  3325. * @index: filter index
  3326. * @cmd_details: pointer to command details structure or NULL
  3327. **/
  3328. i40e_status i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
  3329. struct i40e_asq_cmd_details *cmd_details)
  3330. {
  3331. struct i40e_aq_desc desc;
  3332. struct i40e_aqc_remove_udp_tunnel *cmd =
  3333. (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
  3334. i40e_status status;
  3335. i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
  3336. cmd->index = index;
  3337. status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
  3338. return status;
  3339. }
  3340. /**
  3341. * i40e_aq_delete_element - Delete switch element
  3342. * @hw: pointer to the hw struct
  3343. * @seid: the SEID to delete from the switch
  3344. * @cmd_details: pointer to command details structure or NULL
  3345. *
  3346. * This deletes a switch element from the switch.
  3347. **/
  3348. i40e_status i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
  3349. struct i40e_asq_cmd_details *cmd_details)
  3350. {
  3351. struct i40e_aq_desc desc;
  3352. struct i40e_aqc_switch_seid *cmd =
  3353. (struct i40e_aqc_switch_seid *)&desc.params.raw;
  3354. i40e_status status;
  3355. if (seid == 0)
  3356. return I40E_ERR_PARAM;
  3357. i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
  3358. cmd->seid = cpu_to_le16(seid);
  3359. status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
  3360. return status;
  3361. }
  3362. /**
  3363. * i40e_aq_dcb_updated - DCB Updated Command
  3364. * @hw: pointer to the hw struct
  3365. * @cmd_details: pointer to command details structure or NULL
  3366. *
  3367. * EMP will return when the shared RPB settings have been
  3368. * recomputed and modified. The retval field in the descriptor
  3369. * will be set to 0 when RPB is modified.
  3370. **/
  3371. i40e_status i40e_aq_dcb_updated(struct i40e_hw *hw,
  3372. struct i40e_asq_cmd_details *cmd_details)
  3373. {
  3374. struct i40e_aq_desc desc;
  3375. i40e_status status;
  3376. i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
  3377. status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
  3378. return status;
  3379. }
  3380. /**
  3381. * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
  3382. * @hw: pointer to the hw struct
  3383. * @seid: seid for the physical port/switching component/vsi
  3384. * @buff: Indirect buffer to hold data parameters and response
  3385. * @buff_size: Indirect buffer size
  3386. * @opcode: Tx scheduler AQ command opcode
  3387. * @cmd_details: pointer to command details structure or NULL
  3388. *
  3389. * Generic command handler for Tx scheduler AQ commands
  3390. **/
  3391. static i40e_status i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
  3392. void *buff, u16 buff_size,
  3393. enum i40e_admin_queue_opc opcode,
  3394. struct i40e_asq_cmd_details *cmd_details)
  3395. {
  3396. struct i40e_aq_desc desc;
  3397. struct i40e_aqc_tx_sched_ind *cmd =
  3398. (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
  3399. i40e_status status;
  3400. bool cmd_param_flag = false;
  3401. switch (opcode) {
  3402. case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
  3403. case i40e_aqc_opc_configure_vsi_tc_bw:
  3404. case i40e_aqc_opc_enable_switching_comp_ets:
  3405. case i40e_aqc_opc_modify_switching_comp_ets:
  3406. case i40e_aqc_opc_disable_switching_comp_ets:
  3407. case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
  3408. case i40e_aqc_opc_configure_switching_comp_bw_config:
  3409. cmd_param_flag = true;
  3410. break;
  3411. case i40e_aqc_opc_query_vsi_bw_config:
  3412. case i40e_aqc_opc_query_vsi_ets_sla_config:
  3413. case i40e_aqc_opc_query_switching_comp_ets_config:
  3414. case i40e_aqc_opc_query_port_ets_config:
  3415. case i40e_aqc_opc_query_switching_comp_bw_config:
  3416. cmd_param_flag = false;
  3417. break;
  3418. default:
  3419. return I40E_ERR_PARAM;
  3420. }
  3421. i40e_fill_default_direct_cmd_desc(&desc, opcode);
  3422. /* Indirect command */
  3423. desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
  3424. if (cmd_param_flag)
  3425. desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
  3426. if (buff_size > I40E_AQ_LARGE_BUF)
  3427. desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
  3428. desc.datalen = cpu_to_le16(buff_size);
  3429. cmd->vsi_seid = cpu_to_le16(seid);
  3430. status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
  3431. return status;
  3432. }
  3433. /**
  3434. * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
  3435. * @hw: pointer to the hw struct
  3436. * @seid: VSI seid
  3437. * @credit: BW limit credits (0 = disabled)
  3438. * @max_credit: Max BW limit credits
  3439. * @cmd_details: pointer to command details structure or NULL
  3440. **/
  3441. i40e_status i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
  3442. u16 seid, u16 credit, u8 max_credit,
  3443. struct i40e_asq_cmd_details *cmd_details)
  3444. {
  3445. struct i40e_aq_desc desc;
  3446. struct i40e_aqc_configure_vsi_bw_limit *cmd =
  3447. (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
  3448. i40e_status status;
  3449. i40e_fill_default_direct_cmd_desc(&desc,
  3450. i40e_aqc_opc_configure_vsi_bw_limit);
  3451. cmd->vsi_seid = cpu_to_le16(seid);
  3452. cmd->credit = cpu_to_le16(credit);
  3453. cmd->max_credit = max_credit;
  3454. status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
  3455. return status;
  3456. }
  3457. /**
  3458. * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
  3459. * @hw: pointer to the hw struct
  3460. * @seid: VSI seid
  3461. * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
  3462. * @cmd_details: pointer to command details structure or NULL
  3463. **/
  3464. i40e_status i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
  3465. u16 seid,
  3466. struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
  3467. struct i40e_asq_cmd_details *cmd_details)
  3468. {
  3469. return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
  3470. i40e_aqc_opc_configure_vsi_tc_bw,
  3471. cmd_details);
  3472. }
  3473. /**
  3474. * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
  3475. * @hw: pointer to the hw struct
  3476. * @seid: seid of the switching component connected to Physical Port
  3477. * @ets_data: Buffer holding ETS parameters
  3478. * @opcode: Tx scheduler AQ command opcode
  3479. * @cmd_details: pointer to command details structure or NULL
  3480. **/
  3481. i40e_status i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
  3482. u16 seid,
  3483. struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
  3484. enum i40e_admin_queue_opc opcode,
  3485. struct i40e_asq_cmd_details *cmd_details)
  3486. {
  3487. return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
  3488. sizeof(*ets_data), opcode, cmd_details);
  3489. }
  3490. /**
  3491. * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
  3492. * @hw: pointer to the hw struct
  3493. * @seid: seid of the switching component
  3494. * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
  3495. * @cmd_details: pointer to command details structure or NULL
  3496. **/
  3497. i40e_status i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
  3498. u16 seid,
  3499. struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
  3500. struct i40e_asq_cmd_details *cmd_details)
  3501. {
  3502. return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
  3503. i40e_aqc_opc_configure_switching_comp_bw_config,
  3504. cmd_details);
  3505. }
  3506. /**
  3507. * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
  3508. * @hw: pointer to the hw struct
  3509. * @seid: seid of the VSI
  3510. * @bw_data: Buffer to hold VSI BW configuration
  3511. * @cmd_details: pointer to command details structure or NULL
  3512. **/
  3513. i40e_status i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
  3514. u16 seid,
  3515. struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
  3516. struct i40e_asq_cmd_details *cmd_details)
  3517. {
  3518. return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
  3519. i40e_aqc_opc_query_vsi_bw_config,
  3520. cmd_details);
  3521. }
  3522. /**
  3523. * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
  3524. * @hw: pointer to the hw struct
  3525. * @seid: seid of the VSI
  3526. * @bw_data: Buffer to hold VSI BW configuration per TC
  3527. * @cmd_details: pointer to command details structure or NULL
  3528. **/
  3529. i40e_status i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
  3530. u16 seid,
  3531. struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
  3532. struct i40e_asq_cmd_details *cmd_details)
  3533. {
  3534. return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
  3535. i40e_aqc_opc_query_vsi_ets_sla_config,
  3536. cmd_details);
  3537. }
  3538. /**
  3539. * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
  3540. * @hw: pointer to the hw struct
  3541. * @seid: seid of the switching component
  3542. * @bw_data: Buffer to hold switching component's per TC BW config
  3543. * @cmd_details: pointer to command details structure or NULL
  3544. **/
  3545. i40e_status i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
  3546. u16 seid,
  3547. struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
  3548. struct i40e_asq_cmd_details *cmd_details)
  3549. {
  3550. return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
  3551. i40e_aqc_opc_query_switching_comp_ets_config,
  3552. cmd_details);
  3553. }
  3554. /**
  3555. * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
  3556. * @hw: pointer to the hw struct
  3557. * @seid: seid of the VSI or switching component connected to Physical Port
  3558. * @bw_data: Buffer to hold current ETS configuration for the Physical Port
  3559. * @cmd_details: pointer to command details structure or NULL
  3560. **/
  3561. i40e_status i40e_aq_query_port_ets_config(struct i40e_hw *hw,
  3562. u16 seid,
  3563. struct i40e_aqc_query_port_ets_config_resp *bw_data,
  3564. struct i40e_asq_cmd_details *cmd_details)
  3565. {
  3566. return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
  3567. i40e_aqc_opc_query_port_ets_config,
  3568. cmd_details);
  3569. }
  3570. /**
  3571. * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
  3572. * @hw: pointer to the hw struct
  3573. * @seid: seid of the switching component
  3574. * @bw_data: Buffer to hold switching component's BW configuration
  3575. * @cmd_details: pointer to command details structure or NULL
  3576. **/
  3577. i40e_status i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
  3578. u16 seid,
  3579. struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
  3580. struct i40e_asq_cmd_details *cmd_details)
  3581. {
  3582. return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
  3583. i40e_aqc_opc_query_switching_comp_bw_config,
  3584. cmd_details);
  3585. }
  3586. /**
  3587. * i40e_validate_filter_settings
  3588. * @hw: pointer to the hardware structure
  3589. * @settings: Filter control settings
  3590. *
  3591. * Check and validate the filter control settings passed.
  3592. * The function checks for the valid filter/context sizes being
  3593. * passed for FCoE and PE.
  3594. *
  3595. * Returns 0 if the values passed are valid and within
  3596. * range else returns an error.
  3597. **/
  3598. static i40e_status i40e_validate_filter_settings(struct i40e_hw *hw,
  3599. struct i40e_filter_control_settings *settings)
  3600. {
  3601. u32 fcoe_cntx_size, fcoe_filt_size;
  3602. u32 pe_cntx_size, pe_filt_size;
  3603. u32 fcoe_fmax;
  3604. u32 val;
  3605. /* Validate FCoE settings passed */
  3606. switch (settings->fcoe_filt_num) {
  3607. case I40E_HASH_FILTER_SIZE_1K:
  3608. case I40E_HASH_FILTER_SIZE_2K:
  3609. case I40E_HASH_FILTER_SIZE_4K:
  3610. case I40E_HASH_FILTER_SIZE_8K:
  3611. case I40E_HASH_FILTER_SIZE_16K:
  3612. case I40E_HASH_FILTER_SIZE_32K:
  3613. fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
  3614. fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
  3615. break;
  3616. default:
  3617. return I40E_ERR_PARAM;
  3618. }
  3619. switch (settings->fcoe_cntx_num) {
  3620. case I40E_DMA_CNTX_SIZE_512:
  3621. case I40E_DMA_CNTX_SIZE_1K:
  3622. case I40E_DMA_CNTX_SIZE_2K:
  3623. case I40E_DMA_CNTX_SIZE_4K:
  3624. fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
  3625. fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
  3626. break;
  3627. default:
  3628. return I40E_ERR_PARAM;
  3629. }
  3630. /* Validate PE settings passed */
  3631. switch (settings->pe_filt_num) {
  3632. case I40E_HASH_FILTER_SIZE_1K:
  3633. case I40E_HASH_FILTER_SIZE_2K:
  3634. case I40E_HASH_FILTER_SIZE_4K:
  3635. case I40E_HASH_FILTER_SIZE_8K:
  3636. case I40E_HASH_FILTER_SIZE_16K:
  3637. case I40E_HASH_FILTER_SIZE_32K:
  3638. case I40E_HASH_FILTER_SIZE_64K:
  3639. case I40E_HASH_FILTER_SIZE_128K:
  3640. case I40E_HASH_FILTER_SIZE_256K:
  3641. case I40E_HASH_FILTER_SIZE_512K:
  3642. case I40E_HASH_FILTER_SIZE_1M:
  3643. pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
  3644. pe_filt_size <<= (u32)settings->pe_filt_num;
  3645. break;
  3646. default:
  3647. return I40E_ERR_PARAM;
  3648. }
  3649. switch (settings->pe_cntx_num) {
  3650. case I40E_DMA_CNTX_SIZE_512:
  3651. case I40E_DMA_CNTX_SIZE_1K:
  3652. case I40E_DMA_CNTX_SIZE_2K:
  3653. case I40E_DMA_CNTX_SIZE_4K:
  3654. case I40E_DMA_CNTX_SIZE_8K:
  3655. case I40E_DMA_CNTX_SIZE_16K:
  3656. case I40E_DMA_CNTX_SIZE_32K:
  3657. case I40E_DMA_CNTX_SIZE_64K:
  3658. case I40E_DMA_CNTX_SIZE_128K:
  3659. case I40E_DMA_CNTX_SIZE_256K:
  3660. pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
  3661. pe_cntx_size <<= (u32)settings->pe_cntx_num;
  3662. break;
  3663. default:
  3664. return I40E_ERR_PARAM;
  3665. }
  3666. /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
  3667. val = rd32(hw, I40E_GLHMC_FCOEFMAX);
  3668. fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
  3669. >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
  3670. if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
  3671. return I40E_ERR_INVALID_SIZE;
  3672. return 0;
  3673. }
  3674. /**
  3675. * i40e_set_filter_control
  3676. * @hw: pointer to the hardware structure
  3677. * @settings: Filter control settings
  3678. *
  3679. * Set the Queue Filters for PE/FCoE and enable filters required
  3680. * for a single PF. It is expected that these settings are programmed
  3681. * at the driver initialization time.
  3682. **/
  3683. i40e_status i40e_set_filter_control(struct i40e_hw *hw,
  3684. struct i40e_filter_control_settings *settings)
  3685. {
  3686. i40e_status ret = 0;
  3687. u32 hash_lut_size = 0;
  3688. u32 val;
  3689. if (!settings)
  3690. return I40E_ERR_PARAM;
  3691. /* Validate the input settings */
  3692. ret = i40e_validate_filter_settings(hw, settings);
  3693. if (ret)
  3694. return ret;
  3695. /* Read the PF Queue Filter control register */
  3696. val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
  3697. /* Program required PE hash buckets for the PF */
  3698. val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
  3699. val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
  3700. I40E_PFQF_CTL_0_PEHSIZE_MASK;
  3701. /* Program required PE contexts for the PF */
  3702. val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
  3703. val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
  3704. I40E_PFQF_CTL_0_PEDSIZE_MASK;
  3705. /* Program required FCoE hash buckets for the PF */
  3706. val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
  3707. val |= ((u32)settings->fcoe_filt_num <<
  3708. I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
  3709. I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
  3710. /* Program required FCoE DDP contexts for the PF */
  3711. val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
  3712. val |= ((u32)settings->fcoe_cntx_num <<
  3713. I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
  3714. I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
  3715. /* Program Hash LUT size for the PF */
  3716. val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
  3717. if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
  3718. hash_lut_size = 1;
  3719. val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
  3720. I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
  3721. /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
  3722. if (settings->enable_fdir)
  3723. val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
  3724. if (settings->enable_ethtype)
  3725. val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
  3726. if (settings->enable_macvlan)
  3727. val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
  3728. i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
  3729. return 0;
  3730. }
  3731. /**
  3732. * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
  3733. * @hw: pointer to the hw struct
  3734. * @mac_addr: MAC address to use in the filter
  3735. * @ethtype: Ethertype to use in the filter
  3736. * @flags: Flags that needs to be applied to the filter
  3737. * @vsi_seid: seid of the control VSI
  3738. * @queue: VSI queue number to send the packet to
  3739. * @is_add: Add control packet filter if True else remove
  3740. * @stats: Structure to hold information on control filter counts
  3741. * @cmd_details: pointer to command details structure or NULL
  3742. *
  3743. * This command will Add or Remove control packet filter for a control VSI.
  3744. * In return it will update the total number of perfect filter count in
  3745. * the stats member.
  3746. **/
  3747. i40e_status i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
  3748. u8 *mac_addr, u16 ethtype, u16 flags,
  3749. u16 vsi_seid, u16 queue, bool is_add,
  3750. struct i40e_control_filter_stats *stats,
  3751. struct i40e_asq_cmd_details *cmd_details)
  3752. {
  3753. struct i40e_aq_desc desc;
  3754. struct i40e_aqc_add_remove_control_packet_filter *cmd =
  3755. (struct i40e_aqc_add_remove_control_packet_filter *)
  3756. &desc.params.raw;
  3757. struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
  3758. (struct i40e_aqc_add_remove_control_packet_filter_completion *)
  3759. &desc.params.raw;
  3760. i40e_status status;
  3761. if (vsi_seid == 0)
  3762. return I40E_ERR_PARAM;
  3763. if (is_add) {
  3764. i40e_fill_default_direct_cmd_desc(&desc,
  3765. i40e_aqc_opc_add_control_packet_filter);
  3766. cmd->queue = cpu_to_le16(queue);
  3767. } else {
  3768. i40e_fill_default_direct_cmd_desc(&desc,
  3769. i40e_aqc_opc_remove_control_packet_filter);
  3770. }
  3771. if (mac_addr)
  3772. ether_addr_copy(cmd->mac, mac_addr);
  3773. cmd->etype = cpu_to_le16(ethtype);
  3774. cmd->flags = cpu_to_le16(flags);
  3775. cmd->seid = cpu_to_le16(vsi_seid);
  3776. status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
  3777. if (!status && stats) {
  3778. stats->mac_etype_used = le16_to_cpu(resp->mac_etype_used);
  3779. stats->etype_used = le16_to_cpu(resp->etype_used);
  3780. stats->mac_etype_free = le16_to_cpu(resp->mac_etype_free);
  3781. stats->etype_free = le16_to_cpu(resp->etype_free);
  3782. }
  3783. return status;
  3784. }
  3785. /**
  3786. * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
  3787. * @hw: pointer to the hw struct
  3788. * @seid: VSI seid to add ethertype filter from
  3789. **/
  3790. void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
  3791. u16 seid)
  3792. {
  3793. #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
  3794. u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
  3795. I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
  3796. I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
  3797. u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
  3798. i40e_status status;
  3799. status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
  3800. seid, 0, true, NULL,
  3801. NULL);
  3802. if (status)
  3803. hw_dbg(hw, "Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
  3804. }
  3805. /**
  3806. * i40e_aq_alternate_read
  3807. * @hw: pointer to the hardware structure
  3808. * @reg_addr0: address of first dword to be read
  3809. * @reg_val0: pointer for data read from 'reg_addr0'
  3810. * @reg_addr1: address of second dword to be read
  3811. * @reg_val1: pointer for data read from 'reg_addr1'
  3812. *
  3813. * Read one or two dwords from alternate structure. Fields are indicated
  3814. * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
  3815. * is not passed then only register at 'reg_addr0' is read.
  3816. *
  3817. **/
  3818. static i40e_status i40e_aq_alternate_read(struct i40e_hw *hw,
  3819. u32 reg_addr0, u32 *reg_val0,
  3820. u32 reg_addr1, u32 *reg_val1)
  3821. {
  3822. struct i40e_aq_desc desc;
  3823. struct i40e_aqc_alternate_write *cmd_resp =
  3824. (struct i40e_aqc_alternate_write *)&desc.params.raw;
  3825. i40e_status status;
  3826. if (!reg_val0)
  3827. return I40E_ERR_PARAM;
  3828. i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
  3829. cmd_resp->address0 = cpu_to_le32(reg_addr0);
  3830. cmd_resp->address1 = cpu_to_le32(reg_addr1);
  3831. status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
  3832. if (!status) {
  3833. *reg_val0 = le32_to_cpu(cmd_resp->data0);
  3834. if (reg_val1)
  3835. *reg_val1 = le32_to_cpu(cmd_resp->data1);
  3836. }
  3837. return status;
  3838. }
  3839. /**
  3840. * i40e_aq_resume_port_tx
  3841. * @hw: pointer to the hardware structure
  3842. * @cmd_details: pointer to command details structure or NULL
  3843. *
  3844. * Resume port's Tx traffic
  3845. **/
  3846. i40e_status i40e_aq_resume_port_tx(struct i40e_hw *hw,
  3847. struct i40e_asq_cmd_details *cmd_details)
  3848. {
  3849. struct i40e_aq_desc desc;
  3850. i40e_status status;
  3851. i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
  3852. status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
  3853. return status;
  3854. }
  3855. /**
  3856. * i40e_set_pci_config_data - store PCI bus info
  3857. * @hw: pointer to hardware structure
  3858. * @link_status: the link status word from PCI config space
  3859. *
  3860. * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
  3861. **/
  3862. void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
  3863. {
  3864. hw->bus.type = i40e_bus_type_pci_express;
  3865. switch (link_status & PCI_EXP_LNKSTA_NLW) {
  3866. case PCI_EXP_LNKSTA_NLW_X1:
  3867. hw->bus.width = i40e_bus_width_pcie_x1;
  3868. break;
  3869. case PCI_EXP_LNKSTA_NLW_X2:
  3870. hw->bus.width = i40e_bus_width_pcie_x2;
  3871. break;
  3872. case PCI_EXP_LNKSTA_NLW_X4:
  3873. hw->bus.width = i40e_bus_width_pcie_x4;
  3874. break;
  3875. case PCI_EXP_LNKSTA_NLW_X8:
  3876. hw->bus.width = i40e_bus_width_pcie_x8;
  3877. break;
  3878. default:
  3879. hw->bus.width = i40e_bus_width_unknown;
  3880. break;
  3881. }
  3882. switch (link_status & PCI_EXP_LNKSTA_CLS) {
  3883. case PCI_EXP_LNKSTA_CLS_2_5GB:
  3884. hw->bus.speed = i40e_bus_speed_2500;
  3885. break;
  3886. case PCI_EXP_LNKSTA_CLS_5_0GB:
  3887. hw->bus.speed = i40e_bus_speed_5000;
  3888. break;
  3889. case PCI_EXP_LNKSTA_CLS_8_0GB:
  3890. hw->bus.speed = i40e_bus_speed_8000;
  3891. break;
  3892. default:
  3893. hw->bus.speed = i40e_bus_speed_unknown;
  3894. break;
  3895. }
  3896. }
  3897. /**
  3898. * i40e_aq_debug_dump
  3899. * @hw: pointer to the hardware structure
  3900. * @cluster_id: specific cluster to dump
  3901. * @table_id: table id within cluster
  3902. * @start_index: index of line in the block to read
  3903. * @buff_size: dump buffer size
  3904. * @buff: dump buffer
  3905. * @ret_buff_size: actual buffer size returned
  3906. * @ret_next_table: next block to read
  3907. * @ret_next_index: next index to read
  3908. * @cmd_details: pointer to command details structure or NULL
  3909. *
  3910. * Dump internal FW/HW data for debug purposes.
  3911. *
  3912. **/
  3913. i40e_status i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
  3914. u8 table_id, u32 start_index, u16 buff_size,
  3915. void *buff, u16 *ret_buff_size,
  3916. u8 *ret_next_table, u32 *ret_next_index,
  3917. struct i40e_asq_cmd_details *cmd_details)
  3918. {
  3919. struct i40e_aq_desc desc;
  3920. struct i40e_aqc_debug_dump_internals *cmd =
  3921. (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
  3922. struct i40e_aqc_debug_dump_internals *resp =
  3923. (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
  3924. i40e_status status;
  3925. if (buff_size == 0 || !buff)
  3926. return I40E_ERR_PARAM;
  3927. i40e_fill_default_direct_cmd_desc(&desc,
  3928. i40e_aqc_opc_debug_dump_internals);
  3929. /* Indirect Command */
  3930. desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
  3931. if (buff_size > I40E_AQ_LARGE_BUF)
  3932. desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
  3933. cmd->cluster_id = cluster_id;
  3934. cmd->table_id = table_id;
  3935. cmd->idx = cpu_to_le32(start_index);
  3936. desc.datalen = cpu_to_le16(buff_size);
  3937. status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
  3938. if (!status) {
  3939. if (ret_buff_size)
  3940. *ret_buff_size = le16_to_cpu(desc.datalen);
  3941. if (ret_next_table)
  3942. *ret_next_table = resp->table_id;
  3943. if (ret_next_index)
  3944. *ret_next_index = le32_to_cpu(resp->idx);
  3945. }
  3946. return status;
  3947. }
  3948. /**
  3949. * i40e_read_bw_from_alt_ram
  3950. * @hw: pointer to the hardware structure
  3951. * @max_bw: pointer for max_bw read
  3952. * @min_bw: pointer for min_bw read
  3953. * @min_valid: pointer for bool that is true if min_bw is a valid value
  3954. * @max_valid: pointer for bool that is true if max_bw is a valid value
  3955. *
  3956. * Read bw from the alternate ram for the given pf
  3957. **/
  3958. i40e_status i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
  3959. u32 *max_bw, u32 *min_bw,
  3960. bool *min_valid, bool *max_valid)
  3961. {
  3962. i40e_status status;
  3963. u32 max_bw_addr, min_bw_addr;
  3964. /* Calculate the address of the min/max bw registers */
  3965. max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
  3966. I40E_ALT_STRUCT_MAX_BW_OFFSET +
  3967. (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
  3968. min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
  3969. I40E_ALT_STRUCT_MIN_BW_OFFSET +
  3970. (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
  3971. /* Read the bandwidths from alt ram */
  3972. status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
  3973. min_bw_addr, min_bw);
  3974. if (*min_bw & I40E_ALT_BW_VALID_MASK)
  3975. *min_valid = true;
  3976. else
  3977. *min_valid = false;
  3978. if (*max_bw & I40E_ALT_BW_VALID_MASK)
  3979. *max_valid = true;
  3980. else
  3981. *max_valid = false;
  3982. return status;
  3983. }
  3984. /**
  3985. * i40e_aq_configure_partition_bw
  3986. * @hw: pointer to the hardware structure
  3987. * @bw_data: Buffer holding valid pfs and bw limits
  3988. * @cmd_details: pointer to command details
  3989. *
  3990. * Configure partitions guaranteed/max bw
  3991. **/
  3992. i40e_status i40e_aq_configure_partition_bw(struct i40e_hw *hw,
  3993. struct i40e_aqc_configure_partition_bw_data *bw_data,
  3994. struct i40e_asq_cmd_details *cmd_details)
  3995. {
  3996. i40e_status status;
  3997. struct i40e_aq_desc desc;
  3998. u16 bwd_size = sizeof(*bw_data);
  3999. i40e_fill_default_direct_cmd_desc(&desc,
  4000. i40e_aqc_opc_configure_partition_bw);
  4001. /* Indirect command */
  4002. desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
  4003. desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
  4004. if (bwd_size > I40E_AQ_LARGE_BUF)
  4005. desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
  4006. desc.datalen = cpu_to_le16(bwd_size);
  4007. status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size,
  4008. cmd_details);
  4009. return status;
  4010. }
  4011. /**
  4012. * i40e_read_phy_register_clause22
  4013. * @hw: pointer to the HW structure
  4014. * @reg: register address in the page
  4015. * @phy_addr: PHY address on MDIO interface
  4016. * @value: PHY register value
  4017. *
  4018. * Reads specified PHY register value
  4019. **/
  4020. i40e_status i40e_read_phy_register_clause22(struct i40e_hw *hw,
  4021. u16 reg, u8 phy_addr, u16 *value)
  4022. {
  4023. i40e_status status = I40E_ERR_TIMEOUT;
  4024. u8 port_num = (u8)hw->func_caps.mdio_port_num;
  4025. u32 command = 0;
  4026. u16 retry = 1000;
  4027. command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
  4028. (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
  4029. (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) |
  4030. (I40E_MDIO_CLAUSE22_STCODE_MASK) |
  4031. (I40E_GLGEN_MSCA_MDICMD_MASK);
  4032. wr32(hw, I40E_GLGEN_MSCA(port_num), command);
  4033. do {
  4034. command = rd32(hw, I40E_GLGEN_MSCA(port_num));
  4035. if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
  4036. status = 0;
  4037. break;
  4038. }
  4039. udelay(10);
  4040. retry--;
  4041. } while (retry);
  4042. if (status) {
  4043. i40e_debug(hw, I40E_DEBUG_PHY,
  4044. "PHY: Can't write command to external PHY.\n");
  4045. } else {
  4046. command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
  4047. *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
  4048. I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
  4049. }
  4050. return status;
  4051. }
  4052. /**
  4053. * i40e_write_phy_register_clause22
  4054. * @hw: pointer to the HW structure
  4055. * @reg: register address in the page
  4056. * @phy_addr: PHY address on MDIO interface
  4057. * @value: PHY register value
  4058. *
  4059. * Writes specified PHY register value
  4060. **/
  4061. i40e_status i40e_write_phy_register_clause22(struct i40e_hw *hw,
  4062. u16 reg, u8 phy_addr, u16 value)
  4063. {
  4064. i40e_status status = I40E_ERR_TIMEOUT;
  4065. u8 port_num = (u8)hw->func_caps.mdio_port_num;
  4066. u32 command = 0;
  4067. u16 retry = 1000;
  4068. command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
  4069. wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
  4070. command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
  4071. (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
  4072. (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) |
  4073. (I40E_MDIO_CLAUSE22_STCODE_MASK) |
  4074. (I40E_GLGEN_MSCA_MDICMD_MASK);
  4075. wr32(hw, I40E_GLGEN_MSCA(port_num), command);
  4076. do {
  4077. command = rd32(hw, I40E_GLGEN_MSCA(port_num));
  4078. if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
  4079. status = 0;
  4080. break;
  4081. }
  4082. udelay(10);
  4083. retry--;
  4084. } while (retry);
  4085. return status;
  4086. }
  4087. /**
  4088. * i40e_read_phy_register_clause45
  4089. * @hw: pointer to the HW structure
  4090. * @page: registers page number
  4091. * @reg: register address in the page
  4092. * @phy_addr: PHY address on MDIO interface
  4093. * @value: PHY register value
  4094. *
  4095. * Reads specified PHY register value
  4096. **/
  4097. i40e_status i40e_read_phy_register_clause45(struct i40e_hw *hw,
  4098. u8 page, u16 reg, u8 phy_addr, u16 *value)
  4099. {
  4100. i40e_status status = I40E_ERR_TIMEOUT;
  4101. u32 command = 0;
  4102. u16 retry = 1000;
  4103. u8 port_num = hw->func_caps.mdio_port_num;
  4104. command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
  4105. (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
  4106. (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
  4107. (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
  4108. (I40E_MDIO_CLAUSE45_STCODE_MASK) |
  4109. (I40E_GLGEN_MSCA_MDICMD_MASK) |
  4110. (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
  4111. wr32(hw, I40E_GLGEN_MSCA(port_num), command);
  4112. do {
  4113. command = rd32(hw, I40E_GLGEN_MSCA(port_num));
  4114. if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
  4115. status = 0;
  4116. break;
  4117. }
  4118. usleep_range(10, 20);
  4119. retry--;
  4120. } while (retry);
  4121. if (status) {
  4122. i40e_debug(hw, I40E_DEBUG_PHY,
  4123. "PHY: Can't write command to external PHY.\n");
  4124. goto phy_read_end;
  4125. }
  4126. command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
  4127. (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
  4128. (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) |
  4129. (I40E_MDIO_CLAUSE45_STCODE_MASK) |
  4130. (I40E_GLGEN_MSCA_MDICMD_MASK) |
  4131. (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
  4132. status = I40E_ERR_TIMEOUT;
  4133. retry = 1000;
  4134. wr32(hw, I40E_GLGEN_MSCA(port_num), command);
  4135. do {
  4136. command = rd32(hw, I40E_GLGEN_MSCA(port_num));
  4137. if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
  4138. status = 0;
  4139. break;
  4140. }
  4141. usleep_range(10, 20);
  4142. retry--;
  4143. } while (retry);
  4144. if (!status) {
  4145. command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
  4146. *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
  4147. I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
  4148. } else {
  4149. i40e_debug(hw, I40E_DEBUG_PHY,
  4150. "PHY: Can't read register value from external PHY.\n");
  4151. }
  4152. phy_read_end:
  4153. return status;
  4154. }
  4155. /**
  4156. * i40e_write_phy_register_clause45
  4157. * @hw: pointer to the HW structure
  4158. * @page: registers page number
  4159. * @reg: register address in the page
  4160. * @phy_addr: PHY address on MDIO interface
  4161. * @value: PHY register value
  4162. *
  4163. * Writes value to specified PHY register
  4164. **/
  4165. i40e_status i40e_write_phy_register_clause45(struct i40e_hw *hw,
  4166. u8 page, u16 reg, u8 phy_addr, u16 value)
  4167. {
  4168. i40e_status status = I40E_ERR_TIMEOUT;
  4169. u32 command = 0;
  4170. u16 retry = 1000;
  4171. u8 port_num = hw->func_caps.mdio_port_num;
  4172. command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
  4173. (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
  4174. (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
  4175. (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
  4176. (I40E_MDIO_CLAUSE45_STCODE_MASK) |
  4177. (I40E_GLGEN_MSCA_MDICMD_MASK) |
  4178. (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
  4179. wr32(hw, I40E_GLGEN_MSCA(port_num), command);
  4180. do {
  4181. command = rd32(hw, I40E_GLGEN_MSCA(port_num));
  4182. if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
  4183. status = 0;
  4184. break;
  4185. }
  4186. usleep_range(10, 20);
  4187. retry--;
  4188. } while (retry);
  4189. if (status) {
  4190. i40e_debug(hw, I40E_DEBUG_PHY,
  4191. "PHY: Can't write command to external PHY.\n");
  4192. goto phy_write_end;
  4193. }
  4194. command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
  4195. wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
  4196. command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
  4197. (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
  4198. (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) |
  4199. (I40E_MDIO_CLAUSE45_STCODE_MASK) |
  4200. (I40E_GLGEN_MSCA_MDICMD_MASK) |
  4201. (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
  4202. status = I40E_ERR_TIMEOUT;
  4203. retry = 1000;
  4204. wr32(hw, I40E_GLGEN_MSCA(port_num), command);
  4205. do {
  4206. command = rd32(hw, I40E_GLGEN_MSCA(port_num));
  4207. if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
  4208. status = 0;
  4209. break;
  4210. }
  4211. usleep_range(10, 20);
  4212. retry--;
  4213. } while (retry);
  4214. phy_write_end:
  4215. return status;
  4216. }
  4217. /**
  4218. * i40e_write_phy_register
  4219. * @hw: pointer to the HW structure
  4220. * @page: registers page number
  4221. * @reg: register address in the page
  4222. * @phy_addr: PHY address on MDIO interface
  4223. * @value: PHY register value
  4224. *
  4225. * Writes value to specified PHY register
  4226. **/
  4227. i40e_status i40e_write_phy_register(struct i40e_hw *hw,
  4228. u8 page, u16 reg, u8 phy_addr, u16 value)
  4229. {
  4230. i40e_status status;
  4231. switch (hw->device_id) {
  4232. case I40E_DEV_ID_1G_BASE_T_X722:
  4233. status = i40e_write_phy_register_clause22(hw, reg, phy_addr,
  4234. value);
  4235. break;
  4236. case I40E_DEV_ID_10G_BASE_T:
  4237. case I40E_DEV_ID_10G_BASE_T4:
  4238. case I40E_DEV_ID_10G_BASE_T_X722:
  4239. case I40E_DEV_ID_25G_B:
  4240. case I40E_DEV_ID_25G_SFP28:
  4241. status = i40e_write_phy_register_clause45(hw, page, reg,
  4242. phy_addr, value);
  4243. break;
  4244. default:
  4245. status = I40E_ERR_UNKNOWN_PHY;
  4246. break;
  4247. }
  4248. return status;
  4249. }
  4250. /**
  4251. * i40e_read_phy_register
  4252. * @hw: pointer to the HW structure
  4253. * @page: registers page number
  4254. * @reg: register address in the page
  4255. * @phy_addr: PHY address on MDIO interface
  4256. * @value: PHY register value
  4257. *
  4258. * Reads specified PHY register value
  4259. **/
  4260. i40e_status i40e_read_phy_register(struct i40e_hw *hw,
  4261. u8 page, u16 reg, u8 phy_addr, u16 *value)
  4262. {
  4263. i40e_status status;
  4264. switch (hw->device_id) {
  4265. case I40E_DEV_ID_1G_BASE_T_X722:
  4266. status = i40e_read_phy_register_clause22(hw, reg, phy_addr,
  4267. value);
  4268. break;
  4269. case I40E_DEV_ID_10G_BASE_T:
  4270. case I40E_DEV_ID_10G_BASE_T4:
  4271. case I40E_DEV_ID_10G_BASE_T_X722:
  4272. case I40E_DEV_ID_25G_B:
  4273. case I40E_DEV_ID_25G_SFP28:
  4274. status = i40e_read_phy_register_clause45(hw, page, reg,
  4275. phy_addr, value);
  4276. break;
  4277. default:
  4278. status = I40E_ERR_UNKNOWN_PHY;
  4279. break;
  4280. }
  4281. return status;
  4282. }
  4283. /**
  4284. * i40e_get_phy_address
  4285. * @hw: pointer to the HW structure
  4286. * @dev_num: PHY port num that address we want
  4287. *
  4288. * Gets PHY address for current port
  4289. **/
  4290. u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
  4291. {
  4292. u8 port_num = hw->func_caps.mdio_port_num;
  4293. u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));
  4294. return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;
  4295. }
  4296. /**
  4297. * i40e_blink_phy_led
  4298. * @hw: pointer to the HW structure
  4299. * @time: time how long led will blinks in secs
  4300. * @interval: gap between LED on and off in msecs
  4301. *
  4302. * Blinks PHY link LED
  4303. **/
  4304. i40e_status i40e_blink_phy_link_led(struct i40e_hw *hw,
  4305. u32 time, u32 interval)
  4306. {
  4307. i40e_status status = 0;
  4308. u32 i;
  4309. u16 led_ctl;
  4310. u16 gpio_led_port;
  4311. u16 led_reg;
  4312. u16 led_addr = I40E_PHY_LED_PROV_REG_1;
  4313. u8 phy_addr = 0;
  4314. u8 port_num;
  4315. i = rd32(hw, I40E_PFGEN_PORTNUM);
  4316. port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
  4317. phy_addr = i40e_get_phy_address(hw, port_num);
  4318. for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
  4319. led_addr++) {
  4320. status = i40e_read_phy_register_clause45(hw,
  4321. I40E_PHY_COM_REG_PAGE,
  4322. led_addr, phy_addr,
  4323. &led_reg);
  4324. if (status)
  4325. goto phy_blinking_end;
  4326. led_ctl = led_reg;
  4327. if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
  4328. led_reg = 0;
  4329. status = i40e_write_phy_register_clause45(hw,
  4330. I40E_PHY_COM_REG_PAGE,
  4331. led_addr, phy_addr,
  4332. led_reg);
  4333. if (status)
  4334. goto phy_blinking_end;
  4335. break;
  4336. }
  4337. }
  4338. if (time > 0 && interval > 0) {
  4339. for (i = 0; i < time * 1000; i += interval) {
  4340. status = i40e_read_phy_register_clause45(hw,
  4341. I40E_PHY_COM_REG_PAGE,
  4342. led_addr, phy_addr, &led_reg);
  4343. if (status)
  4344. goto restore_config;
  4345. if (led_reg & I40E_PHY_LED_MANUAL_ON)
  4346. led_reg = 0;
  4347. else
  4348. led_reg = I40E_PHY_LED_MANUAL_ON;
  4349. status = i40e_write_phy_register_clause45(hw,
  4350. I40E_PHY_COM_REG_PAGE,
  4351. led_addr, phy_addr, led_reg);
  4352. if (status)
  4353. goto restore_config;
  4354. msleep(interval);
  4355. }
  4356. }
  4357. restore_config:
  4358. status = i40e_write_phy_register_clause45(hw,
  4359. I40E_PHY_COM_REG_PAGE,
  4360. led_addr, phy_addr, led_ctl);
  4361. phy_blinking_end:
  4362. return status;
  4363. }
  4364. /**
  4365. * i40e_led_get_reg - read LED register
  4366. * @hw: pointer to the HW structure
  4367. * @led_addr: LED register address
  4368. * @reg_val: read register value
  4369. **/
  4370. static enum i40e_status_code i40e_led_get_reg(struct i40e_hw *hw, u16 led_addr,
  4371. u32 *reg_val)
  4372. {
  4373. enum i40e_status_code status;
  4374. u8 phy_addr = 0;
  4375. u8 port_num;
  4376. u32 i;
  4377. *reg_val = 0;
  4378. if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
  4379. status =
  4380. i40e_aq_get_phy_register(hw,
  4381. I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
  4382. I40E_PHY_COM_REG_PAGE,
  4383. I40E_PHY_LED_PROV_REG_1,
  4384. reg_val, NULL);
  4385. } else {
  4386. i = rd32(hw, I40E_PFGEN_PORTNUM);
  4387. port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
  4388. phy_addr = i40e_get_phy_address(hw, port_num);
  4389. status = i40e_read_phy_register_clause45(hw,
  4390. I40E_PHY_COM_REG_PAGE,
  4391. led_addr, phy_addr,
  4392. (u16 *)reg_val);
  4393. }
  4394. return status;
  4395. }
  4396. /**
  4397. * i40e_led_set_reg - write LED register
  4398. * @hw: pointer to the HW structure
  4399. * @led_addr: LED register address
  4400. * @reg_val: register value to write
  4401. **/
  4402. static enum i40e_status_code i40e_led_set_reg(struct i40e_hw *hw, u16 led_addr,
  4403. u32 reg_val)
  4404. {
  4405. enum i40e_status_code status;
  4406. u8 phy_addr = 0;
  4407. u8 port_num;
  4408. u32 i;
  4409. if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
  4410. status =
  4411. i40e_aq_set_phy_register(hw,
  4412. I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
  4413. I40E_PHY_COM_REG_PAGE,
  4414. I40E_PHY_LED_PROV_REG_1,
  4415. reg_val, NULL);
  4416. } else {
  4417. i = rd32(hw, I40E_PFGEN_PORTNUM);
  4418. port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
  4419. phy_addr = i40e_get_phy_address(hw, port_num);
  4420. status = i40e_write_phy_register_clause45(hw,
  4421. I40E_PHY_COM_REG_PAGE,
  4422. led_addr, phy_addr,
  4423. (u16)reg_val);
  4424. }
  4425. return status;
  4426. }
  4427. /**
  4428. * i40e_led_get_phy - return current on/off mode
  4429. * @hw: pointer to the hw struct
  4430. * @led_addr: address of led register to use
  4431. * @val: original value of register to use
  4432. *
  4433. **/
  4434. i40e_status i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
  4435. u16 *val)
  4436. {
  4437. i40e_status status = 0;
  4438. u16 gpio_led_port;
  4439. u8 phy_addr = 0;
  4440. u16 reg_val;
  4441. u16 temp_addr;
  4442. u8 port_num;
  4443. u32 i;
  4444. u32 reg_val_aq;
  4445. if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
  4446. status =
  4447. i40e_aq_get_phy_register(hw,
  4448. I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
  4449. I40E_PHY_COM_REG_PAGE,
  4450. I40E_PHY_LED_PROV_REG_1,
  4451. &reg_val_aq, NULL);
  4452. if (status == I40E_SUCCESS)
  4453. *val = (u16)reg_val_aq;
  4454. return status;
  4455. }
  4456. temp_addr = I40E_PHY_LED_PROV_REG_1;
  4457. i = rd32(hw, I40E_PFGEN_PORTNUM);
  4458. port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
  4459. phy_addr = i40e_get_phy_address(hw, port_num);
  4460. for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
  4461. temp_addr++) {
  4462. status = i40e_read_phy_register_clause45(hw,
  4463. I40E_PHY_COM_REG_PAGE,
  4464. temp_addr, phy_addr,
  4465. &reg_val);
  4466. if (status)
  4467. return status;
  4468. *val = reg_val;
  4469. if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
  4470. *led_addr = temp_addr;
  4471. break;
  4472. }
  4473. }
  4474. return status;
  4475. }
  4476. /**
  4477. * i40e_led_set_phy
  4478. * @hw: pointer to the HW structure
  4479. * @on: true or false
  4480. * @led_addr: address of led register to use
  4481. * @mode: original val plus bit for set or ignore
  4482. *
  4483. * Set led's on or off when controlled by the PHY
  4484. *
  4485. **/
  4486. i40e_status i40e_led_set_phy(struct i40e_hw *hw, bool on,
  4487. u16 led_addr, u32 mode)
  4488. {
  4489. i40e_status status = 0;
  4490. u32 led_ctl = 0;
  4491. u32 led_reg = 0;
  4492. status = i40e_led_get_reg(hw, led_addr, &led_reg);
  4493. if (status)
  4494. return status;
  4495. led_ctl = led_reg;
  4496. if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
  4497. led_reg = 0;
  4498. status = i40e_led_set_reg(hw, led_addr, led_reg);
  4499. if (status)
  4500. return status;
  4501. }
  4502. status = i40e_led_get_reg(hw, led_addr, &led_reg);
  4503. if (status)
  4504. goto restore_config;
  4505. if (on)
  4506. led_reg = I40E_PHY_LED_MANUAL_ON;
  4507. else
  4508. led_reg = 0;
  4509. status = i40e_led_set_reg(hw, led_addr, led_reg);
  4510. if (status)
  4511. goto restore_config;
  4512. if (mode & I40E_PHY_LED_MODE_ORIG) {
  4513. led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
  4514. status = i40e_led_set_reg(hw, led_addr, led_ctl);
  4515. }
  4516. return status;
  4517. restore_config:
  4518. status = i40e_led_set_reg(hw, led_addr, led_ctl);
  4519. return status;
  4520. }
  4521. /**
  4522. * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register
  4523. * @hw: pointer to the hw struct
  4524. * @reg_addr: register address
  4525. * @reg_val: ptr to register value
  4526. * @cmd_details: pointer to command details structure or NULL
  4527. *
  4528. * Use the firmware to read the Rx control register,
  4529. * especially useful if the Rx unit is under heavy pressure
  4530. **/
  4531. i40e_status i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
  4532. u32 reg_addr, u32 *reg_val,
  4533. struct i40e_asq_cmd_details *cmd_details)
  4534. {
  4535. struct i40e_aq_desc desc;
  4536. struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
  4537. (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
  4538. i40e_status status;
  4539. if (!reg_val)
  4540. return I40E_ERR_PARAM;
  4541. i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read);
  4542. cmd_resp->address = cpu_to_le32(reg_addr);
  4543. status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
  4544. if (status == 0)
  4545. *reg_val = le32_to_cpu(cmd_resp->value);
  4546. return status;
  4547. }
  4548. /**
  4549. * i40e_read_rx_ctl - read from an Rx control register
  4550. * @hw: pointer to the hw struct
  4551. * @reg_addr: register address
  4552. **/
  4553. u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
  4554. {
  4555. i40e_status status = 0;
  4556. bool use_register;
  4557. int retry = 5;
  4558. u32 val = 0;
  4559. use_register = (((hw->aq.api_maj_ver == 1) &&
  4560. (hw->aq.api_min_ver < 5)) ||
  4561. (hw->mac.type == I40E_MAC_X722));
  4562. if (!use_register) {
  4563. do_retry:
  4564. status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);
  4565. if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
  4566. usleep_range(1000, 2000);
  4567. retry--;
  4568. goto do_retry;
  4569. }
  4570. }
  4571. /* if the AQ access failed, try the old-fashioned way */
  4572. if (status || use_register)
  4573. val = rd32(hw, reg_addr);
  4574. return val;
  4575. }
  4576. /**
  4577. * i40e_aq_rx_ctl_write_register
  4578. * @hw: pointer to the hw struct
  4579. * @reg_addr: register address
  4580. * @reg_val: register value
  4581. * @cmd_details: pointer to command details structure or NULL
  4582. *
  4583. * Use the firmware to write to an Rx control register,
  4584. * especially useful if the Rx unit is under heavy pressure
  4585. **/
  4586. i40e_status i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
  4587. u32 reg_addr, u32 reg_val,
  4588. struct i40e_asq_cmd_details *cmd_details)
  4589. {
  4590. struct i40e_aq_desc desc;
  4591. struct i40e_aqc_rx_ctl_reg_read_write *cmd =
  4592. (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
  4593. i40e_status status;
  4594. i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write);
  4595. cmd->address = cpu_to_le32(reg_addr);
  4596. cmd->value = cpu_to_le32(reg_val);
  4597. status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
  4598. return status;
  4599. }
  4600. /**
  4601. * i40e_write_rx_ctl - write to an Rx control register
  4602. * @hw: pointer to the hw struct
  4603. * @reg_addr: register address
  4604. * @reg_val: register value
  4605. **/
  4606. void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
  4607. {
  4608. i40e_status status = 0;
  4609. bool use_register;
  4610. int retry = 5;
  4611. use_register = (((hw->aq.api_maj_ver == 1) &&
  4612. (hw->aq.api_min_ver < 5)) ||
  4613. (hw->mac.type == I40E_MAC_X722));
  4614. if (!use_register) {
  4615. do_retry:
  4616. status = i40e_aq_rx_ctl_write_register(hw, reg_addr,
  4617. reg_val, NULL);
  4618. if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
  4619. usleep_range(1000, 2000);
  4620. retry--;
  4621. goto do_retry;
  4622. }
  4623. }
  4624. /* if the AQ access failed, try the old-fashioned way */
  4625. if (status || use_register)
  4626. wr32(hw, reg_addr, reg_val);
  4627. }
  4628. /**
  4629. * i40e_aq_set_phy_register
  4630. * @hw: pointer to the hw struct
  4631. * @phy_select: select which phy should be accessed
  4632. * @dev_addr: PHY device address
  4633. * @reg_addr: PHY register address
  4634. * @reg_val: new register value
  4635. * @cmd_details: pointer to command details structure or NULL
  4636. *
  4637. * Write the external PHY register.
  4638. **/
  4639. i40e_status i40e_aq_set_phy_register(struct i40e_hw *hw,
  4640. u8 phy_select, u8 dev_addr,
  4641. u32 reg_addr, u32 reg_val,
  4642. struct i40e_asq_cmd_details *cmd_details)
  4643. {
  4644. struct i40e_aq_desc desc;
  4645. struct i40e_aqc_phy_register_access *cmd =
  4646. (struct i40e_aqc_phy_register_access *)&desc.params.raw;
  4647. i40e_status status;
  4648. i40e_fill_default_direct_cmd_desc(&desc,
  4649. i40e_aqc_opc_set_phy_register);
  4650. cmd->phy_interface = phy_select;
  4651. cmd->dev_address = dev_addr;
  4652. cmd->reg_address = cpu_to_le32(reg_addr);
  4653. cmd->reg_value = cpu_to_le32(reg_val);
  4654. status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
  4655. return status;
  4656. }
  4657. /**
  4658. * i40e_aq_get_phy_register
  4659. * @hw: pointer to the hw struct
  4660. * @phy_select: select which phy should be accessed
  4661. * @dev_addr: PHY device address
  4662. * @reg_addr: PHY register address
  4663. * @reg_val: read register value
  4664. * @cmd_details: pointer to command details structure or NULL
  4665. *
  4666. * Read the external PHY register.
  4667. **/
  4668. i40e_status i40e_aq_get_phy_register(struct i40e_hw *hw,
  4669. u8 phy_select, u8 dev_addr,
  4670. u32 reg_addr, u32 *reg_val,
  4671. struct i40e_asq_cmd_details *cmd_details)
  4672. {
  4673. struct i40e_aq_desc desc;
  4674. struct i40e_aqc_phy_register_access *cmd =
  4675. (struct i40e_aqc_phy_register_access *)&desc.params.raw;
  4676. i40e_status status;
  4677. i40e_fill_default_direct_cmd_desc(&desc,
  4678. i40e_aqc_opc_get_phy_register);
  4679. cmd->phy_interface = phy_select;
  4680. cmd->dev_address = dev_addr;
  4681. cmd->reg_address = cpu_to_le32(reg_addr);
  4682. status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
  4683. if (!status)
  4684. *reg_val = le32_to_cpu(cmd->reg_value);
  4685. return status;
  4686. }
  4687. /**
  4688. * i40e_aq_write_ddp - Write dynamic device personalization (ddp)
  4689. * @hw: pointer to the hw struct
  4690. * @buff: command buffer (size in bytes = buff_size)
  4691. * @buff_size: buffer size in bytes
  4692. * @track_id: package tracking id
  4693. * @error_offset: returns error offset
  4694. * @error_info: returns error information
  4695. * @cmd_details: pointer to command details structure or NULL
  4696. **/
  4697. enum
  4698. i40e_status_code i40e_aq_write_ddp(struct i40e_hw *hw, void *buff,
  4699. u16 buff_size, u32 track_id,
  4700. u32 *error_offset, u32 *error_info,
  4701. struct i40e_asq_cmd_details *cmd_details)
  4702. {
  4703. struct i40e_aq_desc desc;
  4704. struct i40e_aqc_write_personalization_profile *cmd =
  4705. (struct i40e_aqc_write_personalization_profile *)
  4706. &desc.params.raw;
  4707. struct i40e_aqc_write_ddp_resp *resp;
  4708. i40e_status status;
  4709. i40e_fill_default_direct_cmd_desc(&desc,
  4710. i40e_aqc_opc_write_personalization_profile);
  4711. desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
  4712. if (buff_size > I40E_AQ_LARGE_BUF)
  4713. desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
  4714. desc.datalen = cpu_to_le16(buff_size);
  4715. cmd->profile_track_id = cpu_to_le32(track_id);
  4716. status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
  4717. if (!status) {
  4718. resp = (struct i40e_aqc_write_ddp_resp *)&desc.params.raw;
  4719. if (error_offset)
  4720. *error_offset = le32_to_cpu(resp->error_offset);
  4721. if (error_info)
  4722. *error_info = le32_to_cpu(resp->error_info);
  4723. }
  4724. return status;
  4725. }
  4726. /**
  4727. * i40e_aq_get_ddp_list - Read dynamic device personalization (ddp)
  4728. * @hw: pointer to the hw struct
  4729. * @buff: command buffer (size in bytes = buff_size)
  4730. * @buff_size: buffer size in bytes
  4731. * @flags: AdminQ command flags
  4732. * @cmd_details: pointer to command details structure or NULL
  4733. **/
  4734. enum
  4735. i40e_status_code i40e_aq_get_ddp_list(struct i40e_hw *hw, void *buff,
  4736. u16 buff_size, u8 flags,
  4737. struct i40e_asq_cmd_details *cmd_details)
  4738. {
  4739. struct i40e_aq_desc desc;
  4740. struct i40e_aqc_get_applied_profiles *cmd =
  4741. (struct i40e_aqc_get_applied_profiles *)&desc.params.raw;
  4742. i40e_status status;
  4743. i40e_fill_default_direct_cmd_desc(&desc,
  4744. i40e_aqc_opc_get_personalization_profile_list);
  4745. desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
  4746. if (buff_size > I40E_AQ_LARGE_BUF)
  4747. desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
  4748. desc.datalen = cpu_to_le16(buff_size);
  4749. cmd->flags = flags;
  4750. status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
  4751. return status;
  4752. }
  4753. /**
  4754. * i40e_find_segment_in_package
  4755. * @segment_type: the segment type to search for (i.e., SEGMENT_TYPE_I40E)
  4756. * @pkg_hdr: pointer to the package header to be searched
  4757. *
  4758. * This function searches a package file for a particular segment type. On
  4759. * success it returns a pointer to the segment header, otherwise it will
  4760. * return NULL.
  4761. **/
  4762. struct i40e_generic_seg_header *
  4763. i40e_find_segment_in_package(u32 segment_type,
  4764. struct i40e_package_header *pkg_hdr)
  4765. {
  4766. struct i40e_generic_seg_header *segment;
  4767. u32 i;
  4768. /* Search all package segments for the requested segment type */
  4769. for (i = 0; i < pkg_hdr->segment_count; i++) {
  4770. segment =
  4771. (struct i40e_generic_seg_header *)((u8 *)pkg_hdr +
  4772. pkg_hdr->segment_offset[i]);
  4773. if (segment->type == segment_type)
  4774. return segment;
  4775. }
  4776. return NULL;
  4777. }
  4778. /**
  4779. * i40e_write_profile
  4780. * @hw: pointer to the hardware structure
  4781. * @profile: pointer to the profile segment of the package to be downloaded
  4782. * @track_id: package tracking id
  4783. *
  4784. * Handles the download of a complete package.
  4785. */
  4786. enum i40e_status_code
  4787. i40e_write_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
  4788. u32 track_id)
  4789. {
  4790. i40e_status status = 0;
  4791. struct i40e_section_table *sec_tbl;
  4792. struct i40e_profile_section_header *sec = NULL;
  4793. u32 dev_cnt;
  4794. u32 vendor_dev_id;
  4795. u32 *nvm;
  4796. u32 section_size = 0;
  4797. u32 offset = 0, info = 0;
  4798. u32 i;
  4799. dev_cnt = profile->device_table_count;
  4800. for (i = 0; i < dev_cnt; i++) {
  4801. vendor_dev_id = profile->device_table[i].vendor_dev_id;
  4802. if ((vendor_dev_id >> 16) == PCI_VENDOR_ID_INTEL)
  4803. if (hw->device_id == (vendor_dev_id & 0xFFFF))
  4804. break;
  4805. }
  4806. if (i == dev_cnt) {
  4807. i40e_debug(hw, I40E_DEBUG_PACKAGE, "Device doesn't support DDP");
  4808. return I40E_ERR_DEVICE_NOT_SUPPORTED;
  4809. }
  4810. nvm = (u32 *)&profile->device_table[dev_cnt];
  4811. sec_tbl = (struct i40e_section_table *)&nvm[nvm[0] + 1];
  4812. for (i = 0; i < sec_tbl->section_count; i++) {
  4813. sec = (struct i40e_profile_section_header *)((u8 *)profile +
  4814. sec_tbl->section_offset[i]);
  4815. /* Skip 'AQ', 'note' and 'name' sections */
  4816. if (sec->section.type != SECTION_TYPE_MMIO)
  4817. continue;
  4818. section_size = sec->section.size +
  4819. sizeof(struct i40e_profile_section_header);
  4820. /* Write profile */
  4821. status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size,
  4822. track_id, &offset, &info, NULL);
  4823. if (status) {
  4824. i40e_debug(hw, I40E_DEBUG_PACKAGE,
  4825. "Failed to write profile: offset %d, info %d",
  4826. offset, info);
  4827. break;
  4828. }
  4829. }
  4830. return status;
  4831. }
  4832. /**
  4833. * i40e_add_pinfo_to_list
  4834. * @hw: pointer to the hardware structure
  4835. * @profile: pointer to the profile segment of the package
  4836. * @profile_info_sec: buffer for information section
  4837. * @track_id: package tracking id
  4838. *
  4839. * Register a profile to the list of loaded profiles.
  4840. */
  4841. enum i40e_status_code
  4842. i40e_add_pinfo_to_list(struct i40e_hw *hw,
  4843. struct i40e_profile_segment *profile,
  4844. u8 *profile_info_sec, u32 track_id)
  4845. {
  4846. i40e_status status = 0;
  4847. struct i40e_profile_section_header *sec = NULL;
  4848. struct i40e_profile_info *pinfo;
  4849. u32 offset = 0, info = 0;
  4850. sec = (struct i40e_profile_section_header *)profile_info_sec;
  4851. sec->tbl_size = 1;
  4852. sec->data_end = sizeof(struct i40e_profile_section_header) +
  4853. sizeof(struct i40e_profile_info);
  4854. sec->section.type = SECTION_TYPE_INFO;
  4855. sec->section.offset = sizeof(struct i40e_profile_section_header);
  4856. sec->section.size = sizeof(struct i40e_profile_info);
  4857. pinfo = (struct i40e_profile_info *)(profile_info_sec +
  4858. sec->section.offset);
  4859. pinfo->track_id = track_id;
  4860. pinfo->version = profile->version;
  4861. pinfo->op = I40E_DDP_ADD_TRACKID;
  4862. memcpy(pinfo->name, profile->name, I40E_DDP_NAME_SIZE);
  4863. status = i40e_aq_write_ddp(hw, (void *)sec, sec->data_end,
  4864. track_id, &offset, &info, NULL);
  4865. return status;
  4866. }
  4867. /**
  4868. * i40e_aq_add_cloud_filters
  4869. * @hw: pointer to the hardware structure
  4870. * @seid: VSI seid to add cloud filters from
  4871. * @filters: Buffer which contains the filters to be added
  4872. * @filter_count: number of filters contained in the buffer
  4873. *
  4874. * Set the cloud filters for a given VSI. The contents of the
  4875. * i40e_aqc_cloud_filters_element_data are filled in by the caller
  4876. * of the function.
  4877. *
  4878. **/
  4879. enum i40e_status_code
  4880. i40e_aq_add_cloud_filters(struct i40e_hw *hw, u16 seid,
  4881. struct i40e_aqc_cloud_filters_element_data *filters,
  4882. u8 filter_count)
  4883. {
  4884. struct i40e_aq_desc desc;
  4885. struct i40e_aqc_add_remove_cloud_filters *cmd =
  4886. (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
  4887. enum i40e_status_code status;
  4888. u16 buff_len;
  4889. i40e_fill_default_direct_cmd_desc(&desc,
  4890. i40e_aqc_opc_add_cloud_filters);
  4891. buff_len = filter_count * sizeof(*filters);
  4892. desc.datalen = cpu_to_le16(buff_len);
  4893. desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
  4894. cmd->num_filters = filter_count;
  4895. cmd->seid = cpu_to_le16(seid);
  4896. status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
  4897. return status;
  4898. }
  4899. /**
  4900. * i40e_aq_add_cloud_filters_bb
  4901. * @hw: pointer to the hardware structure
  4902. * @seid: VSI seid to add cloud filters from
  4903. * @filters: Buffer which contains the filters in big buffer to be added
  4904. * @filter_count: number of filters contained in the buffer
  4905. *
  4906. * Set the big buffer cloud filters for a given VSI. The contents of the
  4907. * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the
  4908. * function.
  4909. *
  4910. **/
  4911. enum i40e_status_code
  4912. i40e_aq_add_cloud_filters_bb(struct i40e_hw *hw, u16 seid,
  4913. struct i40e_aqc_cloud_filters_element_bb *filters,
  4914. u8 filter_count)
  4915. {
  4916. struct i40e_aq_desc desc;
  4917. struct i40e_aqc_add_remove_cloud_filters *cmd =
  4918. (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
  4919. i40e_status status;
  4920. u16 buff_len;
  4921. int i;
  4922. i40e_fill_default_direct_cmd_desc(&desc,
  4923. i40e_aqc_opc_add_cloud_filters);
  4924. buff_len = filter_count * sizeof(*filters);
  4925. desc.datalen = cpu_to_le16(buff_len);
  4926. desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
  4927. cmd->num_filters = filter_count;
  4928. cmd->seid = cpu_to_le16(seid);
  4929. cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB;
  4930. for (i = 0; i < filter_count; i++) {
  4931. u16 tnl_type;
  4932. u32 ti;
  4933. tnl_type = (le16_to_cpu(filters[i].element.flags) &
  4934. I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
  4935. I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
  4936. /* Due to hardware eccentricities, the VNI for Geneve is shifted
  4937. * one more byte further than normally used for Tenant ID in
  4938. * other tunnel types.
  4939. */
  4940. if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
  4941. ti = le32_to_cpu(filters[i].element.tenant_id);
  4942. filters[i].element.tenant_id = cpu_to_le32(ti << 8);
  4943. }
  4944. }
  4945. status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
  4946. return status;
  4947. }
  4948. /**
  4949. * i40e_aq_rem_cloud_filters
  4950. * @hw: pointer to the hardware structure
  4951. * @seid: VSI seid to remove cloud filters from
  4952. * @filters: Buffer which contains the filters to be removed
  4953. * @filter_count: number of filters contained in the buffer
  4954. *
  4955. * Remove the cloud filters for a given VSI. The contents of the
  4956. * i40e_aqc_cloud_filters_element_data are filled in by the caller
  4957. * of the function.
  4958. *
  4959. **/
  4960. enum i40e_status_code
  4961. i40e_aq_rem_cloud_filters(struct i40e_hw *hw, u16 seid,
  4962. struct i40e_aqc_cloud_filters_element_data *filters,
  4963. u8 filter_count)
  4964. {
  4965. struct i40e_aq_desc desc;
  4966. struct i40e_aqc_add_remove_cloud_filters *cmd =
  4967. (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
  4968. enum i40e_status_code status;
  4969. u16 buff_len;
  4970. i40e_fill_default_direct_cmd_desc(&desc,
  4971. i40e_aqc_opc_remove_cloud_filters);
  4972. buff_len = filter_count * sizeof(*filters);
  4973. desc.datalen = cpu_to_le16(buff_len);
  4974. desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
  4975. cmd->num_filters = filter_count;
  4976. cmd->seid = cpu_to_le16(seid);
  4977. status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
  4978. return status;
  4979. }
  4980. /**
  4981. * i40e_aq_rem_cloud_filters_bb
  4982. * @hw: pointer to the hardware structure
  4983. * @seid: VSI seid to remove cloud filters from
  4984. * @filters: Buffer which contains the filters in big buffer to be removed
  4985. * @filter_count: number of filters contained in the buffer
  4986. *
  4987. * Remove the big buffer cloud filters for a given VSI. The contents of the
  4988. * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the
  4989. * function.
  4990. *
  4991. **/
  4992. enum i40e_status_code
  4993. i40e_aq_rem_cloud_filters_bb(struct i40e_hw *hw, u16 seid,
  4994. struct i40e_aqc_cloud_filters_element_bb *filters,
  4995. u8 filter_count)
  4996. {
  4997. struct i40e_aq_desc desc;
  4998. struct i40e_aqc_add_remove_cloud_filters *cmd =
  4999. (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
  5000. i40e_status status;
  5001. u16 buff_len;
  5002. int i;
  5003. i40e_fill_default_direct_cmd_desc(&desc,
  5004. i40e_aqc_opc_remove_cloud_filters);
  5005. buff_len = filter_count * sizeof(*filters);
  5006. desc.datalen = cpu_to_le16(buff_len);
  5007. desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
  5008. cmd->num_filters = filter_count;
  5009. cmd->seid = cpu_to_le16(seid);
  5010. cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB;
  5011. for (i = 0; i < filter_count; i++) {
  5012. u16 tnl_type;
  5013. u32 ti;
  5014. tnl_type = (le16_to_cpu(filters[i].element.flags) &
  5015. I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
  5016. I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
  5017. /* Due to hardware eccentricities, the VNI for Geneve is shifted
  5018. * one more byte further than normally used for Tenant ID in
  5019. * other tunnel types.
  5020. */
  5021. if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
  5022. ti = le32_to_cpu(filters[i].element.tenant_id);
  5023. filters[i].element.tenant_id = cpu_to_le32(ti << 8);
  5024. }
  5025. }
  5026. status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
  5027. return status;
  5028. }