armada_overlay.c 15 KB

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  1. /*
  2. * Copyright (C) 2012 Russell King
  3. * Rewritten from the dovefb driver, and Armada510 manuals.
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License version 2 as
  7. * published by the Free Software Foundation.
  8. */
  9. #include <drm/drmP.h>
  10. #include <drm/drm_plane_helper.h>
  11. #include "armada_crtc.h"
  12. #include "armada_drm.h"
  13. #include "armada_fb.h"
  14. #include "armada_gem.h"
  15. #include "armada_hw.h"
  16. #include <drm/armada_drm.h>
  17. #include "armada_ioctlP.h"
  18. struct armada_ovl_plane_properties {
  19. uint32_t colorkey_yr;
  20. uint32_t colorkey_ug;
  21. uint32_t colorkey_vb;
  22. #define K2R(val) (((val) >> 0) & 0xff)
  23. #define K2G(val) (((val) >> 8) & 0xff)
  24. #define K2B(val) (((val) >> 16) & 0xff)
  25. int16_t brightness;
  26. uint16_t contrast;
  27. uint16_t saturation;
  28. uint32_t colorkey_mode;
  29. };
  30. struct armada_ovl_plane {
  31. struct armada_plane base;
  32. struct drm_framebuffer *old_fb;
  33. uint32_t src_hw;
  34. uint32_t dst_hw;
  35. uint32_t dst_yx;
  36. uint32_t ctrl0;
  37. struct {
  38. struct armada_plane_work work;
  39. struct armada_regs regs[13];
  40. } vbl;
  41. struct armada_ovl_plane_properties prop;
  42. };
  43. #define drm_to_armada_ovl_plane(p) \
  44. container_of(p, struct armada_ovl_plane, base.base)
  45. static void
  46. armada_ovl_update_attr(struct armada_ovl_plane_properties *prop,
  47. struct armada_crtc *dcrtc)
  48. {
  49. writel_relaxed(prop->colorkey_yr, dcrtc->base + LCD_SPU_COLORKEY_Y);
  50. writel_relaxed(prop->colorkey_ug, dcrtc->base + LCD_SPU_COLORKEY_U);
  51. writel_relaxed(prop->colorkey_vb, dcrtc->base + LCD_SPU_COLORKEY_V);
  52. writel_relaxed(prop->brightness << 16 | prop->contrast,
  53. dcrtc->base + LCD_SPU_CONTRAST);
  54. /* Docs say 15:0, but it seems to actually be 31:16 on Armada 510 */
  55. writel_relaxed(prop->saturation << 16,
  56. dcrtc->base + LCD_SPU_SATURATION);
  57. writel_relaxed(0x00002000, dcrtc->base + LCD_SPU_CBSH_HUE);
  58. spin_lock_irq(&dcrtc->irq_lock);
  59. armada_updatel(prop->colorkey_mode | CFG_ALPHAM_GRA,
  60. CFG_CKMODE_MASK | CFG_ALPHAM_MASK | CFG_ALPHA_MASK,
  61. dcrtc->base + LCD_SPU_DMA_CTRL1);
  62. armada_updatel(ADV_GRACOLORKEY, 0, dcrtc->base + LCD_SPU_ADV_REG);
  63. spin_unlock_irq(&dcrtc->irq_lock);
  64. }
  65. static void armada_ovl_retire_fb(struct armada_ovl_plane *dplane,
  66. struct drm_framebuffer *fb)
  67. {
  68. struct drm_framebuffer *old_fb;
  69. old_fb = xchg(&dplane->old_fb, fb);
  70. if (old_fb)
  71. armada_drm_queue_unref_work(dplane->base.base.dev, old_fb);
  72. }
  73. /* === Plane support === */
  74. static void armada_ovl_plane_work(struct armada_crtc *dcrtc,
  75. struct armada_plane *plane, struct armada_plane_work *work)
  76. {
  77. struct armada_ovl_plane *dplane = container_of(plane, struct armada_ovl_plane, base);
  78. armada_drm_crtc_update_regs(dcrtc, dplane->vbl.regs);
  79. armada_ovl_retire_fb(dplane, NULL);
  80. }
  81. static int
  82. armada_ovl_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
  83. struct drm_framebuffer *fb,
  84. int crtc_x, int crtc_y, unsigned crtc_w, unsigned crtc_h,
  85. uint32_t src_x, uint32_t src_y, uint32_t src_w, uint32_t src_h)
  86. {
  87. struct armada_ovl_plane *dplane = drm_to_armada_ovl_plane(plane);
  88. struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
  89. struct drm_rect src = {
  90. .x1 = src_x,
  91. .y1 = src_y,
  92. .x2 = src_x + src_w,
  93. .y2 = src_y + src_h,
  94. };
  95. struct drm_rect dest = {
  96. .x1 = crtc_x,
  97. .y1 = crtc_y,
  98. .x2 = crtc_x + crtc_w,
  99. .y2 = crtc_y + crtc_h,
  100. };
  101. const struct drm_rect clip = {
  102. .x2 = crtc->mode.hdisplay,
  103. .y2 = crtc->mode.vdisplay,
  104. };
  105. uint32_t val, ctrl0;
  106. unsigned idx = 0;
  107. bool visible;
  108. int ret;
  109. ret = drm_plane_helper_check_update(plane, crtc, fb, &src, &dest, &clip,
  110. BIT(DRM_ROTATE_0),
  111. 0, INT_MAX, true, false, &visible);
  112. if (ret)
  113. return ret;
  114. ctrl0 = CFG_DMA_FMT(drm_fb_to_armada_fb(fb)->fmt) |
  115. CFG_DMA_MOD(drm_fb_to_armada_fb(fb)->mod) |
  116. CFG_CBSH_ENA | CFG_DMA_HSMOOTH | CFG_DMA_ENA;
  117. /* Does the position/size result in nothing to display? */
  118. if (!visible)
  119. ctrl0 &= ~CFG_DMA_ENA;
  120. if (!dcrtc->plane) {
  121. dcrtc->plane = plane;
  122. armada_ovl_update_attr(&dplane->prop, dcrtc);
  123. }
  124. /* FIXME: overlay on an interlaced display */
  125. /* Just updating the position/size? */
  126. if (plane->fb == fb && dplane->ctrl0 == ctrl0) {
  127. val = (drm_rect_height(&src) & 0xffff0000) |
  128. drm_rect_width(&src) >> 16;
  129. dplane->src_hw = val;
  130. writel_relaxed(val, dcrtc->base + LCD_SPU_DMA_HPXL_VLN);
  131. val = drm_rect_height(&dest) << 16 | drm_rect_width(&dest);
  132. dplane->dst_hw = val;
  133. writel_relaxed(val, dcrtc->base + LCD_SPU_DZM_HPXL_VLN);
  134. val = dest.y1 << 16 | dest.x1;
  135. dplane->dst_yx = val;
  136. writel_relaxed(val, dcrtc->base + LCD_SPU_DMA_OVSA_HPXL_VLN);
  137. return 0;
  138. } else if (~dplane->ctrl0 & ctrl0 & CFG_DMA_ENA) {
  139. /* Power up the Y/U/V FIFOs on ENA 0->1 transitions */
  140. armada_updatel(0, CFG_PDWN16x66 | CFG_PDWN32x66,
  141. dcrtc->base + LCD_SPU_SRAM_PARA1);
  142. }
  143. if (armada_drm_plane_work_wait(&dplane->base, HZ / 25) == 0)
  144. armada_drm_plane_work_cancel(dcrtc, &dplane->base);
  145. if (plane->fb != fb) {
  146. struct armada_gem_object *obj = drm_fb_obj(fb);
  147. uint32_t addr[3], pixel_format;
  148. int i, num_planes, hsub;
  149. /*
  150. * Take a reference on the new framebuffer - we want to
  151. * hold on to it while the hardware is displaying it.
  152. */
  153. drm_framebuffer_reference(fb);
  154. if (plane->fb)
  155. armada_ovl_retire_fb(dplane, plane->fb);
  156. src_y = src.y1 >> 16;
  157. src_x = src.x1 >> 16;
  158. pixel_format = fb->pixel_format;
  159. hsub = drm_format_horz_chroma_subsampling(pixel_format);
  160. num_planes = drm_format_num_planes(pixel_format);
  161. /*
  162. * Annoyingly, shifting a YUYV-format image by one pixel
  163. * causes the U/V planes to toggle. Toggle the UV swap.
  164. * (Unfortunately, this causes momentary colour flickering.)
  165. */
  166. if (src_x & (hsub - 1) && num_planes == 1)
  167. ctrl0 ^= CFG_DMA_MOD(CFG_SWAPUV);
  168. for (i = 0; i < num_planes; i++)
  169. addr[i] = obj->dev_addr + fb->offsets[i] +
  170. src_y * fb->pitches[i] +
  171. src_x * drm_format_plane_cpp(pixel_format, i);
  172. for (; i < ARRAY_SIZE(addr); i++)
  173. addr[i] = 0;
  174. armada_reg_queue_set(dplane->vbl.regs, idx, addr[0],
  175. LCD_SPU_DMA_START_ADDR_Y0);
  176. armada_reg_queue_set(dplane->vbl.regs, idx, addr[1],
  177. LCD_SPU_DMA_START_ADDR_U0);
  178. armada_reg_queue_set(dplane->vbl.regs, idx, addr[2],
  179. LCD_SPU_DMA_START_ADDR_V0);
  180. armada_reg_queue_set(dplane->vbl.regs, idx, addr[0],
  181. LCD_SPU_DMA_START_ADDR_Y1);
  182. armada_reg_queue_set(dplane->vbl.regs, idx, addr[1],
  183. LCD_SPU_DMA_START_ADDR_U1);
  184. armada_reg_queue_set(dplane->vbl.regs, idx, addr[2],
  185. LCD_SPU_DMA_START_ADDR_V1);
  186. val = fb->pitches[0] << 16 | fb->pitches[0];
  187. armada_reg_queue_set(dplane->vbl.regs, idx, val,
  188. LCD_SPU_DMA_PITCH_YC);
  189. val = fb->pitches[1] << 16 | fb->pitches[2];
  190. armada_reg_queue_set(dplane->vbl.regs, idx, val,
  191. LCD_SPU_DMA_PITCH_UV);
  192. }
  193. val = (drm_rect_height(&src) & 0xffff0000) | drm_rect_width(&src) >> 16;
  194. if (dplane->src_hw != val) {
  195. dplane->src_hw = val;
  196. armada_reg_queue_set(dplane->vbl.regs, idx, val,
  197. LCD_SPU_DMA_HPXL_VLN);
  198. }
  199. val = drm_rect_height(&dest) << 16 | drm_rect_width(&dest);
  200. if (dplane->dst_hw != val) {
  201. dplane->dst_hw = val;
  202. armada_reg_queue_set(dplane->vbl.regs, idx, val,
  203. LCD_SPU_DZM_HPXL_VLN);
  204. }
  205. val = dest.y1 << 16 | dest.x1;
  206. if (dplane->dst_yx != val) {
  207. dplane->dst_yx = val;
  208. armada_reg_queue_set(dplane->vbl.regs, idx, val,
  209. LCD_SPU_DMA_OVSA_HPXL_VLN);
  210. }
  211. if (dplane->ctrl0 != ctrl0) {
  212. dplane->ctrl0 = ctrl0;
  213. armada_reg_queue_mod(dplane->vbl.regs, idx, ctrl0,
  214. CFG_CBSH_ENA | CFG_DMAFORMAT | CFG_DMA_FTOGGLE |
  215. CFG_DMA_HSMOOTH | CFG_DMA_TSTMODE |
  216. CFG_DMA_MOD(CFG_SWAPRB | CFG_SWAPUV | CFG_SWAPYU |
  217. CFG_YUV2RGB) | CFG_DMA_ENA,
  218. LCD_SPU_DMA_CTRL0);
  219. }
  220. if (idx) {
  221. armada_reg_queue_end(dplane->vbl.regs, idx);
  222. armada_drm_plane_work_queue(dcrtc, &dplane->base,
  223. &dplane->vbl.work);
  224. }
  225. return 0;
  226. }
  227. static int armada_ovl_plane_disable(struct drm_plane *plane)
  228. {
  229. struct armada_ovl_plane *dplane = drm_to_armada_ovl_plane(plane);
  230. struct drm_framebuffer *fb;
  231. struct armada_crtc *dcrtc;
  232. if (!dplane->base.base.crtc)
  233. return 0;
  234. dcrtc = drm_to_armada_crtc(dplane->base.base.crtc);
  235. armada_drm_plane_work_cancel(dcrtc, &dplane->base);
  236. armada_drm_crtc_plane_disable(dcrtc, plane);
  237. dcrtc->plane = NULL;
  238. dplane->ctrl0 = 0;
  239. fb = xchg(&dplane->old_fb, NULL);
  240. if (fb)
  241. drm_framebuffer_unreference(fb);
  242. return 0;
  243. }
  244. static void armada_ovl_plane_destroy(struct drm_plane *plane)
  245. {
  246. struct armada_ovl_plane *dplane = drm_to_armada_ovl_plane(plane);
  247. drm_plane_cleanup(plane);
  248. kfree(dplane);
  249. }
  250. static int armada_ovl_plane_set_property(struct drm_plane *plane,
  251. struct drm_property *property, uint64_t val)
  252. {
  253. struct armada_private *priv = plane->dev->dev_private;
  254. struct armada_ovl_plane *dplane = drm_to_armada_ovl_plane(plane);
  255. bool update_attr = false;
  256. if (property == priv->colorkey_prop) {
  257. #define CCC(v) ((v) << 24 | (v) << 16 | (v) << 8)
  258. dplane->prop.colorkey_yr = CCC(K2R(val));
  259. dplane->prop.colorkey_ug = CCC(K2G(val));
  260. dplane->prop.colorkey_vb = CCC(K2B(val));
  261. #undef CCC
  262. update_attr = true;
  263. } else if (property == priv->colorkey_min_prop) {
  264. dplane->prop.colorkey_yr &= ~0x00ff0000;
  265. dplane->prop.colorkey_yr |= K2R(val) << 16;
  266. dplane->prop.colorkey_ug &= ~0x00ff0000;
  267. dplane->prop.colorkey_ug |= K2G(val) << 16;
  268. dplane->prop.colorkey_vb &= ~0x00ff0000;
  269. dplane->prop.colorkey_vb |= K2B(val) << 16;
  270. update_attr = true;
  271. } else if (property == priv->colorkey_max_prop) {
  272. dplane->prop.colorkey_yr &= ~0xff000000;
  273. dplane->prop.colorkey_yr |= K2R(val) << 24;
  274. dplane->prop.colorkey_ug &= ~0xff000000;
  275. dplane->prop.colorkey_ug |= K2G(val) << 24;
  276. dplane->prop.colorkey_vb &= ~0xff000000;
  277. dplane->prop.colorkey_vb |= K2B(val) << 24;
  278. update_attr = true;
  279. } else if (property == priv->colorkey_val_prop) {
  280. dplane->prop.colorkey_yr &= ~0x0000ff00;
  281. dplane->prop.colorkey_yr |= K2R(val) << 8;
  282. dplane->prop.colorkey_ug &= ~0x0000ff00;
  283. dplane->prop.colorkey_ug |= K2G(val) << 8;
  284. dplane->prop.colorkey_vb &= ~0x0000ff00;
  285. dplane->prop.colorkey_vb |= K2B(val) << 8;
  286. update_attr = true;
  287. } else if (property == priv->colorkey_alpha_prop) {
  288. dplane->prop.colorkey_yr &= ~0x000000ff;
  289. dplane->prop.colorkey_yr |= K2R(val);
  290. dplane->prop.colorkey_ug &= ~0x000000ff;
  291. dplane->prop.colorkey_ug |= K2G(val);
  292. dplane->prop.colorkey_vb &= ~0x000000ff;
  293. dplane->prop.colorkey_vb |= K2B(val);
  294. update_attr = true;
  295. } else if (property == priv->colorkey_mode_prop) {
  296. dplane->prop.colorkey_mode &= ~CFG_CKMODE_MASK;
  297. dplane->prop.colorkey_mode |= CFG_CKMODE(val);
  298. update_attr = true;
  299. } else if (property == priv->brightness_prop) {
  300. dplane->prop.brightness = val - 256;
  301. update_attr = true;
  302. } else if (property == priv->contrast_prop) {
  303. dplane->prop.contrast = val;
  304. update_attr = true;
  305. } else if (property == priv->saturation_prop) {
  306. dplane->prop.saturation = val;
  307. update_attr = true;
  308. }
  309. if (update_attr && dplane->base.base.crtc)
  310. armada_ovl_update_attr(&dplane->prop,
  311. drm_to_armada_crtc(dplane->base.base.crtc));
  312. return 0;
  313. }
  314. static const struct drm_plane_funcs armada_ovl_plane_funcs = {
  315. .update_plane = armada_ovl_plane_update,
  316. .disable_plane = armada_ovl_plane_disable,
  317. .destroy = armada_ovl_plane_destroy,
  318. .set_property = armada_ovl_plane_set_property,
  319. };
  320. static const uint32_t armada_ovl_formats[] = {
  321. DRM_FORMAT_UYVY,
  322. DRM_FORMAT_YUYV,
  323. DRM_FORMAT_YUV420,
  324. DRM_FORMAT_YVU420,
  325. DRM_FORMAT_YUV422,
  326. DRM_FORMAT_YVU422,
  327. DRM_FORMAT_VYUY,
  328. DRM_FORMAT_YVYU,
  329. DRM_FORMAT_ARGB8888,
  330. DRM_FORMAT_ABGR8888,
  331. DRM_FORMAT_XRGB8888,
  332. DRM_FORMAT_XBGR8888,
  333. DRM_FORMAT_RGB888,
  334. DRM_FORMAT_BGR888,
  335. DRM_FORMAT_ARGB1555,
  336. DRM_FORMAT_ABGR1555,
  337. DRM_FORMAT_RGB565,
  338. DRM_FORMAT_BGR565,
  339. };
  340. static struct drm_prop_enum_list armada_drm_colorkey_enum_list[] = {
  341. { CKMODE_DISABLE, "disabled" },
  342. { CKMODE_Y, "Y component" },
  343. { CKMODE_U, "U component" },
  344. { CKMODE_V, "V component" },
  345. { CKMODE_RGB, "RGB" },
  346. { CKMODE_R, "R component" },
  347. { CKMODE_G, "G component" },
  348. { CKMODE_B, "B component" },
  349. };
  350. static int armada_overlay_create_properties(struct drm_device *dev)
  351. {
  352. struct armada_private *priv = dev->dev_private;
  353. if (priv->colorkey_prop)
  354. return 0;
  355. priv->colorkey_prop = drm_property_create_range(dev, 0,
  356. "colorkey", 0, 0xffffff);
  357. priv->colorkey_min_prop = drm_property_create_range(dev, 0,
  358. "colorkey_min", 0, 0xffffff);
  359. priv->colorkey_max_prop = drm_property_create_range(dev, 0,
  360. "colorkey_max", 0, 0xffffff);
  361. priv->colorkey_val_prop = drm_property_create_range(dev, 0,
  362. "colorkey_val", 0, 0xffffff);
  363. priv->colorkey_alpha_prop = drm_property_create_range(dev, 0,
  364. "colorkey_alpha", 0, 0xffffff);
  365. priv->colorkey_mode_prop = drm_property_create_enum(dev, 0,
  366. "colorkey_mode",
  367. armada_drm_colorkey_enum_list,
  368. ARRAY_SIZE(armada_drm_colorkey_enum_list));
  369. priv->brightness_prop = drm_property_create_range(dev, 0,
  370. "brightness", 0, 256 + 255);
  371. priv->contrast_prop = drm_property_create_range(dev, 0,
  372. "contrast", 0, 0x7fff);
  373. priv->saturation_prop = drm_property_create_range(dev, 0,
  374. "saturation", 0, 0x7fff);
  375. if (!priv->colorkey_prop)
  376. return -ENOMEM;
  377. return 0;
  378. }
  379. int armada_overlay_plane_create(struct drm_device *dev, unsigned long crtcs)
  380. {
  381. struct armada_private *priv = dev->dev_private;
  382. struct drm_mode_object *mobj;
  383. struct armada_ovl_plane *dplane;
  384. int ret;
  385. ret = armada_overlay_create_properties(dev);
  386. if (ret)
  387. return ret;
  388. dplane = kzalloc(sizeof(*dplane), GFP_KERNEL);
  389. if (!dplane)
  390. return -ENOMEM;
  391. ret = armada_drm_plane_init(&dplane->base);
  392. if (ret) {
  393. kfree(dplane);
  394. return ret;
  395. }
  396. dplane->vbl.work.fn = armada_ovl_plane_work;
  397. ret = drm_universal_plane_init(dev, &dplane->base.base, crtcs,
  398. &armada_ovl_plane_funcs,
  399. armada_ovl_formats,
  400. ARRAY_SIZE(armada_ovl_formats),
  401. DRM_PLANE_TYPE_OVERLAY, NULL);
  402. if (ret) {
  403. kfree(dplane);
  404. return ret;
  405. }
  406. dplane->prop.colorkey_yr = 0xfefefe00;
  407. dplane->prop.colorkey_ug = 0x01010100;
  408. dplane->prop.colorkey_vb = 0x01010100;
  409. dplane->prop.colorkey_mode = CFG_CKMODE(CKMODE_RGB);
  410. dplane->prop.brightness = 0;
  411. dplane->prop.contrast = 0x4000;
  412. dplane->prop.saturation = 0x4000;
  413. mobj = &dplane->base.base.base;
  414. drm_object_attach_property(mobj, priv->colorkey_prop,
  415. 0x0101fe);
  416. drm_object_attach_property(mobj, priv->colorkey_min_prop,
  417. 0x0101fe);
  418. drm_object_attach_property(mobj, priv->colorkey_max_prop,
  419. 0x0101fe);
  420. drm_object_attach_property(mobj, priv->colorkey_val_prop,
  421. 0x0101fe);
  422. drm_object_attach_property(mobj, priv->colorkey_alpha_prop,
  423. 0x000000);
  424. drm_object_attach_property(mobj, priv->colorkey_mode_prop,
  425. CKMODE_RGB);
  426. drm_object_attach_property(mobj, priv->brightness_prop, 256);
  427. drm_object_attach_property(mobj, priv->contrast_prop,
  428. dplane->prop.contrast);
  429. drm_object_attach_property(mobj, priv->saturation_prop,
  430. dplane->prop.saturation);
  431. return 0;
  432. }