amdgpu_job.c 5.9 KB

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  1. /*
  2. * Copyright 2015 Advanced Micro Devices, Inc.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice shall be included in
  12. * all copies or substantial portions of the Software.
  13. *
  14. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20. * OTHER DEALINGS IN THE SOFTWARE.
  21. *
  22. *
  23. */
  24. #include <linux/kthread.h>
  25. #include <linux/wait.h>
  26. #include <linux/sched.h>
  27. #include <drm/drmP.h>
  28. #include "amdgpu.h"
  29. #include "amdgpu_trace.h"
  30. static void amdgpu_job_timedout(struct amd_sched_job *s_job)
  31. {
  32. struct amdgpu_job *job = container_of(s_job, struct amdgpu_job, base);
  33. DRM_ERROR("ring %s timeout, last signaled seq=%u, last emitted seq=%u\n",
  34. job->base.sched->name,
  35. atomic_read(&job->ring->fence_drv.last_seq),
  36. job->ring->fence_drv.sync_seq);
  37. amdgpu_gpu_recover(job->adev, job);
  38. }
  39. int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
  40. struct amdgpu_job **job, struct amdgpu_vm *vm)
  41. {
  42. size_t size = sizeof(struct amdgpu_job);
  43. if (num_ibs == 0)
  44. return -EINVAL;
  45. size += sizeof(struct amdgpu_ib) * num_ibs;
  46. *job = kzalloc(size, GFP_KERNEL);
  47. if (!*job)
  48. return -ENOMEM;
  49. (*job)->adev = adev;
  50. (*job)->vm = vm;
  51. (*job)->ibs = (void *)&(*job)[1];
  52. (*job)->num_ibs = num_ibs;
  53. amdgpu_sync_create(&(*job)->sync);
  54. amdgpu_sync_create(&(*job)->dep_sync);
  55. amdgpu_sync_create(&(*job)->sched_sync);
  56. (*job)->vram_lost_counter = atomic_read(&adev->vram_lost_counter);
  57. return 0;
  58. }
  59. int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size,
  60. struct amdgpu_job **job)
  61. {
  62. int r;
  63. r = amdgpu_job_alloc(adev, 1, job, NULL);
  64. if (r)
  65. return r;
  66. r = amdgpu_ib_get(adev, NULL, size, &(*job)->ibs[0]);
  67. if (r)
  68. kfree(*job);
  69. else
  70. (*job)->vm_pd_addr = adev->gart.table_addr;
  71. return r;
  72. }
  73. void amdgpu_job_free_resources(struct amdgpu_job *job)
  74. {
  75. struct dma_fence *f;
  76. unsigned i;
  77. /* use sched fence if available */
  78. f = job->base.s_fence ? &job->base.s_fence->finished : job->fence;
  79. for (i = 0; i < job->num_ibs; ++i)
  80. amdgpu_ib_free(job->adev, &job->ibs[i], f);
  81. }
  82. static void amdgpu_job_free_cb(struct amd_sched_job *s_job)
  83. {
  84. struct amdgpu_job *job = container_of(s_job, struct amdgpu_job, base);
  85. amdgpu_ring_priority_put(job->ring, s_job->s_priority);
  86. dma_fence_put(job->fence);
  87. amdgpu_sync_free(&job->sync);
  88. amdgpu_sync_free(&job->dep_sync);
  89. amdgpu_sync_free(&job->sched_sync);
  90. kfree(job);
  91. }
  92. void amdgpu_job_free(struct amdgpu_job *job)
  93. {
  94. amdgpu_job_free_resources(job);
  95. dma_fence_put(job->fence);
  96. amdgpu_sync_free(&job->sync);
  97. amdgpu_sync_free(&job->dep_sync);
  98. amdgpu_sync_free(&job->sched_sync);
  99. kfree(job);
  100. }
  101. int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring,
  102. struct amd_sched_entity *entity, void *owner,
  103. struct dma_fence **f)
  104. {
  105. int r;
  106. job->ring = ring;
  107. if (!f)
  108. return -EINVAL;
  109. r = amd_sched_job_init(&job->base, &ring->sched, entity, owner);
  110. if (r)
  111. return r;
  112. job->owner = owner;
  113. job->fence_ctx = entity->fence_context;
  114. *f = dma_fence_get(&job->base.s_fence->finished);
  115. amdgpu_job_free_resources(job);
  116. amdgpu_ring_priority_get(job->ring, job->base.s_priority);
  117. amd_sched_entity_push_job(&job->base, entity);
  118. return 0;
  119. }
  120. static struct dma_fence *amdgpu_job_dependency(struct amd_sched_job *sched_job,
  121. struct amd_sched_entity *s_entity)
  122. {
  123. struct amdgpu_job *job = to_amdgpu_job(sched_job);
  124. struct amdgpu_vm *vm = job->vm;
  125. struct dma_fence *fence = amdgpu_sync_get_fence(&job->dep_sync);
  126. int r;
  127. if (amd_sched_dependency_optimized(fence, s_entity)) {
  128. r = amdgpu_sync_fence(job->adev, &job->sched_sync, fence);
  129. if (r)
  130. DRM_ERROR("Error adding fence to sync (%d)\n", r);
  131. }
  132. if (!fence)
  133. fence = amdgpu_sync_get_fence(&job->sync);
  134. while (fence == NULL && vm && !job->vm_id) {
  135. struct amdgpu_ring *ring = job->ring;
  136. r = amdgpu_vm_grab_id(vm, ring, &job->sync,
  137. &job->base.s_fence->finished,
  138. job);
  139. if (r)
  140. DRM_ERROR("Error getting VM ID (%d)\n", r);
  141. fence = amdgpu_sync_get_fence(&job->sync);
  142. }
  143. return fence;
  144. }
  145. static struct dma_fence *amdgpu_job_run(struct amd_sched_job *sched_job)
  146. {
  147. struct dma_fence *fence = NULL, *finished;
  148. struct amdgpu_device *adev;
  149. struct amdgpu_job *job;
  150. int r;
  151. if (!sched_job) {
  152. DRM_ERROR("job is null\n");
  153. return NULL;
  154. }
  155. job = to_amdgpu_job(sched_job);
  156. finished = &job->base.s_fence->finished;
  157. adev = job->adev;
  158. BUG_ON(amdgpu_sync_peek_fence(&job->sync, NULL));
  159. trace_amdgpu_sched_run_job(job);
  160. if (job->vram_lost_counter != atomic_read(&adev->vram_lost_counter))
  161. dma_fence_set_error(finished, -ECANCELED);/* skip IB as well if VRAM lost */
  162. if (finished->error < 0) {
  163. DRM_INFO("Skip scheduling IBs!\n");
  164. } else {
  165. r = amdgpu_ib_schedule(job->ring, job->num_ibs, job->ibs, job,
  166. &fence);
  167. if (r)
  168. DRM_ERROR("Error scheduling IBs (%d)\n", r);
  169. }
  170. /* if gpu reset, hw fence will be replaced here */
  171. dma_fence_put(job->fence);
  172. job->fence = dma_fence_get(fence);
  173. amdgpu_job_free_resources(job);
  174. return fence;
  175. }
  176. const struct amd_sched_backend_ops amdgpu_sched_ops = {
  177. .dependency = amdgpu_job_dependency,
  178. .run_job = amdgpu_job_run,
  179. .timedout_job = amdgpu_job_timedout,
  180. .free_job = amdgpu_job_free_cb
  181. };