bfin_uart.c 39 KB

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  1. /*
  2. * Blackfin On-Chip Serial Driver
  3. *
  4. * Copyright 2006-2011 Analog Devices Inc.
  5. *
  6. * Enter bugs at http://blackfin.uclinux.org/
  7. *
  8. * Licensed under the GPL-2 or later.
  9. */
  10. #if defined(CONFIG_SERIAL_BFIN_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  11. #define SUPPORT_SYSRQ
  12. #endif
  13. #define DRIVER_NAME "bfin-uart"
  14. #define pr_fmt(fmt) DRIVER_NAME ": " fmt
  15. #include <linux/module.h>
  16. #include <linux/ioport.h>
  17. #include <linux/gfp.h>
  18. #include <linux/io.h>
  19. #include <linux/init.h>
  20. #include <linux/console.h>
  21. #include <linux/sysrq.h>
  22. #include <linux/platform_device.h>
  23. #include <linux/tty.h>
  24. #include <linux/tty_flip.h>
  25. #include <linux/serial_core.h>
  26. #include <linux/gpio.h>
  27. #include <linux/irq.h>
  28. #include <linux/kgdb.h>
  29. #include <linux/slab.h>
  30. #include <linux/dma-mapping.h>
  31. #include <asm/portmux.h>
  32. #include <asm/cacheflush.h>
  33. #include <asm/dma.h>
  34. #include <asm/bfin_serial.h>
  35. #ifdef CONFIG_SERIAL_BFIN_MODULE
  36. # undef CONFIG_EARLY_PRINTK
  37. #endif
  38. /* UART name and device definitions */
  39. #define BFIN_SERIAL_DEV_NAME "ttyBF"
  40. #define BFIN_SERIAL_MAJOR 204
  41. #define BFIN_SERIAL_MINOR 64
  42. static struct bfin_serial_port *bfin_serial_ports[BFIN_UART_NR_PORTS];
  43. #if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
  44. defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
  45. # ifndef CONFIG_SERIAL_BFIN_PIO
  46. # error KGDB only support UART in PIO mode.
  47. # endif
  48. static int kgdboc_port_line;
  49. static int kgdboc_break_enabled;
  50. #endif
  51. /*
  52. * Setup for console. Argument comes from the menuconfig
  53. */
  54. #define DMA_RX_XCOUNT 512
  55. #define DMA_RX_YCOUNT (PAGE_SIZE / DMA_RX_XCOUNT)
  56. #define DMA_RX_FLUSH_JIFFIES (HZ / 50)
  57. #ifdef CONFIG_SERIAL_BFIN_DMA
  58. static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart);
  59. #else
  60. static void bfin_serial_tx_chars(struct bfin_serial_port *uart);
  61. #endif
  62. static void bfin_serial_reset_irda(struct uart_port *port);
  63. #if defined(CONFIG_SERIAL_BFIN_CTSRTS) || \
  64. defined(CONFIG_SERIAL_BFIN_HARD_CTSRTS)
  65. static unsigned int bfin_serial_get_mctrl(struct uart_port *port)
  66. {
  67. struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
  68. if (uart->cts_pin < 0)
  69. return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
  70. /* CTS PIN is negative assertive. */
  71. if (UART_GET_CTS(uart))
  72. return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
  73. else
  74. return TIOCM_DSR | TIOCM_CAR;
  75. }
  76. static void bfin_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
  77. {
  78. struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
  79. if (uart->rts_pin < 0)
  80. return;
  81. /* RTS PIN is negative assertive. */
  82. if (mctrl & TIOCM_RTS)
  83. UART_ENABLE_RTS(uart);
  84. else
  85. UART_DISABLE_RTS(uart);
  86. }
  87. /*
  88. * Handle any change of modem status signal.
  89. */
  90. static irqreturn_t bfin_serial_mctrl_cts_int(int irq, void *dev_id)
  91. {
  92. struct bfin_serial_port *uart = dev_id;
  93. unsigned int status = bfin_serial_get_mctrl(&uart->port);
  94. #ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
  95. struct tty_struct *tty = uart->port.state->port.tty;
  96. UART_CLEAR_SCTS(uart);
  97. if (tty->hw_stopped) {
  98. if (status) {
  99. tty->hw_stopped = 0;
  100. uart_write_wakeup(&uart->port);
  101. }
  102. } else {
  103. if (!status)
  104. tty->hw_stopped = 1;
  105. }
  106. #endif
  107. uart_handle_cts_change(&uart->port, status & TIOCM_CTS);
  108. return IRQ_HANDLED;
  109. }
  110. #else
  111. static unsigned int bfin_serial_get_mctrl(struct uart_port *port)
  112. {
  113. return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
  114. }
  115. static void bfin_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
  116. {
  117. }
  118. #endif
  119. /*
  120. * interrupts are disabled on entry
  121. */
  122. static void bfin_serial_stop_tx(struct uart_port *port)
  123. {
  124. struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
  125. #ifdef CONFIG_SERIAL_BFIN_DMA
  126. struct circ_buf *xmit = &uart->port.state->xmit;
  127. #endif
  128. while (!(UART_GET_LSR(uart) & TEMT))
  129. cpu_relax();
  130. #ifdef CONFIG_SERIAL_BFIN_DMA
  131. disable_dma(uart->tx_dma_channel);
  132. xmit->tail = (xmit->tail + uart->tx_count) & (UART_XMIT_SIZE - 1);
  133. uart->port.icount.tx += uart->tx_count;
  134. uart->tx_count = 0;
  135. uart->tx_done = 1;
  136. #else
  137. #if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
  138. /* Clear TFI bit */
  139. UART_PUT_LSR(uart, TFI);
  140. #endif
  141. UART_CLEAR_IER(uart, ETBEI);
  142. #endif
  143. }
  144. /*
  145. * port is locked and interrupts are disabled
  146. */
  147. static void bfin_serial_start_tx(struct uart_port *port)
  148. {
  149. struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
  150. struct tty_struct *tty = uart->port.state->port.tty;
  151. /*
  152. * To avoid losting RX interrupt, we reset IR function
  153. * before sending data.
  154. */
  155. if (tty->termios.c_line == N_IRDA)
  156. bfin_serial_reset_irda(port);
  157. #ifdef CONFIG_SERIAL_BFIN_DMA
  158. if (uart->tx_done)
  159. bfin_serial_dma_tx_chars(uart);
  160. #else
  161. UART_SET_IER(uart, ETBEI);
  162. bfin_serial_tx_chars(uart);
  163. #endif
  164. }
  165. /*
  166. * Interrupts are enabled
  167. */
  168. static void bfin_serial_stop_rx(struct uart_port *port)
  169. {
  170. struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
  171. UART_CLEAR_IER(uart, ERBFI);
  172. }
  173. #if ANOMALY_05000363 && defined(CONFIG_SERIAL_BFIN_PIO)
  174. # define UART_GET_ANOMALY_THRESHOLD(uart) ((uart)->anomaly_threshold)
  175. # define UART_SET_ANOMALY_THRESHOLD(uart, v) ((uart)->anomaly_threshold = (v))
  176. #else
  177. # define UART_GET_ANOMALY_THRESHOLD(uart) 0
  178. # define UART_SET_ANOMALY_THRESHOLD(uart, v)
  179. #endif
  180. #ifdef CONFIG_SERIAL_BFIN_PIO
  181. static void bfin_serial_rx_chars(struct bfin_serial_port *uart)
  182. {
  183. unsigned int status, ch, flg;
  184. static struct timeval anomaly_start = { .tv_sec = 0 };
  185. status = UART_GET_LSR(uart);
  186. UART_CLEAR_LSR(uart);
  187. ch = UART_GET_CHAR(uart);
  188. uart->port.icount.rx++;
  189. #if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
  190. defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
  191. if (kgdb_connected && kgdboc_port_line == uart->port.line
  192. && kgdboc_break_enabled)
  193. if (ch == 0x3) {/* Ctrl + C */
  194. kgdb_breakpoint();
  195. return;
  196. }
  197. if (!uart->port.state)
  198. return;
  199. #endif
  200. if (ANOMALY_05000363) {
  201. /* The BF533 (and BF561) family of processors have a nice anomaly
  202. * where they continuously generate characters for a "single" break.
  203. * We have to basically ignore this flood until the "next" valid
  204. * character comes across. Due to the nature of the flood, it is
  205. * not possible to reliably catch bytes that are sent too quickly
  206. * after this break. So application code talking to the Blackfin
  207. * which sends a break signal must allow at least 1.5 character
  208. * times after the end of the break for things to stabilize. This
  209. * timeout was picked as it must absolutely be larger than 1
  210. * character time +/- some percent. So 1.5 sounds good. All other
  211. * Blackfin families operate properly. Woo.
  212. */
  213. if (anomaly_start.tv_sec) {
  214. struct timeval curr;
  215. suseconds_t usecs;
  216. if ((~ch & (~ch + 1)) & 0xff)
  217. goto known_good_char;
  218. do_gettimeofday(&curr);
  219. if (curr.tv_sec - anomaly_start.tv_sec > 1)
  220. goto known_good_char;
  221. usecs = 0;
  222. if (curr.tv_sec != anomaly_start.tv_sec)
  223. usecs += USEC_PER_SEC;
  224. usecs += curr.tv_usec - anomaly_start.tv_usec;
  225. if (usecs > UART_GET_ANOMALY_THRESHOLD(uart))
  226. goto known_good_char;
  227. if (ch)
  228. anomaly_start.tv_sec = 0;
  229. else
  230. anomaly_start = curr;
  231. return;
  232. known_good_char:
  233. status &= ~BI;
  234. anomaly_start.tv_sec = 0;
  235. }
  236. }
  237. if (status & BI) {
  238. if (ANOMALY_05000363)
  239. if (bfin_revid() < 5)
  240. do_gettimeofday(&anomaly_start);
  241. uart->port.icount.brk++;
  242. if (uart_handle_break(&uart->port))
  243. goto ignore_char;
  244. status &= ~(PE | FE);
  245. }
  246. if (status & PE)
  247. uart->port.icount.parity++;
  248. if (status & OE)
  249. uart->port.icount.overrun++;
  250. if (status & FE)
  251. uart->port.icount.frame++;
  252. status &= uart->port.read_status_mask;
  253. if (status & BI)
  254. flg = TTY_BREAK;
  255. else if (status & PE)
  256. flg = TTY_PARITY;
  257. else if (status & FE)
  258. flg = TTY_FRAME;
  259. else
  260. flg = TTY_NORMAL;
  261. if (uart_handle_sysrq_char(&uart->port, ch))
  262. goto ignore_char;
  263. uart_insert_char(&uart->port, status, OE, ch, flg);
  264. ignore_char:
  265. tty_flip_buffer_push(&uart->port.state->port);
  266. }
  267. static void bfin_serial_tx_chars(struct bfin_serial_port *uart)
  268. {
  269. struct circ_buf *xmit = &uart->port.state->xmit;
  270. if (uart_circ_empty(xmit) || uart_tx_stopped(&uart->port)) {
  271. #if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
  272. /* Clear TFI bit */
  273. UART_PUT_LSR(uart, TFI);
  274. #endif
  275. /* Anomaly notes:
  276. * 05000215 - we always clear ETBEI within last UART TX
  277. * interrupt to end a string. It is always set
  278. * when start a new tx.
  279. */
  280. UART_CLEAR_IER(uart, ETBEI);
  281. return;
  282. }
  283. if (uart->port.x_char) {
  284. UART_PUT_CHAR(uart, uart->port.x_char);
  285. uart->port.icount.tx++;
  286. uart->port.x_char = 0;
  287. }
  288. while ((UART_GET_LSR(uart) & THRE) && xmit->tail != xmit->head) {
  289. UART_PUT_CHAR(uart, xmit->buf[xmit->tail]);
  290. xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
  291. uart->port.icount.tx++;
  292. }
  293. if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
  294. uart_write_wakeup(&uart->port);
  295. }
  296. static irqreturn_t bfin_serial_rx_int(int irq, void *dev_id)
  297. {
  298. struct bfin_serial_port *uart = dev_id;
  299. while (UART_GET_LSR(uart) & DR)
  300. bfin_serial_rx_chars(uart);
  301. return IRQ_HANDLED;
  302. }
  303. static irqreturn_t bfin_serial_tx_int(int irq, void *dev_id)
  304. {
  305. struct bfin_serial_port *uart = dev_id;
  306. spin_lock(&uart->port.lock);
  307. if (UART_GET_LSR(uart) & THRE)
  308. bfin_serial_tx_chars(uart);
  309. spin_unlock(&uart->port.lock);
  310. return IRQ_HANDLED;
  311. }
  312. #endif
  313. #ifdef CONFIG_SERIAL_BFIN_DMA
  314. static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart)
  315. {
  316. struct circ_buf *xmit = &uart->port.state->xmit;
  317. uart->tx_done = 0;
  318. if (uart_circ_empty(xmit) || uart_tx_stopped(&uart->port)) {
  319. uart->tx_count = 0;
  320. uart->tx_done = 1;
  321. return;
  322. }
  323. if (uart->port.x_char) {
  324. UART_PUT_CHAR(uart, uart->port.x_char);
  325. uart->port.icount.tx++;
  326. uart->port.x_char = 0;
  327. }
  328. uart->tx_count = CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE);
  329. if (uart->tx_count > (UART_XMIT_SIZE - xmit->tail))
  330. uart->tx_count = UART_XMIT_SIZE - xmit->tail;
  331. blackfin_dcache_flush_range((unsigned long)(xmit->buf+xmit->tail),
  332. (unsigned long)(xmit->buf+xmit->tail+uart->tx_count));
  333. set_dma_config(uart->tx_dma_channel,
  334. set_bfin_dma_config(DIR_READ, DMA_FLOW_STOP,
  335. INTR_ON_BUF,
  336. DIMENSION_LINEAR,
  337. DATA_SIZE_8,
  338. DMA_SYNC_RESTART));
  339. set_dma_start_addr(uart->tx_dma_channel, (unsigned long)(xmit->buf+xmit->tail));
  340. set_dma_x_count(uart->tx_dma_channel, uart->tx_count);
  341. set_dma_x_modify(uart->tx_dma_channel, 1);
  342. SSYNC();
  343. enable_dma(uart->tx_dma_channel);
  344. UART_SET_IER(uart, ETBEI);
  345. }
  346. static void bfin_serial_dma_rx_chars(struct bfin_serial_port *uart)
  347. {
  348. int i, flg, status;
  349. status = UART_GET_LSR(uart);
  350. UART_CLEAR_LSR(uart);
  351. uart->port.icount.rx +=
  352. CIRC_CNT(uart->rx_dma_buf.head, uart->rx_dma_buf.tail,
  353. UART_XMIT_SIZE);
  354. if (status & BI) {
  355. uart->port.icount.brk++;
  356. if (uart_handle_break(&uart->port))
  357. goto dma_ignore_char;
  358. status &= ~(PE | FE);
  359. }
  360. if (status & PE)
  361. uart->port.icount.parity++;
  362. if (status & OE)
  363. uart->port.icount.overrun++;
  364. if (status & FE)
  365. uart->port.icount.frame++;
  366. status &= uart->port.read_status_mask;
  367. if (status & BI)
  368. flg = TTY_BREAK;
  369. else if (status & PE)
  370. flg = TTY_PARITY;
  371. else if (status & FE)
  372. flg = TTY_FRAME;
  373. else
  374. flg = TTY_NORMAL;
  375. for (i = uart->rx_dma_buf.tail; ; i++) {
  376. if (i >= UART_XMIT_SIZE)
  377. i = 0;
  378. if (i == uart->rx_dma_buf.head)
  379. break;
  380. if (!uart_handle_sysrq_char(&uart->port, uart->rx_dma_buf.buf[i]))
  381. uart_insert_char(&uart->port, status, OE,
  382. uart->rx_dma_buf.buf[i], flg);
  383. }
  384. dma_ignore_char:
  385. tty_flip_buffer_push(&uart->port.state->port);
  386. }
  387. void bfin_serial_rx_dma_timeout(struct bfin_serial_port *uart)
  388. {
  389. int x_pos, pos;
  390. unsigned long flags;
  391. spin_lock_irqsave(&uart->rx_lock, flags);
  392. /* 2D DMA RX buffer ring is used. Because curr_y_count and
  393. * curr_x_count can't be read as an atomic operation,
  394. * curr_y_count should be read before curr_x_count. When
  395. * curr_x_count is read, curr_y_count may already indicate
  396. * next buffer line. But, the position calculated here is
  397. * still indicate the old line. The wrong position data may
  398. * be smaller than current buffer tail, which cause garbages
  399. * are received if it is not prohibit.
  400. */
  401. uart->rx_dma_nrows = get_dma_curr_ycount(uart->rx_dma_channel);
  402. x_pos = get_dma_curr_xcount(uart->rx_dma_channel);
  403. uart->rx_dma_nrows = DMA_RX_YCOUNT - uart->rx_dma_nrows;
  404. if (uart->rx_dma_nrows == DMA_RX_YCOUNT || x_pos == 0)
  405. uart->rx_dma_nrows = 0;
  406. x_pos = DMA_RX_XCOUNT - x_pos;
  407. if (x_pos == DMA_RX_XCOUNT)
  408. x_pos = 0;
  409. pos = uart->rx_dma_nrows * DMA_RX_XCOUNT + x_pos;
  410. /* Ignore receiving data if new position is in the same line of
  411. * current buffer tail and small.
  412. */
  413. if (pos > uart->rx_dma_buf.tail ||
  414. uart->rx_dma_nrows < (uart->rx_dma_buf.tail/DMA_RX_XCOUNT)) {
  415. uart->rx_dma_buf.head = pos;
  416. bfin_serial_dma_rx_chars(uart);
  417. uart->rx_dma_buf.tail = uart->rx_dma_buf.head;
  418. }
  419. spin_unlock_irqrestore(&uart->rx_lock, flags);
  420. mod_timer(&(uart->rx_dma_timer), jiffies + DMA_RX_FLUSH_JIFFIES);
  421. }
  422. static irqreturn_t bfin_serial_dma_tx_int(int irq, void *dev_id)
  423. {
  424. struct bfin_serial_port *uart = dev_id;
  425. struct circ_buf *xmit = &uart->port.state->xmit;
  426. spin_lock(&uart->port.lock);
  427. if (!(get_dma_curr_irqstat(uart->tx_dma_channel)&DMA_RUN)) {
  428. disable_dma(uart->tx_dma_channel);
  429. clear_dma_irqstat(uart->tx_dma_channel);
  430. /* Anomaly notes:
  431. * 05000215 - we always clear ETBEI within last UART TX
  432. * interrupt to end a string. It is always set
  433. * when start a new tx.
  434. */
  435. UART_CLEAR_IER(uart, ETBEI);
  436. uart->port.icount.tx += uart->tx_count;
  437. if (!(xmit->tail == 0 && xmit->head == 0)) {
  438. xmit->tail = (xmit->tail + uart->tx_count) & (UART_XMIT_SIZE - 1);
  439. if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
  440. uart_write_wakeup(&uart->port);
  441. }
  442. bfin_serial_dma_tx_chars(uart);
  443. }
  444. spin_unlock(&uart->port.lock);
  445. return IRQ_HANDLED;
  446. }
  447. static irqreturn_t bfin_serial_dma_rx_int(int irq, void *dev_id)
  448. {
  449. struct bfin_serial_port *uart = dev_id;
  450. unsigned int irqstat;
  451. int x_pos, pos;
  452. spin_lock(&uart->rx_lock);
  453. irqstat = get_dma_curr_irqstat(uart->rx_dma_channel);
  454. clear_dma_irqstat(uart->rx_dma_channel);
  455. uart->rx_dma_nrows = get_dma_curr_ycount(uart->rx_dma_channel);
  456. x_pos = get_dma_curr_xcount(uart->rx_dma_channel);
  457. uart->rx_dma_nrows = DMA_RX_YCOUNT - uart->rx_dma_nrows;
  458. if (uart->rx_dma_nrows == DMA_RX_YCOUNT || x_pos == 0)
  459. uart->rx_dma_nrows = 0;
  460. pos = uart->rx_dma_nrows * DMA_RX_XCOUNT;
  461. if (pos > uart->rx_dma_buf.tail ||
  462. uart->rx_dma_nrows < (uart->rx_dma_buf.tail/DMA_RX_XCOUNT)) {
  463. uart->rx_dma_buf.head = pos;
  464. bfin_serial_dma_rx_chars(uart);
  465. uart->rx_dma_buf.tail = uart->rx_dma_buf.head;
  466. }
  467. spin_unlock(&uart->rx_lock);
  468. return IRQ_HANDLED;
  469. }
  470. #endif
  471. /*
  472. * Return TIOCSER_TEMT when transmitter is not busy.
  473. */
  474. static unsigned int bfin_serial_tx_empty(struct uart_port *port)
  475. {
  476. struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
  477. unsigned int lsr;
  478. lsr = UART_GET_LSR(uart);
  479. if (lsr & TEMT)
  480. return TIOCSER_TEMT;
  481. else
  482. return 0;
  483. }
  484. static void bfin_serial_break_ctl(struct uart_port *port, int break_state)
  485. {
  486. struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
  487. u32 lcr = UART_GET_LCR(uart);
  488. if (break_state)
  489. lcr |= SB;
  490. else
  491. lcr &= ~SB;
  492. UART_PUT_LCR(uart, lcr);
  493. SSYNC();
  494. }
  495. static int bfin_serial_startup(struct uart_port *port)
  496. {
  497. struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
  498. #ifdef CONFIG_SERIAL_BFIN_DMA
  499. dma_addr_t dma_handle;
  500. if (request_dma(uart->rx_dma_channel, "BFIN_UART_RX") < 0) {
  501. printk(KERN_NOTICE "Unable to attach Blackfin UART RX DMA channel\n");
  502. return -EBUSY;
  503. }
  504. if (request_dma(uart->tx_dma_channel, "BFIN_UART_TX") < 0) {
  505. printk(KERN_NOTICE "Unable to attach Blackfin UART TX DMA channel\n");
  506. free_dma(uart->rx_dma_channel);
  507. return -EBUSY;
  508. }
  509. set_dma_callback(uart->rx_dma_channel, bfin_serial_dma_rx_int, uart);
  510. set_dma_callback(uart->tx_dma_channel, bfin_serial_dma_tx_int, uart);
  511. uart->rx_dma_buf.buf = (unsigned char *)dma_alloc_coherent(NULL, PAGE_SIZE, &dma_handle, GFP_DMA);
  512. uart->rx_dma_buf.head = 0;
  513. uart->rx_dma_buf.tail = 0;
  514. uart->rx_dma_nrows = 0;
  515. set_dma_config(uart->rx_dma_channel,
  516. set_bfin_dma_config(DIR_WRITE, DMA_FLOW_AUTO,
  517. INTR_ON_ROW, DIMENSION_2D,
  518. DATA_SIZE_8,
  519. DMA_SYNC_RESTART));
  520. set_dma_x_count(uart->rx_dma_channel, DMA_RX_XCOUNT);
  521. set_dma_x_modify(uart->rx_dma_channel, 1);
  522. set_dma_y_count(uart->rx_dma_channel, DMA_RX_YCOUNT);
  523. set_dma_y_modify(uart->rx_dma_channel, 1);
  524. set_dma_start_addr(uart->rx_dma_channel, (unsigned long)uart->rx_dma_buf.buf);
  525. enable_dma(uart->rx_dma_channel);
  526. uart->rx_dma_timer.data = (unsigned long)(uart);
  527. uart->rx_dma_timer.function = (void *)bfin_serial_rx_dma_timeout;
  528. uart->rx_dma_timer.expires = jiffies + DMA_RX_FLUSH_JIFFIES;
  529. add_timer(&(uart->rx_dma_timer));
  530. #else
  531. # if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
  532. defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
  533. if (kgdboc_port_line == uart->port.line && kgdboc_break_enabled)
  534. kgdboc_break_enabled = 0;
  535. else {
  536. # endif
  537. if (request_irq(uart->rx_irq, bfin_serial_rx_int, 0,
  538. "BFIN_UART_RX", uart)) {
  539. printk(KERN_NOTICE "Unable to attach BlackFin UART RX interrupt\n");
  540. return -EBUSY;
  541. }
  542. if (request_irq
  543. (uart->tx_irq, bfin_serial_tx_int, 0,
  544. "BFIN_UART_TX", uart)) {
  545. printk(KERN_NOTICE "Unable to attach BlackFin UART TX interrupt\n");
  546. free_irq(uart->rx_irq, uart);
  547. return -EBUSY;
  548. }
  549. # ifdef CONFIG_BF54x
  550. {
  551. /*
  552. * UART2 and UART3 on BF548 share interrupt PINs and DMA
  553. * controllers with SPORT2 and SPORT3. UART rx and tx
  554. * interrupts are generated in PIO mode only when configure
  555. * their peripheral mapping registers properly, which means
  556. * request corresponding DMA channels in PIO mode as well.
  557. */
  558. unsigned uart_dma_ch_rx, uart_dma_ch_tx;
  559. switch (uart->rx_irq) {
  560. case IRQ_UART3_RX:
  561. uart_dma_ch_rx = CH_UART3_RX;
  562. uart_dma_ch_tx = CH_UART3_TX;
  563. break;
  564. case IRQ_UART2_RX:
  565. uart_dma_ch_rx = CH_UART2_RX;
  566. uart_dma_ch_tx = CH_UART2_TX;
  567. break;
  568. default:
  569. uart_dma_ch_rx = uart_dma_ch_tx = 0;
  570. break;
  571. }
  572. if (uart_dma_ch_rx &&
  573. request_dma(uart_dma_ch_rx, "BFIN_UART_RX") < 0) {
  574. printk(KERN_NOTICE"Fail to attach UART interrupt\n");
  575. free_irq(uart->rx_irq, uart);
  576. free_irq(uart->tx_irq, uart);
  577. return -EBUSY;
  578. }
  579. if (uart_dma_ch_tx &&
  580. request_dma(uart_dma_ch_tx, "BFIN_UART_TX") < 0) {
  581. printk(KERN_NOTICE "Fail to attach UART interrupt\n");
  582. free_dma(uart_dma_ch_rx);
  583. free_irq(uart->rx_irq, uart);
  584. free_irq(uart->tx_irq, uart);
  585. return -EBUSY;
  586. }
  587. }
  588. # endif
  589. # if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
  590. defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
  591. }
  592. # endif
  593. #endif
  594. #ifdef CONFIG_SERIAL_BFIN_CTSRTS
  595. if (uart->cts_pin >= 0) {
  596. if (request_irq(gpio_to_irq(uart->cts_pin),
  597. bfin_serial_mctrl_cts_int,
  598. IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING |
  599. 0, "BFIN_UART_CTS", uart)) {
  600. uart->cts_pin = -1;
  601. pr_info("Unable to attach BlackFin UART CTS interrupt. So, disable it.\n");
  602. }
  603. }
  604. if (uart->rts_pin >= 0) {
  605. if (gpio_request(uart->rts_pin, DRIVER_NAME)) {
  606. pr_info("fail to request RTS PIN at GPIO_%d\n", uart->rts_pin);
  607. uart->rts_pin = -1;
  608. } else
  609. gpio_direction_output(uart->rts_pin, 0);
  610. }
  611. #endif
  612. #ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
  613. if (uart->cts_pin >= 0) {
  614. if (request_irq(uart->status_irq, bfin_serial_mctrl_cts_int,
  615. 0, "BFIN_UART_MODEM_STATUS", uart)) {
  616. uart->cts_pin = -1;
  617. dev_info(port->dev, "Unable to attach BlackFin UART Modem Status interrupt.\n");
  618. }
  619. /* CTS RTS PINs are negative assertive. */
  620. UART_PUT_MCR(uart, UART_GET_MCR(uart) | ACTS);
  621. UART_SET_IER(uart, EDSSI);
  622. }
  623. #endif
  624. UART_SET_IER(uart, ERBFI);
  625. return 0;
  626. }
  627. static void bfin_serial_shutdown(struct uart_port *port)
  628. {
  629. struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
  630. #ifdef CONFIG_SERIAL_BFIN_DMA
  631. disable_dma(uart->tx_dma_channel);
  632. free_dma(uart->tx_dma_channel);
  633. disable_dma(uart->rx_dma_channel);
  634. free_dma(uart->rx_dma_channel);
  635. del_timer(&(uart->rx_dma_timer));
  636. dma_free_coherent(NULL, PAGE_SIZE, uart->rx_dma_buf.buf, 0);
  637. #else
  638. #ifdef CONFIG_BF54x
  639. switch (uart->port.irq) {
  640. case IRQ_UART3_RX:
  641. free_dma(CH_UART3_RX);
  642. free_dma(CH_UART3_TX);
  643. break;
  644. case IRQ_UART2_RX:
  645. free_dma(CH_UART2_RX);
  646. free_dma(CH_UART2_TX);
  647. break;
  648. default:
  649. break;
  650. }
  651. #endif
  652. free_irq(uart->rx_irq, uart);
  653. free_irq(uart->tx_irq, uart);
  654. #endif
  655. #ifdef CONFIG_SERIAL_BFIN_CTSRTS
  656. if (uart->cts_pin >= 0)
  657. free_irq(gpio_to_irq(uart->cts_pin), uart);
  658. if (uart->rts_pin >= 0)
  659. gpio_free(uart->rts_pin);
  660. #endif
  661. #ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
  662. if (uart->cts_pin >= 0)
  663. free_irq(uart->status_irq, uart);
  664. #endif
  665. }
  666. static void
  667. bfin_serial_set_termios(struct uart_port *port, struct ktermios *termios,
  668. struct ktermios *old)
  669. {
  670. struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
  671. unsigned long flags;
  672. unsigned int baud, quot;
  673. unsigned int ier, lcr = 0;
  674. unsigned long timeout;
  675. #ifdef CONFIG_SERIAL_BFIN_CTSRTS
  676. if (old == NULL && uart->cts_pin != -1)
  677. termios->c_cflag |= CRTSCTS;
  678. else if (uart->cts_pin == -1)
  679. termios->c_cflag &= ~CRTSCTS;
  680. #endif
  681. switch (termios->c_cflag & CSIZE) {
  682. case CS8:
  683. lcr = WLS(8);
  684. break;
  685. case CS7:
  686. lcr = WLS(7);
  687. break;
  688. case CS6:
  689. lcr = WLS(6);
  690. break;
  691. case CS5:
  692. lcr = WLS(5);
  693. break;
  694. default:
  695. printk(KERN_ERR "%s: word length not supported\n",
  696. __func__);
  697. }
  698. /* Anomaly notes:
  699. * 05000231 - STOP bit is always set to 1 whatever the user is set.
  700. */
  701. if (termios->c_cflag & CSTOPB) {
  702. if (ANOMALY_05000231)
  703. printk(KERN_WARNING "STOP bits other than 1 is not "
  704. "supported in case of anomaly 05000231.\n");
  705. else
  706. lcr |= STB;
  707. }
  708. if (termios->c_cflag & PARENB)
  709. lcr |= PEN;
  710. if (!(termios->c_cflag & PARODD))
  711. lcr |= EPS;
  712. if (termios->c_cflag & CMSPAR)
  713. lcr |= STP;
  714. spin_lock_irqsave(&uart->port.lock, flags);
  715. port->read_status_mask = OE;
  716. if (termios->c_iflag & INPCK)
  717. port->read_status_mask |= (FE | PE);
  718. if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
  719. port->read_status_mask |= BI;
  720. /*
  721. * Characters to ignore
  722. */
  723. port->ignore_status_mask = 0;
  724. if (termios->c_iflag & IGNPAR)
  725. port->ignore_status_mask |= FE | PE;
  726. if (termios->c_iflag & IGNBRK) {
  727. port->ignore_status_mask |= BI;
  728. /*
  729. * If we're ignoring parity and break indicators,
  730. * ignore overruns too (for real raw support).
  731. */
  732. if (termios->c_iflag & IGNPAR)
  733. port->ignore_status_mask |= OE;
  734. }
  735. baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
  736. quot = uart_get_divisor(port, baud);
  737. /* If discipline is not IRDA, apply ANOMALY_05000230 */
  738. if (termios->c_line != N_IRDA)
  739. quot -= ANOMALY_05000230;
  740. UART_SET_ANOMALY_THRESHOLD(uart, USEC_PER_SEC / baud * 15);
  741. /* Wait till the transfer buffer is empty */
  742. timeout = jiffies + msecs_to_jiffies(10);
  743. while (UART_GET_GCTL(uart) & UCEN && !(UART_GET_LSR(uart) & TEMT))
  744. if (time_after(jiffies, timeout)) {
  745. dev_warn(port->dev, "timeout waiting for TX buffer empty\n");
  746. break;
  747. }
  748. /* Disable UART */
  749. ier = UART_GET_IER(uart);
  750. UART_PUT_GCTL(uart, UART_GET_GCTL(uart) & ~UCEN);
  751. UART_DISABLE_INTS(uart);
  752. /* Set DLAB in LCR to Access CLK */
  753. UART_SET_DLAB(uart);
  754. UART_PUT_CLK(uart, quot);
  755. SSYNC();
  756. /* Clear DLAB in LCR to Access THR RBR IER */
  757. UART_CLEAR_DLAB(uart);
  758. UART_PUT_LCR(uart, (UART_GET_LCR(uart) & ~LCR_MASK) | lcr);
  759. /* Enable UART */
  760. UART_ENABLE_INTS(uart, ier);
  761. UART_PUT_GCTL(uart, UART_GET_GCTL(uart) | UCEN);
  762. /* Port speed changed, update the per-port timeout. */
  763. uart_update_timeout(port, termios->c_cflag, baud);
  764. spin_unlock_irqrestore(&uart->port.lock, flags);
  765. }
  766. static const char *bfin_serial_type(struct uart_port *port)
  767. {
  768. struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
  769. return uart->port.type == PORT_BFIN ? "BFIN-UART" : NULL;
  770. }
  771. /*
  772. * Release the memory region(s) being used by 'port'.
  773. */
  774. static void bfin_serial_release_port(struct uart_port *port)
  775. {
  776. }
  777. /*
  778. * Request the memory region(s) being used by 'port'.
  779. */
  780. static int bfin_serial_request_port(struct uart_port *port)
  781. {
  782. return 0;
  783. }
  784. /*
  785. * Configure/autoconfigure the port.
  786. */
  787. static void bfin_serial_config_port(struct uart_port *port, int flags)
  788. {
  789. struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
  790. if (flags & UART_CONFIG_TYPE &&
  791. bfin_serial_request_port(&uart->port) == 0)
  792. uart->port.type = PORT_BFIN;
  793. }
  794. /*
  795. * Verify the new serial_struct (for TIOCSSERIAL).
  796. * The only change we allow are to the flags and type, and
  797. * even then only between PORT_BFIN and PORT_UNKNOWN
  798. */
  799. static int
  800. bfin_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
  801. {
  802. return 0;
  803. }
  804. /*
  805. * Enable the IrDA function if tty->ldisc.num is N_IRDA.
  806. * In other cases, disable IrDA function.
  807. */
  808. static void bfin_serial_set_ldisc(struct uart_port *port, int ld)
  809. {
  810. struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
  811. unsigned int val;
  812. switch (ld) {
  813. case N_IRDA:
  814. val = UART_GET_GCTL(uart);
  815. val |= (UMOD_IRDA | RPOLC);
  816. UART_PUT_GCTL(uart, val);
  817. break;
  818. default:
  819. val = UART_GET_GCTL(uart);
  820. val &= ~(UMOD_MASK | RPOLC);
  821. UART_PUT_GCTL(uart, val);
  822. }
  823. }
  824. static void bfin_serial_reset_irda(struct uart_port *port)
  825. {
  826. struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
  827. unsigned int val;
  828. val = UART_GET_GCTL(uart);
  829. val &= ~(UMOD_MASK | RPOLC);
  830. UART_PUT_GCTL(uart, val);
  831. SSYNC();
  832. val |= (UMOD_IRDA | RPOLC);
  833. UART_PUT_GCTL(uart, val);
  834. SSYNC();
  835. }
  836. #ifdef CONFIG_CONSOLE_POLL
  837. /* Anomaly notes:
  838. * 05000099 - Because we only use THRE in poll_put and DR in poll_get,
  839. * losing other bits of UART_LSR is not a problem here.
  840. */
  841. static void bfin_serial_poll_put_char(struct uart_port *port, unsigned char chr)
  842. {
  843. struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
  844. while (!(UART_GET_LSR(uart) & THRE))
  845. cpu_relax();
  846. UART_CLEAR_DLAB(uart);
  847. UART_PUT_CHAR(uart, (unsigned char)chr);
  848. }
  849. static int bfin_serial_poll_get_char(struct uart_port *port)
  850. {
  851. struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
  852. unsigned char chr;
  853. while (!(UART_GET_LSR(uart) & DR))
  854. cpu_relax();
  855. UART_CLEAR_DLAB(uart);
  856. chr = UART_GET_CHAR(uart);
  857. return chr;
  858. }
  859. #endif
  860. static struct uart_ops bfin_serial_pops = {
  861. .tx_empty = bfin_serial_tx_empty,
  862. .set_mctrl = bfin_serial_set_mctrl,
  863. .get_mctrl = bfin_serial_get_mctrl,
  864. .stop_tx = bfin_serial_stop_tx,
  865. .start_tx = bfin_serial_start_tx,
  866. .stop_rx = bfin_serial_stop_rx,
  867. .break_ctl = bfin_serial_break_ctl,
  868. .startup = bfin_serial_startup,
  869. .shutdown = bfin_serial_shutdown,
  870. .set_termios = bfin_serial_set_termios,
  871. .set_ldisc = bfin_serial_set_ldisc,
  872. .type = bfin_serial_type,
  873. .release_port = bfin_serial_release_port,
  874. .request_port = bfin_serial_request_port,
  875. .config_port = bfin_serial_config_port,
  876. .verify_port = bfin_serial_verify_port,
  877. #ifdef CONFIG_CONSOLE_POLL
  878. .poll_put_char = bfin_serial_poll_put_char,
  879. .poll_get_char = bfin_serial_poll_get_char,
  880. #endif
  881. };
  882. #if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
  883. /*
  884. * If the port was already initialised (eg, by a boot loader),
  885. * try to determine the current setup.
  886. */
  887. static void __init
  888. bfin_serial_console_get_options(struct bfin_serial_port *uart, int *baud,
  889. int *parity, int *bits)
  890. {
  891. unsigned int status;
  892. status = UART_GET_IER(uart) & (ERBFI | ETBEI);
  893. if (status == (ERBFI | ETBEI)) {
  894. /* ok, the port was enabled */
  895. u32 lcr, clk;
  896. lcr = UART_GET_LCR(uart);
  897. *parity = 'n';
  898. if (lcr & PEN) {
  899. if (lcr & EPS)
  900. *parity = 'e';
  901. else
  902. *parity = 'o';
  903. }
  904. *bits = ((lcr & WLS_MASK) >> WLS_OFFSET) + 5;
  905. /* Set DLAB in LCR to Access CLK */
  906. UART_SET_DLAB(uart);
  907. clk = UART_GET_CLK(uart);
  908. /* Clear DLAB in LCR to Access THR RBR IER */
  909. UART_CLEAR_DLAB(uart);
  910. *baud = get_sclk() / (16*clk);
  911. }
  912. pr_debug("%s:baud = %d, parity = %c, bits= %d\n", __func__, *baud, *parity, *bits);
  913. }
  914. static struct uart_driver bfin_serial_reg;
  915. static void bfin_serial_console_putchar(struct uart_port *port, int ch)
  916. {
  917. struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
  918. while (!(UART_GET_LSR(uart) & THRE))
  919. barrier();
  920. UART_PUT_CHAR(uart, ch);
  921. }
  922. #endif /* defined (CONFIG_SERIAL_BFIN_CONSOLE) ||
  923. defined (CONFIG_EARLY_PRINTK) */
  924. #ifdef CONFIG_SERIAL_BFIN_CONSOLE
  925. #define CLASS_BFIN_CONSOLE "bfin-console"
  926. /*
  927. * Interrupts are disabled on entering
  928. */
  929. static void
  930. bfin_serial_console_write(struct console *co, const char *s, unsigned int count)
  931. {
  932. struct bfin_serial_port *uart = bfin_serial_ports[co->index];
  933. unsigned long flags;
  934. spin_lock_irqsave(&uart->port.lock, flags);
  935. uart_console_write(&uart->port, s, count, bfin_serial_console_putchar);
  936. spin_unlock_irqrestore(&uart->port.lock, flags);
  937. }
  938. static int __init
  939. bfin_serial_console_setup(struct console *co, char *options)
  940. {
  941. struct bfin_serial_port *uart;
  942. int baud = 57600;
  943. int bits = 8;
  944. int parity = 'n';
  945. # if defined(CONFIG_SERIAL_BFIN_CTSRTS) || \
  946. defined(CONFIG_SERIAL_BFIN_HARD_CTSRTS)
  947. int flow = 'r';
  948. # else
  949. int flow = 'n';
  950. # endif
  951. /*
  952. * Check whether an invalid uart number has been specified, and
  953. * if so, search for the first available port that does have
  954. * console support.
  955. */
  956. if (co->index < 0 || co->index >= BFIN_UART_NR_PORTS)
  957. return -ENODEV;
  958. uart = bfin_serial_ports[co->index];
  959. if (!uart)
  960. return -ENODEV;
  961. if (options)
  962. uart_parse_options(options, &baud, &parity, &bits, &flow);
  963. else
  964. bfin_serial_console_get_options(uart, &baud, &parity, &bits);
  965. return uart_set_options(&uart->port, co, baud, parity, bits, flow);
  966. }
  967. static struct console bfin_serial_console = {
  968. .name = BFIN_SERIAL_DEV_NAME,
  969. .write = bfin_serial_console_write,
  970. .device = uart_console_device,
  971. .setup = bfin_serial_console_setup,
  972. .flags = CON_PRINTBUFFER,
  973. .index = -1,
  974. .data = &bfin_serial_reg,
  975. };
  976. #define BFIN_SERIAL_CONSOLE (&bfin_serial_console)
  977. #else
  978. #define BFIN_SERIAL_CONSOLE NULL
  979. #endif /* CONFIG_SERIAL_BFIN_CONSOLE */
  980. #ifdef CONFIG_EARLY_PRINTK
  981. static struct bfin_serial_port bfin_earlyprintk_port;
  982. #define CLASS_BFIN_EARLYPRINTK "bfin-earlyprintk"
  983. /*
  984. * Interrupts are disabled on entering
  985. */
  986. static void
  987. bfin_earlyprintk_console_write(struct console *co, const char *s, unsigned int count)
  988. {
  989. unsigned long flags;
  990. if (bfin_earlyprintk_port.port.line != co->index)
  991. return;
  992. spin_lock_irqsave(&bfin_earlyprintk_port.port.lock, flags);
  993. uart_console_write(&bfin_earlyprintk_port.port, s, count,
  994. bfin_serial_console_putchar);
  995. spin_unlock_irqrestore(&bfin_earlyprintk_port.port.lock, flags);
  996. }
  997. /*
  998. * This should have a .setup or .early_setup in it, but then things get called
  999. * without the command line options, and the baud rate gets messed up - so
  1000. * don't let the common infrastructure play with things. (see calls to setup
  1001. * & earlysetup in ./kernel/printk.c:register_console()
  1002. */
  1003. static struct console bfin_early_serial_console __initdata = {
  1004. .name = "early_BFuart",
  1005. .write = bfin_earlyprintk_console_write,
  1006. .device = uart_console_device,
  1007. .flags = CON_PRINTBUFFER,
  1008. .index = -1,
  1009. .data = &bfin_serial_reg,
  1010. };
  1011. #endif
  1012. static struct uart_driver bfin_serial_reg = {
  1013. .owner = THIS_MODULE,
  1014. .driver_name = DRIVER_NAME,
  1015. .dev_name = BFIN_SERIAL_DEV_NAME,
  1016. .major = BFIN_SERIAL_MAJOR,
  1017. .minor = BFIN_SERIAL_MINOR,
  1018. .nr = BFIN_UART_NR_PORTS,
  1019. .cons = BFIN_SERIAL_CONSOLE,
  1020. };
  1021. static int bfin_serial_suspend(struct platform_device *pdev, pm_message_t state)
  1022. {
  1023. struct bfin_serial_port *uart = platform_get_drvdata(pdev);
  1024. return uart_suspend_port(&bfin_serial_reg, &uart->port);
  1025. }
  1026. static int bfin_serial_resume(struct platform_device *pdev)
  1027. {
  1028. struct bfin_serial_port *uart = platform_get_drvdata(pdev);
  1029. return uart_resume_port(&bfin_serial_reg, &uart->port);
  1030. }
  1031. static int bfin_serial_probe(struct platform_device *pdev)
  1032. {
  1033. struct resource *res;
  1034. struct bfin_serial_port *uart = NULL;
  1035. int ret = 0;
  1036. if (pdev->id < 0 || pdev->id >= BFIN_UART_NR_PORTS) {
  1037. dev_err(&pdev->dev, "Wrong bfin uart platform device id.\n");
  1038. return -ENOENT;
  1039. }
  1040. if (bfin_serial_ports[pdev->id] == NULL) {
  1041. uart = kzalloc(sizeof(*uart), GFP_KERNEL);
  1042. if (!uart) {
  1043. dev_err(&pdev->dev,
  1044. "fail to malloc bfin_serial_port\n");
  1045. return -ENOMEM;
  1046. }
  1047. bfin_serial_ports[pdev->id] = uart;
  1048. #ifdef CONFIG_EARLY_PRINTK
  1049. if (!(bfin_earlyprintk_port.port.membase
  1050. && bfin_earlyprintk_port.port.line == pdev->id)) {
  1051. /*
  1052. * If the peripheral PINs of current port is allocated
  1053. * in earlyprintk probe stage, don't do it again.
  1054. */
  1055. #endif
  1056. ret = peripheral_request_list(
  1057. dev_get_platdata(&pdev->dev),
  1058. DRIVER_NAME);
  1059. if (ret) {
  1060. dev_err(&pdev->dev,
  1061. "fail to request bfin serial peripherals\n");
  1062. goto out_error_free_mem;
  1063. }
  1064. #ifdef CONFIG_EARLY_PRINTK
  1065. }
  1066. #endif
  1067. spin_lock_init(&uart->port.lock);
  1068. uart->port.uartclk = get_sclk();
  1069. uart->port.fifosize = BFIN_UART_TX_FIFO_SIZE;
  1070. uart->port.ops = &bfin_serial_pops;
  1071. uart->port.line = pdev->id;
  1072. uart->port.iotype = UPIO_MEM;
  1073. uart->port.flags = UPF_BOOT_AUTOCONF;
  1074. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1075. if (res == NULL) {
  1076. dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
  1077. ret = -ENOENT;
  1078. goto out_error_free_peripherals;
  1079. }
  1080. uart->port.membase = ioremap(res->start, resource_size(res));
  1081. if (!uart->port.membase) {
  1082. dev_err(&pdev->dev, "Cannot map uart IO\n");
  1083. ret = -ENXIO;
  1084. goto out_error_free_peripherals;
  1085. }
  1086. uart->port.mapbase = res->start;
  1087. uart->tx_irq = platform_get_irq(pdev, 0);
  1088. if (uart->tx_irq < 0) {
  1089. dev_err(&pdev->dev, "No uart TX IRQ specified\n");
  1090. ret = -ENOENT;
  1091. goto out_error_unmap;
  1092. }
  1093. uart->rx_irq = platform_get_irq(pdev, 1);
  1094. if (uart->rx_irq < 0) {
  1095. dev_err(&pdev->dev, "No uart RX IRQ specified\n");
  1096. ret = -ENOENT;
  1097. goto out_error_unmap;
  1098. }
  1099. uart->port.irq = uart->rx_irq;
  1100. uart->status_irq = platform_get_irq(pdev, 2);
  1101. if (uart->status_irq < 0) {
  1102. dev_err(&pdev->dev, "No uart status IRQ specified\n");
  1103. ret = -ENOENT;
  1104. goto out_error_unmap;
  1105. }
  1106. #ifdef CONFIG_SERIAL_BFIN_DMA
  1107. spin_lock_init(&uart->rx_lock);
  1108. uart->tx_done = 1;
  1109. uart->tx_count = 0;
  1110. res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
  1111. if (res == NULL) {
  1112. dev_err(&pdev->dev, "No uart TX DMA channel specified\n");
  1113. ret = -ENOENT;
  1114. goto out_error_unmap;
  1115. }
  1116. uart->tx_dma_channel = res->start;
  1117. res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
  1118. if (res == NULL) {
  1119. dev_err(&pdev->dev, "No uart RX DMA channel specified\n");
  1120. ret = -ENOENT;
  1121. goto out_error_unmap;
  1122. }
  1123. uart->rx_dma_channel = res->start;
  1124. init_timer(&(uart->rx_dma_timer));
  1125. #endif
  1126. #if defined(CONFIG_SERIAL_BFIN_CTSRTS) || \
  1127. defined(CONFIG_SERIAL_BFIN_HARD_CTSRTS)
  1128. res = platform_get_resource(pdev, IORESOURCE_IO, 0);
  1129. if (res == NULL)
  1130. uart->cts_pin = -1;
  1131. else
  1132. uart->cts_pin = res->start;
  1133. res = platform_get_resource(pdev, IORESOURCE_IO, 1);
  1134. if (res == NULL)
  1135. uart->rts_pin = -1;
  1136. else
  1137. uart->rts_pin = res->start;
  1138. #endif
  1139. }
  1140. #ifdef CONFIG_SERIAL_BFIN_CONSOLE
  1141. if (!is_early_platform_device(pdev)) {
  1142. #endif
  1143. uart = bfin_serial_ports[pdev->id];
  1144. uart->port.dev = &pdev->dev;
  1145. dev_set_drvdata(&pdev->dev, uart);
  1146. ret = uart_add_one_port(&bfin_serial_reg, &uart->port);
  1147. #ifdef CONFIG_SERIAL_BFIN_CONSOLE
  1148. }
  1149. #endif
  1150. if (!ret)
  1151. return 0;
  1152. if (uart) {
  1153. out_error_unmap:
  1154. iounmap(uart->port.membase);
  1155. out_error_free_peripherals:
  1156. peripheral_free_list(dev_get_platdata(&pdev->dev));
  1157. out_error_free_mem:
  1158. kfree(uart);
  1159. bfin_serial_ports[pdev->id] = NULL;
  1160. }
  1161. return ret;
  1162. }
  1163. static int bfin_serial_remove(struct platform_device *pdev)
  1164. {
  1165. struct bfin_serial_port *uart = platform_get_drvdata(pdev);
  1166. dev_set_drvdata(&pdev->dev, NULL);
  1167. if (uart) {
  1168. uart_remove_one_port(&bfin_serial_reg, &uart->port);
  1169. iounmap(uart->port.membase);
  1170. peripheral_free_list(dev_get_platdata(&pdev->dev));
  1171. kfree(uart);
  1172. bfin_serial_ports[pdev->id] = NULL;
  1173. }
  1174. return 0;
  1175. }
  1176. static struct platform_driver bfin_serial_driver = {
  1177. .probe = bfin_serial_probe,
  1178. .remove = bfin_serial_remove,
  1179. .suspend = bfin_serial_suspend,
  1180. .resume = bfin_serial_resume,
  1181. .driver = {
  1182. .name = DRIVER_NAME,
  1183. .owner = THIS_MODULE,
  1184. },
  1185. };
  1186. #if defined(CONFIG_SERIAL_BFIN_CONSOLE)
  1187. static struct early_platform_driver early_bfin_serial_driver __initdata = {
  1188. .class_str = CLASS_BFIN_CONSOLE,
  1189. .pdrv = &bfin_serial_driver,
  1190. .requested_id = EARLY_PLATFORM_ID_UNSET,
  1191. };
  1192. static int __init bfin_serial_rs_console_init(void)
  1193. {
  1194. early_platform_driver_register(&early_bfin_serial_driver, DRIVER_NAME);
  1195. early_platform_driver_probe(CLASS_BFIN_CONSOLE, BFIN_UART_NR_PORTS, 0);
  1196. register_console(&bfin_serial_console);
  1197. return 0;
  1198. }
  1199. console_initcall(bfin_serial_rs_console_init);
  1200. #endif
  1201. #ifdef CONFIG_EARLY_PRINTK
  1202. /*
  1203. * Memory can't be allocated dynamically during earlyprink init stage.
  1204. * So, do individual probe for earlyprink with a static uart port variable.
  1205. */
  1206. static int bfin_earlyprintk_probe(struct platform_device *pdev)
  1207. {
  1208. struct resource *res;
  1209. int ret;
  1210. if (pdev->id < 0 || pdev->id >= BFIN_UART_NR_PORTS) {
  1211. dev_err(&pdev->dev, "Wrong earlyprintk platform device id.\n");
  1212. return -ENOENT;
  1213. }
  1214. ret = peripheral_request_list(dev_get_platdata(&pdev->dev),
  1215. DRIVER_NAME);
  1216. if (ret) {
  1217. dev_err(&pdev->dev,
  1218. "fail to request bfin serial peripherals\n");
  1219. return ret;
  1220. }
  1221. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1222. if (res == NULL) {
  1223. dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
  1224. ret = -ENOENT;
  1225. goto out_error_free_peripherals;
  1226. }
  1227. bfin_earlyprintk_port.port.membase = ioremap(res->start,
  1228. resource_size(res));
  1229. if (!bfin_earlyprintk_port.port.membase) {
  1230. dev_err(&pdev->dev, "Cannot map uart IO\n");
  1231. ret = -ENXIO;
  1232. goto out_error_free_peripherals;
  1233. }
  1234. bfin_earlyprintk_port.port.mapbase = res->start;
  1235. bfin_earlyprintk_port.port.line = pdev->id;
  1236. bfin_earlyprintk_port.port.uartclk = get_sclk();
  1237. bfin_earlyprintk_port.port.fifosize = BFIN_UART_TX_FIFO_SIZE;
  1238. spin_lock_init(&bfin_earlyprintk_port.port.lock);
  1239. return 0;
  1240. out_error_free_peripherals:
  1241. peripheral_free_list(dev_get_platdata(&pdev->dev));
  1242. return ret;
  1243. }
  1244. static struct platform_driver bfin_earlyprintk_driver = {
  1245. .probe = bfin_earlyprintk_probe,
  1246. .driver = {
  1247. .name = DRIVER_NAME,
  1248. .owner = THIS_MODULE,
  1249. },
  1250. };
  1251. static struct early_platform_driver early_bfin_earlyprintk_driver __initdata = {
  1252. .class_str = CLASS_BFIN_EARLYPRINTK,
  1253. .pdrv = &bfin_earlyprintk_driver,
  1254. .requested_id = EARLY_PLATFORM_ID_UNSET,
  1255. };
  1256. struct console __init *bfin_earlyserial_init(unsigned int port,
  1257. unsigned int cflag)
  1258. {
  1259. struct ktermios t;
  1260. char port_name[20];
  1261. if (port < 0 || port >= BFIN_UART_NR_PORTS)
  1262. return NULL;
  1263. /*
  1264. * Only probe resource of the given port in earlyprintk boot arg.
  1265. * The expected port id should be indicated in port name string.
  1266. */
  1267. snprintf(port_name, 20, DRIVER_NAME ".%d", port);
  1268. early_platform_driver_register(&early_bfin_earlyprintk_driver,
  1269. port_name);
  1270. early_platform_driver_probe(CLASS_BFIN_EARLYPRINTK, 1, 0);
  1271. if (!bfin_earlyprintk_port.port.membase)
  1272. return NULL;
  1273. #ifdef CONFIG_SERIAL_BFIN_CONSOLE
  1274. /*
  1275. * If we are using early serial, don't let the normal console rewind
  1276. * log buffer, since that causes things to be printed multiple times
  1277. */
  1278. bfin_serial_console.flags &= ~CON_PRINTBUFFER;
  1279. #endif
  1280. bfin_early_serial_console.index = port;
  1281. t.c_cflag = cflag;
  1282. t.c_iflag = 0;
  1283. t.c_oflag = 0;
  1284. t.c_lflag = ICANON;
  1285. t.c_line = port;
  1286. bfin_serial_set_termios(&bfin_earlyprintk_port.port, &t, &t);
  1287. return &bfin_early_serial_console;
  1288. }
  1289. #endif /* CONFIG_EARLY_PRINTK */
  1290. static int __init bfin_serial_init(void)
  1291. {
  1292. int ret;
  1293. pr_info("Blackfin serial driver\n");
  1294. ret = uart_register_driver(&bfin_serial_reg);
  1295. if (ret) {
  1296. pr_err("failed to register %s:%d\n",
  1297. bfin_serial_reg.driver_name, ret);
  1298. }
  1299. ret = platform_driver_register(&bfin_serial_driver);
  1300. if (ret) {
  1301. pr_err("fail to register bfin uart\n");
  1302. uart_unregister_driver(&bfin_serial_reg);
  1303. }
  1304. return ret;
  1305. }
  1306. static void __exit bfin_serial_exit(void)
  1307. {
  1308. platform_driver_unregister(&bfin_serial_driver);
  1309. uart_unregister_driver(&bfin_serial_reg);
  1310. }
  1311. module_init(bfin_serial_init);
  1312. module_exit(bfin_serial_exit);
  1313. MODULE_AUTHOR("Sonic Zhang, Aubrey Li");
  1314. MODULE_DESCRIPTION("Blackfin generic serial port driver");
  1315. MODULE_LICENSE("GPL");
  1316. MODULE_ALIAS_CHARDEV_MAJOR(BFIN_SERIAL_MAJOR);
  1317. MODULE_ALIAS("platform:bfin-uart");