cnic.c 148 KB

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  1. /* cnic.c: QLogic CNIC core network driver.
  2. *
  3. * Copyright (c) 2006-2014 Broadcom Corporation
  4. * Copyright (c) 2014 QLogic Corporation
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation.
  9. *
  10. * Original skeleton written by: John(Zongxi) Chen (zongxi@broadcom.com)
  11. * Previously modified and maintained by: Michael Chan <mchan@broadcom.com>
  12. * Maintained By: Dept-HSGLinuxNICDev@qlogic.com
  13. */
  14. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  15. #include <linux/module.h>
  16. #include <linux/kernel.h>
  17. #include <linux/errno.h>
  18. #include <linux/list.h>
  19. #include <linux/slab.h>
  20. #include <linux/pci.h>
  21. #include <linux/init.h>
  22. #include <linux/netdevice.h>
  23. #include <linux/uio_driver.h>
  24. #include <linux/in.h>
  25. #include <linux/dma-mapping.h>
  26. #include <linux/delay.h>
  27. #include <linux/ethtool.h>
  28. #include <linux/if_vlan.h>
  29. #include <linux/prefetch.h>
  30. #include <linux/random.h>
  31. #if IS_ENABLED(CONFIG_VLAN_8021Q)
  32. #define BCM_VLAN 1
  33. #endif
  34. #include <net/ip.h>
  35. #include <net/tcp.h>
  36. #include <net/route.h>
  37. #include <net/ipv6.h>
  38. #include <net/ip6_route.h>
  39. #include <net/ip6_checksum.h>
  40. #include <scsi/iscsi_if.h>
  41. #define BCM_CNIC 1
  42. #include "cnic_if.h"
  43. #include "bnx2.h"
  44. #include "bnx2x/bnx2x.h"
  45. #include "bnx2x/bnx2x_reg.h"
  46. #include "bnx2x/bnx2x_fw_defs.h"
  47. #include "bnx2x/bnx2x_hsi.h"
  48. #include "../../../scsi/bnx2i/57xx_iscsi_constants.h"
  49. #include "../../../scsi/bnx2i/57xx_iscsi_hsi.h"
  50. #include "../../../scsi/bnx2fc/bnx2fc_constants.h"
  51. #include "cnic.h"
  52. #include "cnic_defs.h"
  53. #define CNIC_MODULE_NAME "cnic"
  54. static char version[] =
  55. "QLogic NetXtreme II CNIC Driver " CNIC_MODULE_NAME " v" CNIC_MODULE_VERSION " (" CNIC_MODULE_RELDATE ")\n";
  56. MODULE_AUTHOR("Michael Chan <mchan@broadcom.com> and John(Zongxi) "
  57. "Chen (zongxi@broadcom.com");
  58. MODULE_DESCRIPTION("QLogic NetXtreme II CNIC Driver");
  59. MODULE_LICENSE("GPL");
  60. MODULE_VERSION(CNIC_MODULE_VERSION);
  61. /* cnic_dev_list modifications are protected by both rtnl and cnic_dev_lock */
  62. static LIST_HEAD(cnic_dev_list);
  63. static LIST_HEAD(cnic_udev_list);
  64. static DEFINE_RWLOCK(cnic_dev_lock);
  65. static DEFINE_MUTEX(cnic_lock);
  66. static struct cnic_ulp_ops __rcu *cnic_ulp_tbl[MAX_CNIC_ULP_TYPE];
  67. /* helper function, assuming cnic_lock is held */
  68. static inline struct cnic_ulp_ops *cnic_ulp_tbl_prot(int type)
  69. {
  70. return rcu_dereference_protected(cnic_ulp_tbl[type],
  71. lockdep_is_held(&cnic_lock));
  72. }
  73. static int cnic_service_bnx2(void *, void *);
  74. static int cnic_service_bnx2x(void *, void *);
  75. static int cnic_ctl(void *, struct cnic_ctl_info *);
  76. static struct cnic_ops cnic_bnx2_ops = {
  77. .cnic_owner = THIS_MODULE,
  78. .cnic_handler = cnic_service_bnx2,
  79. .cnic_ctl = cnic_ctl,
  80. };
  81. static struct cnic_ops cnic_bnx2x_ops = {
  82. .cnic_owner = THIS_MODULE,
  83. .cnic_handler = cnic_service_bnx2x,
  84. .cnic_ctl = cnic_ctl,
  85. };
  86. static struct workqueue_struct *cnic_wq;
  87. static void cnic_shutdown_rings(struct cnic_dev *);
  88. static void cnic_init_rings(struct cnic_dev *);
  89. static int cnic_cm_set_pg(struct cnic_sock *);
  90. static int cnic_uio_open(struct uio_info *uinfo, struct inode *inode)
  91. {
  92. struct cnic_uio_dev *udev = uinfo->priv;
  93. struct cnic_dev *dev;
  94. if (!capable(CAP_NET_ADMIN))
  95. return -EPERM;
  96. if (udev->uio_dev != -1)
  97. return -EBUSY;
  98. rtnl_lock();
  99. dev = udev->dev;
  100. if (!dev || !test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  101. rtnl_unlock();
  102. return -ENODEV;
  103. }
  104. udev->uio_dev = iminor(inode);
  105. cnic_shutdown_rings(dev);
  106. cnic_init_rings(dev);
  107. rtnl_unlock();
  108. return 0;
  109. }
  110. static int cnic_uio_close(struct uio_info *uinfo, struct inode *inode)
  111. {
  112. struct cnic_uio_dev *udev = uinfo->priv;
  113. udev->uio_dev = -1;
  114. return 0;
  115. }
  116. static inline void cnic_hold(struct cnic_dev *dev)
  117. {
  118. atomic_inc(&dev->ref_count);
  119. }
  120. static inline void cnic_put(struct cnic_dev *dev)
  121. {
  122. atomic_dec(&dev->ref_count);
  123. }
  124. static inline void csk_hold(struct cnic_sock *csk)
  125. {
  126. atomic_inc(&csk->ref_count);
  127. }
  128. static inline void csk_put(struct cnic_sock *csk)
  129. {
  130. atomic_dec(&csk->ref_count);
  131. }
  132. static struct cnic_dev *cnic_from_netdev(struct net_device *netdev)
  133. {
  134. struct cnic_dev *cdev;
  135. read_lock(&cnic_dev_lock);
  136. list_for_each_entry(cdev, &cnic_dev_list, list) {
  137. if (netdev == cdev->netdev) {
  138. cnic_hold(cdev);
  139. read_unlock(&cnic_dev_lock);
  140. return cdev;
  141. }
  142. }
  143. read_unlock(&cnic_dev_lock);
  144. return NULL;
  145. }
  146. static inline void ulp_get(struct cnic_ulp_ops *ulp_ops)
  147. {
  148. atomic_inc(&ulp_ops->ref_count);
  149. }
  150. static inline void ulp_put(struct cnic_ulp_ops *ulp_ops)
  151. {
  152. atomic_dec(&ulp_ops->ref_count);
  153. }
  154. static void cnic_ctx_wr(struct cnic_dev *dev, u32 cid_addr, u32 off, u32 val)
  155. {
  156. struct cnic_local *cp = dev->cnic_priv;
  157. struct cnic_eth_dev *ethdev = cp->ethdev;
  158. struct drv_ctl_info info;
  159. struct drv_ctl_io *io = &info.data.io;
  160. info.cmd = DRV_CTL_CTX_WR_CMD;
  161. io->cid_addr = cid_addr;
  162. io->offset = off;
  163. io->data = val;
  164. ethdev->drv_ctl(dev->netdev, &info);
  165. }
  166. static void cnic_ctx_tbl_wr(struct cnic_dev *dev, u32 off, dma_addr_t addr)
  167. {
  168. struct cnic_local *cp = dev->cnic_priv;
  169. struct cnic_eth_dev *ethdev = cp->ethdev;
  170. struct drv_ctl_info info;
  171. struct drv_ctl_io *io = &info.data.io;
  172. info.cmd = DRV_CTL_CTXTBL_WR_CMD;
  173. io->offset = off;
  174. io->dma_addr = addr;
  175. ethdev->drv_ctl(dev->netdev, &info);
  176. }
  177. static void cnic_ring_ctl(struct cnic_dev *dev, u32 cid, u32 cl_id, int start)
  178. {
  179. struct cnic_local *cp = dev->cnic_priv;
  180. struct cnic_eth_dev *ethdev = cp->ethdev;
  181. struct drv_ctl_info info;
  182. struct drv_ctl_l2_ring *ring = &info.data.ring;
  183. if (start)
  184. info.cmd = DRV_CTL_START_L2_CMD;
  185. else
  186. info.cmd = DRV_CTL_STOP_L2_CMD;
  187. ring->cid = cid;
  188. ring->client_id = cl_id;
  189. ethdev->drv_ctl(dev->netdev, &info);
  190. }
  191. static void cnic_reg_wr_ind(struct cnic_dev *dev, u32 off, u32 val)
  192. {
  193. struct cnic_local *cp = dev->cnic_priv;
  194. struct cnic_eth_dev *ethdev = cp->ethdev;
  195. struct drv_ctl_info info;
  196. struct drv_ctl_io *io = &info.data.io;
  197. info.cmd = DRV_CTL_IO_WR_CMD;
  198. io->offset = off;
  199. io->data = val;
  200. ethdev->drv_ctl(dev->netdev, &info);
  201. }
  202. static u32 cnic_reg_rd_ind(struct cnic_dev *dev, u32 off)
  203. {
  204. struct cnic_local *cp = dev->cnic_priv;
  205. struct cnic_eth_dev *ethdev = cp->ethdev;
  206. struct drv_ctl_info info;
  207. struct drv_ctl_io *io = &info.data.io;
  208. info.cmd = DRV_CTL_IO_RD_CMD;
  209. io->offset = off;
  210. ethdev->drv_ctl(dev->netdev, &info);
  211. return io->data;
  212. }
  213. static void cnic_ulp_ctl(struct cnic_dev *dev, int ulp_type, bool reg)
  214. {
  215. struct cnic_local *cp = dev->cnic_priv;
  216. struct cnic_eth_dev *ethdev = cp->ethdev;
  217. struct drv_ctl_info info;
  218. struct fcoe_capabilities *fcoe_cap =
  219. &info.data.register_data.fcoe_features;
  220. if (reg) {
  221. info.cmd = DRV_CTL_ULP_REGISTER_CMD;
  222. if (ulp_type == CNIC_ULP_FCOE && dev->fcoe_cap)
  223. memcpy(fcoe_cap, dev->fcoe_cap, sizeof(*fcoe_cap));
  224. } else {
  225. info.cmd = DRV_CTL_ULP_UNREGISTER_CMD;
  226. }
  227. info.data.ulp_type = ulp_type;
  228. ethdev->drv_ctl(dev->netdev, &info);
  229. }
  230. static int cnic_in_use(struct cnic_sock *csk)
  231. {
  232. return test_bit(SK_F_INUSE, &csk->flags);
  233. }
  234. static void cnic_spq_completion(struct cnic_dev *dev, int cmd, u32 count)
  235. {
  236. struct cnic_local *cp = dev->cnic_priv;
  237. struct cnic_eth_dev *ethdev = cp->ethdev;
  238. struct drv_ctl_info info;
  239. info.cmd = cmd;
  240. info.data.credit.credit_count = count;
  241. ethdev->drv_ctl(dev->netdev, &info);
  242. }
  243. static int cnic_get_l5_cid(struct cnic_local *cp, u32 cid, u32 *l5_cid)
  244. {
  245. u32 i;
  246. if (!cp->ctx_tbl)
  247. return -EINVAL;
  248. for (i = 0; i < cp->max_cid_space; i++) {
  249. if (cp->ctx_tbl[i].cid == cid) {
  250. *l5_cid = i;
  251. return 0;
  252. }
  253. }
  254. return -EINVAL;
  255. }
  256. static int cnic_send_nlmsg(struct cnic_local *cp, u32 type,
  257. struct cnic_sock *csk)
  258. {
  259. struct iscsi_path path_req;
  260. char *buf = NULL;
  261. u16 len = 0;
  262. u32 msg_type = ISCSI_KEVENT_IF_DOWN;
  263. struct cnic_ulp_ops *ulp_ops;
  264. struct cnic_uio_dev *udev = cp->udev;
  265. int rc = 0, retry = 0;
  266. if (!udev || udev->uio_dev == -1)
  267. return -ENODEV;
  268. if (csk) {
  269. len = sizeof(path_req);
  270. buf = (char *) &path_req;
  271. memset(&path_req, 0, len);
  272. msg_type = ISCSI_KEVENT_PATH_REQ;
  273. path_req.handle = (u64) csk->l5_cid;
  274. if (test_bit(SK_F_IPV6, &csk->flags)) {
  275. memcpy(&path_req.dst.v6_addr, &csk->dst_ip[0],
  276. sizeof(struct in6_addr));
  277. path_req.ip_addr_len = 16;
  278. } else {
  279. memcpy(&path_req.dst.v4_addr, &csk->dst_ip[0],
  280. sizeof(struct in_addr));
  281. path_req.ip_addr_len = 4;
  282. }
  283. path_req.vlan_id = csk->vlan_id;
  284. path_req.pmtu = csk->mtu;
  285. }
  286. while (retry < 3) {
  287. rc = 0;
  288. rcu_read_lock();
  289. ulp_ops = rcu_dereference(cp->ulp_ops[CNIC_ULP_ISCSI]);
  290. if (ulp_ops)
  291. rc = ulp_ops->iscsi_nl_send_msg(
  292. cp->ulp_handle[CNIC_ULP_ISCSI],
  293. msg_type, buf, len);
  294. rcu_read_unlock();
  295. if (rc == 0 || msg_type != ISCSI_KEVENT_PATH_REQ)
  296. break;
  297. msleep(100);
  298. retry++;
  299. }
  300. return rc;
  301. }
  302. static void cnic_cm_upcall(struct cnic_local *, struct cnic_sock *, u8);
  303. static int cnic_iscsi_nl_msg_recv(struct cnic_dev *dev, u32 msg_type,
  304. char *buf, u16 len)
  305. {
  306. int rc = -EINVAL;
  307. switch (msg_type) {
  308. case ISCSI_UEVENT_PATH_UPDATE: {
  309. struct cnic_local *cp;
  310. u32 l5_cid;
  311. struct cnic_sock *csk;
  312. struct iscsi_path *path_resp;
  313. if (len < sizeof(*path_resp))
  314. break;
  315. path_resp = (struct iscsi_path *) buf;
  316. cp = dev->cnic_priv;
  317. l5_cid = (u32) path_resp->handle;
  318. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  319. break;
  320. rcu_read_lock();
  321. if (!rcu_dereference(cp->ulp_ops[CNIC_ULP_L4])) {
  322. rc = -ENODEV;
  323. rcu_read_unlock();
  324. break;
  325. }
  326. csk = &cp->csk_tbl[l5_cid];
  327. csk_hold(csk);
  328. if (cnic_in_use(csk) &&
  329. test_bit(SK_F_CONNECT_START, &csk->flags)) {
  330. csk->vlan_id = path_resp->vlan_id;
  331. memcpy(csk->ha, path_resp->mac_addr, ETH_ALEN);
  332. if (test_bit(SK_F_IPV6, &csk->flags))
  333. memcpy(&csk->src_ip[0], &path_resp->src.v6_addr,
  334. sizeof(struct in6_addr));
  335. else
  336. memcpy(&csk->src_ip[0], &path_resp->src.v4_addr,
  337. sizeof(struct in_addr));
  338. if (is_valid_ether_addr(csk->ha)) {
  339. cnic_cm_set_pg(csk);
  340. } else if (!test_bit(SK_F_OFFLD_SCHED, &csk->flags) &&
  341. !test_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  342. cnic_cm_upcall(cp, csk,
  343. L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
  344. clear_bit(SK_F_CONNECT_START, &csk->flags);
  345. }
  346. }
  347. csk_put(csk);
  348. rcu_read_unlock();
  349. rc = 0;
  350. }
  351. }
  352. return rc;
  353. }
  354. static int cnic_offld_prep(struct cnic_sock *csk)
  355. {
  356. if (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  357. return 0;
  358. if (!test_bit(SK_F_CONNECT_START, &csk->flags)) {
  359. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  360. return 0;
  361. }
  362. return 1;
  363. }
  364. static int cnic_close_prep(struct cnic_sock *csk)
  365. {
  366. clear_bit(SK_F_CONNECT_START, &csk->flags);
  367. smp_mb__after_atomic();
  368. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  369. while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  370. msleep(1);
  371. return 1;
  372. }
  373. return 0;
  374. }
  375. static int cnic_abort_prep(struct cnic_sock *csk)
  376. {
  377. clear_bit(SK_F_CONNECT_START, &csk->flags);
  378. smp_mb__after_atomic();
  379. while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  380. msleep(1);
  381. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  382. csk->state = L4_KCQE_OPCODE_VALUE_RESET_COMP;
  383. return 1;
  384. }
  385. return 0;
  386. }
  387. int cnic_register_driver(int ulp_type, struct cnic_ulp_ops *ulp_ops)
  388. {
  389. struct cnic_dev *dev;
  390. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  391. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  392. return -EINVAL;
  393. }
  394. mutex_lock(&cnic_lock);
  395. if (cnic_ulp_tbl_prot(ulp_type)) {
  396. pr_err("%s: Type %d has already been registered\n",
  397. __func__, ulp_type);
  398. mutex_unlock(&cnic_lock);
  399. return -EBUSY;
  400. }
  401. read_lock(&cnic_dev_lock);
  402. list_for_each_entry(dev, &cnic_dev_list, list) {
  403. struct cnic_local *cp = dev->cnic_priv;
  404. clear_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]);
  405. }
  406. read_unlock(&cnic_dev_lock);
  407. atomic_set(&ulp_ops->ref_count, 0);
  408. rcu_assign_pointer(cnic_ulp_tbl[ulp_type], ulp_ops);
  409. mutex_unlock(&cnic_lock);
  410. /* Prevent race conditions with netdev_event */
  411. rtnl_lock();
  412. list_for_each_entry(dev, &cnic_dev_list, list) {
  413. struct cnic_local *cp = dev->cnic_priv;
  414. if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]))
  415. ulp_ops->cnic_init(dev);
  416. }
  417. rtnl_unlock();
  418. return 0;
  419. }
  420. int cnic_unregister_driver(int ulp_type)
  421. {
  422. struct cnic_dev *dev;
  423. struct cnic_ulp_ops *ulp_ops;
  424. int i = 0;
  425. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  426. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  427. return -EINVAL;
  428. }
  429. mutex_lock(&cnic_lock);
  430. ulp_ops = cnic_ulp_tbl_prot(ulp_type);
  431. if (!ulp_ops) {
  432. pr_err("%s: Type %d has not been registered\n",
  433. __func__, ulp_type);
  434. goto out_unlock;
  435. }
  436. read_lock(&cnic_dev_lock);
  437. list_for_each_entry(dev, &cnic_dev_list, list) {
  438. struct cnic_local *cp = dev->cnic_priv;
  439. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  440. pr_err("%s: Type %d still has devices registered\n",
  441. __func__, ulp_type);
  442. read_unlock(&cnic_dev_lock);
  443. goto out_unlock;
  444. }
  445. }
  446. read_unlock(&cnic_dev_lock);
  447. RCU_INIT_POINTER(cnic_ulp_tbl[ulp_type], NULL);
  448. mutex_unlock(&cnic_lock);
  449. synchronize_rcu();
  450. while ((atomic_read(&ulp_ops->ref_count) != 0) && (i < 20)) {
  451. msleep(100);
  452. i++;
  453. }
  454. if (atomic_read(&ulp_ops->ref_count) != 0)
  455. pr_warn("%s: Failed waiting for ref count to go to zero\n",
  456. __func__);
  457. return 0;
  458. out_unlock:
  459. mutex_unlock(&cnic_lock);
  460. return -EINVAL;
  461. }
  462. static int cnic_start_hw(struct cnic_dev *);
  463. static void cnic_stop_hw(struct cnic_dev *);
  464. static int cnic_register_device(struct cnic_dev *dev, int ulp_type,
  465. void *ulp_ctx)
  466. {
  467. struct cnic_local *cp = dev->cnic_priv;
  468. struct cnic_ulp_ops *ulp_ops;
  469. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  470. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  471. return -EINVAL;
  472. }
  473. mutex_lock(&cnic_lock);
  474. if (cnic_ulp_tbl_prot(ulp_type) == NULL) {
  475. pr_err("%s: Driver with type %d has not been registered\n",
  476. __func__, ulp_type);
  477. mutex_unlock(&cnic_lock);
  478. return -EAGAIN;
  479. }
  480. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  481. pr_err("%s: Type %d has already been registered to this device\n",
  482. __func__, ulp_type);
  483. mutex_unlock(&cnic_lock);
  484. return -EBUSY;
  485. }
  486. clear_bit(ULP_F_START, &cp->ulp_flags[ulp_type]);
  487. cp->ulp_handle[ulp_type] = ulp_ctx;
  488. ulp_ops = cnic_ulp_tbl_prot(ulp_type);
  489. rcu_assign_pointer(cp->ulp_ops[ulp_type], ulp_ops);
  490. cnic_hold(dev);
  491. if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
  492. if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[ulp_type]))
  493. ulp_ops->cnic_start(cp->ulp_handle[ulp_type]);
  494. mutex_unlock(&cnic_lock);
  495. cnic_ulp_ctl(dev, ulp_type, true);
  496. return 0;
  497. }
  498. EXPORT_SYMBOL(cnic_register_driver);
  499. static int cnic_unregister_device(struct cnic_dev *dev, int ulp_type)
  500. {
  501. struct cnic_local *cp = dev->cnic_priv;
  502. int i = 0;
  503. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  504. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  505. return -EINVAL;
  506. }
  507. if (ulp_type == CNIC_ULP_ISCSI)
  508. cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
  509. mutex_lock(&cnic_lock);
  510. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  511. RCU_INIT_POINTER(cp->ulp_ops[ulp_type], NULL);
  512. cnic_put(dev);
  513. } else {
  514. pr_err("%s: device not registered to this ulp type %d\n",
  515. __func__, ulp_type);
  516. mutex_unlock(&cnic_lock);
  517. return -EINVAL;
  518. }
  519. mutex_unlock(&cnic_lock);
  520. if (ulp_type == CNIC_ULP_FCOE)
  521. dev->fcoe_cap = NULL;
  522. synchronize_rcu();
  523. while (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]) &&
  524. i < 20) {
  525. msleep(100);
  526. i++;
  527. }
  528. if (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]))
  529. netdev_warn(dev->netdev, "Failed waiting for ULP up call to complete\n");
  530. cnic_ulp_ctl(dev, ulp_type, false);
  531. return 0;
  532. }
  533. EXPORT_SYMBOL(cnic_unregister_driver);
  534. static int cnic_init_id_tbl(struct cnic_id_tbl *id_tbl, u32 size, u32 start_id,
  535. u32 next)
  536. {
  537. id_tbl->start = start_id;
  538. id_tbl->max = size;
  539. id_tbl->next = next;
  540. spin_lock_init(&id_tbl->lock);
  541. id_tbl->table = kzalloc(DIV_ROUND_UP(size, 32) * 4, GFP_KERNEL);
  542. if (!id_tbl->table)
  543. return -ENOMEM;
  544. return 0;
  545. }
  546. static void cnic_free_id_tbl(struct cnic_id_tbl *id_tbl)
  547. {
  548. kfree(id_tbl->table);
  549. id_tbl->table = NULL;
  550. }
  551. static int cnic_alloc_id(struct cnic_id_tbl *id_tbl, u32 id)
  552. {
  553. int ret = -1;
  554. id -= id_tbl->start;
  555. if (id >= id_tbl->max)
  556. return ret;
  557. spin_lock(&id_tbl->lock);
  558. if (!test_bit(id, id_tbl->table)) {
  559. set_bit(id, id_tbl->table);
  560. ret = 0;
  561. }
  562. spin_unlock(&id_tbl->lock);
  563. return ret;
  564. }
  565. /* Returns -1 if not successful */
  566. static u32 cnic_alloc_new_id(struct cnic_id_tbl *id_tbl)
  567. {
  568. u32 id;
  569. spin_lock(&id_tbl->lock);
  570. id = find_next_zero_bit(id_tbl->table, id_tbl->max, id_tbl->next);
  571. if (id >= id_tbl->max) {
  572. id = -1;
  573. if (id_tbl->next != 0) {
  574. id = find_first_zero_bit(id_tbl->table, id_tbl->next);
  575. if (id >= id_tbl->next)
  576. id = -1;
  577. }
  578. }
  579. if (id < id_tbl->max) {
  580. set_bit(id, id_tbl->table);
  581. id_tbl->next = (id + 1) & (id_tbl->max - 1);
  582. id += id_tbl->start;
  583. }
  584. spin_unlock(&id_tbl->lock);
  585. return id;
  586. }
  587. static void cnic_free_id(struct cnic_id_tbl *id_tbl, u32 id)
  588. {
  589. if (id == -1)
  590. return;
  591. id -= id_tbl->start;
  592. if (id >= id_tbl->max)
  593. return;
  594. clear_bit(id, id_tbl->table);
  595. }
  596. static void cnic_free_dma(struct cnic_dev *dev, struct cnic_dma *dma)
  597. {
  598. int i;
  599. if (!dma->pg_arr)
  600. return;
  601. for (i = 0; i < dma->num_pages; i++) {
  602. if (dma->pg_arr[i]) {
  603. dma_free_coherent(&dev->pcidev->dev, CNIC_PAGE_SIZE,
  604. dma->pg_arr[i], dma->pg_map_arr[i]);
  605. dma->pg_arr[i] = NULL;
  606. }
  607. }
  608. if (dma->pgtbl) {
  609. dma_free_coherent(&dev->pcidev->dev, dma->pgtbl_size,
  610. dma->pgtbl, dma->pgtbl_map);
  611. dma->pgtbl = NULL;
  612. }
  613. kfree(dma->pg_arr);
  614. dma->pg_arr = NULL;
  615. dma->num_pages = 0;
  616. }
  617. static void cnic_setup_page_tbl(struct cnic_dev *dev, struct cnic_dma *dma)
  618. {
  619. int i;
  620. __le32 *page_table = (__le32 *) dma->pgtbl;
  621. for (i = 0; i < dma->num_pages; i++) {
  622. /* Each entry needs to be in big endian format. */
  623. *page_table = cpu_to_le32((u64) dma->pg_map_arr[i] >> 32);
  624. page_table++;
  625. *page_table = cpu_to_le32(dma->pg_map_arr[i] & 0xffffffff);
  626. page_table++;
  627. }
  628. }
  629. static void cnic_setup_page_tbl_le(struct cnic_dev *dev, struct cnic_dma *dma)
  630. {
  631. int i;
  632. __le32 *page_table = (__le32 *) dma->pgtbl;
  633. for (i = 0; i < dma->num_pages; i++) {
  634. /* Each entry needs to be in little endian format. */
  635. *page_table = cpu_to_le32(dma->pg_map_arr[i] & 0xffffffff);
  636. page_table++;
  637. *page_table = cpu_to_le32((u64) dma->pg_map_arr[i] >> 32);
  638. page_table++;
  639. }
  640. }
  641. static int cnic_alloc_dma(struct cnic_dev *dev, struct cnic_dma *dma,
  642. int pages, int use_pg_tbl)
  643. {
  644. int i, size;
  645. struct cnic_local *cp = dev->cnic_priv;
  646. size = pages * (sizeof(void *) + sizeof(dma_addr_t));
  647. dma->pg_arr = kzalloc(size, GFP_ATOMIC);
  648. if (dma->pg_arr == NULL)
  649. return -ENOMEM;
  650. dma->pg_map_arr = (dma_addr_t *) (dma->pg_arr + pages);
  651. dma->num_pages = pages;
  652. for (i = 0; i < pages; i++) {
  653. dma->pg_arr[i] = dma_alloc_coherent(&dev->pcidev->dev,
  654. CNIC_PAGE_SIZE,
  655. &dma->pg_map_arr[i],
  656. GFP_ATOMIC);
  657. if (dma->pg_arr[i] == NULL)
  658. goto error;
  659. }
  660. if (!use_pg_tbl)
  661. return 0;
  662. dma->pgtbl_size = ((pages * 8) + CNIC_PAGE_SIZE - 1) &
  663. ~(CNIC_PAGE_SIZE - 1);
  664. dma->pgtbl = dma_alloc_coherent(&dev->pcidev->dev, dma->pgtbl_size,
  665. &dma->pgtbl_map, GFP_ATOMIC);
  666. if (dma->pgtbl == NULL)
  667. goto error;
  668. cp->setup_pgtbl(dev, dma);
  669. return 0;
  670. error:
  671. cnic_free_dma(dev, dma);
  672. return -ENOMEM;
  673. }
  674. static void cnic_free_context(struct cnic_dev *dev)
  675. {
  676. struct cnic_local *cp = dev->cnic_priv;
  677. int i;
  678. for (i = 0; i < cp->ctx_blks; i++) {
  679. if (cp->ctx_arr[i].ctx) {
  680. dma_free_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
  681. cp->ctx_arr[i].ctx,
  682. cp->ctx_arr[i].mapping);
  683. cp->ctx_arr[i].ctx = NULL;
  684. }
  685. }
  686. }
  687. static void __cnic_free_uio_rings(struct cnic_uio_dev *udev)
  688. {
  689. if (udev->l2_buf) {
  690. dma_free_coherent(&udev->pdev->dev, udev->l2_buf_size,
  691. udev->l2_buf, udev->l2_buf_map);
  692. udev->l2_buf = NULL;
  693. }
  694. if (udev->l2_ring) {
  695. dma_free_coherent(&udev->pdev->dev, udev->l2_ring_size,
  696. udev->l2_ring, udev->l2_ring_map);
  697. udev->l2_ring = NULL;
  698. }
  699. }
  700. static void __cnic_free_uio(struct cnic_uio_dev *udev)
  701. {
  702. uio_unregister_device(&udev->cnic_uinfo);
  703. __cnic_free_uio_rings(udev);
  704. pci_dev_put(udev->pdev);
  705. kfree(udev);
  706. }
  707. static void cnic_free_uio(struct cnic_uio_dev *udev)
  708. {
  709. if (!udev)
  710. return;
  711. write_lock(&cnic_dev_lock);
  712. list_del_init(&udev->list);
  713. write_unlock(&cnic_dev_lock);
  714. __cnic_free_uio(udev);
  715. }
  716. static void cnic_free_resc(struct cnic_dev *dev)
  717. {
  718. struct cnic_local *cp = dev->cnic_priv;
  719. struct cnic_uio_dev *udev = cp->udev;
  720. if (udev) {
  721. udev->dev = NULL;
  722. cp->udev = NULL;
  723. if (udev->uio_dev == -1)
  724. __cnic_free_uio_rings(udev);
  725. }
  726. cnic_free_context(dev);
  727. kfree(cp->ctx_arr);
  728. cp->ctx_arr = NULL;
  729. cp->ctx_blks = 0;
  730. cnic_free_dma(dev, &cp->gbl_buf_info);
  731. cnic_free_dma(dev, &cp->kwq_info);
  732. cnic_free_dma(dev, &cp->kwq_16_data_info);
  733. cnic_free_dma(dev, &cp->kcq2.dma);
  734. cnic_free_dma(dev, &cp->kcq1.dma);
  735. kfree(cp->iscsi_tbl);
  736. cp->iscsi_tbl = NULL;
  737. kfree(cp->ctx_tbl);
  738. cp->ctx_tbl = NULL;
  739. cnic_free_id_tbl(&cp->fcoe_cid_tbl);
  740. cnic_free_id_tbl(&cp->cid_tbl);
  741. }
  742. static int cnic_alloc_context(struct cnic_dev *dev)
  743. {
  744. struct cnic_local *cp = dev->cnic_priv;
  745. if (BNX2_CHIP(cp) == BNX2_CHIP_5709) {
  746. int i, k, arr_size;
  747. cp->ctx_blk_size = CNIC_PAGE_SIZE;
  748. cp->cids_per_blk = CNIC_PAGE_SIZE / 128;
  749. arr_size = BNX2_MAX_CID / cp->cids_per_blk *
  750. sizeof(struct cnic_ctx);
  751. cp->ctx_arr = kzalloc(arr_size, GFP_KERNEL);
  752. if (cp->ctx_arr == NULL)
  753. return -ENOMEM;
  754. k = 0;
  755. for (i = 0; i < 2; i++) {
  756. u32 j, reg, off, lo, hi;
  757. if (i == 0)
  758. off = BNX2_PG_CTX_MAP;
  759. else
  760. off = BNX2_ISCSI_CTX_MAP;
  761. reg = cnic_reg_rd_ind(dev, off);
  762. lo = reg >> 16;
  763. hi = reg & 0xffff;
  764. for (j = lo; j < hi; j += cp->cids_per_blk, k++)
  765. cp->ctx_arr[k].cid = j;
  766. }
  767. cp->ctx_blks = k;
  768. if (cp->ctx_blks >= (BNX2_MAX_CID / cp->cids_per_blk)) {
  769. cp->ctx_blks = 0;
  770. return -ENOMEM;
  771. }
  772. for (i = 0; i < cp->ctx_blks; i++) {
  773. cp->ctx_arr[i].ctx =
  774. dma_alloc_coherent(&dev->pcidev->dev,
  775. CNIC_PAGE_SIZE,
  776. &cp->ctx_arr[i].mapping,
  777. GFP_KERNEL);
  778. if (cp->ctx_arr[i].ctx == NULL)
  779. return -ENOMEM;
  780. }
  781. }
  782. return 0;
  783. }
  784. static u16 cnic_bnx2_next_idx(u16 idx)
  785. {
  786. return idx + 1;
  787. }
  788. static u16 cnic_bnx2_hw_idx(u16 idx)
  789. {
  790. return idx;
  791. }
  792. static u16 cnic_bnx2x_next_idx(u16 idx)
  793. {
  794. idx++;
  795. if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
  796. idx++;
  797. return idx;
  798. }
  799. static u16 cnic_bnx2x_hw_idx(u16 idx)
  800. {
  801. if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
  802. idx++;
  803. return idx;
  804. }
  805. static int cnic_alloc_kcq(struct cnic_dev *dev, struct kcq_info *info,
  806. bool use_pg_tbl)
  807. {
  808. int err, i, use_page_tbl = 0;
  809. struct kcqe **kcq;
  810. if (use_pg_tbl)
  811. use_page_tbl = 1;
  812. err = cnic_alloc_dma(dev, &info->dma, KCQ_PAGE_CNT, use_page_tbl);
  813. if (err)
  814. return err;
  815. kcq = (struct kcqe **) info->dma.pg_arr;
  816. info->kcq = kcq;
  817. info->next_idx = cnic_bnx2_next_idx;
  818. info->hw_idx = cnic_bnx2_hw_idx;
  819. if (use_pg_tbl)
  820. return 0;
  821. info->next_idx = cnic_bnx2x_next_idx;
  822. info->hw_idx = cnic_bnx2x_hw_idx;
  823. for (i = 0; i < KCQ_PAGE_CNT; i++) {
  824. struct bnx2x_bd_chain_next *next =
  825. (struct bnx2x_bd_chain_next *) &kcq[i][MAX_KCQE_CNT];
  826. int j = i + 1;
  827. if (j >= KCQ_PAGE_CNT)
  828. j = 0;
  829. next->addr_hi = (u64) info->dma.pg_map_arr[j] >> 32;
  830. next->addr_lo = info->dma.pg_map_arr[j] & 0xffffffff;
  831. }
  832. return 0;
  833. }
  834. static int __cnic_alloc_uio_rings(struct cnic_uio_dev *udev, int pages)
  835. {
  836. struct cnic_local *cp = udev->dev->cnic_priv;
  837. if (udev->l2_ring)
  838. return 0;
  839. udev->l2_ring_size = pages * CNIC_PAGE_SIZE;
  840. udev->l2_ring = dma_alloc_coherent(&udev->pdev->dev, udev->l2_ring_size,
  841. &udev->l2_ring_map,
  842. GFP_KERNEL | __GFP_COMP);
  843. if (!udev->l2_ring)
  844. return -ENOMEM;
  845. udev->l2_buf_size = (cp->l2_rx_ring_size + 1) * cp->l2_single_buf_size;
  846. udev->l2_buf_size = CNIC_PAGE_ALIGN(udev->l2_buf_size);
  847. udev->l2_buf = dma_alloc_coherent(&udev->pdev->dev, udev->l2_buf_size,
  848. &udev->l2_buf_map,
  849. GFP_KERNEL | __GFP_COMP);
  850. if (!udev->l2_buf) {
  851. __cnic_free_uio_rings(udev);
  852. return -ENOMEM;
  853. }
  854. return 0;
  855. }
  856. static int cnic_alloc_uio_rings(struct cnic_dev *dev, int pages)
  857. {
  858. struct cnic_local *cp = dev->cnic_priv;
  859. struct cnic_uio_dev *udev;
  860. list_for_each_entry(udev, &cnic_udev_list, list) {
  861. if (udev->pdev == dev->pcidev) {
  862. udev->dev = dev;
  863. if (__cnic_alloc_uio_rings(udev, pages)) {
  864. udev->dev = NULL;
  865. return -ENOMEM;
  866. }
  867. cp->udev = udev;
  868. return 0;
  869. }
  870. }
  871. udev = kzalloc(sizeof(struct cnic_uio_dev), GFP_ATOMIC);
  872. if (!udev)
  873. return -ENOMEM;
  874. udev->uio_dev = -1;
  875. udev->dev = dev;
  876. udev->pdev = dev->pcidev;
  877. if (__cnic_alloc_uio_rings(udev, pages))
  878. goto err_udev;
  879. list_add(&udev->list, &cnic_udev_list);
  880. pci_dev_get(udev->pdev);
  881. cp->udev = udev;
  882. return 0;
  883. err_udev:
  884. kfree(udev);
  885. return -ENOMEM;
  886. }
  887. static int cnic_init_uio(struct cnic_dev *dev)
  888. {
  889. struct cnic_local *cp = dev->cnic_priv;
  890. struct cnic_uio_dev *udev = cp->udev;
  891. struct uio_info *uinfo;
  892. int ret = 0;
  893. if (!udev)
  894. return -ENOMEM;
  895. uinfo = &udev->cnic_uinfo;
  896. uinfo->mem[0].addr = pci_resource_start(dev->pcidev, 0);
  897. uinfo->mem[0].internal_addr = dev->regview;
  898. uinfo->mem[0].memtype = UIO_MEM_PHYS;
  899. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  900. uinfo->mem[0].size = MB_GET_CID_ADDR(TX_TSS_CID +
  901. TX_MAX_TSS_RINGS + 1);
  902. uinfo->mem[1].addr = (unsigned long) cp->status_blk.gen &
  903. CNIC_PAGE_MASK;
  904. if (cp->ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)
  905. uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE * 9;
  906. else
  907. uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE;
  908. uinfo->name = "bnx2_cnic";
  909. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  910. uinfo->mem[0].size = pci_resource_len(dev->pcidev, 0);
  911. uinfo->mem[1].addr = (unsigned long) cp->bnx2x_def_status_blk &
  912. CNIC_PAGE_MASK;
  913. uinfo->mem[1].size = sizeof(*cp->bnx2x_def_status_blk);
  914. uinfo->name = "bnx2x_cnic";
  915. }
  916. uinfo->mem[1].memtype = UIO_MEM_LOGICAL;
  917. uinfo->mem[2].addr = (unsigned long) udev->l2_ring;
  918. uinfo->mem[2].size = udev->l2_ring_size;
  919. uinfo->mem[2].memtype = UIO_MEM_LOGICAL;
  920. uinfo->mem[3].addr = (unsigned long) udev->l2_buf;
  921. uinfo->mem[3].size = udev->l2_buf_size;
  922. uinfo->mem[3].memtype = UIO_MEM_LOGICAL;
  923. uinfo->version = CNIC_MODULE_VERSION;
  924. uinfo->irq = UIO_IRQ_CUSTOM;
  925. uinfo->open = cnic_uio_open;
  926. uinfo->release = cnic_uio_close;
  927. if (udev->uio_dev == -1) {
  928. if (!uinfo->priv) {
  929. uinfo->priv = udev;
  930. ret = uio_register_device(&udev->pdev->dev, uinfo);
  931. }
  932. } else {
  933. cnic_init_rings(dev);
  934. }
  935. return ret;
  936. }
  937. static int cnic_alloc_bnx2_resc(struct cnic_dev *dev)
  938. {
  939. struct cnic_local *cp = dev->cnic_priv;
  940. int ret;
  941. ret = cnic_alloc_dma(dev, &cp->kwq_info, KWQ_PAGE_CNT, 1);
  942. if (ret)
  943. goto error;
  944. cp->kwq = (struct kwqe **) cp->kwq_info.pg_arr;
  945. ret = cnic_alloc_kcq(dev, &cp->kcq1, true);
  946. if (ret)
  947. goto error;
  948. ret = cnic_alloc_context(dev);
  949. if (ret)
  950. goto error;
  951. ret = cnic_alloc_uio_rings(dev, 2);
  952. if (ret)
  953. goto error;
  954. ret = cnic_init_uio(dev);
  955. if (ret)
  956. goto error;
  957. return 0;
  958. error:
  959. cnic_free_resc(dev);
  960. return ret;
  961. }
  962. static int cnic_alloc_bnx2x_context(struct cnic_dev *dev)
  963. {
  964. struct cnic_local *cp = dev->cnic_priv;
  965. struct bnx2x *bp = netdev_priv(dev->netdev);
  966. int ctx_blk_size = cp->ethdev->ctx_blk_size;
  967. int total_mem, blks, i;
  968. total_mem = BNX2X_CONTEXT_MEM_SIZE * cp->max_cid_space;
  969. blks = total_mem / ctx_blk_size;
  970. if (total_mem % ctx_blk_size)
  971. blks++;
  972. if (blks > cp->ethdev->ctx_tbl_len)
  973. return -ENOMEM;
  974. cp->ctx_arr = kcalloc(blks, sizeof(struct cnic_ctx), GFP_KERNEL);
  975. if (cp->ctx_arr == NULL)
  976. return -ENOMEM;
  977. cp->ctx_blks = blks;
  978. cp->ctx_blk_size = ctx_blk_size;
  979. if (!CHIP_IS_E1(bp))
  980. cp->ctx_align = 0;
  981. else
  982. cp->ctx_align = ctx_blk_size;
  983. cp->cids_per_blk = ctx_blk_size / BNX2X_CONTEXT_MEM_SIZE;
  984. for (i = 0; i < blks; i++) {
  985. cp->ctx_arr[i].ctx =
  986. dma_alloc_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
  987. &cp->ctx_arr[i].mapping,
  988. GFP_KERNEL);
  989. if (cp->ctx_arr[i].ctx == NULL)
  990. return -ENOMEM;
  991. if (cp->ctx_align && cp->ctx_blk_size == ctx_blk_size) {
  992. if (cp->ctx_arr[i].mapping & (cp->ctx_align - 1)) {
  993. cnic_free_context(dev);
  994. cp->ctx_blk_size += cp->ctx_align;
  995. i = -1;
  996. continue;
  997. }
  998. }
  999. }
  1000. return 0;
  1001. }
  1002. static int cnic_alloc_bnx2x_resc(struct cnic_dev *dev)
  1003. {
  1004. struct cnic_local *cp = dev->cnic_priv;
  1005. struct bnx2x *bp = netdev_priv(dev->netdev);
  1006. struct cnic_eth_dev *ethdev = cp->ethdev;
  1007. u32 start_cid = ethdev->starting_cid;
  1008. int i, j, n, ret, pages;
  1009. struct cnic_dma *kwq_16_dma = &cp->kwq_16_data_info;
  1010. cp->max_cid_space = MAX_ISCSI_TBL_SZ;
  1011. cp->iscsi_start_cid = start_cid;
  1012. cp->fcoe_start_cid = start_cid + MAX_ISCSI_TBL_SZ;
  1013. if (BNX2X_CHIP_IS_E2_PLUS(bp)) {
  1014. cp->max_cid_space += dev->max_fcoe_conn;
  1015. cp->fcoe_init_cid = ethdev->fcoe_init_cid;
  1016. if (!cp->fcoe_init_cid)
  1017. cp->fcoe_init_cid = 0x10;
  1018. }
  1019. cp->iscsi_tbl = kzalloc(sizeof(struct cnic_iscsi) * MAX_ISCSI_TBL_SZ,
  1020. GFP_KERNEL);
  1021. if (!cp->iscsi_tbl)
  1022. goto error;
  1023. cp->ctx_tbl = kzalloc(sizeof(struct cnic_context) *
  1024. cp->max_cid_space, GFP_KERNEL);
  1025. if (!cp->ctx_tbl)
  1026. goto error;
  1027. for (i = 0; i < MAX_ISCSI_TBL_SZ; i++) {
  1028. cp->ctx_tbl[i].proto.iscsi = &cp->iscsi_tbl[i];
  1029. cp->ctx_tbl[i].ulp_proto_id = CNIC_ULP_ISCSI;
  1030. }
  1031. for (i = MAX_ISCSI_TBL_SZ; i < cp->max_cid_space; i++)
  1032. cp->ctx_tbl[i].ulp_proto_id = CNIC_ULP_FCOE;
  1033. pages = CNIC_PAGE_ALIGN(cp->max_cid_space * CNIC_KWQ16_DATA_SIZE) /
  1034. CNIC_PAGE_SIZE;
  1035. ret = cnic_alloc_dma(dev, kwq_16_dma, pages, 0);
  1036. if (ret)
  1037. return -ENOMEM;
  1038. n = CNIC_PAGE_SIZE / CNIC_KWQ16_DATA_SIZE;
  1039. for (i = 0, j = 0; i < cp->max_cid_space; i++) {
  1040. long off = CNIC_KWQ16_DATA_SIZE * (i % n);
  1041. cp->ctx_tbl[i].kwqe_data = kwq_16_dma->pg_arr[j] + off;
  1042. cp->ctx_tbl[i].kwqe_data_mapping = kwq_16_dma->pg_map_arr[j] +
  1043. off;
  1044. if ((i % n) == (n - 1))
  1045. j++;
  1046. }
  1047. ret = cnic_alloc_kcq(dev, &cp->kcq1, false);
  1048. if (ret)
  1049. goto error;
  1050. if (CNIC_SUPPORTS_FCOE(bp)) {
  1051. ret = cnic_alloc_kcq(dev, &cp->kcq2, true);
  1052. if (ret)
  1053. goto error;
  1054. }
  1055. pages = CNIC_PAGE_ALIGN(BNX2X_ISCSI_GLB_BUF_SIZE) / CNIC_PAGE_SIZE;
  1056. ret = cnic_alloc_dma(dev, &cp->gbl_buf_info, pages, 0);
  1057. if (ret)
  1058. goto error;
  1059. ret = cnic_alloc_bnx2x_context(dev);
  1060. if (ret)
  1061. goto error;
  1062. if (cp->ethdev->drv_state & CNIC_DRV_STATE_NO_ISCSI)
  1063. return 0;
  1064. cp->bnx2x_def_status_blk = cp->ethdev->irq_arr[1].status_blk;
  1065. cp->l2_rx_ring_size = 15;
  1066. ret = cnic_alloc_uio_rings(dev, 4);
  1067. if (ret)
  1068. goto error;
  1069. ret = cnic_init_uio(dev);
  1070. if (ret)
  1071. goto error;
  1072. return 0;
  1073. error:
  1074. cnic_free_resc(dev);
  1075. return -ENOMEM;
  1076. }
  1077. static inline u32 cnic_kwq_avail(struct cnic_local *cp)
  1078. {
  1079. return cp->max_kwq_idx -
  1080. ((cp->kwq_prod_idx - cp->kwq_con_idx) & cp->max_kwq_idx);
  1081. }
  1082. static int cnic_submit_bnx2_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
  1083. u32 num_wqes)
  1084. {
  1085. struct cnic_local *cp = dev->cnic_priv;
  1086. struct kwqe *prod_qe;
  1087. u16 prod, sw_prod, i;
  1088. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  1089. return -EAGAIN; /* bnx2 is down */
  1090. spin_lock_bh(&cp->cnic_ulp_lock);
  1091. if (num_wqes > cnic_kwq_avail(cp) &&
  1092. !test_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags)) {
  1093. spin_unlock_bh(&cp->cnic_ulp_lock);
  1094. return -EAGAIN;
  1095. }
  1096. clear_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags);
  1097. prod = cp->kwq_prod_idx;
  1098. sw_prod = prod & MAX_KWQ_IDX;
  1099. for (i = 0; i < num_wqes; i++) {
  1100. prod_qe = &cp->kwq[KWQ_PG(sw_prod)][KWQ_IDX(sw_prod)];
  1101. memcpy(prod_qe, wqes[i], sizeof(struct kwqe));
  1102. prod++;
  1103. sw_prod = prod & MAX_KWQ_IDX;
  1104. }
  1105. cp->kwq_prod_idx = prod;
  1106. CNIC_WR16(dev, cp->kwq_io_addr, cp->kwq_prod_idx);
  1107. spin_unlock_bh(&cp->cnic_ulp_lock);
  1108. return 0;
  1109. }
  1110. static void *cnic_get_kwqe_16_data(struct cnic_local *cp, u32 l5_cid,
  1111. union l5cm_specific_data *l5_data)
  1112. {
  1113. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1114. dma_addr_t map;
  1115. map = ctx->kwqe_data_mapping;
  1116. l5_data->phy_address.lo = (u64) map & 0xffffffff;
  1117. l5_data->phy_address.hi = (u64) map >> 32;
  1118. return ctx->kwqe_data;
  1119. }
  1120. static int cnic_submit_kwqe_16(struct cnic_dev *dev, u32 cmd, u32 cid,
  1121. u32 type, union l5cm_specific_data *l5_data)
  1122. {
  1123. struct cnic_local *cp = dev->cnic_priv;
  1124. struct bnx2x *bp = netdev_priv(dev->netdev);
  1125. struct l5cm_spe kwqe;
  1126. struct kwqe_16 *kwq[1];
  1127. u16 type_16;
  1128. int ret;
  1129. kwqe.hdr.conn_and_cmd_data =
  1130. cpu_to_le32(((cmd << SPE_HDR_CMD_ID_SHIFT) |
  1131. BNX2X_HW_CID(bp, cid)));
  1132. type_16 = (type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
  1133. type_16 |= (bp->pfid << SPE_HDR_FUNCTION_ID_SHIFT) &
  1134. SPE_HDR_FUNCTION_ID;
  1135. kwqe.hdr.type = cpu_to_le16(type_16);
  1136. kwqe.hdr.reserved1 = 0;
  1137. kwqe.data.phy_address.lo = cpu_to_le32(l5_data->phy_address.lo);
  1138. kwqe.data.phy_address.hi = cpu_to_le32(l5_data->phy_address.hi);
  1139. kwq[0] = (struct kwqe_16 *) &kwqe;
  1140. spin_lock_bh(&cp->cnic_ulp_lock);
  1141. ret = cp->ethdev->drv_submit_kwqes_16(dev->netdev, kwq, 1);
  1142. spin_unlock_bh(&cp->cnic_ulp_lock);
  1143. if (ret == 1)
  1144. return 0;
  1145. return ret;
  1146. }
  1147. static void cnic_reply_bnx2x_kcqes(struct cnic_dev *dev, int ulp_type,
  1148. struct kcqe *cqes[], u32 num_cqes)
  1149. {
  1150. struct cnic_local *cp = dev->cnic_priv;
  1151. struct cnic_ulp_ops *ulp_ops;
  1152. rcu_read_lock();
  1153. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  1154. if (likely(ulp_ops)) {
  1155. ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
  1156. cqes, num_cqes);
  1157. }
  1158. rcu_read_unlock();
  1159. }
  1160. static void cnic_bnx2x_set_tcp_options(struct cnic_dev *dev, int time_stamps,
  1161. int en_tcp_dack)
  1162. {
  1163. struct bnx2x *bp = netdev_priv(dev->netdev);
  1164. u8 xstorm_flags = XSTORM_L5CM_TCP_FLAGS_WND_SCL_EN;
  1165. u16 tstorm_flags = 0;
  1166. if (time_stamps) {
  1167. xstorm_flags |= XSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
  1168. tstorm_flags |= TSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
  1169. }
  1170. if (en_tcp_dack)
  1171. tstorm_flags |= TSTORM_L5CM_TCP_FLAGS_DELAYED_ACK_EN;
  1172. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1173. XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(bp->pfid), xstorm_flags);
  1174. CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
  1175. TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(bp->pfid), tstorm_flags);
  1176. }
  1177. static int cnic_bnx2x_iscsi_init1(struct cnic_dev *dev, struct kwqe *kwqe)
  1178. {
  1179. struct cnic_local *cp = dev->cnic_priv;
  1180. struct bnx2x *bp = netdev_priv(dev->netdev);
  1181. struct iscsi_kwqe_init1 *req1 = (struct iscsi_kwqe_init1 *) kwqe;
  1182. int hq_bds, pages;
  1183. u32 pfid = bp->pfid;
  1184. cp->num_iscsi_tasks = req1->num_tasks_per_conn;
  1185. cp->num_ccells = req1->num_ccells_per_conn;
  1186. cp->task_array_size = BNX2X_ISCSI_TASK_CONTEXT_SIZE *
  1187. cp->num_iscsi_tasks;
  1188. cp->r2tq_size = cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS *
  1189. BNX2X_ISCSI_R2TQE_SIZE;
  1190. cp->hq_size = cp->num_ccells * BNX2X_ISCSI_HQ_BD_SIZE;
  1191. pages = CNIC_PAGE_ALIGN(cp->hq_size) / CNIC_PAGE_SIZE;
  1192. hq_bds = pages * (CNIC_PAGE_SIZE / BNX2X_ISCSI_HQ_BD_SIZE);
  1193. cp->num_cqs = req1->num_cqs;
  1194. if (!dev->max_iscsi_conn)
  1195. return 0;
  1196. /* init Tstorm RAM */
  1197. CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_RQ_SIZE_OFFSET(pfid),
  1198. req1->rq_num_wqes);
  1199. CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1200. CNIC_PAGE_SIZE);
  1201. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1202. TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), CNIC_PAGE_BITS);
  1203. CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
  1204. TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1205. req1->num_tasks_per_conn);
  1206. /* init Ustorm RAM */
  1207. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1208. USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(pfid),
  1209. req1->rq_buffer_size);
  1210. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1211. CNIC_PAGE_SIZE);
  1212. CNIC_WR8(dev, BAR_USTRORM_INTMEM +
  1213. USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), CNIC_PAGE_BITS);
  1214. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1215. USTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1216. req1->num_tasks_per_conn);
  1217. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_RQ_SIZE_OFFSET(pfid),
  1218. req1->rq_num_wqes);
  1219. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_CQ_SIZE_OFFSET(pfid),
  1220. req1->cq_num_wqes);
  1221. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_R2TQ_SIZE_OFFSET(pfid),
  1222. cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
  1223. /* init Xstorm RAM */
  1224. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1225. CNIC_PAGE_SIZE);
  1226. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1227. XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), CNIC_PAGE_BITS);
  1228. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  1229. XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1230. req1->num_tasks_per_conn);
  1231. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_HQ_SIZE_OFFSET(pfid),
  1232. hq_bds);
  1233. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_SQ_SIZE_OFFSET(pfid),
  1234. req1->num_tasks_per_conn);
  1235. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_R2TQ_SIZE_OFFSET(pfid),
  1236. cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
  1237. /* init Cstorm RAM */
  1238. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1239. CNIC_PAGE_SIZE);
  1240. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  1241. CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), CNIC_PAGE_BITS);
  1242. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  1243. CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1244. req1->num_tasks_per_conn);
  1245. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_CQ_SIZE_OFFSET(pfid),
  1246. req1->cq_num_wqes);
  1247. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_HQ_SIZE_OFFSET(pfid),
  1248. hq_bds);
  1249. cnic_bnx2x_set_tcp_options(dev,
  1250. req1->flags & ISCSI_KWQE_INIT1_TIME_STAMPS_ENABLE,
  1251. req1->flags & ISCSI_KWQE_INIT1_DELAYED_ACK_ENABLE);
  1252. return 0;
  1253. }
  1254. static int cnic_bnx2x_iscsi_init2(struct cnic_dev *dev, struct kwqe *kwqe)
  1255. {
  1256. struct iscsi_kwqe_init2 *req2 = (struct iscsi_kwqe_init2 *) kwqe;
  1257. struct bnx2x *bp = netdev_priv(dev->netdev);
  1258. u32 pfid = bp->pfid;
  1259. struct iscsi_kcqe kcqe;
  1260. struct kcqe *cqes[1];
  1261. memset(&kcqe, 0, sizeof(kcqe));
  1262. if (!dev->max_iscsi_conn) {
  1263. kcqe.completion_status =
  1264. ISCSI_KCQE_COMPLETION_STATUS_ISCSI_NOT_SUPPORTED;
  1265. goto done;
  1266. }
  1267. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  1268. TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid), req2->error_bit_map[0]);
  1269. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  1270. TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid) + 4,
  1271. req2->error_bit_map[1]);
  1272. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1273. USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfid), req2->max_cq_sqn);
  1274. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  1275. USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid), req2->error_bit_map[0]);
  1276. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  1277. USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid) + 4,
  1278. req2->error_bit_map[1]);
  1279. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  1280. CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfid), req2->max_cq_sqn);
  1281. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1282. done:
  1283. kcqe.op_code = ISCSI_KCQE_OPCODE_INIT;
  1284. cqes[0] = (struct kcqe *) &kcqe;
  1285. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1286. return 0;
  1287. }
  1288. static void cnic_free_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
  1289. {
  1290. struct cnic_local *cp = dev->cnic_priv;
  1291. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1292. if (ctx->ulp_proto_id == CNIC_ULP_ISCSI) {
  1293. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1294. cnic_free_dma(dev, &iscsi->hq_info);
  1295. cnic_free_dma(dev, &iscsi->r2tq_info);
  1296. cnic_free_dma(dev, &iscsi->task_array_info);
  1297. cnic_free_id(&cp->cid_tbl, ctx->cid);
  1298. } else {
  1299. cnic_free_id(&cp->fcoe_cid_tbl, ctx->cid);
  1300. }
  1301. ctx->cid = 0;
  1302. }
  1303. static int cnic_alloc_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
  1304. {
  1305. u32 cid;
  1306. int ret, pages;
  1307. struct cnic_local *cp = dev->cnic_priv;
  1308. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1309. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1310. if (ctx->ulp_proto_id == CNIC_ULP_FCOE) {
  1311. cid = cnic_alloc_new_id(&cp->fcoe_cid_tbl);
  1312. if (cid == -1) {
  1313. ret = -ENOMEM;
  1314. goto error;
  1315. }
  1316. ctx->cid = cid;
  1317. return 0;
  1318. }
  1319. cid = cnic_alloc_new_id(&cp->cid_tbl);
  1320. if (cid == -1) {
  1321. ret = -ENOMEM;
  1322. goto error;
  1323. }
  1324. ctx->cid = cid;
  1325. pages = CNIC_PAGE_ALIGN(cp->task_array_size) / CNIC_PAGE_SIZE;
  1326. ret = cnic_alloc_dma(dev, &iscsi->task_array_info, pages, 1);
  1327. if (ret)
  1328. goto error;
  1329. pages = CNIC_PAGE_ALIGN(cp->r2tq_size) / CNIC_PAGE_SIZE;
  1330. ret = cnic_alloc_dma(dev, &iscsi->r2tq_info, pages, 1);
  1331. if (ret)
  1332. goto error;
  1333. pages = CNIC_PAGE_ALIGN(cp->hq_size) / CNIC_PAGE_SIZE;
  1334. ret = cnic_alloc_dma(dev, &iscsi->hq_info, pages, 1);
  1335. if (ret)
  1336. goto error;
  1337. return 0;
  1338. error:
  1339. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1340. return ret;
  1341. }
  1342. static void *cnic_get_bnx2x_ctx(struct cnic_dev *dev, u32 cid, int init,
  1343. struct regpair *ctx_addr)
  1344. {
  1345. struct cnic_local *cp = dev->cnic_priv;
  1346. struct cnic_eth_dev *ethdev = cp->ethdev;
  1347. int blk = (cid - ethdev->starting_cid) / cp->cids_per_blk;
  1348. int off = (cid - ethdev->starting_cid) % cp->cids_per_blk;
  1349. unsigned long align_off = 0;
  1350. dma_addr_t ctx_map;
  1351. void *ctx;
  1352. if (cp->ctx_align) {
  1353. unsigned long mask = cp->ctx_align - 1;
  1354. if (cp->ctx_arr[blk].mapping & mask)
  1355. align_off = cp->ctx_align -
  1356. (cp->ctx_arr[blk].mapping & mask);
  1357. }
  1358. ctx_map = cp->ctx_arr[blk].mapping + align_off +
  1359. (off * BNX2X_CONTEXT_MEM_SIZE);
  1360. ctx = cp->ctx_arr[blk].ctx + align_off +
  1361. (off * BNX2X_CONTEXT_MEM_SIZE);
  1362. if (init)
  1363. memset(ctx, 0, BNX2X_CONTEXT_MEM_SIZE);
  1364. ctx_addr->lo = ctx_map & 0xffffffff;
  1365. ctx_addr->hi = (u64) ctx_map >> 32;
  1366. return ctx;
  1367. }
  1368. static int cnic_setup_bnx2x_ctx(struct cnic_dev *dev, struct kwqe *wqes[],
  1369. u32 num)
  1370. {
  1371. struct cnic_local *cp = dev->cnic_priv;
  1372. struct bnx2x *bp = netdev_priv(dev->netdev);
  1373. struct iscsi_kwqe_conn_offload1 *req1 =
  1374. (struct iscsi_kwqe_conn_offload1 *) wqes[0];
  1375. struct iscsi_kwqe_conn_offload2 *req2 =
  1376. (struct iscsi_kwqe_conn_offload2 *) wqes[1];
  1377. struct iscsi_kwqe_conn_offload3 *req3;
  1378. struct cnic_context *ctx = &cp->ctx_tbl[req1->iscsi_conn_id];
  1379. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1380. u32 cid = ctx->cid;
  1381. u32 hw_cid = BNX2X_HW_CID(bp, cid);
  1382. struct iscsi_context *ictx;
  1383. struct regpair context_addr;
  1384. int i, j, n = 2, n_max;
  1385. u8 port = BP_PORT(bp);
  1386. ctx->ctx_flags = 0;
  1387. if (!req2->num_additional_wqes)
  1388. return -EINVAL;
  1389. n_max = req2->num_additional_wqes + 2;
  1390. ictx = cnic_get_bnx2x_ctx(dev, cid, 1, &context_addr);
  1391. if (ictx == NULL)
  1392. return -ENOMEM;
  1393. req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
  1394. ictx->xstorm_ag_context.hq_prod = 1;
  1395. ictx->xstorm_st_context.iscsi.first_burst_length =
  1396. ISCSI_DEF_FIRST_BURST_LEN;
  1397. ictx->xstorm_st_context.iscsi.max_send_pdu_length =
  1398. ISCSI_DEF_MAX_RECV_SEG_LEN;
  1399. ictx->xstorm_st_context.iscsi.sq_pbl_base.lo =
  1400. req1->sq_page_table_addr_lo;
  1401. ictx->xstorm_st_context.iscsi.sq_pbl_base.hi =
  1402. req1->sq_page_table_addr_hi;
  1403. ictx->xstorm_st_context.iscsi.sq_curr_pbe.lo = req2->sq_first_pte.hi;
  1404. ictx->xstorm_st_context.iscsi.sq_curr_pbe.hi = req2->sq_first_pte.lo;
  1405. ictx->xstorm_st_context.iscsi.hq_pbl_base.lo =
  1406. iscsi->hq_info.pgtbl_map & 0xffffffff;
  1407. ictx->xstorm_st_context.iscsi.hq_pbl_base.hi =
  1408. (u64) iscsi->hq_info.pgtbl_map >> 32;
  1409. ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.lo =
  1410. iscsi->hq_info.pgtbl[0];
  1411. ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.hi =
  1412. iscsi->hq_info.pgtbl[1];
  1413. ictx->xstorm_st_context.iscsi.r2tq_pbl_base.lo =
  1414. iscsi->r2tq_info.pgtbl_map & 0xffffffff;
  1415. ictx->xstorm_st_context.iscsi.r2tq_pbl_base.hi =
  1416. (u64) iscsi->r2tq_info.pgtbl_map >> 32;
  1417. ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.lo =
  1418. iscsi->r2tq_info.pgtbl[0];
  1419. ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.hi =
  1420. iscsi->r2tq_info.pgtbl[1];
  1421. ictx->xstorm_st_context.iscsi.task_pbl_base.lo =
  1422. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1423. ictx->xstorm_st_context.iscsi.task_pbl_base.hi =
  1424. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1425. ictx->xstorm_st_context.iscsi.task_pbl_cache_idx =
  1426. BNX2X_ISCSI_PBL_NOT_CACHED;
  1427. ictx->xstorm_st_context.iscsi.flags.flags |=
  1428. XSTORM_ISCSI_CONTEXT_FLAGS_B_IMMEDIATE_DATA;
  1429. ictx->xstorm_st_context.iscsi.flags.flags |=
  1430. XSTORM_ISCSI_CONTEXT_FLAGS_B_INITIAL_R2T;
  1431. ictx->xstorm_st_context.common.ethernet.reserved_vlan_type =
  1432. ETH_P_8021Q;
  1433. if (BNX2X_CHIP_IS_E2_PLUS(bp) &&
  1434. bp->common.chip_port_mode == CHIP_2_PORT_MODE) {
  1435. port = 0;
  1436. }
  1437. ictx->xstorm_st_context.common.flags =
  1438. 1 << XSTORM_COMMON_CONTEXT_SECTION_PHYSQ_INITIALIZED_SHIFT;
  1439. ictx->xstorm_st_context.common.flags =
  1440. port << XSTORM_COMMON_CONTEXT_SECTION_PBF_PORT_SHIFT;
  1441. ictx->tstorm_st_context.iscsi.hdr_bytes_2_fetch = ISCSI_HEADER_SIZE;
  1442. /* TSTORM requires the base address of RQ DB & not PTE */
  1443. ictx->tstorm_st_context.iscsi.rq_db_phy_addr.lo =
  1444. req2->rq_page_table_addr_lo & CNIC_PAGE_MASK;
  1445. ictx->tstorm_st_context.iscsi.rq_db_phy_addr.hi =
  1446. req2->rq_page_table_addr_hi;
  1447. ictx->tstorm_st_context.iscsi.iscsi_conn_id = req1->iscsi_conn_id;
  1448. ictx->tstorm_st_context.tcp.cwnd = 0x5A8;
  1449. ictx->tstorm_st_context.tcp.flags2 |=
  1450. TSTORM_TCP_ST_CONTEXT_SECTION_DA_EN;
  1451. ictx->tstorm_st_context.tcp.ooo_support_mode =
  1452. TCP_TSTORM_OOO_DROP_AND_PROC_ACK;
  1453. ictx->timers_context.flags |= TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG;
  1454. ictx->ustorm_st_context.ring.rq.pbl_base.lo =
  1455. req2->rq_page_table_addr_lo;
  1456. ictx->ustorm_st_context.ring.rq.pbl_base.hi =
  1457. req2->rq_page_table_addr_hi;
  1458. ictx->ustorm_st_context.ring.rq.curr_pbe.lo = req3->qp_first_pte[0].hi;
  1459. ictx->ustorm_st_context.ring.rq.curr_pbe.hi = req3->qp_first_pte[0].lo;
  1460. ictx->ustorm_st_context.ring.r2tq.pbl_base.lo =
  1461. iscsi->r2tq_info.pgtbl_map & 0xffffffff;
  1462. ictx->ustorm_st_context.ring.r2tq.pbl_base.hi =
  1463. (u64) iscsi->r2tq_info.pgtbl_map >> 32;
  1464. ictx->ustorm_st_context.ring.r2tq.curr_pbe.lo =
  1465. iscsi->r2tq_info.pgtbl[0];
  1466. ictx->ustorm_st_context.ring.r2tq.curr_pbe.hi =
  1467. iscsi->r2tq_info.pgtbl[1];
  1468. ictx->ustorm_st_context.ring.cq_pbl_base.lo =
  1469. req1->cq_page_table_addr_lo;
  1470. ictx->ustorm_st_context.ring.cq_pbl_base.hi =
  1471. req1->cq_page_table_addr_hi;
  1472. ictx->ustorm_st_context.ring.cq[0].cq_sn = ISCSI_INITIAL_SN;
  1473. ictx->ustorm_st_context.ring.cq[0].curr_pbe.lo = req2->cq_first_pte.hi;
  1474. ictx->ustorm_st_context.ring.cq[0].curr_pbe.hi = req2->cq_first_pte.lo;
  1475. ictx->ustorm_st_context.task_pbe_cache_index =
  1476. BNX2X_ISCSI_PBL_NOT_CACHED;
  1477. ictx->ustorm_st_context.task_pdu_cache_index =
  1478. BNX2X_ISCSI_PDU_HEADER_NOT_CACHED;
  1479. for (i = 1, j = 1; i < cp->num_cqs; i++, j++) {
  1480. if (j == 3) {
  1481. if (n >= n_max)
  1482. break;
  1483. req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
  1484. j = 0;
  1485. }
  1486. ictx->ustorm_st_context.ring.cq[i].cq_sn = ISCSI_INITIAL_SN;
  1487. ictx->ustorm_st_context.ring.cq[i].curr_pbe.lo =
  1488. req3->qp_first_pte[j].hi;
  1489. ictx->ustorm_st_context.ring.cq[i].curr_pbe.hi =
  1490. req3->qp_first_pte[j].lo;
  1491. }
  1492. ictx->ustorm_st_context.task_pbl_base.lo =
  1493. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1494. ictx->ustorm_st_context.task_pbl_base.hi =
  1495. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1496. ictx->ustorm_st_context.tce_phy_addr.lo =
  1497. iscsi->task_array_info.pgtbl[0];
  1498. ictx->ustorm_st_context.tce_phy_addr.hi =
  1499. iscsi->task_array_info.pgtbl[1];
  1500. ictx->ustorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
  1501. ictx->ustorm_st_context.num_cqs = cp->num_cqs;
  1502. ictx->ustorm_st_context.negotiated_rx |= ISCSI_DEF_MAX_RECV_SEG_LEN;
  1503. ictx->ustorm_st_context.negotiated_rx_and_flags |=
  1504. ISCSI_DEF_MAX_BURST_LEN;
  1505. ictx->ustorm_st_context.negotiated_rx |=
  1506. ISCSI_DEFAULT_MAX_OUTSTANDING_R2T <<
  1507. USTORM_ISCSI_ST_CONTEXT_MAX_OUTSTANDING_R2TS_SHIFT;
  1508. ictx->cstorm_st_context.hq_pbl_base.lo =
  1509. iscsi->hq_info.pgtbl_map & 0xffffffff;
  1510. ictx->cstorm_st_context.hq_pbl_base.hi =
  1511. (u64) iscsi->hq_info.pgtbl_map >> 32;
  1512. ictx->cstorm_st_context.hq_curr_pbe.lo = iscsi->hq_info.pgtbl[0];
  1513. ictx->cstorm_st_context.hq_curr_pbe.hi = iscsi->hq_info.pgtbl[1];
  1514. ictx->cstorm_st_context.task_pbl_base.lo =
  1515. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1516. ictx->cstorm_st_context.task_pbl_base.hi =
  1517. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1518. /* CSTORM and USTORM initialization is different, CSTORM requires
  1519. * CQ DB base & not PTE addr */
  1520. ictx->cstorm_st_context.cq_db_base.lo =
  1521. req1->cq_page_table_addr_lo & CNIC_PAGE_MASK;
  1522. ictx->cstorm_st_context.cq_db_base.hi = req1->cq_page_table_addr_hi;
  1523. ictx->cstorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
  1524. ictx->cstorm_st_context.cq_proc_en_bit_map = (1 << cp->num_cqs) - 1;
  1525. for (i = 0; i < cp->num_cqs; i++) {
  1526. ictx->cstorm_st_context.cq_c_prod_sqn_arr.sqn[i] =
  1527. ISCSI_INITIAL_SN;
  1528. ictx->cstorm_st_context.cq_c_sqn_2_notify_arr.sqn[i] =
  1529. ISCSI_INITIAL_SN;
  1530. }
  1531. ictx->xstorm_ag_context.cdu_reserved =
  1532. CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_XCM_AG,
  1533. ISCSI_CONNECTION_TYPE);
  1534. ictx->ustorm_ag_context.cdu_usage =
  1535. CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_UCM_AG,
  1536. ISCSI_CONNECTION_TYPE);
  1537. return 0;
  1538. }
  1539. static int cnic_bnx2x_iscsi_ofld1(struct cnic_dev *dev, struct kwqe *wqes[],
  1540. u32 num, int *work)
  1541. {
  1542. struct iscsi_kwqe_conn_offload1 *req1;
  1543. struct iscsi_kwqe_conn_offload2 *req2;
  1544. struct cnic_local *cp = dev->cnic_priv;
  1545. struct bnx2x *bp = netdev_priv(dev->netdev);
  1546. struct cnic_context *ctx;
  1547. struct iscsi_kcqe kcqe;
  1548. struct kcqe *cqes[1];
  1549. u32 l5_cid;
  1550. int ret = 0;
  1551. if (num < 2) {
  1552. *work = num;
  1553. return -EINVAL;
  1554. }
  1555. req1 = (struct iscsi_kwqe_conn_offload1 *) wqes[0];
  1556. req2 = (struct iscsi_kwqe_conn_offload2 *) wqes[1];
  1557. if ((num - 2) < req2->num_additional_wqes) {
  1558. *work = num;
  1559. return -EINVAL;
  1560. }
  1561. *work = 2 + req2->num_additional_wqes;
  1562. l5_cid = req1->iscsi_conn_id;
  1563. if (l5_cid >= MAX_ISCSI_TBL_SZ)
  1564. return -EINVAL;
  1565. memset(&kcqe, 0, sizeof(kcqe));
  1566. kcqe.op_code = ISCSI_KCQE_OPCODE_OFFLOAD_CONN;
  1567. kcqe.iscsi_conn_id = l5_cid;
  1568. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE;
  1569. ctx = &cp->ctx_tbl[l5_cid];
  1570. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags)) {
  1571. kcqe.completion_status =
  1572. ISCSI_KCQE_COMPLETION_STATUS_CID_BUSY;
  1573. goto done;
  1574. }
  1575. if (atomic_inc_return(&cp->iscsi_conn) > dev->max_iscsi_conn) {
  1576. atomic_dec(&cp->iscsi_conn);
  1577. goto done;
  1578. }
  1579. ret = cnic_alloc_bnx2x_conn_resc(dev, l5_cid);
  1580. if (ret) {
  1581. atomic_dec(&cp->iscsi_conn);
  1582. ret = 0;
  1583. goto done;
  1584. }
  1585. ret = cnic_setup_bnx2x_ctx(dev, wqes, num);
  1586. if (ret < 0) {
  1587. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1588. atomic_dec(&cp->iscsi_conn);
  1589. goto done;
  1590. }
  1591. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1592. kcqe.iscsi_conn_context_id = BNX2X_HW_CID(bp, cp->ctx_tbl[l5_cid].cid);
  1593. done:
  1594. cqes[0] = (struct kcqe *) &kcqe;
  1595. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1596. return 0;
  1597. }
  1598. static int cnic_bnx2x_iscsi_update(struct cnic_dev *dev, struct kwqe *kwqe)
  1599. {
  1600. struct cnic_local *cp = dev->cnic_priv;
  1601. struct iscsi_kwqe_conn_update *req =
  1602. (struct iscsi_kwqe_conn_update *) kwqe;
  1603. void *data;
  1604. union l5cm_specific_data l5_data;
  1605. u32 l5_cid, cid = BNX2X_SW_CID(req->context_id);
  1606. int ret;
  1607. if (cnic_get_l5_cid(cp, cid, &l5_cid) != 0)
  1608. return -EINVAL;
  1609. data = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1610. if (!data)
  1611. return -ENOMEM;
  1612. memcpy(data, kwqe, sizeof(struct kwqe));
  1613. ret = cnic_submit_kwqe_16(dev, ISCSI_RAMROD_CMD_ID_UPDATE_CONN,
  1614. req->context_id, ISCSI_CONNECTION_TYPE, &l5_data);
  1615. return ret;
  1616. }
  1617. static int cnic_bnx2x_destroy_ramrod(struct cnic_dev *dev, u32 l5_cid)
  1618. {
  1619. struct cnic_local *cp = dev->cnic_priv;
  1620. struct bnx2x *bp = netdev_priv(dev->netdev);
  1621. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1622. union l5cm_specific_data l5_data;
  1623. int ret;
  1624. u32 hw_cid;
  1625. init_waitqueue_head(&ctx->waitq);
  1626. ctx->wait_cond = 0;
  1627. memset(&l5_data, 0, sizeof(l5_data));
  1628. hw_cid = BNX2X_HW_CID(bp, ctx->cid);
  1629. ret = cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_COMMON_CFC_DEL,
  1630. hw_cid, NONE_CONNECTION_TYPE, &l5_data);
  1631. if (ret == 0) {
  1632. wait_event_timeout(ctx->waitq, ctx->wait_cond, CNIC_RAMROD_TMO);
  1633. if (unlikely(test_bit(CTX_FL_CID_ERROR, &ctx->ctx_flags)))
  1634. return -EBUSY;
  1635. }
  1636. return 0;
  1637. }
  1638. static int cnic_bnx2x_iscsi_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
  1639. {
  1640. struct cnic_local *cp = dev->cnic_priv;
  1641. struct iscsi_kwqe_conn_destroy *req =
  1642. (struct iscsi_kwqe_conn_destroy *) kwqe;
  1643. u32 l5_cid = req->reserved0;
  1644. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1645. int ret = 0;
  1646. struct iscsi_kcqe kcqe;
  1647. struct kcqe *cqes[1];
  1648. if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  1649. goto skip_cfc_delete;
  1650. if (!time_after(jiffies, ctx->timestamp + (2 * HZ))) {
  1651. unsigned long delta = ctx->timestamp + (2 * HZ) - jiffies;
  1652. if (delta > (2 * HZ))
  1653. delta = 0;
  1654. set_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags);
  1655. queue_delayed_work(cnic_wq, &cp->delete_task, delta);
  1656. goto destroy_reply;
  1657. }
  1658. ret = cnic_bnx2x_destroy_ramrod(dev, l5_cid);
  1659. skip_cfc_delete:
  1660. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1661. if (!ret) {
  1662. atomic_dec(&cp->iscsi_conn);
  1663. clear_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  1664. }
  1665. destroy_reply:
  1666. memset(&kcqe, 0, sizeof(kcqe));
  1667. kcqe.op_code = ISCSI_KCQE_OPCODE_DESTROY_CONN;
  1668. kcqe.iscsi_conn_id = l5_cid;
  1669. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1670. kcqe.iscsi_conn_context_id = req->context_id;
  1671. cqes[0] = (struct kcqe *) &kcqe;
  1672. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1673. return 0;
  1674. }
  1675. static void cnic_init_storm_conn_bufs(struct cnic_dev *dev,
  1676. struct l4_kwq_connect_req1 *kwqe1,
  1677. struct l4_kwq_connect_req3 *kwqe3,
  1678. struct l5cm_active_conn_buffer *conn_buf)
  1679. {
  1680. struct l5cm_conn_addr_params *conn_addr = &conn_buf->conn_addr_buf;
  1681. struct l5cm_xstorm_conn_buffer *xstorm_buf =
  1682. &conn_buf->xstorm_conn_buffer;
  1683. struct l5cm_tstorm_conn_buffer *tstorm_buf =
  1684. &conn_buf->tstorm_conn_buffer;
  1685. struct regpair context_addr;
  1686. u32 cid = BNX2X_SW_CID(kwqe1->cid);
  1687. struct in6_addr src_ip, dst_ip;
  1688. int i;
  1689. u32 *addrp;
  1690. addrp = (u32 *) &conn_addr->local_ip_addr;
  1691. for (i = 0; i < 4; i++, addrp++)
  1692. src_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
  1693. addrp = (u32 *) &conn_addr->remote_ip_addr;
  1694. for (i = 0; i < 4; i++, addrp++)
  1695. dst_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
  1696. cnic_get_bnx2x_ctx(dev, cid, 0, &context_addr);
  1697. xstorm_buf->context_addr.hi = context_addr.hi;
  1698. xstorm_buf->context_addr.lo = context_addr.lo;
  1699. xstorm_buf->mss = 0xffff;
  1700. xstorm_buf->rcv_buf = kwqe3->rcv_buf;
  1701. if (kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE)
  1702. xstorm_buf->params |= L5CM_XSTORM_CONN_BUFFER_NAGLE_ENABLE;
  1703. xstorm_buf->pseudo_header_checksum =
  1704. swab16(~csum_ipv6_magic(&src_ip, &dst_ip, 0, IPPROTO_TCP, 0));
  1705. if (kwqe3->ka_timeout) {
  1706. tstorm_buf->ka_enable = 1;
  1707. tstorm_buf->ka_timeout = kwqe3->ka_timeout;
  1708. tstorm_buf->ka_interval = kwqe3->ka_interval;
  1709. tstorm_buf->ka_max_probe_count = kwqe3->ka_max_probe_count;
  1710. }
  1711. tstorm_buf->max_rt_time = 0xffffffff;
  1712. }
  1713. static void cnic_init_bnx2x_mac(struct cnic_dev *dev)
  1714. {
  1715. struct bnx2x *bp = netdev_priv(dev->netdev);
  1716. u32 pfid = bp->pfid;
  1717. u8 *mac = dev->mac_addr;
  1718. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1719. XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(pfid), mac[0]);
  1720. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1721. XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(pfid), mac[1]);
  1722. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1723. XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(pfid), mac[2]);
  1724. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1725. XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(pfid), mac[3]);
  1726. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1727. XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(pfid), mac[4]);
  1728. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1729. XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(pfid), mac[5]);
  1730. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1731. TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfid), mac[5]);
  1732. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1733. TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
  1734. mac[4]);
  1735. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1736. TSTORM_ISCSI_TCP_VARS_MID_LOCAL_MAC_ADDR_OFFSET(pfid), mac[3]);
  1737. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1738. TSTORM_ISCSI_TCP_VARS_MID_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
  1739. mac[2]);
  1740. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1741. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid), mac[1]);
  1742. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1743. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
  1744. mac[0]);
  1745. }
  1746. static int cnic_bnx2x_connect(struct cnic_dev *dev, struct kwqe *wqes[],
  1747. u32 num, int *work)
  1748. {
  1749. struct cnic_local *cp = dev->cnic_priv;
  1750. struct bnx2x *bp = netdev_priv(dev->netdev);
  1751. struct l4_kwq_connect_req1 *kwqe1 =
  1752. (struct l4_kwq_connect_req1 *) wqes[0];
  1753. struct l4_kwq_connect_req3 *kwqe3;
  1754. struct l5cm_active_conn_buffer *conn_buf;
  1755. struct l5cm_conn_addr_params *conn_addr;
  1756. union l5cm_specific_data l5_data;
  1757. u32 l5_cid = kwqe1->pg_cid;
  1758. struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
  1759. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1760. int ret;
  1761. if (num < 2) {
  1762. *work = num;
  1763. return -EINVAL;
  1764. }
  1765. if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6)
  1766. *work = 3;
  1767. else
  1768. *work = 2;
  1769. if (num < *work) {
  1770. *work = num;
  1771. return -EINVAL;
  1772. }
  1773. if (sizeof(*conn_buf) > CNIC_KWQ16_DATA_SIZE) {
  1774. netdev_err(dev->netdev, "conn_buf size too big\n");
  1775. return -ENOMEM;
  1776. }
  1777. conn_buf = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1778. if (!conn_buf)
  1779. return -ENOMEM;
  1780. memset(conn_buf, 0, sizeof(*conn_buf));
  1781. conn_addr = &conn_buf->conn_addr_buf;
  1782. conn_addr->remote_addr_0 = csk->ha[0];
  1783. conn_addr->remote_addr_1 = csk->ha[1];
  1784. conn_addr->remote_addr_2 = csk->ha[2];
  1785. conn_addr->remote_addr_3 = csk->ha[3];
  1786. conn_addr->remote_addr_4 = csk->ha[4];
  1787. conn_addr->remote_addr_5 = csk->ha[5];
  1788. if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6) {
  1789. struct l4_kwq_connect_req2 *kwqe2 =
  1790. (struct l4_kwq_connect_req2 *) wqes[1];
  1791. conn_addr->local_ip_addr.ip_addr_hi_hi = kwqe2->src_ip_v6_4;
  1792. conn_addr->local_ip_addr.ip_addr_hi_lo = kwqe2->src_ip_v6_3;
  1793. conn_addr->local_ip_addr.ip_addr_lo_hi = kwqe2->src_ip_v6_2;
  1794. conn_addr->remote_ip_addr.ip_addr_hi_hi = kwqe2->dst_ip_v6_4;
  1795. conn_addr->remote_ip_addr.ip_addr_hi_lo = kwqe2->dst_ip_v6_3;
  1796. conn_addr->remote_ip_addr.ip_addr_lo_hi = kwqe2->dst_ip_v6_2;
  1797. conn_addr->params |= L5CM_CONN_ADDR_PARAMS_IP_VERSION;
  1798. }
  1799. kwqe3 = (struct l4_kwq_connect_req3 *) wqes[*work - 1];
  1800. conn_addr->local_ip_addr.ip_addr_lo_lo = kwqe1->src_ip;
  1801. conn_addr->remote_ip_addr.ip_addr_lo_lo = kwqe1->dst_ip;
  1802. conn_addr->local_tcp_port = kwqe1->src_port;
  1803. conn_addr->remote_tcp_port = kwqe1->dst_port;
  1804. conn_addr->pmtu = kwqe3->pmtu;
  1805. cnic_init_storm_conn_bufs(dev, kwqe1, kwqe3, conn_buf);
  1806. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  1807. XSTORM_ISCSI_LOCAL_VLAN_OFFSET(bp->pfid), csk->vlan_id);
  1808. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_TCP_CONNECT,
  1809. kwqe1->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1810. if (!ret)
  1811. set_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  1812. return ret;
  1813. }
  1814. static int cnic_bnx2x_close(struct cnic_dev *dev, struct kwqe *kwqe)
  1815. {
  1816. struct l4_kwq_close_req *req = (struct l4_kwq_close_req *) kwqe;
  1817. union l5cm_specific_data l5_data;
  1818. int ret;
  1819. memset(&l5_data, 0, sizeof(l5_data));
  1820. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_CLOSE,
  1821. req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1822. return ret;
  1823. }
  1824. static int cnic_bnx2x_reset(struct cnic_dev *dev, struct kwqe *kwqe)
  1825. {
  1826. struct l4_kwq_reset_req *req = (struct l4_kwq_reset_req *) kwqe;
  1827. union l5cm_specific_data l5_data;
  1828. int ret;
  1829. memset(&l5_data, 0, sizeof(l5_data));
  1830. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_ABORT,
  1831. req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1832. return ret;
  1833. }
  1834. static int cnic_bnx2x_offload_pg(struct cnic_dev *dev, struct kwqe *kwqe)
  1835. {
  1836. struct l4_kwq_offload_pg *req = (struct l4_kwq_offload_pg *) kwqe;
  1837. struct l4_kcq kcqe;
  1838. struct kcqe *cqes[1];
  1839. memset(&kcqe, 0, sizeof(kcqe));
  1840. kcqe.pg_host_opaque = req->host_opaque;
  1841. kcqe.pg_cid = req->host_opaque;
  1842. kcqe.op_code = L4_KCQE_OPCODE_VALUE_OFFLOAD_PG;
  1843. cqes[0] = (struct kcqe *) &kcqe;
  1844. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
  1845. return 0;
  1846. }
  1847. static int cnic_bnx2x_update_pg(struct cnic_dev *dev, struct kwqe *kwqe)
  1848. {
  1849. struct l4_kwq_update_pg *req = (struct l4_kwq_update_pg *) kwqe;
  1850. struct l4_kcq kcqe;
  1851. struct kcqe *cqes[1];
  1852. memset(&kcqe, 0, sizeof(kcqe));
  1853. kcqe.pg_host_opaque = req->pg_host_opaque;
  1854. kcqe.pg_cid = req->pg_cid;
  1855. kcqe.op_code = L4_KCQE_OPCODE_VALUE_UPDATE_PG;
  1856. cqes[0] = (struct kcqe *) &kcqe;
  1857. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
  1858. return 0;
  1859. }
  1860. static int cnic_bnx2x_fcoe_stat(struct cnic_dev *dev, struct kwqe *kwqe)
  1861. {
  1862. struct fcoe_kwqe_stat *req;
  1863. struct fcoe_stat_ramrod_params *fcoe_stat;
  1864. union l5cm_specific_data l5_data;
  1865. struct cnic_local *cp = dev->cnic_priv;
  1866. struct bnx2x *bp = netdev_priv(dev->netdev);
  1867. int ret;
  1868. u32 cid;
  1869. req = (struct fcoe_kwqe_stat *) kwqe;
  1870. cid = BNX2X_HW_CID(bp, cp->fcoe_init_cid);
  1871. fcoe_stat = cnic_get_kwqe_16_data(cp, BNX2X_FCOE_L5_CID_BASE, &l5_data);
  1872. if (!fcoe_stat)
  1873. return -ENOMEM;
  1874. memset(fcoe_stat, 0, sizeof(*fcoe_stat));
  1875. memcpy(&fcoe_stat->stat_kwqe, req, sizeof(*req));
  1876. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_STAT_FUNC, cid,
  1877. FCOE_CONNECTION_TYPE, &l5_data);
  1878. return ret;
  1879. }
  1880. static int cnic_bnx2x_fcoe_init1(struct cnic_dev *dev, struct kwqe *wqes[],
  1881. u32 num, int *work)
  1882. {
  1883. int ret;
  1884. struct cnic_local *cp = dev->cnic_priv;
  1885. struct bnx2x *bp = netdev_priv(dev->netdev);
  1886. u32 cid;
  1887. struct fcoe_init_ramrod_params *fcoe_init;
  1888. struct fcoe_kwqe_init1 *req1;
  1889. struct fcoe_kwqe_init2 *req2;
  1890. struct fcoe_kwqe_init3 *req3;
  1891. union l5cm_specific_data l5_data;
  1892. if (num < 3) {
  1893. *work = num;
  1894. return -EINVAL;
  1895. }
  1896. req1 = (struct fcoe_kwqe_init1 *) wqes[0];
  1897. req2 = (struct fcoe_kwqe_init2 *) wqes[1];
  1898. req3 = (struct fcoe_kwqe_init3 *) wqes[2];
  1899. if (req2->hdr.op_code != FCOE_KWQE_OPCODE_INIT2) {
  1900. *work = 1;
  1901. return -EINVAL;
  1902. }
  1903. if (req3->hdr.op_code != FCOE_KWQE_OPCODE_INIT3) {
  1904. *work = 2;
  1905. return -EINVAL;
  1906. }
  1907. if (sizeof(*fcoe_init) > CNIC_KWQ16_DATA_SIZE) {
  1908. netdev_err(dev->netdev, "fcoe_init size too big\n");
  1909. return -ENOMEM;
  1910. }
  1911. fcoe_init = cnic_get_kwqe_16_data(cp, BNX2X_FCOE_L5_CID_BASE, &l5_data);
  1912. if (!fcoe_init)
  1913. return -ENOMEM;
  1914. memset(fcoe_init, 0, sizeof(*fcoe_init));
  1915. memcpy(&fcoe_init->init_kwqe1, req1, sizeof(*req1));
  1916. memcpy(&fcoe_init->init_kwqe2, req2, sizeof(*req2));
  1917. memcpy(&fcoe_init->init_kwqe3, req3, sizeof(*req3));
  1918. fcoe_init->eq_pbl_base.lo = cp->kcq2.dma.pgtbl_map & 0xffffffff;
  1919. fcoe_init->eq_pbl_base.hi = (u64) cp->kcq2.dma.pgtbl_map >> 32;
  1920. fcoe_init->eq_pbl_size = cp->kcq2.dma.num_pages;
  1921. fcoe_init->sb_num = cp->status_blk_num;
  1922. fcoe_init->eq_prod = MAX_KCQ_IDX;
  1923. fcoe_init->sb_id = HC_INDEX_FCOE_EQ_CONS;
  1924. cp->kcq2.sw_prod_idx = 0;
  1925. cid = BNX2X_HW_CID(bp, cp->fcoe_init_cid);
  1926. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_INIT_FUNC, cid,
  1927. FCOE_CONNECTION_TYPE, &l5_data);
  1928. *work = 3;
  1929. return ret;
  1930. }
  1931. static int cnic_bnx2x_fcoe_ofld1(struct cnic_dev *dev, struct kwqe *wqes[],
  1932. u32 num, int *work)
  1933. {
  1934. int ret = 0;
  1935. u32 cid = -1, l5_cid;
  1936. struct cnic_local *cp = dev->cnic_priv;
  1937. struct bnx2x *bp = netdev_priv(dev->netdev);
  1938. struct fcoe_kwqe_conn_offload1 *req1;
  1939. struct fcoe_kwqe_conn_offload2 *req2;
  1940. struct fcoe_kwqe_conn_offload3 *req3;
  1941. struct fcoe_kwqe_conn_offload4 *req4;
  1942. struct fcoe_conn_offload_ramrod_params *fcoe_offload;
  1943. struct cnic_context *ctx;
  1944. struct fcoe_context *fctx;
  1945. struct regpair ctx_addr;
  1946. union l5cm_specific_data l5_data;
  1947. struct fcoe_kcqe kcqe;
  1948. struct kcqe *cqes[1];
  1949. if (num < 4) {
  1950. *work = num;
  1951. return -EINVAL;
  1952. }
  1953. req1 = (struct fcoe_kwqe_conn_offload1 *) wqes[0];
  1954. req2 = (struct fcoe_kwqe_conn_offload2 *) wqes[1];
  1955. req3 = (struct fcoe_kwqe_conn_offload3 *) wqes[2];
  1956. req4 = (struct fcoe_kwqe_conn_offload4 *) wqes[3];
  1957. *work = 4;
  1958. l5_cid = req1->fcoe_conn_id;
  1959. if (l5_cid >= dev->max_fcoe_conn)
  1960. goto err_reply;
  1961. l5_cid += BNX2X_FCOE_L5_CID_BASE;
  1962. ctx = &cp->ctx_tbl[l5_cid];
  1963. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  1964. goto err_reply;
  1965. ret = cnic_alloc_bnx2x_conn_resc(dev, l5_cid);
  1966. if (ret) {
  1967. ret = 0;
  1968. goto err_reply;
  1969. }
  1970. cid = ctx->cid;
  1971. fctx = cnic_get_bnx2x_ctx(dev, cid, 1, &ctx_addr);
  1972. if (fctx) {
  1973. u32 hw_cid = BNX2X_HW_CID(bp, cid);
  1974. u32 val;
  1975. val = CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_XCM_AG,
  1976. FCOE_CONNECTION_TYPE);
  1977. fctx->xstorm_ag_context.cdu_reserved = val;
  1978. val = CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_UCM_AG,
  1979. FCOE_CONNECTION_TYPE);
  1980. fctx->ustorm_ag_context.cdu_usage = val;
  1981. }
  1982. if (sizeof(*fcoe_offload) > CNIC_KWQ16_DATA_SIZE) {
  1983. netdev_err(dev->netdev, "fcoe_offload size too big\n");
  1984. goto err_reply;
  1985. }
  1986. fcoe_offload = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1987. if (!fcoe_offload)
  1988. goto err_reply;
  1989. memset(fcoe_offload, 0, sizeof(*fcoe_offload));
  1990. memcpy(&fcoe_offload->offload_kwqe1, req1, sizeof(*req1));
  1991. memcpy(&fcoe_offload->offload_kwqe2, req2, sizeof(*req2));
  1992. memcpy(&fcoe_offload->offload_kwqe3, req3, sizeof(*req3));
  1993. memcpy(&fcoe_offload->offload_kwqe4, req4, sizeof(*req4));
  1994. cid = BNX2X_HW_CID(bp, cid);
  1995. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_OFFLOAD_CONN, cid,
  1996. FCOE_CONNECTION_TYPE, &l5_data);
  1997. if (!ret)
  1998. set_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  1999. return ret;
  2000. err_reply:
  2001. if (cid != -1)
  2002. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  2003. memset(&kcqe, 0, sizeof(kcqe));
  2004. kcqe.op_code = FCOE_KCQE_OPCODE_OFFLOAD_CONN;
  2005. kcqe.fcoe_conn_id = req1->fcoe_conn_id;
  2006. kcqe.completion_status = FCOE_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE;
  2007. cqes[0] = (struct kcqe *) &kcqe;
  2008. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_FCOE, cqes, 1);
  2009. return ret;
  2010. }
  2011. static int cnic_bnx2x_fcoe_enable(struct cnic_dev *dev, struct kwqe *kwqe)
  2012. {
  2013. struct fcoe_kwqe_conn_enable_disable *req;
  2014. struct fcoe_conn_enable_disable_ramrod_params *fcoe_enable;
  2015. union l5cm_specific_data l5_data;
  2016. int ret;
  2017. u32 cid, l5_cid;
  2018. struct cnic_local *cp = dev->cnic_priv;
  2019. req = (struct fcoe_kwqe_conn_enable_disable *) kwqe;
  2020. cid = req->context_id;
  2021. l5_cid = req->conn_id + BNX2X_FCOE_L5_CID_BASE;
  2022. if (sizeof(*fcoe_enable) > CNIC_KWQ16_DATA_SIZE) {
  2023. netdev_err(dev->netdev, "fcoe_enable size too big\n");
  2024. return -ENOMEM;
  2025. }
  2026. fcoe_enable = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  2027. if (!fcoe_enable)
  2028. return -ENOMEM;
  2029. memset(fcoe_enable, 0, sizeof(*fcoe_enable));
  2030. memcpy(&fcoe_enable->enable_disable_kwqe, req, sizeof(*req));
  2031. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_ENABLE_CONN, cid,
  2032. FCOE_CONNECTION_TYPE, &l5_data);
  2033. return ret;
  2034. }
  2035. static int cnic_bnx2x_fcoe_disable(struct cnic_dev *dev, struct kwqe *kwqe)
  2036. {
  2037. struct fcoe_kwqe_conn_enable_disable *req;
  2038. struct fcoe_conn_enable_disable_ramrod_params *fcoe_disable;
  2039. union l5cm_specific_data l5_data;
  2040. int ret;
  2041. u32 cid, l5_cid;
  2042. struct cnic_local *cp = dev->cnic_priv;
  2043. req = (struct fcoe_kwqe_conn_enable_disable *) kwqe;
  2044. cid = req->context_id;
  2045. l5_cid = req->conn_id;
  2046. if (l5_cid >= dev->max_fcoe_conn)
  2047. return -EINVAL;
  2048. l5_cid += BNX2X_FCOE_L5_CID_BASE;
  2049. if (sizeof(*fcoe_disable) > CNIC_KWQ16_DATA_SIZE) {
  2050. netdev_err(dev->netdev, "fcoe_disable size too big\n");
  2051. return -ENOMEM;
  2052. }
  2053. fcoe_disable = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  2054. if (!fcoe_disable)
  2055. return -ENOMEM;
  2056. memset(fcoe_disable, 0, sizeof(*fcoe_disable));
  2057. memcpy(&fcoe_disable->enable_disable_kwqe, req, sizeof(*req));
  2058. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_DISABLE_CONN, cid,
  2059. FCOE_CONNECTION_TYPE, &l5_data);
  2060. return ret;
  2061. }
  2062. static int cnic_bnx2x_fcoe_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
  2063. {
  2064. struct fcoe_kwqe_conn_destroy *req;
  2065. union l5cm_specific_data l5_data;
  2066. int ret;
  2067. u32 cid, l5_cid;
  2068. struct cnic_local *cp = dev->cnic_priv;
  2069. struct cnic_context *ctx;
  2070. struct fcoe_kcqe kcqe;
  2071. struct kcqe *cqes[1];
  2072. req = (struct fcoe_kwqe_conn_destroy *) kwqe;
  2073. cid = req->context_id;
  2074. l5_cid = req->conn_id;
  2075. if (l5_cid >= dev->max_fcoe_conn)
  2076. return -EINVAL;
  2077. l5_cid += BNX2X_FCOE_L5_CID_BASE;
  2078. ctx = &cp->ctx_tbl[l5_cid];
  2079. init_waitqueue_head(&ctx->waitq);
  2080. ctx->wait_cond = 0;
  2081. memset(&kcqe, 0, sizeof(kcqe));
  2082. kcqe.completion_status = FCOE_KCQE_COMPLETION_STATUS_ERROR;
  2083. memset(&l5_data, 0, sizeof(l5_data));
  2084. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_TERMINATE_CONN, cid,
  2085. FCOE_CONNECTION_TYPE, &l5_data);
  2086. if (ret == 0) {
  2087. wait_event_timeout(ctx->waitq, ctx->wait_cond, CNIC_RAMROD_TMO);
  2088. if (ctx->wait_cond)
  2089. kcqe.completion_status = 0;
  2090. }
  2091. set_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags);
  2092. queue_delayed_work(cnic_wq, &cp->delete_task, msecs_to_jiffies(2000));
  2093. kcqe.op_code = FCOE_KCQE_OPCODE_DESTROY_CONN;
  2094. kcqe.fcoe_conn_id = req->conn_id;
  2095. kcqe.fcoe_conn_context_id = cid;
  2096. cqes[0] = (struct kcqe *) &kcqe;
  2097. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_FCOE, cqes, 1);
  2098. return ret;
  2099. }
  2100. static void cnic_bnx2x_delete_wait(struct cnic_dev *dev, u32 start_cid)
  2101. {
  2102. struct cnic_local *cp = dev->cnic_priv;
  2103. u32 i;
  2104. for (i = start_cid; i < cp->max_cid_space; i++) {
  2105. struct cnic_context *ctx = &cp->ctx_tbl[i];
  2106. int j;
  2107. while (test_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
  2108. msleep(10);
  2109. for (j = 0; j < 5; j++) {
  2110. if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  2111. break;
  2112. msleep(20);
  2113. }
  2114. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  2115. netdev_warn(dev->netdev, "CID %x not deleted\n",
  2116. ctx->cid);
  2117. }
  2118. }
  2119. static int cnic_bnx2x_fcoe_fw_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
  2120. {
  2121. struct fcoe_kwqe_destroy *req;
  2122. union l5cm_specific_data l5_data;
  2123. struct cnic_local *cp = dev->cnic_priv;
  2124. struct bnx2x *bp = netdev_priv(dev->netdev);
  2125. int ret;
  2126. u32 cid;
  2127. cnic_bnx2x_delete_wait(dev, MAX_ISCSI_TBL_SZ);
  2128. req = (struct fcoe_kwqe_destroy *) kwqe;
  2129. cid = BNX2X_HW_CID(bp, cp->fcoe_init_cid);
  2130. memset(&l5_data, 0, sizeof(l5_data));
  2131. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_DESTROY_FUNC, cid,
  2132. FCOE_CONNECTION_TYPE, &l5_data);
  2133. return ret;
  2134. }
  2135. static void cnic_bnx2x_kwqe_err(struct cnic_dev *dev, struct kwqe *kwqe)
  2136. {
  2137. struct cnic_local *cp = dev->cnic_priv;
  2138. struct kcqe kcqe;
  2139. struct kcqe *cqes[1];
  2140. u32 cid;
  2141. u32 opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
  2142. u32 layer_code = kwqe->kwqe_op_flag & KWQE_LAYER_MASK;
  2143. u32 kcqe_op;
  2144. int ulp_type;
  2145. cid = kwqe->kwqe_info0;
  2146. memset(&kcqe, 0, sizeof(kcqe));
  2147. if (layer_code == KWQE_FLAGS_LAYER_MASK_L5_FCOE) {
  2148. u32 l5_cid = 0;
  2149. ulp_type = CNIC_ULP_FCOE;
  2150. if (opcode == FCOE_KWQE_OPCODE_DISABLE_CONN) {
  2151. struct fcoe_kwqe_conn_enable_disable *req;
  2152. req = (struct fcoe_kwqe_conn_enable_disable *) kwqe;
  2153. kcqe_op = FCOE_KCQE_OPCODE_DISABLE_CONN;
  2154. cid = req->context_id;
  2155. l5_cid = req->conn_id;
  2156. } else if (opcode == FCOE_KWQE_OPCODE_DESTROY) {
  2157. kcqe_op = FCOE_KCQE_OPCODE_DESTROY_FUNC;
  2158. } else {
  2159. return;
  2160. }
  2161. kcqe.kcqe_op_flag = kcqe_op << KCQE_FLAGS_OPCODE_SHIFT;
  2162. kcqe.kcqe_op_flag |= KCQE_FLAGS_LAYER_MASK_L5_FCOE;
  2163. kcqe.kcqe_info1 = FCOE_KCQE_COMPLETION_STATUS_PARITY_ERROR;
  2164. kcqe.kcqe_info2 = cid;
  2165. kcqe.kcqe_info0 = l5_cid;
  2166. } else if (layer_code == KWQE_FLAGS_LAYER_MASK_L5_ISCSI) {
  2167. ulp_type = CNIC_ULP_ISCSI;
  2168. if (opcode == ISCSI_KWQE_OPCODE_UPDATE_CONN)
  2169. cid = kwqe->kwqe_info1;
  2170. kcqe.kcqe_op_flag = (opcode + 0x10) << KCQE_FLAGS_OPCODE_SHIFT;
  2171. kcqe.kcqe_op_flag |= KCQE_FLAGS_LAYER_MASK_L5_ISCSI;
  2172. kcqe.kcqe_info1 = ISCSI_KCQE_COMPLETION_STATUS_PARITY_ERR;
  2173. kcqe.kcqe_info2 = cid;
  2174. cnic_get_l5_cid(cp, BNX2X_SW_CID(cid), &kcqe.kcqe_info0);
  2175. } else if (layer_code == KWQE_FLAGS_LAYER_MASK_L4) {
  2176. struct l4_kcq *l4kcqe = (struct l4_kcq *) &kcqe;
  2177. ulp_type = CNIC_ULP_L4;
  2178. if (opcode == L4_KWQE_OPCODE_VALUE_CONNECT1)
  2179. kcqe_op = L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE;
  2180. else if (opcode == L4_KWQE_OPCODE_VALUE_RESET)
  2181. kcqe_op = L4_KCQE_OPCODE_VALUE_RESET_COMP;
  2182. else if (opcode == L4_KWQE_OPCODE_VALUE_CLOSE)
  2183. kcqe_op = L4_KCQE_OPCODE_VALUE_CLOSE_COMP;
  2184. else
  2185. return;
  2186. kcqe.kcqe_op_flag = (kcqe_op << KCQE_FLAGS_OPCODE_SHIFT) |
  2187. KCQE_FLAGS_LAYER_MASK_L4;
  2188. l4kcqe->status = L4_KCQE_COMPLETION_STATUS_PARITY_ERROR;
  2189. l4kcqe->cid = cid;
  2190. cnic_get_l5_cid(cp, BNX2X_SW_CID(cid), &l4kcqe->conn_id);
  2191. } else {
  2192. return;
  2193. }
  2194. cqes[0] = &kcqe;
  2195. cnic_reply_bnx2x_kcqes(dev, ulp_type, cqes, 1);
  2196. }
  2197. static int cnic_submit_bnx2x_iscsi_kwqes(struct cnic_dev *dev,
  2198. struct kwqe *wqes[], u32 num_wqes)
  2199. {
  2200. int i, work, ret;
  2201. u32 opcode;
  2202. struct kwqe *kwqe;
  2203. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  2204. return -EAGAIN; /* bnx2 is down */
  2205. for (i = 0; i < num_wqes; ) {
  2206. kwqe = wqes[i];
  2207. opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
  2208. work = 1;
  2209. switch (opcode) {
  2210. case ISCSI_KWQE_OPCODE_INIT1:
  2211. ret = cnic_bnx2x_iscsi_init1(dev, kwqe);
  2212. break;
  2213. case ISCSI_KWQE_OPCODE_INIT2:
  2214. ret = cnic_bnx2x_iscsi_init2(dev, kwqe);
  2215. break;
  2216. case ISCSI_KWQE_OPCODE_OFFLOAD_CONN1:
  2217. ret = cnic_bnx2x_iscsi_ofld1(dev, &wqes[i],
  2218. num_wqes - i, &work);
  2219. break;
  2220. case ISCSI_KWQE_OPCODE_UPDATE_CONN:
  2221. ret = cnic_bnx2x_iscsi_update(dev, kwqe);
  2222. break;
  2223. case ISCSI_KWQE_OPCODE_DESTROY_CONN:
  2224. ret = cnic_bnx2x_iscsi_destroy(dev, kwqe);
  2225. break;
  2226. case L4_KWQE_OPCODE_VALUE_CONNECT1:
  2227. ret = cnic_bnx2x_connect(dev, &wqes[i], num_wqes - i,
  2228. &work);
  2229. break;
  2230. case L4_KWQE_OPCODE_VALUE_CLOSE:
  2231. ret = cnic_bnx2x_close(dev, kwqe);
  2232. break;
  2233. case L4_KWQE_OPCODE_VALUE_RESET:
  2234. ret = cnic_bnx2x_reset(dev, kwqe);
  2235. break;
  2236. case L4_KWQE_OPCODE_VALUE_OFFLOAD_PG:
  2237. ret = cnic_bnx2x_offload_pg(dev, kwqe);
  2238. break;
  2239. case L4_KWQE_OPCODE_VALUE_UPDATE_PG:
  2240. ret = cnic_bnx2x_update_pg(dev, kwqe);
  2241. break;
  2242. case L4_KWQE_OPCODE_VALUE_UPLOAD_PG:
  2243. ret = 0;
  2244. break;
  2245. default:
  2246. ret = 0;
  2247. netdev_err(dev->netdev, "Unknown type of KWQE(0x%x)\n",
  2248. opcode);
  2249. break;
  2250. }
  2251. if (ret < 0) {
  2252. netdev_err(dev->netdev, "KWQE(0x%x) failed\n",
  2253. opcode);
  2254. /* Possibly bnx2x parity error, send completion
  2255. * to ulp drivers with error code to speed up
  2256. * cleanup and reset recovery.
  2257. */
  2258. if (ret == -EIO || ret == -EAGAIN)
  2259. cnic_bnx2x_kwqe_err(dev, kwqe);
  2260. }
  2261. i += work;
  2262. }
  2263. return 0;
  2264. }
  2265. static int cnic_submit_bnx2x_fcoe_kwqes(struct cnic_dev *dev,
  2266. struct kwqe *wqes[], u32 num_wqes)
  2267. {
  2268. struct bnx2x *bp = netdev_priv(dev->netdev);
  2269. int i, work, ret;
  2270. u32 opcode;
  2271. struct kwqe *kwqe;
  2272. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  2273. return -EAGAIN; /* bnx2 is down */
  2274. if (!BNX2X_CHIP_IS_E2_PLUS(bp))
  2275. return -EINVAL;
  2276. for (i = 0; i < num_wqes; ) {
  2277. kwqe = wqes[i];
  2278. opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
  2279. work = 1;
  2280. switch (opcode) {
  2281. case FCOE_KWQE_OPCODE_INIT1:
  2282. ret = cnic_bnx2x_fcoe_init1(dev, &wqes[i],
  2283. num_wqes - i, &work);
  2284. break;
  2285. case FCOE_KWQE_OPCODE_OFFLOAD_CONN1:
  2286. ret = cnic_bnx2x_fcoe_ofld1(dev, &wqes[i],
  2287. num_wqes - i, &work);
  2288. break;
  2289. case FCOE_KWQE_OPCODE_ENABLE_CONN:
  2290. ret = cnic_bnx2x_fcoe_enable(dev, kwqe);
  2291. break;
  2292. case FCOE_KWQE_OPCODE_DISABLE_CONN:
  2293. ret = cnic_bnx2x_fcoe_disable(dev, kwqe);
  2294. break;
  2295. case FCOE_KWQE_OPCODE_DESTROY_CONN:
  2296. ret = cnic_bnx2x_fcoe_destroy(dev, kwqe);
  2297. break;
  2298. case FCOE_KWQE_OPCODE_DESTROY:
  2299. ret = cnic_bnx2x_fcoe_fw_destroy(dev, kwqe);
  2300. break;
  2301. case FCOE_KWQE_OPCODE_STAT:
  2302. ret = cnic_bnx2x_fcoe_stat(dev, kwqe);
  2303. break;
  2304. default:
  2305. ret = 0;
  2306. netdev_err(dev->netdev, "Unknown type of KWQE(0x%x)\n",
  2307. opcode);
  2308. break;
  2309. }
  2310. if (ret < 0) {
  2311. netdev_err(dev->netdev, "KWQE(0x%x) failed\n",
  2312. opcode);
  2313. /* Possibly bnx2x parity error, send completion
  2314. * to ulp drivers with error code to speed up
  2315. * cleanup and reset recovery.
  2316. */
  2317. if (ret == -EIO || ret == -EAGAIN)
  2318. cnic_bnx2x_kwqe_err(dev, kwqe);
  2319. }
  2320. i += work;
  2321. }
  2322. return 0;
  2323. }
  2324. static int cnic_submit_bnx2x_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
  2325. u32 num_wqes)
  2326. {
  2327. int ret = -EINVAL;
  2328. u32 layer_code;
  2329. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  2330. return -EAGAIN; /* bnx2x is down */
  2331. if (!num_wqes)
  2332. return 0;
  2333. layer_code = wqes[0]->kwqe_op_flag & KWQE_LAYER_MASK;
  2334. switch (layer_code) {
  2335. case KWQE_FLAGS_LAYER_MASK_L5_ISCSI:
  2336. case KWQE_FLAGS_LAYER_MASK_L4:
  2337. case KWQE_FLAGS_LAYER_MASK_L2:
  2338. ret = cnic_submit_bnx2x_iscsi_kwqes(dev, wqes, num_wqes);
  2339. break;
  2340. case KWQE_FLAGS_LAYER_MASK_L5_FCOE:
  2341. ret = cnic_submit_bnx2x_fcoe_kwqes(dev, wqes, num_wqes);
  2342. break;
  2343. }
  2344. return ret;
  2345. }
  2346. static inline u32 cnic_get_kcqe_layer_mask(u32 opflag)
  2347. {
  2348. if (unlikely(KCQE_OPCODE(opflag) == FCOE_RAMROD_CMD_ID_TERMINATE_CONN))
  2349. return KCQE_FLAGS_LAYER_MASK_L4;
  2350. return opflag & KCQE_FLAGS_LAYER_MASK;
  2351. }
  2352. static void service_kcqes(struct cnic_dev *dev, int num_cqes)
  2353. {
  2354. struct cnic_local *cp = dev->cnic_priv;
  2355. int i, j, comp = 0;
  2356. i = 0;
  2357. j = 1;
  2358. while (num_cqes) {
  2359. struct cnic_ulp_ops *ulp_ops;
  2360. int ulp_type;
  2361. u32 kcqe_op_flag = cp->completed_kcq[i]->kcqe_op_flag;
  2362. u32 kcqe_layer = cnic_get_kcqe_layer_mask(kcqe_op_flag);
  2363. if (unlikely(kcqe_op_flag & KCQE_RAMROD_COMPLETION))
  2364. comp++;
  2365. while (j < num_cqes) {
  2366. u32 next_op = cp->completed_kcq[i + j]->kcqe_op_flag;
  2367. if (cnic_get_kcqe_layer_mask(next_op) != kcqe_layer)
  2368. break;
  2369. if (unlikely(next_op & KCQE_RAMROD_COMPLETION))
  2370. comp++;
  2371. j++;
  2372. }
  2373. if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_RDMA)
  2374. ulp_type = CNIC_ULP_RDMA;
  2375. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_ISCSI)
  2376. ulp_type = CNIC_ULP_ISCSI;
  2377. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_FCOE)
  2378. ulp_type = CNIC_ULP_FCOE;
  2379. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L4)
  2380. ulp_type = CNIC_ULP_L4;
  2381. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L2)
  2382. goto end;
  2383. else {
  2384. netdev_err(dev->netdev, "Unknown type of KCQE(0x%x)\n",
  2385. kcqe_op_flag);
  2386. goto end;
  2387. }
  2388. rcu_read_lock();
  2389. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  2390. if (likely(ulp_ops)) {
  2391. ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
  2392. cp->completed_kcq + i, j);
  2393. }
  2394. rcu_read_unlock();
  2395. end:
  2396. num_cqes -= j;
  2397. i += j;
  2398. j = 1;
  2399. }
  2400. if (unlikely(comp))
  2401. cnic_spq_completion(dev, DRV_CTL_RET_L5_SPQ_CREDIT_CMD, comp);
  2402. }
  2403. static int cnic_get_kcqes(struct cnic_dev *dev, struct kcq_info *info)
  2404. {
  2405. struct cnic_local *cp = dev->cnic_priv;
  2406. u16 i, ri, hw_prod, last;
  2407. struct kcqe *kcqe;
  2408. int kcqe_cnt = 0, last_cnt = 0;
  2409. i = ri = last = info->sw_prod_idx;
  2410. ri &= MAX_KCQ_IDX;
  2411. hw_prod = *info->hw_prod_idx_ptr;
  2412. hw_prod = info->hw_idx(hw_prod);
  2413. while ((i != hw_prod) && (kcqe_cnt < MAX_COMPLETED_KCQE)) {
  2414. kcqe = &info->kcq[KCQ_PG(ri)][KCQ_IDX(ri)];
  2415. cp->completed_kcq[kcqe_cnt++] = kcqe;
  2416. i = info->next_idx(i);
  2417. ri = i & MAX_KCQ_IDX;
  2418. if (likely(!(kcqe->kcqe_op_flag & KCQE_FLAGS_NEXT))) {
  2419. last_cnt = kcqe_cnt;
  2420. last = i;
  2421. }
  2422. }
  2423. info->sw_prod_idx = last;
  2424. return last_cnt;
  2425. }
  2426. static int cnic_l2_completion(struct cnic_local *cp)
  2427. {
  2428. u16 hw_cons, sw_cons;
  2429. struct cnic_uio_dev *udev = cp->udev;
  2430. union eth_rx_cqe *cqe, *cqe_ring = (union eth_rx_cqe *)
  2431. (udev->l2_ring + (2 * CNIC_PAGE_SIZE));
  2432. u32 cmd;
  2433. int comp = 0;
  2434. if (!test_bit(CNIC_F_BNX2X_CLASS, &cp->dev->flags))
  2435. return 0;
  2436. hw_cons = *cp->rx_cons_ptr;
  2437. if ((hw_cons & BNX2X_MAX_RCQ_DESC_CNT) == BNX2X_MAX_RCQ_DESC_CNT)
  2438. hw_cons++;
  2439. sw_cons = cp->rx_cons;
  2440. while (sw_cons != hw_cons) {
  2441. u8 cqe_fp_flags;
  2442. cqe = &cqe_ring[sw_cons & BNX2X_MAX_RCQ_DESC_CNT];
  2443. cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
  2444. if (cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE) {
  2445. cmd = le32_to_cpu(cqe->ramrod_cqe.conn_and_cmd_data);
  2446. cmd >>= COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT;
  2447. if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP ||
  2448. cmd == RAMROD_CMD_ID_ETH_HALT)
  2449. comp++;
  2450. }
  2451. sw_cons = BNX2X_NEXT_RCQE(sw_cons);
  2452. }
  2453. return comp;
  2454. }
  2455. static void cnic_chk_pkt_rings(struct cnic_local *cp)
  2456. {
  2457. u16 rx_cons, tx_cons;
  2458. int comp = 0;
  2459. if (!test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
  2460. return;
  2461. rx_cons = *cp->rx_cons_ptr;
  2462. tx_cons = *cp->tx_cons_ptr;
  2463. if (cp->tx_cons != tx_cons || cp->rx_cons != rx_cons) {
  2464. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  2465. comp = cnic_l2_completion(cp);
  2466. cp->tx_cons = tx_cons;
  2467. cp->rx_cons = rx_cons;
  2468. if (cp->udev)
  2469. uio_event_notify(&cp->udev->cnic_uinfo);
  2470. }
  2471. if (comp)
  2472. clear_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  2473. }
  2474. static u32 cnic_service_bnx2_queues(struct cnic_dev *dev)
  2475. {
  2476. struct cnic_local *cp = dev->cnic_priv;
  2477. u32 status_idx = (u16) *cp->kcq1.status_idx_ptr;
  2478. int kcqe_cnt;
  2479. /* status block index must be read before reading other fields */
  2480. rmb();
  2481. cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
  2482. while ((kcqe_cnt = cnic_get_kcqes(dev, &cp->kcq1))) {
  2483. service_kcqes(dev, kcqe_cnt);
  2484. /* Tell compiler that status_blk fields can change. */
  2485. barrier();
  2486. status_idx = (u16) *cp->kcq1.status_idx_ptr;
  2487. /* status block index must be read first */
  2488. rmb();
  2489. cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
  2490. }
  2491. CNIC_WR16(dev, cp->kcq1.io_addr, cp->kcq1.sw_prod_idx);
  2492. cnic_chk_pkt_rings(cp);
  2493. return status_idx;
  2494. }
  2495. static int cnic_service_bnx2(void *data, void *status_blk)
  2496. {
  2497. struct cnic_dev *dev = data;
  2498. if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags))) {
  2499. struct status_block *sblk = status_blk;
  2500. return sblk->status_idx;
  2501. }
  2502. return cnic_service_bnx2_queues(dev);
  2503. }
  2504. static void cnic_service_bnx2_msix(unsigned long data)
  2505. {
  2506. struct cnic_dev *dev = (struct cnic_dev *) data;
  2507. struct cnic_local *cp = dev->cnic_priv;
  2508. cp->last_status_idx = cnic_service_bnx2_queues(dev);
  2509. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  2510. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
  2511. }
  2512. static void cnic_doirq(struct cnic_dev *dev)
  2513. {
  2514. struct cnic_local *cp = dev->cnic_priv;
  2515. if (likely(test_bit(CNIC_F_CNIC_UP, &dev->flags))) {
  2516. u16 prod = cp->kcq1.sw_prod_idx & MAX_KCQ_IDX;
  2517. prefetch(cp->status_blk.gen);
  2518. prefetch(&cp->kcq1.kcq[KCQ_PG(prod)][KCQ_IDX(prod)]);
  2519. tasklet_schedule(&cp->cnic_irq_task);
  2520. }
  2521. }
  2522. static irqreturn_t cnic_irq(int irq, void *dev_instance)
  2523. {
  2524. struct cnic_dev *dev = dev_instance;
  2525. struct cnic_local *cp = dev->cnic_priv;
  2526. if (cp->ack_int)
  2527. cp->ack_int(dev);
  2528. cnic_doirq(dev);
  2529. return IRQ_HANDLED;
  2530. }
  2531. static inline void cnic_ack_bnx2x_int(struct cnic_dev *dev, u8 id, u8 storm,
  2532. u16 index, u8 op, u8 update)
  2533. {
  2534. struct bnx2x *bp = netdev_priv(dev->netdev);
  2535. u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp) * 32 +
  2536. COMMAND_REG_INT_ACK);
  2537. struct igu_ack_register igu_ack;
  2538. igu_ack.status_block_index = index;
  2539. igu_ack.sb_id_and_flags =
  2540. ((id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
  2541. (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
  2542. (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
  2543. (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
  2544. CNIC_WR(dev, hc_addr, (*(u32 *)&igu_ack));
  2545. }
  2546. static void cnic_ack_igu_sb(struct cnic_dev *dev, u8 igu_sb_id, u8 segment,
  2547. u16 index, u8 op, u8 update)
  2548. {
  2549. struct igu_regular cmd_data;
  2550. u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id) * 8;
  2551. cmd_data.sb_id_and_flags =
  2552. (index << IGU_REGULAR_SB_INDEX_SHIFT) |
  2553. (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) |
  2554. (update << IGU_REGULAR_BUPDATE_SHIFT) |
  2555. (op << IGU_REGULAR_ENABLE_INT_SHIFT);
  2556. CNIC_WR(dev, igu_addr, cmd_data.sb_id_and_flags);
  2557. }
  2558. static void cnic_ack_bnx2x_msix(struct cnic_dev *dev)
  2559. {
  2560. struct cnic_local *cp = dev->cnic_priv;
  2561. cnic_ack_bnx2x_int(dev, cp->bnx2x_igu_sb_id, CSTORM_ID, 0,
  2562. IGU_INT_DISABLE, 0);
  2563. }
  2564. static void cnic_ack_bnx2x_e2_msix(struct cnic_dev *dev)
  2565. {
  2566. struct cnic_local *cp = dev->cnic_priv;
  2567. cnic_ack_igu_sb(dev, cp->bnx2x_igu_sb_id, IGU_SEG_ACCESS_DEF, 0,
  2568. IGU_INT_DISABLE, 0);
  2569. }
  2570. static void cnic_arm_bnx2x_msix(struct cnic_dev *dev, u32 idx)
  2571. {
  2572. struct cnic_local *cp = dev->cnic_priv;
  2573. cnic_ack_bnx2x_int(dev, cp->bnx2x_igu_sb_id, CSTORM_ID, idx,
  2574. IGU_INT_ENABLE, 1);
  2575. }
  2576. static void cnic_arm_bnx2x_e2_msix(struct cnic_dev *dev, u32 idx)
  2577. {
  2578. struct cnic_local *cp = dev->cnic_priv;
  2579. cnic_ack_igu_sb(dev, cp->bnx2x_igu_sb_id, IGU_SEG_ACCESS_DEF, idx,
  2580. IGU_INT_ENABLE, 1);
  2581. }
  2582. static u32 cnic_service_bnx2x_kcq(struct cnic_dev *dev, struct kcq_info *info)
  2583. {
  2584. u32 last_status = *info->status_idx_ptr;
  2585. int kcqe_cnt;
  2586. /* status block index must be read before reading the KCQ */
  2587. rmb();
  2588. while ((kcqe_cnt = cnic_get_kcqes(dev, info))) {
  2589. service_kcqes(dev, kcqe_cnt);
  2590. /* Tell compiler that sblk fields can change. */
  2591. barrier();
  2592. last_status = *info->status_idx_ptr;
  2593. /* status block index must be read before reading the KCQ */
  2594. rmb();
  2595. }
  2596. return last_status;
  2597. }
  2598. static void cnic_service_bnx2x_bh(unsigned long data)
  2599. {
  2600. struct cnic_dev *dev = (struct cnic_dev *) data;
  2601. struct cnic_local *cp = dev->cnic_priv;
  2602. struct bnx2x *bp = netdev_priv(dev->netdev);
  2603. u32 status_idx, new_status_idx;
  2604. if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags)))
  2605. return;
  2606. while (1) {
  2607. status_idx = cnic_service_bnx2x_kcq(dev, &cp->kcq1);
  2608. CNIC_WR16(dev, cp->kcq1.io_addr,
  2609. cp->kcq1.sw_prod_idx + MAX_KCQ_IDX);
  2610. if (!CNIC_SUPPORTS_FCOE(bp)) {
  2611. cp->arm_int(dev, status_idx);
  2612. break;
  2613. }
  2614. new_status_idx = cnic_service_bnx2x_kcq(dev, &cp->kcq2);
  2615. if (new_status_idx != status_idx)
  2616. continue;
  2617. CNIC_WR16(dev, cp->kcq2.io_addr, cp->kcq2.sw_prod_idx +
  2618. MAX_KCQ_IDX);
  2619. cnic_ack_igu_sb(dev, cp->bnx2x_igu_sb_id, IGU_SEG_ACCESS_DEF,
  2620. status_idx, IGU_INT_ENABLE, 1);
  2621. break;
  2622. }
  2623. }
  2624. static int cnic_service_bnx2x(void *data, void *status_blk)
  2625. {
  2626. struct cnic_dev *dev = data;
  2627. struct cnic_local *cp = dev->cnic_priv;
  2628. if (!(cp->ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  2629. cnic_doirq(dev);
  2630. cnic_chk_pkt_rings(cp);
  2631. return 0;
  2632. }
  2633. static void cnic_ulp_stop_one(struct cnic_local *cp, int if_type)
  2634. {
  2635. struct cnic_ulp_ops *ulp_ops;
  2636. if (if_type == CNIC_ULP_ISCSI)
  2637. cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
  2638. mutex_lock(&cnic_lock);
  2639. ulp_ops = rcu_dereference_protected(cp->ulp_ops[if_type],
  2640. lockdep_is_held(&cnic_lock));
  2641. if (!ulp_ops) {
  2642. mutex_unlock(&cnic_lock);
  2643. return;
  2644. }
  2645. set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2646. mutex_unlock(&cnic_lock);
  2647. if (test_and_clear_bit(ULP_F_START, &cp->ulp_flags[if_type]))
  2648. ulp_ops->cnic_stop(cp->ulp_handle[if_type]);
  2649. clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2650. }
  2651. static void cnic_ulp_stop(struct cnic_dev *dev)
  2652. {
  2653. struct cnic_local *cp = dev->cnic_priv;
  2654. int if_type;
  2655. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++)
  2656. cnic_ulp_stop_one(cp, if_type);
  2657. }
  2658. static void cnic_ulp_start(struct cnic_dev *dev)
  2659. {
  2660. struct cnic_local *cp = dev->cnic_priv;
  2661. int if_type;
  2662. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
  2663. struct cnic_ulp_ops *ulp_ops;
  2664. mutex_lock(&cnic_lock);
  2665. ulp_ops = rcu_dereference_protected(cp->ulp_ops[if_type],
  2666. lockdep_is_held(&cnic_lock));
  2667. if (!ulp_ops || !ulp_ops->cnic_start) {
  2668. mutex_unlock(&cnic_lock);
  2669. continue;
  2670. }
  2671. set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2672. mutex_unlock(&cnic_lock);
  2673. if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[if_type]))
  2674. ulp_ops->cnic_start(cp->ulp_handle[if_type]);
  2675. clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2676. }
  2677. }
  2678. static int cnic_copy_ulp_stats(struct cnic_dev *dev, int ulp_type)
  2679. {
  2680. struct cnic_local *cp = dev->cnic_priv;
  2681. struct cnic_ulp_ops *ulp_ops;
  2682. int rc;
  2683. mutex_lock(&cnic_lock);
  2684. ulp_ops = rcu_dereference_protected(cp->ulp_ops[ulp_type],
  2685. lockdep_is_held(&cnic_lock));
  2686. if (ulp_ops && ulp_ops->cnic_get_stats)
  2687. rc = ulp_ops->cnic_get_stats(cp->ulp_handle[ulp_type]);
  2688. else
  2689. rc = -ENODEV;
  2690. mutex_unlock(&cnic_lock);
  2691. return rc;
  2692. }
  2693. static int cnic_ctl(void *data, struct cnic_ctl_info *info)
  2694. {
  2695. struct cnic_dev *dev = data;
  2696. int ulp_type = CNIC_ULP_ISCSI;
  2697. switch (info->cmd) {
  2698. case CNIC_CTL_STOP_CMD:
  2699. cnic_hold(dev);
  2700. cnic_ulp_stop(dev);
  2701. cnic_stop_hw(dev);
  2702. cnic_put(dev);
  2703. break;
  2704. case CNIC_CTL_START_CMD:
  2705. cnic_hold(dev);
  2706. if (!cnic_start_hw(dev))
  2707. cnic_ulp_start(dev);
  2708. cnic_put(dev);
  2709. break;
  2710. case CNIC_CTL_STOP_ISCSI_CMD: {
  2711. struct cnic_local *cp = dev->cnic_priv;
  2712. set_bit(CNIC_LCL_FL_STOP_ISCSI, &cp->cnic_local_flags);
  2713. queue_delayed_work(cnic_wq, &cp->delete_task, 0);
  2714. break;
  2715. }
  2716. case CNIC_CTL_COMPLETION_CMD: {
  2717. struct cnic_ctl_completion *comp = &info->data.comp;
  2718. u32 cid = BNX2X_SW_CID(comp->cid);
  2719. u32 l5_cid;
  2720. struct cnic_local *cp = dev->cnic_priv;
  2721. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  2722. break;
  2723. if (cnic_get_l5_cid(cp, cid, &l5_cid) == 0) {
  2724. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  2725. if (unlikely(comp->error)) {
  2726. set_bit(CTX_FL_CID_ERROR, &ctx->ctx_flags);
  2727. netdev_err(dev->netdev,
  2728. "CID %x CFC delete comp error %x\n",
  2729. cid, comp->error);
  2730. }
  2731. ctx->wait_cond = 1;
  2732. wake_up(&ctx->waitq);
  2733. }
  2734. break;
  2735. }
  2736. case CNIC_CTL_FCOE_STATS_GET_CMD:
  2737. ulp_type = CNIC_ULP_FCOE;
  2738. /* fall through */
  2739. case CNIC_CTL_ISCSI_STATS_GET_CMD:
  2740. cnic_hold(dev);
  2741. cnic_copy_ulp_stats(dev, ulp_type);
  2742. cnic_put(dev);
  2743. break;
  2744. default:
  2745. return -EINVAL;
  2746. }
  2747. return 0;
  2748. }
  2749. static void cnic_ulp_init(struct cnic_dev *dev)
  2750. {
  2751. int i;
  2752. struct cnic_local *cp = dev->cnic_priv;
  2753. for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
  2754. struct cnic_ulp_ops *ulp_ops;
  2755. mutex_lock(&cnic_lock);
  2756. ulp_ops = cnic_ulp_tbl_prot(i);
  2757. if (!ulp_ops || !ulp_ops->cnic_init) {
  2758. mutex_unlock(&cnic_lock);
  2759. continue;
  2760. }
  2761. ulp_get(ulp_ops);
  2762. mutex_unlock(&cnic_lock);
  2763. if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[i]))
  2764. ulp_ops->cnic_init(dev);
  2765. ulp_put(ulp_ops);
  2766. }
  2767. }
  2768. static void cnic_ulp_exit(struct cnic_dev *dev)
  2769. {
  2770. int i;
  2771. struct cnic_local *cp = dev->cnic_priv;
  2772. for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
  2773. struct cnic_ulp_ops *ulp_ops;
  2774. mutex_lock(&cnic_lock);
  2775. ulp_ops = cnic_ulp_tbl_prot(i);
  2776. if (!ulp_ops || !ulp_ops->cnic_exit) {
  2777. mutex_unlock(&cnic_lock);
  2778. continue;
  2779. }
  2780. ulp_get(ulp_ops);
  2781. mutex_unlock(&cnic_lock);
  2782. if (test_and_clear_bit(ULP_F_INIT, &cp->ulp_flags[i]))
  2783. ulp_ops->cnic_exit(dev);
  2784. ulp_put(ulp_ops);
  2785. }
  2786. }
  2787. static int cnic_cm_offload_pg(struct cnic_sock *csk)
  2788. {
  2789. struct cnic_dev *dev = csk->dev;
  2790. struct l4_kwq_offload_pg *l4kwqe;
  2791. struct kwqe *wqes[1];
  2792. l4kwqe = (struct l4_kwq_offload_pg *) &csk->kwqe1;
  2793. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2794. wqes[0] = (struct kwqe *) l4kwqe;
  2795. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_OFFLOAD_PG;
  2796. l4kwqe->flags =
  2797. L4_LAYER_CODE << L4_KWQ_OFFLOAD_PG_LAYER_CODE_SHIFT;
  2798. l4kwqe->l2hdr_nbytes = ETH_HLEN;
  2799. l4kwqe->da0 = csk->ha[0];
  2800. l4kwqe->da1 = csk->ha[1];
  2801. l4kwqe->da2 = csk->ha[2];
  2802. l4kwqe->da3 = csk->ha[3];
  2803. l4kwqe->da4 = csk->ha[4];
  2804. l4kwqe->da5 = csk->ha[5];
  2805. l4kwqe->sa0 = dev->mac_addr[0];
  2806. l4kwqe->sa1 = dev->mac_addr[1];
  2807. l4kwqe->sa2 = dev->mac_addr[2];
  2808. l4kwqe->sa3 = dev->mac_addr[3];
  2809. l4kwqe->sa4 = dev->mac_addr[4];
  2810. l4kwqe->sa5 = dev->mac_addr[5];
  2811. l4kwqe->etype = ETH_P_IP;
  2812. l4kwqe->ipid_start = DEF_IPID_START;
  2813. l4kwqe->host_opaque = csk->l5_cid;
  2814. if (csk->vlan_id) {
  2815. l4kwqe->pg_flags |= L4_KWQ_OFFLOAD_PG_VLAN_TAGGING;
  2816. l4kwqe->vlan_tag = csk->vlan_id;
  2817. l4kwqe->l2hdr_nbytes += 4;
  2818. }
  2819. return dev->submit_kwqes(dev, wqes, 1);
  2820. }
  2821. static int cnic_cm_update_pg(struct cnic_sock *csk)
  2822. {
  2823. struct cnic_dev *dev = csk->dev;
  2824. struct l4_kwq_update_pg *l4kwqe;
  2825. struct kwqe *wqes[1];
  2826. l4kwqe = (struct l4_kwq_update_pg *) &csk->kwqe1;
  2827. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2828. wqes[0] = (struct kwqe *) l4kwqe;
  2829. l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPDATE_PG;
  2830. l4kwqe->flags =
  2831. L4_LAYER_CODE << L4_KWQ_UPDATE_PG_LAYER_CODE_SHIFT;
  2832. l4kwqe->pg_cid = csk->pg_cid;
  2833. l4kwqe->da0 = csk->ha[0];
  2834. l4kwqe->da1 = csk->ha[1];
  2835. l4kwqe->da2 = csk->ha[2];
  2836. l4kwqe->da3 = csk->ha[3];
  2837. l4kwqe->da4 = csk->ha[4];
  2838. l4kwqe->da5 = csk->ha[5];
  2839. l4kwqe->pg_host_opaque = csk->l5_cid;
  2840. l4kwqe->pg_valids = L4_KWQ_UPDATE_PG_VALIDS_DA;
  2841. return dev->submit_kwqes(dev, wqes, 1);
  2842. }
  2843. static int cnic_cm_upload_pg(struct cnic_sock *csk)
  2844. {
  2845. struct cnic_dev *dev = csk->dev;
  2846. struct l4_kwq_upload *l4kwqe;
  2847. struct kwqe *wqes[1];
  2848. l4kwqe = (struct l4_kwq_upload *) &csk->kwqe1;
  2849. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2850. wqes[0] = (struct kwqe *) l4kwqe;
  2851. l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPLOAD_PG;
  2852. l4kwqe->flags =
  2853. L4_LAYER_CODE << L4_KWQ_UPLOAD_LAYER_CODE_SHIFT;
  2854. l4kwqe->cid = csk->pg_cid;
  2855. return dev->submit_kwqes(dev, wqes, 1);
  2856. }
  2857. static int cnic_cm_conn_req(struct cnic_sock *csk)
  2858. {
  2859. struct cnic_dev *dev = csk->dev;
  2860. struct l4_kwq_connect_req1 *l4kwqe1;
  2861. struct l4_kwq_connect_req2 *l4kwqe2;
  2862. struct l4_kwq_connect_req3 *l4kwqe3;
  2863. struct kwqe *wqes[3];
  2864. u8 tcp_flags = 0;
  2865. int num_wqes = 2;
  2866. l4kwqe1 = (struct l4_kwq_connect_req1 *) &csk->kwqe1;
  2867. l4kwqe2 = (struct l4_kwq_connect_req2 *) &csk->kwqe2;
  2868. l4kwqe3 = (struct l4_kwq_connect_req3 *) &csk->kwqe3;
  2869. memset(l4kwqe1, 0, sizeof(*l4kwqe1));
  2870. memset(l4kwqe2, 0, sizeof(*l4kwqe2));
  2871. memset(l4kwqe3, 0, sizeof(*l4kwqe3));
  2872. l4kwqe3->op_code = L4_KWQE_OPCODE_VALUE_CONNECT3;
  2873. l4kwqe3->flags =
  2874. L4_LAYER_CODE << L4_KWQ_CONNECT_REQ3_LAYER_CODE_SHIFT;
  2875. l4kwqe3->ka_timeout = csk->ka_timeout;
  2876. l4kwqe3->ka_interval = csk->ka_interval;
  2877. l4kwqe3->ka_max_probe_count = csk->ka_max_probe_count;
  2878. l4kwqe3->tos = csk->tos;
  2879. l4kwqe3->ttl = csk->ttl;
  2880. l4kwqe3->snd_seq_scale = csk->snd_seq_scale;
  2881. l4kwqe3->pmtu = csk->mtu;
  2882. l4kwqe3->rcv_buf = csk->rcv_buf;
  2883. l4kwqe3->snd_buf = csk->snd_buf;
  2884. l4kwqe3->seed = csk->seed;
  2885. wqes[0] = (struct kwqe *) l4kwqe1;
  2886. if (test_bit(SK_F_IPV6, &csk->flags)) {
  2887. wqes[1] = (struct kwqe *) l4kwqe2;
  2888. wqes[2] = (struct kwqe *) l4kwqe3;
  2889. num_wqes = 3;
  2890. l4kwqe1->conn_flags = L4_KWQ_CONNECT_REQ1_IP_V6;
  2891. l4kwqe2->op_code = L4_KWQE_OPCODE_VALUE_CONNECT2;
  2892. l4kwqe2->flags =
  2893. L4_KWQ_CONNECT_REQ2_LINKED_WITH_NEXT |
  2894. L4_LAYER_CODE << L4_KWQ_CONNECT_REQ2_LAYER_CODE_SHIFT;
  2895. l4kwqe2->src_ip_v6_2 = be32_to_cpu(csk->src_ip[1]);
  2896. l4kwqe2->src_ip_v6_3 = be32_to_cpu(csk->src_ip[2]);
  2897. l4kwqe2->src_ip_v6_4 = be32_to_cpu(csk->src_ip[3]);
  2898. l4kwqe2->dst_ip_v6_2 = be32_to_cpu(csk->dst_ip[1]);
  2899. l4kwqe2->dst_ip_v6_3 = be32_to_cpu(csk->dst_ip[2]);
  2900. l4kwqe2->dst_ip_v6_4 = be32_to_cpu(csk->dst_ip[3]);
  2901. l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct ipv6hdr) -
  2902. sizeof(struct tcphdr);
  2903. } else {
  2904. wqes[1] = (struct kwqe *) l4kwqe3;
  2905. l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct iphdr) -
  2906. sizeof(struct tcphdr);
  2907. }
  2908. l4kwqe1->op_code = L4_KWQE_OPCODE_VALUE_CONNECT1;
  2909. l4kwqe1->flags =
  2910. (L4_LAYER_CODE << L4_KWQ_CONNECT_REQ1_LAYER_CODE_SHIFT) |
  2911. L4_KWQ_CONNECT_REQ3_LINKED_WITH_NEXT;
  2912. l4kwqe1->cid = csk->cid;
  2913. l4kwqe1->pg_cid = csk->pg_cid;
  2914. l4kwqe1->src_ip = be32_to_cpu(csk->src_ip[0]);
  2915. l4kwqe1->dst_ip = be32_to_cpu(csk->dst_ip[0]);
  2916. l4kwqe1->src_port = be16_to_cpu(csk->src_port);
  2917. l4kwqe1->dst_port = be16_to_cpu(csk->dst_port);
  2918. if (csk->tcp_flags & SK_TCP_NO_DELAY_ACK)
  2919. tcp_flags |= L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK;
  2920. if (csk->tcp_flags & SK_TCP_KEEP_ALIVE)
  2921. tcp_flags |= L4_KWQ_CONNECT_REQ1_KEEP_ALIVE;
  2922. if (csk->tcp_flags & SK_TCP_NAGLE)
  2923. tcp_flags |= L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE;
  2924. if (csk->tcp_flags & SK_TCP_TIMESTAMP)
  2925. tcp_flags |= L4_KWQ_CONNECT_REQ1_TIME_STAMP;
  2926. if (csk->tcp_flags & SK_TCP_SACK)
  2927. tcp_flags |= L4_KWQ_CONNECT_REQ1_SACK;
  2928. if (csk->tcp_flags & SK_TCP_SEG_SCALING)
  2929. tcp_flags |= L4_KWQ_CONNECT_REQ1_SEG_SCALING;
  2930. l4kwqe1->tcp_flags = tcp_flags;
  2931. return dev->submit_kwqes(dev, wqes, num_wqes);
  2932. }
  2933. static int cnic_cm_close_req(struct cnic_sock *csk)
  2934. {
  2935. struct cnic_dev *dev = csk->dev;
  2936. struct l4_kwq_close_req *l4kwqe;
  2937. struct kwqe *wqes[1];
  2938. l4kwqe = (struct l4_kwq_close_req *) &csk->kwqe2;
  2939. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2940. wqes[0] = (struct kwqe *) l4kwqe;
  2941. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_CLOSE;
  2942. l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_CLOSE_REQ_LAYER_CODE_SHIFT;
  2943. l4kwqe->cid = csk->cid;
  2944. return dev->submit_kwqes(dev, wqes, 1);
  2945. }
  2946. static int cnic_cm_abort_req(struct cnic_sock *csk)
  2947. {
  2948. struct cnic_dev *dev = csk->dev;
  2949. struct l4_kwq_reset_req *l4kwqe;
  2950. struct kwqe *wqes[1];
  2951. l4kwqe = (struct l4_kwq_reset_req *) &csk->kwqe2;
  2952. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2953. wqes[0] = (struct kwqe *) l4kwqe;
  2954. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_RESET;
  2955. l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_RESET_REQ_LAYER_CODE_SHIFT;
  2956. l4kwqe->cid = csk->cid;
  2957. return dev->submit_kwqes(dev, wqes, 1);
  2958. }
  2959. static int cnic_cm_create(struct cnic_dev *dev, int ulp_type, u32 cid,
  2960. u32 l5_cid, struct cnic_sock **csk, void *context)
  2961. {
  2962. struct cnic_local *cp = dev->cnic_priv;
  2963. struct cnic_sock *csk1;
  2964. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  2965. return -EINVAL;
  2966. if (cp->ctx_tbl) {
  2967. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  2968. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  2969. return -EAGAIN;
  2970. }
  2971. csk1 = &cp->csk_tbl[l5_cid];
  2972. if (atomic_read(&csk1->ref_count))
  2973. return -EAGAIN;
  2974. if (test_and_set_bit(SK_F_INUSE, &csk1->flags))
  2975. return -EBUSY;
  2976. csk1->dev = dev;
  2977. csk1->cid = cid;
  2978. csk1->l5_cid = l5_cid;
  2979. csk1->ulp_type = ulp_type;
  2980. csk1->context = context;
  2981. csk1->ka_timeout = DEF_KA_TIMEOUT;
  2982. csk1->ka_interval = DEF_KA_INTERVAL;
  2983. csk1->ka_max_probe_count = DEF_KA_MAX_PROBE_COUNT;
  2984. csk1->tos = DEF_TOS;
  2985. csk1->ttl = DEF_TTL;
  2986. csk1->snd_seq_scale = DEF_SND_SEQ_SCALE;
  2987. csk1->rcv_buf = DEF_RCV_BUF;
  2988. csk1->snd_buf = DEF_SND_BUF;
  2989. csk1->seed = DEF_SEED;
  2990. csk1->tcp_flags = 0;
  2991. *csk = csk1;
  2992. return 0;
  2993. }
  2994. static void cnic_cm_cleanup(struct cnic_sock *csk)
  2995. {
  2996. if (csk->src_port) {
  2997. struct cnic_dev *dev = csk->dev;
  2998. struct cnic_local *cp = dev->cnic_priv;
  2999. cnic_free_id(&cp->csk_port_tbl, be16_to_cpu(csk->src_port));
  3000. csk->src_port = 0;
  3001. }
  3002. }
  3003. static void cnic_close_conn(struct cnic_sock *csk)
  3004. {
  3005. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags)) {
  3006. cnic_cm_upload_pg(csk);
  3007. clear_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
  3008. }
  3009. cnic_cm_cleanup(csk);
  3010. }
  3011. static int cnic_cm_destroy(struct cnic_sock *csk)
  3012. {
  3013. if (!cnic_in_use(csk))
  3014. return -EINVAL;
  3015. csk_hold(csk);
  3016. clear_bit(SK_F_INUSE, &csk->flags);
  3017. smp_mb__after_atomic();
  3018. while (atomic_read(&csk->ref_count) != 1)
  3019. msleep(1);
  3020. cnic_cm_cleanup(csk);
  3021. csk->flags = 0;
  3022. csk_put(csk);
  3023. return 0;
  3024. }
  3025. static inline u16 cnic_get_vlan(struct net_device *dev,
  3026. struct net_device **vlan_dev)
  3027. {
  3028. if (dev->priv_flags & IFF_802_1Q_VLAN) {
  3029. *vlan_dev = vlan_dev_real_dev(dev);
  3030. return vlan_dev_vlan_id(dev);
  3031. }
  3032. *vlan_dev = dev;
  3033. return 0;
  3034. }
  3035. static int cnic_get_v4_route(struct sockaddr_in *dst_addr,
  3036. struct dst_entry **dst)
  3037. {
  3038. #if defined(CONFIG_INET)
  3039. struct rtable *rt;
  3040. rt = ip_route_output(&init_net, dst_addr->sin_addr.s_addr, 0, 0, 0);
  3041. if (!IS_ERR(rt)) {
  3042. *dst = &rt->dst;
  3043. return 0;
  3044. }
  3045. return PTR_ERR(rt);
  3046. #else
  3047. return -ENETUNREACH;
  3048. #endif
  3049. }
  3050. static int cnic_get_v6_route(struct sockaddr_in6 *dst_addr,
  3051. struct dst_entry **dst)
  3052. {
  3053. #if IS_ENABLED(CONFIG_IPV6)
  3054. struct flowi6 fl6;
  3055. memset(&fl6, 0, sizeof(fl6));
  3056. fl6.daddr = dst_addr->sin6_addr;
  3057. if (ipv6_addr_type(&fl6.daddr) & IPV6_ADDR_LINKLOCAL)
  3058. fl6.flowi6_oif = dst_addr->sin6_scope_id;
  3059. *dst = ip6_route_output(&init_net, NULL, &fl6);
  3060. if ((*dst)->error) {
  3061. dst_release(*dst);
  3062. *dst = NULL;
  3063. return -ENETUNREACH;
  3064. } else
  3065. return 0;
  3066. #endif
  3067. return -ENETUNREACH;
  3068. }
  3069. static struct cnic_dev *cnic_cm_select_dev(struct sockaddr_in *dst_addr,
  3070. int ulp_type)
  3071. {
  3072. struct cnic_dev *dev = NULL;
  3073. struct dst_entry *dst;
  3074. struct net_device *netdev = NULL;
  3075. int err = -ENETUNREACH;
  3076. if (dst_addr->sin_family == AF_INET)
  3077. err = cnic_get_v4_route(dst_addr, &dst);
  3078. else if (dst_addr->sin_family == AF_INET6) {
  3079. struct sockaddr_in6 *dst_addr6 =
  3080. (struct sockaddr_in6 *) dst_addr;
  3081. err = cnic_get_v6_route(dst_addr6, &dst);
  3082. } else
  3083. return NULL;
  3084. if (err)
  3085. return NULL;
  3086. if (!dst->dev)
  3087. goto done;
  3088. cnic_get_vlan(dst->dev, &netdev);
  3089. dev = cnic_from_netdev(netdev);
  3090. done:
  3091. dst_release(dst);
  3092. if (dev)
  3093. cnic_put(dev);
  3094. return dev;
  3095. }
  3096. static int cnic_resolve_addr(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  3097. {
  3098. struct cnic_dev *dev = csk->dev;
  3099. struct cnic_local *cp = dev->cnic_priv;
  3100. return cnic_send_nlmsg(cp, ISCSI_KEVENT_PATH_REQ, csk);
  3101. }
  3102. static int cnic_get_route(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  3103. {
  3104. struct cnic_dev *dev = csk->dev;
  3105. struct cnic_local *cp = dev->cnic_priv;
  3106. int is_v6, rc = 0;
  3107. struct dst_entry *dst = NULL;
  3108. struct net_device *realdev;
  3109. __be16 local_port;
  3110. u32 port_id;
  3111. if (saddr->local.v6.sin6_family == AF_INET6 &&
  3112. saddr->remote.v6.sin6_family == AF_INET6)
  3113. is_v6 = 1;
  3114. else if (saddr->local.v4.sin_family == AF_INET &&
  3115. saddr->remote.v4.sin_family == AF_INET)
  3116. is_v6 = 0;
  3117. else
  3118. return -EINVAL;
  3119. clear_bit(SK_F_IPV6, &csk->flags);
  3120. if (is_v6) {
  3121. set_bit(SK_F_IPV6, &csk->flags);
  3122. cnic_get_v6_route(&saddr->remote.v6, &dst);
  3123. memcpy(&csk->dst_ip[0], &saddr->remote.v6.sin6_addr,
  3124. sizeof(struct in6_addr));
  3125. csk->dst_port = saddr->remote.v6.sin6_port;
  3126. local_port = saddr->local.v6.sin6_port;
  3127. } else {
  3128. cnic_get_v4_route(&saddr->remote.v4, &dst);
  3129. csk->dst_ip[0] = saddr->remote.v4.sin_addr.s_addr;
  3130. csk->dst_port = saddr->remote.v4.sin_port;
  3131. local_port = saddr->local.v4.sin_port;
  3132. }
  3133. csk->vlan_id = 0;
  3134. csk->mtu = dev->netdev->mtu;
  3135. if (dst && dst->dev) {
  3136. u16 vlan = cnic_get_vlan(dst->dev, &realdev);
  3137. if (realdev == dev->netdev) {
  3138. csk->vlan_id = vlan;
  3139. csk->mtu = dst_mtu(dst);
  3140. }
  3141. }
  3142. port_id = be16_to_cpu(local_port);
  3143. if (port_id >= CNIC_LOCAL_PORT_MIN &&
  3144. port_id < CNIC_LOCAL_PORT_MAX) {
  3145. if (cnic_alloc_id(&cp->csk_port_tbl, port_id))
  3146. port_id = 0;
  3147. } else
  3148. port_id = 0;
  3149. if (!port_id) {
  3150. port_id = cnic_alloc_new_id(&cp->csk_port_tbl);
  3151. if (port_id == -1) {
  3152. rc = -ENOMEM;
  3153. goto err_out;
  3154. }
  3155. local_port = cpu_to_be16(port_id);
  3156. }
  3157. csk->src_port = local_port;
  3158. err_out:
  3159. dst_release(dst);
  3160. return rc;
  3161. }
  3162. static void cnic_init_csk_state(struct cnic_sock *csk)
  3163. {
  3164. csk->state = 0;
  3165. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3166. clear_bit(SK_F_CLOSING, &csk->flags);
  3167. }
  3168. static int cnic_cm_connect(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  3169. {
  3170. struct cnic_local *cp = csk->dev->cnic_priv;
  3171. int err = 0;
  3172. if (cp->ethdev->drv_state & CNIC_DRV_STATE_NO_ISCSI)
  3173. return -EOPNOTSUPP;
  3174. if (!cnic_in_use(csk))
  3175. return -EINVAL;
  3176. if (test_and_set_bit(SK_F_CONNECT_START, &csk->flags))
  3177. return -EINVAL;
  3178. cnic_init_csk_state(csk);
  3179. err = cnic_get_route(csk, saddr);
  3180. if (err)
  3181. goto err_out;
  3182. err = cnic_resolve_addr(csk, saddr);
  3183. if (!err)
  3184. return 0;
  3185. err_out:
  3186. clear_bit(SK_F_CONNECT_START, &csk->flags);
  3187. return err;
  3188. }
  3189. static int cnic_cm_abort(struct cnic_sock *csk)
  3190. {
  3191. struct cnic_local *cp = csk->dev->cnic_priv;
  3192. u32 opcode = L4_KCQE_OPCODE_VALUE_RESET_COMP;
  3193. if (!cnic_in_use(csk))
  3194. return -EINVAL;
  3195. if (cnic_abort_prep(csk))
  3196. return cnic_cm_abort_req(csk);
  3197. /* Getting here means that we haven't started connect, or
  3198. * connect was not successful, or it has been reset by the target.
  3199. */
  3200. cp->close_conn(csk, opcode);
  3201. if (csk->state != opcode) {
  3202. /* Wait for remote reset sequence to complete */
  3203. while (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
  3204. msleep(1);
  3205. return -EALREADY;
  3206. }
  3207. return 0;
  3208. }
  3209. static int cnic_cm_close(struct cnic_sock *csk)
  3210. {
  3211. if (!cnic_in_use(csk))
  3212. return -EINVAL;
  3213. if (cnic_close_prep(csk)) {
  3214. csk->state = L4_KCQE_OPCODE_VALUE_CLOSE_COMP;
  3215. return cnic_cm_close_req(csk);
  3216. } else {
  3217. /* Wait for remote reset sequence to complete */
  3218. while (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
  3219. msleep(1);
  3220. return -EALREADY;
  3221. }
  3222. return 0;
  3223. }
  3224. static void cnic_cm_upcall(struct cnic_local *cp, struct cnic_sock *csk,
  3225. u8 opcode)
  3226. {
  3227. struct cnic_ulp_ops *ulp_ops;
  3228. int ulp_type = csk->ulp_type;
  3229. rcu_read_lock();
  3230. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  3231. if (ulp_ops) {
  3232. if (opcode == L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE)
  3233. ulp_ops->cm_connect_complete(csk);
  3234. else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_COMP)
  3235. ulp_ops->cm_close_complete(csk);
  3236. else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED)
  3237. ulp_ops->cm_remote_abort(csk);
  3238. else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_COMP)
  3239. ulp_ops->cm_abort_complete(csk);
  3240. else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED)
  3241. ulp_ops->cm_remote_close(csk);
  3242. }
  3243. rcu_read_unlock();
  3244. }
  3245. static int cnic_cm_set_pg(struct cnic_sock *csk)
  3246. {
  3247. if (cnic_offld_prep(csk)) {
  3248. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
  3249. cnic_cm_update_pg(csk);
  3250. else
  3251. cnic_cm_offload_pg(csk);
  3252. }
  3253. return 0;
  3254. }
  3255. static void cnic_cm_process_offld_pg(struct cnic_dev *dev, struct l4_kcq *kcqe)
  3256. {
  3257. struct cnic_local *cp = dev->cnic_priv;
  3258. u32 l5_cid = kcqe->pg_host_opaque;
  3259. u8 opcode = kcqe->op_code;
  3260. struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
  3261. csk_hold(csk);
  3262. if (!cnic_in_use(csk))
  3263. goto done;
  3264. if (opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
  3265. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3266. goto done;
  3267. }
  3268. /* Possible PG kcqe status: SUCCESS, OFFLOADED_PG, or CTX_ALLOC_FAIL */
  3269. if (kcqe->status == L4_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAIL) {
  3270. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3271. cnic_cm_upcall(cp, csk,
  3272. L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
  3273. goto done;
  3274. }
  3275. csk->pg_cid = kcqe->pg_cid;
  3276. set_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
  3277. cnic_cm_conn_req(csk);
  3278. done:
  3279. csk_put(csk);
  3280. }
  3281. static void cnic_process_fcoe_term_conn(struct cnic_dev *dev, struct kcqe *kcqe)
  3282. {
  3283. struct cnic_local *cp = dev->cnic_priv;
  3284. struct fcoe_kcqe *fc_kcqe = (struct fcoe_kcqe *) kcqe;
  3285. u32 l5_cid = fc_kcqe->fcoe_conn_id + BNX2X_FCOE_L5_CID_BASE;
  3286. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  3287. ctx->timestamp = jiffies;
  3288. ctx->wait_cond = 1;
  3289. wake_up(&ctx->waitq);
  3290. }
  3291. static void cnic_cm_process_kcqe(struct cnic_dev *dev, struct kcqe *kcqe)
  3292. {
  3293. struct cnic_local *cp = dev->cnic_priv;
  3294. struct l4_kcq *l4kcqe = (struct l4_kcq *) kcqe;
  3295. u8 opcode = l4kcqe->op_code;
  3296. u32 l5_cid;
  3297. struct cnic_sock *csk;
  3298. if (opcode == FCOE_RAMROD_CMD_ID_TERMINATE_CONN) {
  3299. cnic_process_fcoe_term_conn(dev, kcqe);
  3300. return;
  3301. }
  3302. if (opcode == L4_KCQE_OPCODE_VALUE_OFFLOAD_PG ||
  3303. opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
  3304. cnic_cm_process_offld_pg(dev, l4kcqe);
  3305. return;
  3306. }
  3307. l5_cid = l4kcqe->conn_id;
  3308. if (opcode & 0x80)
  3309. l5_cid = l4kcqe->cid;
  3310. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  3311. return;
  3312. csk = &cp->csk_tbl[l5_cid];
  3313. csk_hold(csk);
  3314. if (!cnic_in_use(csk)) {
  3315. csk_put(csk);
  3316. return;
  3317. }
  3318. switch (opcode) {
  3319. case L5CM_RAMROD_CMD_ID_TCP_CONNECT:
  3320. if (l4kcqe->status != 0) {
  3321. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3322. cnic_cm_upcall(cp, csk,
  3323. L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
  3324. }
  3325. break;
  3326. case L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE:
  3327. if (l4kcqe->status == 0)
  3328. set_bit(SK_F_OFFLD_COMPLETE, &csk->flags);
  3329. else if (l4kcqe->status ==
  3330. L4_KCQE_COMPLETION_STATUS_PARITY_ERROR)
  3331. set_bit(SK_F_HW_ERR, &csk->flags);
  3332. smp_mb__before_atomic();
  3333. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3334. cnic_cm_upcall(cp, csk, opcode);
  3335. break;
  3336. case L5CM_RAMROD_CMD_ID_CLOSE: {
  3337. struct iscsi_kcqe *l5kcqe = (struct iscsi_kcqe *) kcqe;
  3338. if (l4kcqe->status != 0 || l5kcqe->completion_status != 0) {
  3339. netdev_warn(dev->netdev, "RAMROD CLOSE compl with status 0x%x completion status 0x%x\n",
  3340. l4kcqe->status, l5kcqe->completion_status);
  3341. opcode = L4_KCQE_OPCODE_VALUE_CLOSE_COMP;
  3342. /* Fall through */
  3343. } else {
  3344. break;
  3345. }
  3346. }
  3347. case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
  3348. case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
  3349. case L4_KCQE_OPCODE_VALUE_RESET_COMP:
  3350. case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
  3351. case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
  3352. if (l4kcqe->status == L4_KCQE_COMPLETION_STATUS_PARITY_ERROR)
  3353. set_bit(SK_F_HW_ERR, &csk->flags);
  3354. cp->close_conn(csk, opcode);
  3355. break;
  3356. case L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED:
  3357. /* after we already sent CLOSE_REQ */
  3358. if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags) &&
  3359. !test_bit(SK_F_OFFLD_COMPLETE, &csk->flags) &&
  3360. csk->state == L4_KCQE_OPCODE_VALUE_CLOSE_COMP)
  3361. cp->close_conn(csk, L4_KCQE_OPCODE_VALUE_RESET_COMP);
  3362. else
  3363. cnic_cm_upcall(cp, csk, opcode);
  3364. break;
  3365. }
  3366. csk_put(csk);
  3367. }
  3368. static void cnic_cm_indicate_kcqe(void *data, struct kcqe *kcqe[], u32 num)
  3369. {
  3370. struct cnic_dev *dev = data;
  3371. int i;
  3372. for (i = 0; i < num; i++)
  3373. cnic_cm_process_kcqe(dev, kcqe[i]);
  3374. }
  3375. static struct cnic_ulp_ops cm_ulp_ops = {
  3376. .indicate_kcqes = cnic_cm_indicate_kcqe,
  3377. };
  3378. static void cnic_cm_free_mem(struct cnic_dev *dev)
  3379. {
  3380. struct cnic_local *cp = dev->cnic_priv;
  3381. kfree(cp->csk_tbl);
  3382. cp->csk_tbl = NULL;
  3383. cnic_free_id_tbl(&cp->csk_port_tbl);
  3384. }
  3385. static int cnic_cm_alloc_mem(struct cnic_dev *dev)
  3386. {
  3387. struct cnic_local *cp = dev->cnic_priv;
  3388. u32 port_id;
  3389. cp->csk_tbl = kzalloc(sizeof(struct cnic_sock) * MAX_CM_SK_TBL_SZ,
  3390. GFP_KERNEL);
  3391. if (!cp->csk_tbl)
  3392. return -ENOMEM;
  3393. port_id = prandom_u32();
  3394. port_id %= CNIC_LOCAL_PORT_RANGE;
  3395. if (cnic_init_id_tbl(&cp->csk_port_tbl, CNIC_LOCAL_PORT_RANGE,
  3396. CNIC_LOCAL_PORT_MIN, port_id)) {
  3397. cnic_cm_free_mem(dev);
  3398. return -ENOMEM;
  3399. }
  3400. return 0;
  3401. }
  3402. static int cnic_ready_to_close(struct cnic_sock *csk, u32 opcode)
  3403. {
  3404. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  3405. /* Unsolicited RESET_COMP or RESET_RECEIVED */
  3406. opcode = L4_KCQE_OPCODE_VALUE_RESET_RECEIVED;
  3407. csk->state = opcode;
  3408. }
  3409. /* 1. If event opcode matches the expected event in csk->state
  3410. * 2. If the expected event is CLOSE_COMP or RESET_COMP, we accept any
  3411. * event
  3412. * 3. If the expected event is 0, meaning the connection was never
  3413. * never established, we accept the opcode from cm_abort.
  3414. */
  3415. if (opcode == csk->state || csk->state == 0 ||
  3416. csk->state == L4_KCQE_OPCODE_VALUE_CLOSE_COMP ||
  3417. csk->state == L4_KCQE_OPCODE_VALUE_RESET_COMP) {
  3418. if (!test_and_set_bit(SK_F_CLOSING, &csk->flags)) {
  3419. if (csk->state == 0)
  3420. csk->state = opcode;
  3421. return 1;
  3422. }
  3423. }
  3424. return 0;
  3425. }
  3426. static void cnic_close_bnx2_conn(struct cnic_sock *csk, u32 opcode)
  3427. {
  3428. struct cnic_dev *dev = csk->dev;
  3429. struct cnic_local *cp = dev->cnic_priv;
  3430. if (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED) {
  3431. cnic_cm_upcall(cp, csk, opcode);
  3432. return;
  3433. }
  3434. clear_bit(SK_F_CONNECT_START, &csk->flags);
  3435. cnic_close_conn(csk);
  3436. csk->state = opcode;
  3437. cnic_cm_upcall(cp, csk, opcode);
  3438. }
  3439. static void cnic_cm_stop_bnx2_hw(struct cnic_dev *dev)
  3440. {
  3441. }
  3442. static int cnic_cm_init_bnx2_hw(struct cnic_dev *dev)
  3443. {
  3444. u32 seed;
  3445. seed = prandom_u32();
  3446. cnic_ctx_wr(dev, 45, 0, seed);
  3447. return 0;
  3448. }
  3449. static void cnic_close_bnx2x_conn(struct cnic_sock *csk, u32 opcode)
  3450. {
  3451. struct cnic_dev *dev = csk->dev;
  3452. struct cnic_local *cp = dev->cnic_priv;
  3453. struct cnic_context *ctx = &cp->ctx_tbl[csk->l5_cid];
  3454. union l5cm_specific_data l5_data;
  3455. u32 cmd = 0;
  3456. int close_complete = 0;
  3457. switch (opcode) {
  3458. case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
  3459. case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
  3460. case L4_KCQE_OPCODE_VALUE_RESET_COMP:
  3461. if (cnic_ready_to_close(csk, opcode)) {
  3462. if (test_bit(SK_F_HW_ERR, &csk->flags))
  3463. close_complete = 1;
  3464. else if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
  3465. cmd = L5CM_RAMROD_CMD_ID_SEARCHER_DELETE;
  3466. else
  3467. close_complete = 1;
  3468. }
  3469. break;
  3470. case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
  3471. cmd = L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD;
  3472. break;
  3473. case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
  3474. close_complete = 1;
  3475. break;
  3476. }
  3477. if (cmd) {
  3478. memset(&l5_data, 0, sizeof(l5_data));
  3479. cnic_submit_kwqe_16(dev, cmd, csk->cid, ISCSI_CONNECTION_TYPE,
  3480. &l5_data);
  3481. } else if (close_complete) {
  3482. ctx->timestamp = jiffies;
  3483. cnic_close_conn(csk);
  3484. cnic_cm_upcall(cp, csk, csk->state);
  3485. }
  3486. }
  3487. static void cnic_cm_stop_bnx2x_hw(struct cnic_dev *dev)
  3488. {
  3489. struct cnic_local *cp = dev->cnic_priv;
  3490. if (!cp->ctx_tbl)
  3491. return;
  3492. if (!netif_running(dev->netdev))
  3493. return;
  3494. cnic_bnx2x_delete_wait(dev, 0);
  3495. cancel_delayed_work(&cp->delete_task);
  3496. flush_workqueue(cnic_wq);
  3497. if (atomic_read(&cp->iscsi_conn) != 0)
  3498. netdev_warn(dev->netdev, "%d iSCSI connections not destroyed\n",
  3499. atomic_read(&cp->iscsi_conn));
  3500. }
  3501. static int cnic_cm_init_bnx2x_hw(struct cnic_dev *dev)
  3502. {
  3503. struct bnx2x *bp = netdev_priv(dev->netdev);
  3504. u32 pfid = bp->pfid;
  3505. u32 port = BP_PORT(bp);
  3506. cnic_init_bnx2x_mac(dev);
  3507. cnic_bnx2x_set_tcp_options(dev, 0, 1);
  3508. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  3509. XSTORM_ISCSI_LOCAL_VLAN_OFFSET(pfid), 0);
  3510. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  3511. XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_ENABLED_OFFSET(port), 1);
  3512. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  3513. XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_MAX_COUNT_OFFSET(port),
  3514. DEF_MAX_DA_COUNT);
  3515. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  3516. XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(pfid), DEF_TTL);
  3517. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  3518. XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(pfid), DEF_TOS);
  3519. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  3520. XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(pfid), 2);
  3521. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  3522. XSTORM_TCP_TX_SWS_TIMER_VAL_OFFSET(pfid), DEF_SWS_TIMER);
  3523. CNIC_WR(dev, BAR_TSTRORM_INTMEM + TSTORM_TCP_MAX_CWND_OFFSET(pfid),
  3524. DEF_MAX_CWND);
  3525. return 0;
  3526. }
  3527. static void cnic_delete_task(struct work_struct *work)
  3528. {
  3529. struct cnic_local *cp;
  3530. struct cnic_dev *dev;
  3531. u32 i;
  3532. int need_resched = 0;
  3533. cp = container_of(work, struct cnic_local, delete_task.work);
  3534. dev = cp->dev;
  3535. if (test_and_clear_bit(CNIC_LCL_FL_STOP_ISCSI, &cp->cnic_local_flags)) {
  3536. struct drv_ctl_info info;
  3537. cnic_ulp_stop_one(cp, CNIC_ULP_ISCSI);
  3538. info.cmd = DRV_CTL_ISCSI_STOPPED_CMD;
  3539. cp->ethdev->drv_ctl(dev->netdev, &info);
  3540. }
  3541. for (i = 0; i < cp->max_cid_space; i++) {
  3542. struct cnic_context *ctx = &cp->ctx_tbl[i];
  3543. int err;
  3544. if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags) ||
  3545. !test_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
  3546. continue;
  3547. if (!time_after(jiffies, ctx->timestamp + (2 * HZ))) {
  3548. need_resched = 1;
  3549. continue;
  3550. }
  3551. if (!test_and_clear_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
  3552. continue;
  3553. err = cnic_bnx2x_destroy_ramrod(dev, i);
  3554. cnic_free_bnx2x_conn_resc(dev, i);
  3555. if (!err) {
  3556. if (ctx->ulp_proto_id == CNIC_ULP_ISCSI)
  3557. atomic_dec(&cp->iscsi_conn);
  3558. clear_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  3559. }
  3560. }
  3561. if (need_resched)
  3562. queue_delayed_work(cnic_wq, &cp->delete_task,
  3563. msecs_to_jiffies(10));
  3564. }
  3565. static int cnic_cm_open(struct cnic_dev *dev)
  3566. {
  3567. struct cnic_local *cp = dev->cnic_priv;
  3568. int err;
  3569. err = cnic_cm_alloc_mem(dev);
  3570. if (err)
  3571. return err;
  3572. err = cp->start_cm(dev);
  3573. if (err)
  3574. goto err_out;
  3575. INIT_DELAYED_WORK(&cp->delete_task, cnic_delete_task);
  3576. dev->cm_create = cnic_cm_create;
  3577. dev->cm_destroy = cnic_cm_destroy;
  3578. dev->cm_connect = cnic_cm_connect;
  3579. dev->cm_abort = cnic_cm_abort;
  3580. dev->cm_close = cnic_cm_close;
  3581. dev->cm_select_dev = cnic_cm_select_dev;
  3582. cp->ulp_handle[CNIC_ULP_L4] = dev;
  3583. rcu_assign_pointer(cp->ulp_ops[CNIC_ULP_L4], &cm_ulp_ops);
  3584. return 0;
  3585. err_out:
  3586. cnic_cm_free_mem(dev);
  3587. return err;
  3588. }
  3589. static int cnic_cm_shutdown(struct cnic_dev *dev)
  3590. {
  3591. struct cnic_local *cp = dev->cnic_priv;
  3592. int i;
  3593. if (!cp->csk_tbl)
  3594. return 0;
  3595. for (i = 0; i < MAX_CM_SK_TBL_SZ; i++) {
  3596. struct cnic_sock *csk = &cp->csk_tbl[i];
  3597. clear_bit(SK_F_INUSE, &csk->flags);
  3598. cnic_cm_cleanup(csk);
  3599. }
  3600. cnic_cm_free_mem(dev);
  3601. return 0;
  3602. }
  3603. static void cnic_init_context(struct cnic_dev *dev, u32 cid)
  3604. {
  3605. u32 cid_addr;
  3606. int i;
  3607. cid_addr = GET_CID_ADDR(cid);
  3608. for (i = 0; i < CTX_SIZE; i += 4)
  3609. cnic_ctx_wr(dev, cid_addr, i, 0);
  3610. }
  3611. static int cnic_setup_5709_context(struct cnic_dev *dev, int valid)
  3612. {
  3613. struct cnic_local *cp = dev->cnic_priv;
  3614. int ret = 0, i;
  3615. u32 valid_bit = valid ? BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID : 0;
  3616. if (BNX2_CHIP(cp) != BNX2_CHIP_5709)
  3617. return 0;
  3618. for (i = 0; i < cp->ctx_blks; i++) {
  3619. int j;
  3620. u32 idx = cp->ctx_arr[i].cid / cp->cids_per_blk;
  3621. u32 val;
  3622. memset(cp->ctx_arr[i].ctx, 0, CNIC_PAGE_SIZE);
  3623. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA0,
  3624. (cp->ctx_arr[i].mapping & 0xffffffff) | valid_bit);
  3625. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA1,
  3626. (u64) cp->ctx_arr[i].mapping >> 32);
  3627. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL, idx |
  3628. BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
  3629. for (j = 0; j < 10; j++) {
  3630. val = CNIC_RD(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL);
  3631. if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
  3632. break;
  3633. udelay(5);
  3634. }
  3635. if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
  3636. ret = -EBUSY;
  3637. break;
  3638. }
  3639. }
  3640. return ret;
  3641. }
  3642. static void cnic_free_irq(struct cnic_dev *dev)
  3643. {
  3644. struct cnic_local *cp = dev->cnic_priv;
  3645. struct cnic_eth_dev *ethdev = cp->ethdev;
  3646. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3647. cp->disable_int_sync(dev);
  3648. tasklet_kill(&cp->cnic_irq_task);
  3649. free_irq(ethdev->irq_arr[0].vector, dev);
  3650. }
  3651. }
  3652. static int cnic_request_irq(struct cnic_dev *dev)
  3653. {
  3654. struct cnic_local *cp = dev->cnic_priv;
  3655. struct cnic_eth_dev *ethdev = cp->ethdev;
  3656. int err;
  3657. err = request_irq(ethdev->irq_arr[0].vector, cnic_irq, 0, "cnic", dev);
  3658. if (err)
  3659. tasklet_disable(&cp->cnic_irq_task);
  3660. return err;
  3661. }
  3662. static int cnic_init_bnx2_irq(struct cnic_dev *dev)
  3663. {
  3664. struct cnic_local *cp = dev->cnic_priv;
  3665. struct cnic_eth_dev *ethdev = cp->ethdev;
  3666. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3667. int err, i = 0;
  3668. int sblk_num = cp->status_blk_num;
  3669. u32 base = ((sblk_num - 1) * BNX2_HC_SB_CONFIG_SIZE) +
  3670. BNX2_HC_SB_CONFIG_1;
  3671. CNIC_WR(dev, base, BNX2_HC_SB_CONFIG_1_ONE_SHOT);
  3672. CNIC_WR(dev, base + BNX2_HC_COMP_PROD_TRIP_OFF, (2 << 16) | 8);
  3673. CNIC_WR(dev, base + BNX2_HC_COM_TICKS_OFF, (64 << 16) | 220);
  3674. CNIC_WR(dev, base + BNX2_HC_CMD_TICKS_OFF, (64 << 16) | 220);
  3675. cp->last_status_idx = cp->status_blk.bnx2->status_idx;
  3676. tasklet_init(&cp->cnic_irq_task, cnic_service_bnx2_msix,
  3677. (unsigned long) dev);
  3678. err = cnic_request_irq(dev);
  3679. if (err)
  3680. return err;
  3681. while (cp->status_blk.bnx2->status_completion_producer_index &&
  3682. i < 10) {
  3683. CNIC_WR(dev, BNX2_HC_COALESCE_NOW,
  3684. 1 << (11 + sblk_num));
  3685. udelay(10);
  3686. i++;
  3687. barrier();
  3688. }
  3689. if (cp->status_blk.bnx2->status_completion_producer_index) {
  3690. cnic_free_irq(dev);
  3691. goto failed;
  3692. }
  3693. } else {
  3694. struct status_block *sblk = cp->status_blk.gen;
  3695. u32 hc_cmd = CNIC_RD(dev, BNX2_HC_COMMAND);
  3696. int i = 0;
  3697. while (sblk->status_completion_producer_index && i < 10) {
  3698. CNIC_WR(dev, BNX2_HC_COMMAND,
  3699. hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
  3700. udelay(10);
  3701. i++;
  3702. barrier();
  3703. }
  3704. if (sblk->status_completion_producer_index)
  3705. goto failed;
  3706. }
  3707. return 0;
  3708. failed:
  3709. netdev_err(dev->netdev, "KCQ index not resetting to 0\n");
  3710. return -EBUSY;
  3711. }
  3712. static void cnic_enable_bnx2_int(struct cnic_dev *dev)
  3713. {
  3714. struct cnic_local *cp = dev->cnic_priv;
  3715. struct cnic_eth_dev *ethdev = cp->ethdev;
  3716. if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  3717. return;
  3718. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  3719. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
  3720. }
  3721. static void cnic_disable_bnx2_int_sync(struct cnic_dev *dev)
  3722. {
  3723. struct cnic_local *cp = dev->cnic_priv;
  3724. struct cnic_eth_dev *ethdev = cp->ethdev;
  3725. if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  3726. return;
  3727. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  3728. BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
  3729. CNIC_RD(dev, BNX2_PCICFG_INT_ACK_CMD);
  3730. synchronize_irq(ethdev->irq_arr[0].vector);
  3731. }
  3732. static void cnic_init_bnx2_tx_ring(struct cnic_dev *dev)
  3733. {
  3734. struct cnic_local *cp = dev->cnic_priv;
  3735. struct cnic_eth_dev *ethdev = cp->ethdev;
  3736. struct cnic_uio_dev *udev = cp->udev;
  3737. u32 cid_addr, tx_cid, sb_id;
  3738. u32 val, offset0, offset1, offset2, offset3;
  3739. int i;
  3740. struct bnx2_tx_bd *txbd;
  3741. dma_addr_t buf_map, ring_map = udev->l2_ring_map;
  3742. struct status_block *s_blk = cp->status_blk.gen;
  3743. sb_id = cp->status_blk_num;
  3744. tx_cid = 20;
  3745. cp->tx_cons_ptr = &s_blk->status_tx_quick_consumer_index2;
  3746. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3747. struct status_block_msix *sblk = cp->status_blk.bnx2;
  3748. tx_cid = TX_TSS_CID + sb_id - 1;
  3749. CNIC_WR(dev, BNX2_TSCH_TSS_CFG, (sb_id << 24) |
  3750. (TX_TSS_CID << 7));
  3751. cp->tx_cons_ptr = &sblk->status_tx_quick_consumer_index;
  3752. }
  3753. cp->tx_cons = *cp->tx_cons_ptr;
  3754. cid_addr = GET_CID_ADDR(tx_cid);
  3755. if (BNX2_CHIP(cp) == BNX2_CHIP_5709) {
  3756. u32 cid_addr2 = GET_CID_ADDR(tx_cid + 4) + 0x40;
  3757. for (i = 0; i < PHY_CTX_SIZE; i += 4)
  3758. cnic_ctx_wr(dev, cid_addr2, i, 0);
  3759. offset0 = BNX2_L2CTX_TYPE_XI;
  3760. offset1 = BNX2_L2CTX_CMD_TYPE_XI;
  3761. offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
  3762. offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
  3763. } else {
  3764. cnic_init_context(dev, tx_cid);
  3765. cnic_init_context(dev, tx_cid + 1);
  3766. offset0 = BNX2_L2CTX_TYPE;
  3767. offset1 = BNX2_L2CTX_CMD_TYPE;
  3768. offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
  3769. offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
  3770. }
  3771. val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
  3772. cnic_ctx_wr(dev, cid_addr, offset0, val);
  3773. val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
  3774. cnic_ctx_wr(dev, cid_addr, offset1, val);
  3775. txbd = udev->l2_ring;
  3776. buf_map = udev->l2_buf_map;
  3777. for (i = 0; i < BNX2_MAX_TX_DESC_CNT; i++, txbd++) {
  3778. txbd->tx_bd_haddr_hi = (u64) buf_map >> 32;
  3779. txbd->tx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
  3780. }
  3781. val = (u64) ring_map >> 32;
  3782. cnic_ctx_wr(dev, cid_addr, offset2, val);
  3783. txbd->tx_bd_haddr_hi = val;
  3784. val = (u64) ring_map & 0xffffffff;
  3785. cnic_ctx_wr(dev, cid_addr, offset3, val);
  3786. txbd->tx_bd_haddr_lo = val;
  3787. }
  3788. static void cnic_init_bnx2_rx_ring(struct cnic_dev *dev)
  3789. {
  3790. struct cnic_local *cp = dev->cnic_priv;
  3791. struct cnic_eth_dev *ethdev = cp->ethdev;
  3792. struct cnic_uio_dev *udev = cp->udev;
  3793. u32 cid_addr, sb_id, val, coal_reg, coal_val;
  3794. int i;
  3795. struct bnx2_rx_bd *rxbd;
  3796. struct status_block *s_blk = cp->status_blk.gen;
  3797. dma_addr_t ring_map = udev->l2_ring_map;
  3798. sb_id = cp->status_blk_num;
  3799. cnic_init_context(dev, 2);
  3800. cp->rx_cons_ptr = &s_blk->status_rx_quick_consumer_index2;
  3801. coal_reg = BNX2_HC_COMMAND;
  3802. coal_val = CNIC_RD(dev, coal_reg);
  3803. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3804. struct status_block_msix *sblk = cp->status_blk.bnx2;
  3805. cp->rx_cons_ptr = &sblk->status_rx_quick_consumer_index;
  3806. coal_reg = BNX2_HC_COALESCE_NOW;
  3807. coal_val = 1 << (11 + sb_id);
  3808. }
  3809. i = 0;
  3810. while (!(*cp->rx_cons_ptr != 0) && i < 10) {
  3811. CNIC_WR(dev, coal_reg, coal_val);
  3812. udelay(10);
  3813. i++;
  3814. barrier();
  3815. }
  3816. cp->rx_cons = *cp->rx_cons_ptr;
  3817. cid_addr = GET_CID_ADDR(2);
  3818. val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE |
  3819. BNX2_L2CTX_CTX_TYPE_SIZE_L2 | (0x02 << 8);
  3820. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_CTX_TYPE, val);
  3821. if (sb_id == 0)
  3822. val = 2 << BNX2_L2CTX_L2_STATUSB_NUM_SHIFT;
  3823. else
  3824. val = BNX2_L2CTX_L2_STATUSB_NUM(sb_id);
  3825. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_HOST_BDIDX, val);
  3826. rxbd = udev->l2_ring + CNIC_PAGE_SIZE;
  3827. for (i = 0; i < BNX2_MAX_RX_DESC_CNT; i++, rxbd++) {
  3828. dma_addr_t buf_map;
  3829. int n = (i % cp->l2_rx_ring_size) + 1;
  3830. buf_map = udev->l2_buf_map + (n * cp->l2_single_buf_size);
  3831. rxbd->rx_bd_len = cp->l2_single_buf_size;
  3832. rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
  3833. rxbd->rx_bd_haddr_hi = (u64) buf_map >> 32;
  3834. rxbd->rx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
  3835. }
  3836. val = (u64) (ring_map + CNIC_PAGE_SIZE) >> 32;
  3837. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
  3838. rxbd->rx_bd_haddr_hi = val;
  3839. val = (u64) (ring_map + CNIC_PAGE_SIZE) & 0xffffffff;
  3840. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
  3841. rxbd->rx_bd_haddr_lo = val;
  3842. val = cnic_reg_rd_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD);
  3843. cnic_reg_wr_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD, val | (1 << 2));
  3844. }
  3845. static void cnic_shutdown_bnx2_rx_ring(struct cnic_dev *dev)
  3846. {
  3847. struct kwqe *wqes[1], l2kwqe;
  3848. memset(&l2kwqe, 0, sizeof(l2kwqe));
  3849. wqes[0] = &l2kwqe;
  3850. l2kwqe.kwqe_op_flag = (L2_LAYER_CODE << KWQE_LAYER_SHIFT) |
  3851. (L2_KWQE_OPCODE_VALUE_FLUSH <<
  3852. KWQE_OPCODE_SHIFT) | 2;
  3853. dev->submit_kwqes(dev, wqes, 1);
  3854. }
  3855. static void cnic_set_bnx2_mac(struct cnic_dev *dev)
  3856. {
  3857. struct cnic_local *cp = dev->cnic_priv;
  3858. u32 val;
  3859. val = cp->func << 2;
  3860. cp->shmem_base = cnic_reg_rd_ind(dev, BNX2_SHM_HDR_ADDR_0 + val);
  3861. val = cnic_reg_rd_ind(dev, cp->shmem_base +
  3862. BNX2_PORT_HW_CFG_ISCSI_MAC_UPPER);
  3863. dev->mac_addr[0] = (u8) (val >> 8);
  3864. dev->mac_addr[1] = (u8) val;
  3865. CNIC_WR(dev, BNX2_EMAC_MAC_MATCH4, val);
  3866. val = cnic_reg_rd_ind(dev, cp->shmem_base +
  3867. BNX2_PORT_HW_CFG_ISCSI_MAC_LOWER);
  3868. dev->mac_addr[2] = (u8) (val >> 24);
  3869. dev->mac_addr[3] = (u8) (val >> 16);
  3870. dev->mac_addr[4] = (u8) (val >> 8);
  3871. dev->mac_addr[5] = (u8) val;
  3872. CNIC_WR(dev, BNX2_EMAC_MAC_MATCH5, val);
  3873. val = 4 | BNX2_RPM_SORT_USER2_BC_EN;
  3874. if (BNX2_CHIP(cp) != BNX2_CHIP_5709)
  3875. val |= BNX2_RPM_SORT_USER2_PROM_VLAN;
  3876. CNIC_WR(dev, BNX2_RPM_SORT_USER2, 0x0);
  3877. CNIC_WR(dev, BNX2_RPM_SORT_USER2, val);
  3878. CNIC_WR(dev, BNX2_RPM_SORT_USER2, val | BNX2_RPM_SORT_USER2_ENA);
  3879. }
  3880. static int cnic_start_bnx2_hw(struct cnic_dev *dev)
  3881. {
  3882. struct cnic_local *cp = dev->cnic_priv;
  3883. struct cnic_eth_dev *ethdev = cp->ethdev;
  3884. struct status_block *sblk = cp->status_blk.gen;
  3885. u32 val, kcq_cid_addr, kwq_cid_addr;
  3886. int err;
  3887. cnic_set_bnx2_mac(dev);
  3888. val = CNIC_RD(dev, BNX2_MQ_CONFIG);
  3889. val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
  3890. if (CNIC_PAGE_BITS > 12)
  3891. val |= (12 - 8) << 4;
  3892. else
  3893. val |= (CNIC_PAGE_BITS - 8) << 4;
  3894. CNIC_WR(dev, BNX2_MQ_CONFIG, val);
  3895. CNIC_WR(dev, BNX2_HC_COMP_PROD_TRIP, (2 << 16) | 8);
  3896. CNIC_WR(dev, BNX2_HC_COM_TICKS, (64 << 16) | 220);
  3897. CNIC_WR(dev, BNX2_HC_CMD_TICKS, (64 << 16) | 220);
  3898. err = cnic_setup_5709_context(dev, 1);
  3899. if (err)
  3900. return err;
  3901. cnic_init_context(dev, KWQ_CID);
  3902. cnic_init_context(dev, KCQ_CID);
  3903. kwq_cid_addr = GET_CID_ADDR(KWQ_CID);
  3904. cp->kwq_io_addr = MB_GET_CID_ADDR(KWQ_CID) + L5_KRNLQ_HOST_QIDX;
  3905. cp->max_kwq_idx = MAX_KWQ_IDX;
  3906. cp->kwq_prod_idx = 0;
  3907. cp->kwq_con_idx = 0;
  3908. set_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags);
  3909. if (BNX2_CHIP(cp) == BNX2_CHIP_5706 || BNX2_CHIP(cp) == BNX2_CHIP_5708)
  3910. cp->kwq_con_idx_ptr = &sblk->status_rx_quick_consumer_index15;
  3911. else
  3912. cp->kwq_con_idx_ptr = &sblk->status_cmd_consumer_index;
  3913. /* Initialize the kernel work queue context. */
  3914. val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
  3915. (CNIC_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
  3916. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_TYPE, val);
  3917. val = (CNIC_PAGE_SIZE / sizeof(struct kwqe) - 1) << 16;
  3918. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
  3919. val = ((CNIC_PAGE_SIZE / sizeof(struct kwqe)) << 16) | KWQ_PAGE_CNT;
  3920. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
  3921. val = (u32) ((u64) cp->kwq_info.pgtbl_map >> 32);
  3922. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
  3923. val = (u32) cp->kwq_info.pgtbl_map;
  3924. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
  3925. kcq_cid_addr = GET_CID_ADDR(KCQ_CID);
  3926. cp->kcq1.io_addr = MB_GET_CID_ADDR(KCQ_CID) + L5_KRNLQ_HOST_QIDX;
  3927. cp->kcq1.sw_prod_idx = 0;
  3928. cp->kcq1.hw_prod_idx_ptr =
  3929. &sblk->status_completion_producer_index;
  3930. cp->kcq1.status_idx_ptr = &sblk->status_idx;
  3931. /* Initialize the kernel complete queue context. */
  3932. val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
  3933. (CNIC_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
  3934. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_TYPE, val);
  3935. val = (CNIC_PAGE_SIZE / sizeof(struct kcqe) - 1) << 16;
  3936. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
  3937. val = ((CNIC_PAGE_SIZE / sizeof(struct kcqe)) << 16) | KCQ_PAGE_CNT;
  3938. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
  3939. val = (u32) ((u64) cp->kcq1.dma.pgtbl_map >> 32);
  3940. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
  3941. val = (u32) cp->kcq1.dma.pgtbl_map;
  3942. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
  3943. cp->int_num = 0;
  3944. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3945. struct status_block_msix *msblk = cp->status_blk.bnx2;
  3946. u32 sb_id = cp->status_blk_num;
  3947. u32 sb = BNX2_L2CTX_L5_STATUSB_NUM(sb_id);
  3948. cp->kcq1.hw_prod_idx_ptr =
  3949. &msblk->status_completion_producer_index;
  3950. cp->kcq1.status_idx_ptr = &msblk->status_idx;
  3951. cp->kwq_con_idx_ptr = &msblk->status_cmd_consumer_index;
  3952. cp->int_num = sb_id << BNX2_PCICFG_INT_ACK_CMD_INT_NUM_SHIFT;
  3953. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
  3954. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
  3955. }
  3956. /* Enable Commnad Scheduler notification when we write to the
  3957. * host producer index of the kernel contexts. */
  3958. CNIC_WR(dev, BNX2_MQ_KNL_CMD_MASK1, 2);
  3959. /* Enable Command Scheduler notification when we write to either
  3960. * the Send Queue or Receive Queue producer indexes of the kernel
  3961. * bypass contexts. */
  3962. CNIC_WR(dev, BNX2_MQ_KNL_BYP_CMD_MASK1, 7);
  3963. CNIC_WR(dev, BNX2_MQ_KNL_BYP_WRITE_MASK1, 7);
  3964. /* Notify COM when the driver post an application buffer. */
  3965. CNIC_WR(dev, BNX2_MQ_KNL_RX_V2P_MASK2, 0x2000);
  3966. /* Set the CP and COM doorbells. These two processors polls the
  3967. * doorbell for a non zero value before running. This must be done
  3968. * after setting up the kernel queue contexts. */
  3969. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 1);
  3970. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 1);
  3971. cnic_init_bnx2_tx_ring(dev);
  3972. cnic_init_bnx2_rx_ring(dev);
  3973. err = cnic_init_bnx2_irq(dev);
  3974. if (err) {
  3975. netdev_err(dev->netdev, "cnic_init_irq failed\n");
  3976. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
  3977. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
  3978. return err;
  3979. }
  3980. ethdev->drv_state |= CNIC_DRV_STATE_HANDLES_IRQ;
  3981. return 0;
  3982. }
  3983. static void cnic_setup_bnx2x_context(struct cnic_dev *dev)
  3984. {
  3985. struct cnic_local *cp = dev->cnic_priv;
  3986. struct cnic_eth_dev *ethdev = cp->ethdev;
  3987. u32 start_offset = ethdev->ctx_tbl_offset;
  3988. int i;
  3989. for (i = 0; i < cp->ctx_blks; i++) {
  3990. struct cnic_ctx *ctx = &cp->ctx_arr[i];
  3991. dma_addr_t map = ctx->mapping;
  3992. if (cp->ctx_align) {
  3993. unsigned long mask = cp->ctx_align - 1;
  3994. map = (map + mask) & ~mask;
  3995. }
  3996. cnic_ctx_tbl_wr(dev, start_offset + i, map);
  3997. }
  3998. }
  3999. static int cnic_init_bnx2x_irq(struct cnic_dev *dev)
  4000. {
  4001. struct cnic_local *cp = dev->cnic_priv;
  4002. struct cnic_eth_dev *ethdev = cp->ethdev;
  4003. int err = 0;
  4004. tasklet_init(&cp->cnic_irq_task, cnic_service_bnx2x_bh,
  4005. (unsigned long) dev);
  4006. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)
  4007. err = cnic_request_irq(dev);
  4008. return err;
  4009. }
  4010. static inline void cnic_storm_memset_hc_disable(struct cnic_dev *dev,
  4011. u16 sb_id, u8 sb_index,
  4012. u8 disable)
  4013. {
  4014. struct bnx2x *bp = netdev_priv(dev->netdev);
  4015. u32 addr = BAR_CSTRORM_INTMEM +
  4016. CSTORM_STATUS_BLOCK_DATA_OFFSET(sb_id) +
  4017. offsetof(struct hc_status_block_data_e1x, index_data) +
  4018. sizeof(struct hc_index_data)*sb_index +
  4019. offsetof(struct hc_index_data, flags);
  4020. u16 flags = CNIC_RD16(dev, addr);
  4021. /* clear and set */
  4022. flags &= ~HC_INDEX_DATA_HC_ENABLED;
  4023. flags |= (((~disable) << HC_INDEX_DATA_HC_ENABLED_SHIFT) &
  4024. HC_INDEX_DATA_HC_ENABLED);
  4025. CNIC_WR16(dev, addr, flags);
  4026. }
  4027. static void cnic_enable_bnx2x_int(struct cnic_dev *dev)
  4028. {
  4029. struct cnic_local *cp = dev->cnic_priv;
  4030. struct bnx2x *bp = netdev_priv(dev->netdev);
  4031. u8 sb_id = cp->status_blk_num;
  4032. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  4033. CSTORM_STATUS_BLOCK_DATA_OFFSET(sb_id) +
  4034. offsetof(struct hc_status_block_data_e1x, index_data) +
  4035. sizeof(struct hc_index_data)*HC_INDEX_ISCSI_EQ_CONS +
  4036. offsetof(struct hc_index_data, timeout), 64 / 4);
  4037. cnic_storm_memset_hc_disable(dev, sb_id, HC_INDEX_ISCSI_EQ_CONS, 0);
  4038. }
  4039. static void cnic_disable_bnx2x_int_sync(struct cnic_dev *dev)
  4040. {
  4041. }
  4042. static void cnic_init_bnx2x_tx_ring(struct cnic_dev *dev,
  4043. struct client_init_ramrod_data *data)
  4044. {
  4045. struct cnic_local *cp = dev->cnic_priv;
  4046. struct bnx2x *bp = netdev_priv(dev->netdev);
  4047. struct cnic_uio_dev *udev = cp->udev;
  4048. union eth_tx_bd_types *txbd = (union eth_tx_bd_types *) udev->l2_ring;
  4049. dma_addr_t buf_map, ring_map = udev->l2_ring_map;
  4050. struct host_sp_status_block *sb = cp->bnx2x_def_status_blk;
  4051. int i;
  4052. u32 cli = cp->ethdev->iscsi_l2_client_id;
  4053. u32 val;
  4054. memset(txbd, 0, CNIC_PAGE_SIZE);
  4055. buf_map = udev->l2_buf_map;
  4056. for (i = 0; i < BNX2_MAX_TX_DESC_CNT; i += 3, txbd += 3) {
  4057. struct eth_tx_start_bd *start_bd = &txbd->start_bd;
  4058. struct eth_tx_parse_bd_e1x *pbd_e1x =
  4059. &((txbd + 1)->parse_bd_e1x);
  4060. struct eth_tx_parse_bd_e2 *pbd_e2 = &((txbd + 1)->parse_bd_e2);
  4061. struct eth_tx_bd *reg_bd = &((txbd + 2)->reg_bd);
  4062. start_bd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
  4063. start_bd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
  4064. reg_bd->addr_hi = start_bd->addr_hi;
  4065. reg_bd->addr_lo = start_bd->addr_lo + 0x10;
  4066. start_bd->nbytes = cpu_to_le16(0x10);
  4067. start_bd->nbd = cpu_to_le16(3);
  4068. start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
  4069. start_bd->general_data &= ~ETH_TX_START_BD_PARSE_NBDS;
  4070. start_bd->general_data |= (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
  4071. if (BNX2X_CHIP_IS_E2_PLUS(bp))
  4072. pbd_e2->parsing_data = (UNICAST_ADDRESS <<
  4073. ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT);
  4074. else
  4075. pbd_e1x->global_data = (UNICAST_ADDRESS <<
  4076. ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE_SHIFT);
  4077. }
  4078. val = (u64) ring_map >> 32;
  4079. txbd->next_bd.addr_hi = cpu_to_le32(val);
  4080. data->tx.tx_bd_page_base.hi = cpu_to_le32(val);
  4081. val = (u64) ring_map & 0xffffffff;
  4082. txbd->next_bd.addr_lo = cpu_to_le32(val);
  4083. data->tx.tx_bd_page_base.lo = cpu_to_le32(val);
  4084. /* Other ramrod params */
  4085. data->tx.tx_sb_index_number = HC_SP_INDEX_ETH_ISCSI_CQ_CONS;
  4086. data->tx.tx_status_block_id = BNX2X_DEF_SB_ID;
  4087. /* reset xstorm per client statistics */
  4088. if (cli < MAX_STAT_COUNTER_ID) {
  4089. data->general.statistics_zero_flg = 1;
  4090. data->general.statistics_en_flg = 1;
  4091. data->general.statistics_counter_id = cli;
  4092. }
  4093. cp->tx_cons_ptr =
  4094. &sb->sp_sb.index_values[HC_SP_INDEX_ETH_ISCSI_CQ_CONS];
  4095. }
  4096. static void cnic_init_bnx2x_rx_ring(struct cnic_dev *dev,
  4097. struct client_init_ramrod_data *data)
  4098. {
  4099. struct cnic_local *cp = dev->cnic_priv;
  4100. struct bnx2x *bp = netdev_priv(dev->netdev);
  4101. struct cnic_uio_dev *udev = cp->udev;
  4102. struct eth_rx_bd *rxbd = (struct eth_rx_bd *) (udev->l2_ring +
  4103. CNIC_PAGE_SIZE);
  4104. struct eth_rx_cqe_next_page *rxcqe = (struct eth_rx_cqe_next_page *)
  4105. (udev->l2_ring + (2 * CNIC_PAGE_SIZE));
  4106. struct host_sp_status_block *sb = cp->bnx2x_def_status_blk;
  4107. int i;
  4108. u32 cli = cp->ethdev->iscsi_l2_client_id;
  4109. int cl_qzone_id = BNX2X_CL_QZONE_ID(bp, cli);
  4110. u32 val;
  4111. dma_addr_t ring_map = udev->l2_ring_map;
  4112. /* General data */
  4113. data->general.client_id = cli;
  4114. data->general.activate_flg = 1;
  4115. data->general.sp_client_id = cli;
  4116. data->general.mtu = cpu_to_le16(cp->l2_single_buf_size - 14);
  4117. data->general.func_id = bp->pfid;
  4118. for (i = 0; i < BNX2X_MAX_RX_DESC_CNT; i++, rxbd++) {
  4119. dma_addr_t buf_map;
  4120. int n = (i % cp->l2_rx_ring_size) + 1;
  4121. buf_map = udev->l2_buf_map + (n * cp->l2_single_buf_size);
  4122. rxbd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
  4123. rxbd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
  4124. }
  4125. val = (u64) (ring_map + CNIC_PAGE_SIZE) >> 32;
  4126. rxbd->addr_hi = cpu_to_le32(val);
  4127. data->rx.bd_page_base.hi = cpu_to_le32(val);
  4128. val = (u64) (ring_map + CNIC_PAGE_SIZE) & 0xffffffff;
  4129. rxbd->addr_lo = cpu_to_le32(val);
  4130. data->rx.bd_page_base.lo = cpu_to_le32(val);
  4131. rxcqe += BNX2X_MAX_RCQ_DESC_CNT;
  4132. val = (u64) (ring_map + (2 * CNIC_PAGE_SIZE)) >> 32;
  4133. rxcqe->addr_hi = cpu_to_le32(val);
  4134. data->rx.cqe_page_base.hi = cpu_to_le32(val);
  4135. val = (u64) (ring_map + (2 * CNIC_PAGE_SIZE)) & 0xffffffff;
  4136. rxcqe->addr_lo = cpu_to_le32(val);
  4137. data->rx.cqe_page_base.lo = cpu_to_le32(val);
  4138. /* Other ramrod params */
  4139. data->rx.client_qzone_id = cl_qzone_id;
  4140. data->rx.rx_sb_index_number = HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS;
  4141. data->rx.status_block_id = BNX2X_DEF_SB_ID;
  4142. data->rx.cache_line_alignment_log_size = L1_CACHE_SHIFT;
  4143. data->rx.max_bytes_on_bd = cpu_to_le16(cp->l2_single_buf_size);
  4144. data->rx.outer_vlan_removal_enable_flg = 1;
  4145. data->rx.silent_vlan_removal_flg = 1;
  4146. data->rx.silent_vlan_value = 0;
  4147. data->rx.silent_vlan_mask = 0xffff;
  4148. cp->rx_cons_ptr =
  4149. &sb->sp_sb.index_values[HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS];
  4150. cp->rx_cons = *cp->rx_cons_ptr;
  4151. }
  4152. static void cnic_init_bnx2x_kcq(struct cnic_dev *dev)
  4153. {
  4154. struct cnic_local *cp = dev->cnic_priv;
  4155. struct bnx2x *bp = netdev_priv(dev->netdev);
  4156. u32 pfid = bp->pfid;
  4157. cp->kcq1.io_addr = BAR_CSTRORM_INTMEM +
  4158. CSTORM_ISCSI_EQ_PROD_OFFSET(pfid, 0);
  4159. cp->kcq1.sw_prod_idx = 0;
  4160. if (BNX2X_CHIP_IS_E2_PLUS(bp)) {
  4161. struct host_hc_status_block_e2 *sb = cp->status_blk.gen;
  4162. cp->kcq1.hw_prod_idx_ptr =
  4163. &sb->sb.index_values[HC_INDEX_ISCSI_EQ_CONS];
  4164. cp->kcq1.status_idx_ptr =
  4165. &sb->sb.running_index[SM_RX_ID];
  4166. } else {
  4167. struct host_hc_status_block_e1x *sb = cp->status_blk.gen;
  4168. cp->kcq1.hw_prod_idx_ptr =
  4169. &sb->sb.index_values[HC_INDEX_ISCSI_EQ_CONS];
  4170. cp->kcq1.status_idx_ptr =
  4171. &sb->sb.running_index[SM_RX_ID];
  4172. }
  4173. if (BNX2X_CHIP_IS_E2_PLUS(bp)) {
  4174. struct host_hc_status_block_e2 *sb = cp->status_blk.gen;
  4175. cp->kcq2.io_addr = BAR_USTRORM_INTMEM +
  4176. USTORM_FCOE_EQ_PROD_OFFSET(pfid);
  4177. cp->kcq2.sw_prod_idx = 0;
  4178. cp->kcq2.hw_prod_idx_ptr =
  4179. &sb->sb.index_values[HC_INDEX_FCOE_EQ_CONS];
  4180. cp->kcq2.status_idx_ptr =
  4181. &sb->sb.running_index[SM_RX_ID];
  4182. }
  4183. }
  4184. static int cnic_start_bnx2x_hw(struct cnic_dev *dev)
  4185. {
  4186. struct cnic_local *cp = dev->cnic_priv;
  4187. struct bnx2x *bp = netdev_priv(dev->netdev);
  4188. struct cnic_eth_dev *ethdev = cp->ethdev;
  4189. int func, ret;
  4190. u32 pfid;
  4191. dev->stats_addr = ethdev->addr_drv_info_to_mcp;
  4192. cp->func = bp->pf_num;
  4193. func = CNIC_FUNC(cp);
  4194. pfid = bp->pfid;
  4195. ret = cnic_init_id_tbl(&cp->cid_tbl, MAX_ISCSI_TBL_SZ,
  4196. cp->iscsi_start_cid, 0);
  4197. if (ret)
  4198. return -ENOMEM;
  4199. if (BNX2X_CHIP_IS_E2_PLUS(bp)) {
  4200. ret = cnic_init_id_tbl(&cp->fcoe_cid_tbl, dev->max_fcoe_conn,
  4201. cp->fcoe_start_cid, 0);
  4202. if (ret)
  4203. return -ENOMEM;
  4204. }
  4205. cp->bnx2x_igu_sb_id = ethdev->irq_arr[0].status_blk_num2;
  4206. cnic_init_bnx2x_kcq(dev);
  4207. /* Only 1 EQ */
  4208. CNIC_WR16(dev, cp->kcq1.io_addr, MAX_KCQ_IDX);
  4209. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4210. CSTORM_ISCSI_EQ_CONS_OFFSET(pfid, 0), 0);
  4211. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4212. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfid, 0),
  4213. cp->kcq1.dma.pg_map_arr[1] & 0xffffffff);
  4214. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4215. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfid, 0) + 4,
  4216. (u64) cp->kcq1.dma.pg_map_arr[1] >> 32);
  4217. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4218. CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfid, 0),
  4219. cp->kcq1.dma.pg_map_arr[0] & 0xffffffff);
  4220. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4221. CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfid, 0) + 4,
  4222. (u64) cp->kcq1.dma.pg_map_arr[0] >> 32);
  4223. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  4224. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(pfid, 0), 1);
  4225. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  4226. CSTORM_ISCSI_EQ_SB_NUM_OFFSET(pfid, 0), cp->status_blk_num);
  4227. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  4228. CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(pfid, 0),
  4229. HC_INDEX_ISCSI_EQ_CONS);
  4230. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  4231. USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfid),
  4232. cp->gbl_buf_info.pg_map_arr[0] & 0xffffffff);
  4233. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  4234. USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfid) + 4,
  4235. (u64) cp->gbl_buf_info.pg_map_arr[0] >> 32);
  4236. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  4237. TSTORM_ISCSI_TCP_LOCAL_ADV_WND_OFFSET(pfid), DEF_RCV_BUF);
  4238. cnic_setup_bnx2x_context(dev);
  4239. ret = cnic_init_bnx2x_irq(dev);
  4240. if (ret)
  4241. return ret;
  4242. ethdev->drv_state |= CNIC_DRV_STATE_HANDLES_IRQ;
  4243. return 0;
  4244. }
  4245. static void cnic_init_rings(struct cnic_dev *dev)
  4246. {
  4247. struct cnic_local *cp = dev->cnic_priv;
  4248. struct bnx2x *bp = netdev_priv(dev->netdev);
  4249. struct cnic_uio_dev *udev = cp->udev;
  4250. if (test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
  4251. return;
  4252. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  4253. cnic_init_bnx2_tx_ring(dev);
  4254. cnic_init_bnx2_rx_ring(dev);
  4255. set_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
  4256. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  4257. u32 cli = cp->ethdev->iscsi_l2_client_id;
  4258. u32 cid = cp->ethdev->iscsi_l2_cid;
  4259. u32 cl_qzone_id;
  4260. struct client_init_ramrod_data *data;
  4261. union l5cm_specific_data l5_data;
  4262. struct ustorm_eth_rx_producers rx_prods = {0};
  4263. u32 off, i, *cid_ptr;
  4264. rx_prods.bd_prod = 0;
  4265. rx_prods.cqe_prod = BNX2X_MAX_RCQ_DESC_CNT;
  4266. barrier();
  4267. cl_qzone_id = BNX2X_CL_QZONE_ID(bp, cli);
  4268. off = BAR_USTRORM_INTMEM +
  4269. (BNX2X_CHIP_IS_E2_PLUS(bp) ?
  4270. USTORM_RX_PRODS_E2_OFFSET(cl_qzone_id) :
  4271. USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), cli));
  4272. for (i = 0; i < sizeof(struct ustorm_eth_rx_producers) / 4; i++)
  4273. CNIC_WR(dev, off + i * 4, ((u32 *) &rx_prods)[i]);
  4274. set_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  4275. data = udev->l2_buf;
  4276. cid_ptr = udev->l2_buf + 12;
  4277. memset(data, 0, sizeof(*data));
  4278. cnic_init_bnx2x_tx_ring(dev, data);
  4279. cnic_init_bnx2x_rx_ring(dev, data);
  4280. l5_data.phy_address.lo = udev->l2_buf_map & 0xffffffff;
  4281. l5_data.phy_address.hi = (u64) udev->l2_buf_map >> 32;
  4282. set_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
  4283. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_CLIENT_SETUP,
  4284. cid, ETH_CONNECTION_TYPE, &l5_data);
  4285. i = 0;
  4286. while (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags) &&
  4287. ++i < 10)
  4288. msleep(1);
  4289. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  4290. netdev_err(dev->netdev,
  4291. "iSCSI CLIENT_SETUP did not complete\n");
  4292. cnic_spq_completion(dev, DRV_CTL_RET_L2_SPQ_CREDIT_CMD, 1);
  4293. cnic_ring_ctl(dev, cid, cli, 1);
  4294. *cid_ptr = cid >> 4;
  4295. *(cid_ptr + 1) = cid * bp->db_size;
  4296. *(cid_ptr + 2) = UIO_USE_TX_DOORBELL;
  4297. }
  4298. }
  4299. static void cnic_shutdown_rings(struct cnic_dev *dev)
  4300. {
  4301. struct cnic_local *cp = dev->cnic_priv;
  4302. struct cnic_uio_dev *udev = cp->udev;
  4303. void *rx_ring;
  4304. if (!test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
  4305. return;
  4306. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  4307. cnic_shutdown_bnx2_rx_ring(dev);
  4308. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  4309. u32 cli = cp->ethdev->iscsi_l2_client_id;
  4310. u32 cid = cp->ethdev->iscsi_l2_cid;
  4311. union l5cm_specific_data l5_data;
  4312. int i;
  4313. cnic_ring_ctl(dev, cid, cli, 0);
  4314. set_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  4315. l5_data.phy_address.lo = cli;
  4316. l5_data.phy_address.hi = 0;
  4317. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_HALT,
  4318. cid, ETH_CONNECTION_TYPE, &l5_data);
  4319. i = 0;
  4320. while (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags) &&
  4321. ++i < 10)
  4322. msleep(1);
  4323. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  4324. netdev_err(dev->netdev,
  4325. "iSCSI CLIENT_HALT did not complete\n");
  4326. cnic_spq_completion(dev, DRV_CTL_RET_L2_SPQ_CREDIT_CMD, 1);
  4327. memset(&l5_data, 0, sizeof(l5_data));
  4328. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_COMMON_CFC_DEL,
  4329. cid, NONE_CONNECTION_TYPE, &l5_data);
  4330. msleep(10);
  4331. }
  4332. clear_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
  4333. rx_ring = udev->l2_ring + CNIC_PAGE_SIZE;
  4334. memset(rx_ring, 0, CNIC_PAGE_SIZE);
  4335. }
  4336. static int cnic_register_netdev(struct cnic_dev *dev)
  4337. {
  4338. struct cnic_local *cp = dev->cnic_priv;
  4339. struct cnic_eth_dev *ethdev = cp->ethdev;
  4340. int err;
  4341. if (!ethdev)
  4342. return -ENODEV;
  4343. if (ethdev->drv_state & CNIC_DRV_STATE_REGD)
  4344. return 0;
  4345. err = ethdev->drv_register_cnic(dev->netdev, cp->cnic_ops, dev);
  4346. if (err)
  4347. netdev_err(dev->netdev, "register_cnic failed\n");
  4348. /* Read iSCSI config again. On some bnx2x device, iSCSI config
  4349. * can change after firmware is downloaded.
  4350. */
  4351. dev->max_iscsi_conn = ethdev->max_iscsi_conn;
  4352. if (ethdev->drv_state & CNIC_DRV_STATE_NO_ISCSI)
  4353. dev->max_iscsi_conn = 0;
  4354. return err;
  4355. }
  4356. static void cnic_unregister_netdev(struct cnic_dev *dev)
  4357. {
  4358. struct cnic_local *cp = dev->cnic_priv;
  4359. struct cnic_eth_dev *ethdev = cp->ethdev;
  4360. if (!ethdev)
  4361. return;
  4362. ethdev->drv_unregister_cnic(dev->netdev);
  4363. }
  4364. static int cnic_start_hw(struct cnic_dev *dev)
  4365. {
  4366. struct cnic_local *cp = dev->cnic_priv;
  4367. struct cnic_eth_dev *ethdev = cp->ethdev;
  4368. int err;
  4369. if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
  4370. return -EALREADY;
  4371. dev->regview = ethdev->io_base;
  4372. pci_dev_get(dev->pcidev);
  4373. cp->func = PCI_FUNC(dev->pcidev->devfn);
  4374. cp->status_blk.gen = ethdev->irq_arr[0].status_blk;
  4375. cp->status_blk_num = ethdev->irq_arr[0].status_blk_num;
  4376. err = cp->alloc_resc(dev);
  4377. if (err) {
  4378. netdev_err(dev->netdev, "allocate resource failure\n");
  4379. goto err1;
  4380. }
  4381. err = cp->start_hw(dev);
  4382. if (err)
  4383. goto err1;
  4384. err = cnic_cm_open(dev);
  4385. if (err)
  4386. goto err1;
  4387. set_bit(CNIC_F_CNIC_UP, &dev->flags);
  4388. cp->enable_int(dev);
  4389. return 0;
  4390. err1:
  4391. cp->free_resc(dev);
  4392. pci_dev_put(dev->pcidev);
  4393. return err;
  4394. }
  4395. static void cnic_stop_bnx2_hw(struct cnic_dev *dev)
  4396. {
  4397. cnic_disable_bnx2_int_sync(dev);
  4398. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
  4399. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
  4400. cnic_init_context(dev, KWQ_CID);
  4401. cnic_init_context(dev, KCQ_CID);
  4402. cnic_setup_5709_context(dev, 0);
  4403. cnic_free_irq(dev);
  4404. cnic_free_resc(dev);
  4405. }
  4406. static void cnic_stop_bnx2x_hw(struct cnic_dev *dev)
  4407. {
  4408. struct cnic_local *cp = dev->cnic_priv;
  4409. struct bnx2x *bp = netdev_priv(dev->netdev);
  4410. u32 hc_index = HC_INDEX_ISCSI_EQ_CONS;
  4411. u32 sb_id = cp->status_blk_num;
  4412. u32 idx_off, syn_off;
  4413. cnic_free_irq(dev);
  4414. if (BNX2X_CHIP_IS_E2_PLUS(bp)) {
  4415. idx_off = offsetof(struct hc_status_block_e2, index_values) +
  4416. (hc_index * sizeof(u16));
  4417. syn_off = CSTORM_HC_SYNC_LINE_INDEX_E2_OFFSET(hc_index, sb_id);
  4418. } else {
  4419. idx_off = offsetof(struct hc_status_block_e1x, index_values) +
  4420. (hc_index * sizeof(u16));
  4421. syn_off = CSTORM_HC_SYNC_LINE_INDEX_E1X_OFFSET(hc_index, sb_id);
  4422. }
  4423. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + syn_off, 0);
  4424. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_STATUS_BLOCK_OFFSET(sb_id) +
  4425. idx_off, 0);
  4426. *cp->kcq1.hw_prod_idx_ptr = 0;
  4427. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4428. CSTORM_ISCSI_EQ_CONS_OFFSET(bp->pfid, 0), 0);
  4429. CNIC_WR16(dev, cp->kcq1.io_addr, 0);
  4430. cnic_free_resc(dev);
  4431. }
  4432. static void cnic_stop_hw(struct cnic_dev *dev)
  4433. {
  4434. if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  4435. struct cnic_local *cp = dev->cnic_priv;
  4436. int i = 0;
  4437. /* Need to wait for the ring shutdown event to complete
  4438. * before clearing the CNIC_UP flag.
  4439. */
  4440. while (cp->udev && cp->udev->uio_dev != -1 && i < 15) {
  4441. msleep(100);
  4442. i++;
  4443. }
  4444. cnic_shutdown_rings(dev);
  4445. cp->stop_cm(dev);
  4446. cp->ethdev->drv_state &= ~CNIC_DRV_STATE_HANDLES_IRQ;
  4447. clear_bit(CNIC_F_CNIC_UP, &dev->flags);
  4448. RCU_INIT_POINTER(cp->ulp_ops[CNIC_ULP_L4], NULL);
  4449. synchronize_rcu();
  4450. cnic_cm_shutdown(dev);
  4451. cp->stop_hw(dev);
  4452. pci_dev_put(dev->pcidev);
  4453. }
  4454. }
  4455. static void cnic_free_dev(struct cnic_dev *dev)
  4456. {
  4457. int i = 0;
  4458. while ((atomic_read(&dev->ref_count) != 0) && i < 10) {
  4459. msleep(100);
  4460. i++;
  4461. }
  4462. if (atomic_read(&dev->ref_count) != 0)
  4463. netdev_err(dev->netdev, "Failed waiting for ref count to go to zero\n");
  4464. netdev_info(dev->netdev, "Removed CNIC device\n");
  4465. dev_put(dev->netdev);
  4466. kfree(dev);
  4467. }
  4468. static struct cnic_dev *cnic_alloc_dev(struct net_device *dev,
  4469. struct pci_dev *pdev)
  4470. {
  4471. struct cnic_dev *cdev;
  4472. struct cnic_local *cp;
  4473. int alloc_size;
  4474. alloc_size = sizeof(struct cnic_dev) + sizeof(struct cnic_local);
  4475. cdev = kzalloc(alloc_size, GFP_KERNEL);
  4476. if (cdev == NULL)
  4477. return NULL;
  4478. cdev->netdev = dev;
  4479. cdev->cnic_priv = (char *)cdev + sizeof(struct cnic_dev);
  4480. cdev->register_device = cnic_register_device;
  4481. cdev->unregister_device = cnic_unregister_device;
  4482. cdev->iscsi_nl_msg_recv = cnic_iscsi_nl_msg_recv;
  4483. cp = cdev->cnic_priv;
  4484. cp->dev = cdev;
  4485. cp->l2_single_buf_size = 0x400;
  4486. cp->l2_rx_ring_size = 3;
  4487. spin_lock_init(&cp->cnic_ulp_lock);
  4488. netdev_info(dev, "Added CNIC device\n");
  4489. return cdev;
  4490. }
  4491. static struct cnic_dev *init_bnx2_cnic(struct net_device *dev)
  4492. {
  4493. struct pci_dev *pdev;
  4494. struct cnic_dev *cdev;
  4495. struct cnic_local *cp;
  4496. struct bnx2 *bp = netdev_priv(dev);
  4497. struct cnic_eth_dev *ethdev = NULL;
  4498. if (bp->cnic_probe)
  4499. ethdev = (bp->cnic_probe)(dev);
  4500. if (!ethdev)
  4501. return NULL;
  4502. pdev = ethdev->pdev;
  4503. if (!pdev)
  4504. return NULL;
  4505. dev_hold(dev);
  4506. pci_dev_get(pdev);
  4507. if ((pdev->device == PCI_DEVICE_ID_NX2_5709 ||
  4508. pdev->device == PCI_DEVICE_ID_NX2_5709S) &&
  4509. (pdev->revision < 0x10)) {
  4510. pci_dev_put(pdev);
  4511. goto cnic_err;
  4512. }
  4513. pci_dev_put(pdev);
  4514. cdev = cnic_alloc_dev(dev, pdev);
  4515. if (cdev == NULL)
  4516. goto cnic_err;
  4517. set_bit(CNIC_F_BNX2_CLASS, &cdev->flags);
  4518. cdev->submit_kwqes = cnic_submit_bnx2_kwqes;
  4519. cp = cdev->cnic_priv;
  4520. cp->ethdev = ethdev;
  4521. cdev->pcidev = pdev;
  4522. cp->chip_id = ethdev->chip_id;
  4523. cdev->max_iscsi_conn = ethdev->max_iscsi_conn;
  4524. cp->cnic_ops = &cnic_bnx2_ops;
  4525. cp->start_hw = cnic_start_bnx2_hw;
  4526. cp->stop_hw = cnic_stop_bnx2_hw;
  4527. cp->setup_pgtbl = cnic_setup_page_tbl;
  4528. cp->alloc_resc = cnic_alloc_bnx2_resc;
  4529. cp->free_resc = cnic_free_resc;
  4530. cp->start_cm = cnic_cm_init_bnx2_hw;
  4531. cp->stop_cm = cnic_cm_stop_bnx2_hw;
  4532. cp->enable_int = cnic_enable_bnx2_int;
  4533. cp->disable_int_sync = cnic_disable_bnx2_int_sync;
  4534. cp->close_conn = cnic_close_bnx2_conn;
  4535. return cdev;
  4536. cnic_err:
  4537. dev_put(dev);
  4538. return NULL;
  4539. }
  4540. static struct cnic_dev *init_bnx2x_cnic(struct net_device *dev)
  4541. {
  4542. struct pci_dev *pdev;
  4543. struct cnic_dev *cdev;
  4544. struct cnic_local *cp;
  4545. struct bnx2x *bp = netdev_priv(dev);
  4546. struct cnic_eth_dev *ethdev = NULL;
  4547. if (bp->cnic_probe)
  4548. ethdev = bp->cnic_probe(dev);
  4549. if (!ethdev)
  4550. return NULL;
  4551. pdev = ethdev->pdev;
  4552. if (!pdev)
  4553. return NULL;
  4554. dev_hold(dev);
  4555. cdev = cnic_alloc_dev(dev, pdev);
  4556. if (cdev == NULL) {
  4557. dev_put(dev);
  4558. return NULL;
  4559. }
  4560. set_bit(CNIC_F_BNX2X_CLASS, &cdev->flags);
  4561. cdev->submit_kwqes = cnic_submit_bnx2x_kwqes;
  4562. cp = cdev->cnic_priv;
  4563. cp->ethdev = ethdev;
  4564. cdev->pcidev = pdev;
  4565. cp->chip_id = ethdev->chip_id;
  4566. cdev->stats_addr = ethdev->addr_drv_info_to_mcp;
  4567. if (!(ethdev->drv_state & CNIC_DRV_STATE_NO_ISCSI))
  4568. cdev->max_iscsi_conn = ethdev->max_iscsi_conn;
  4569. if (CNIC_SUPPORTS_FCOE(bp)) {
  4570. cdev->max_fcoe_conn = ethdev->max_fcoe_conn;
  4571. cdev->max_fcoe_exchanges = ethdev->max_fcoe_exchanges;
  4572. }
  4573. if (cdev->max_fcoe_conn > BNX2X_FCOE_NUM_CONNECTIONS)
  4574. cdev->max_fcoe_conn = BNX2X_FCOE_NUM_CONNECTIONS;
  4575. memcpy(cdev->mac_addr, ethdev->iscsi_mac, ETH_ALEN);
  4576. cp->cnic_ops = &cnic_bnx2x_ops;
  4577. cp->start_hw = cnic_start_bnx2x_hw;
  4578. cp->stop_hw = cnic_stop_bnx2x_hw;
  4579. cp->setup_pgtbl = cnic_setup_page_tbl_le;
  4580. cp->alloc_resc = cnic_alloc_bnx2x_resc;
  4581. cp->free_resc = cnic_free_resc;
  4582. cp->start_cm = cnic_cm_init_bnx2x_hw;
  4583. cp->stop_cm = cnic_cm_stop_bnx2x_hw;
  4584. cp->enable_int = cnic_enable_bnx2x_int;
  4585. cp->disable_int_sync = cnic_disable_bnx2x_int_sync;
  4586. if (BNX2X_CHIP_IS_E2_PLUS(bp)) {
  4587. cp->ack_int = cnic_ack_bnx2x_e2_msix;
  4588. cp->arm_int = cnic_arm_bnx2x_e2_msix;
  4589. } else {
  4590. cp->ack_int = cnic_ack_bnx2x_msix;
  4591. cp->arm_int = cnic_arm_bnx2x_msix;
  4592. }
  4593. cp->close_conn = cnic_close_bnx2x_conn;
  4594. return cdev;
  4595. }
  4596. static struct cnic_dev *is_cnic_dev(struct net_device *dev)
  4597. {
  4598. struct ethtool_drvinfo drvinfo;
  4599. struct cnic_dev *cdev = NULL;
  4600. if (dev->ethtool_ops && dev->ethtool_ops->get_drvinfo) {
  4601. memset(&drvinfo, 0, sizeof(drvinfo));
  4602. dev->ethtool_ops->get_drvinfo(dev, &drvinfo);
  4603. if (!strcmp(drvinfo.driver, "bnx2"))
  4604. cdev = init_bnx2_cnic(dev);
  4605. if (!strcmp(drvinfo.driver, "bnx2x"))
  4606. cdev = init_bnx2x_cnic(dev);
  4607. if (cdev) {
  4608. write_lock(&cnic_dev_lock);
  4609. list_add(&cdev->list, &cnic_dev_list);
  4610. write_unlock(&cnic_dev_lock);
  4611. }
  4612. }
  4613. return cdev;
  4614. }
  4615. static void cnic_rcv_netevent(struct cnic_local *cp, unsigned long event,
  4616. u16 vlan_id)
  4617. {
  4618. int if_type;
  4619. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
  4620. struct cnic_ulp_ops *ulp_ops;
  4621. void *ctx;
  4622. mutex_lock(&cnic_lock);
  4623. ulp_ops = rcu_dereference_protected(cp->ulp_ops[if_type],
  4624. lockdep_is_held(&cnic_lock));
  4625. if (!ulp_ops || !ulp_ops->indicate_netevent) {
  4626. mutex_unlock(&cnic_lock);
  4627. continue;
  4628. }
  4629. ctx = cp->ulp_handle[if_type];
  4630. set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  4631. mutex_unlock(&cnic_lock);
  4632. ulp_ops->indicate_netevent(ctx, event, vlan_id);
  4633. clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  4634. }
  4635. }
  4636. /* netdev event handler */
  4637. static int cnic_netdev_event(struct notifier_block *this, unsigned long event,
  4638. void *ptr)
  4639. {
  4640. struct net_device *netdev = netdev_notifier_info_to_dev(ptr);
  4641. struct cnic_dev *dev;
  4642. int new_dev = 0;
  4643. dev = cnic_from_netdev(netdev);
  4644. if (!dev && event == NETDEV_REGISTER) {
  4645. /* Check for the hot-plug device */
  4646. dev = is_cnic_dev(netdev);
  4647. if (dev) {
  4648. new_dev = 1;
  4649. cnic_hold(dev);
  4650. }
  4651. }
  4652. if (dev) {
  4653. struct cnic_local *cp = dev->cnic_priv;
  4654. if (new_dev)
  4655. cnic_ulp_init(dev);
  4656. else if (event == NETDEV_UNREGISTER)
  4657. cnic_ulp_exit(dev);
  4658. if (event == NETDEV_UP) {
  4659. if (cnic_register_netdev(dev) != 0) {
  4660. cnic_put(dev);
  4661. goto done;
  4662. }
  4663. if (!cnic_start_hw(dev))
  4664. cnic_ulp_start(dev);
  4665. }
  4666. cnic_rcv_netevent(cp, event, 0);
  4667. if (event == NETDEV_GOING_DOWN) {
  4668. cnic_ulp_stop(dev);
  4669. cnic_stop_hw(dev);
  4670. cnic_unregister_netdev(dev);
  4671. } else if (event == NETDEV_UNREGISTER) {
  4672. write_lock(&cnic_dev_lock);
  4673. list_del_init(&dev->list);
  4674. write_unlock(&cnic_dev_lock);
  4675. cnic_put(dev);
  4676. cnic_free_dev(dev);
  4677. goto done;
  4678. }
  4679. cnic_put(dev);
  4680. } else {
  4681. struct net_device *realdev;
  4682. u16 vid;
  4683. vid = cnic_get_vlan(netdev, &realdev);
  4684. if (realdev) {
  4685. dev = cnic_from_netdev(realdev);
  4686. if (dev) {
  4687. vid |= VLAN_TAG_PRESENT;
  4688. cnic_rcv_netevent(dev->cnic_priv, event, vid);
  4689. cnic_put(dev);
  4690. }
  4691. }
  4692. }
  4693. done:
  4694. return NOTIFY_DONE;
  4695. }
  4696. static struct notifier_block cnic_netdev_notifier = {
  4697. .notifier_call = cnic_netdev_event
  4698. };
  4699. static void cnic_release(void)
  4700. {
  4701. struct cnic_uio_dev *udev;
  4702. while (!list_empty(&cnic_udev_list)) {
  4703. udev = list_entry(cnic_udev_list.next, struct cnic_uio_dev,
  4704. list);
  4705. cnic_free_uio(udev);
  4706. }
  4707. }
  4708. static int __init cnic_init(void)
  4709. {
  4710. int rc = 0;
  4711. pr_info("%s", version);
  4712. rc = register_netdevice_notifier(&cnic_netdev_notifier);
  4713. if (rc) {
  4714. cnic_release();
  4715. return rc;
  4716. }
  4717. cnic_wq = create_singlethread_workqueue("cnic_wq");
  4718. if (!cnic_wq) {
  4719. cnic_release();
  4720. unregister_netdevice_notifier(&cnic_netdev_notifier);
  4721. return -ENOMEM;
  4722. }
  4723. return 0;
  4724. }
  4725. static void __exit cnic_exit(void)
  4726. {
  4727. unregister_netdevice_notifier(&cnic_netdev_notifier);
  4728. cnic_release();
  4729. destroy_workqueue(cnic_wq);
  4730. }
  4731. module_init(cnic_init);
  4732. module_exit(cnic_exit);