omap-mailbox.c 17 KB

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  1. /*
  2. * OMAP mailbox driver
  3. *
  4. * Copyright (C) 2006-2009 Nokia Corporation. All rights reserved.
  5. * Copyright (C) 2013-2014 Texas Instruments Inc.
  6. *
  7. * Contact: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
  8. * Suman Anna <s-anna@ti.com>
  9. *
  10. * This program is free software; you can redistribute it and/or
  11. * modify it under the terms of the GNU General Public License
  12. * version 2 as published by the Free Software Foundation.
  13. *
  14. * This program is distributed in the hope that it will be useful, but
  15. * WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  17. * General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  22. * 02110-1301 USA
  23. *
  24. */
  25. #include <linux/interrupt.h>
  26. #include <linux/spinlock.h>
  27. #include <linux/mutex.h>
  28. #include <linux/slab.h>
  29. #include <linux/kfifo.h>
  30. #include <linux/err.h>
  31. #include <linux/notifier.h>
  32. #include <linux/module.h>
  33. #include <linux/platform_device.h>
  34. #include <linux/pm_runtime.h>
  35. #include <linux/platform_data/mailbox-omap.h>
  36. #include <linux/omap-mailbox.h>
  37. #define MAILBOX_REVISION 0x000
  38. #define MAILBOX_MESSAGE(m) (0x040 + 4 * (m))
  39. #define MAILBOX_FIFOSTATUS(m) (0x080 + 4 * (m))
  40. #define MAILBOX_MSGSTATUS(m) (0x0c0 + 4 * (m))
  41. #define OMAP2_MAILBOX_IRQSTATUS(u) (0x100 + 8 * (u))
  42. #define OMAP2_MAILBOX_IRQENABLE(u) (0x104 + 8 * (u))
  43. #define OMAP4_MAILBOX_IRQSTATUS(u) (0x104 + 0x10 * (u))
  44. #define OMAP4_MAILBOX_IRQENABLE(u) (0x108 + 0x10 * (u))
  45. #define OMAP4_MAILBOX_IRQENABLE_CLR(u) (0x10c + 0x10 * (u))
  46. #define MAILBOX_IRQSTATUS(type, u) (type ? OMAP4_MAILBOX_IRQSTATUS(u) : \
  47. OMAP2_MAILBOX_IRQSTATUS(u))
  48. #define MAILBOX_IRQENABLE(type, u) (type ? OMAP4_MAILBOX_IRQENABLE(u) : \
  49. OMAP2_MAILBOX_IRQENABLE(u))
  50. #define MAILBOX_IRQDISABLE(type, u) (type ? OMAP4_MAILBOX_IRQENABLE_CLR(u) \
  51. : OMAP2_MAILBOX_IRQENABLE(u))
  52. #define MAILBOX_IRQ_NEWMSG(m) (1 << (2 * (m)))
  53. #define MAILBOX_IRQ_NOTFULL(m) (1 << (2 * (m) + 1))
  54. #define MBOX_REG_SIZE 0x120
  55. #define OMAP4_MBOX_REG_SIZE 0x130
  56. #define MBOX_NR_REGS (MBOX_REG_SIZE / sizeof(u32))
  57. #define OMAP4_MBOX_NR_REGS (OMAP4_MBOX_REG_SIZE / sizeof(u32))
  58. struct omap_mbox_fifo {
  59. unsigned long msg;
  60. unsigned long fifo_stat;
  61. unsigned long msg_stat;
  62. unsigned long irqenable;
  63. unsigned long irqstatus;
  64. unsigned long irqdisable;
  65. u32 intr_bit;
  66. };
  67. struct omap_mbox_queue {
  68. spinlock_t lock;
  69. struct kfifo fifo;
  70. struct work_struct work;
  71. struct tasklet_struct tasklet;
  72. struct omap_mbox *mbox;
  73. bool full;
  74. };
  75. struct omap_mbox_device {
  76. struct device *dev;
  77. struct mutex cfg_lock;
  78. void __iomem *mbox_base;
  79. u32 num_users;
  80. u32 num_fifos;
  81. struct omap_mbox **mboxes;
  82. struct list_head elem;
  83. };
  84. struct omap_mbox {
  85. const char *name;
  86. int irq;
  87. struct omap_mbox_queue *txq, *rxq;
  88. struct device *dev;
  89. struct omap_mbox_device *parent;
  90. struct omap_mbox_fifo tx_fifo;
  91. struct omap_mbox_fifo rx_fifo;
  92. u32 ctx[OMAP4_MBOX_NR_REGS];
  93. u32 intr_type;
  94. int use_count;
  95. struct blocking_notifier_head notifier;
  96. };
  97. /* global variables for the mailbox devices */
  98. static DEFINE_MUTEX(omap_mbox_devices_lock);
  99. static LIST_HEAD(omap_mbox_devices);
  100. static unsigned int mbox_kfifo_size = CONFIG_OMAP_MBOX_KFIFO_SIZE;
  101. module_param(mbox_kfifo_size, uint, S_IRUGO);
  102. MODULE_PARM_DESC(mbox_kfifo_size, "Size of omap's mailbox kfifo (bytes)");
  103. static inline
  104. unsigned int mbox_read_reg(struct omap_mbox_device *mdev, size_t ofs)
  105. {
  106. return __raw_readl(mdev->mbox_base + ofs);
  107. }
  108. static inline
  109. void mbox_write_reg(struct omap_mbox_device *mdev, u32 val, size_t ofs)
  110. {
  111. __raw_writel(val, mdev->mbox_base + ofs);
  112. }
  113. /* Mailbox FIFO handle functions */
  114. static mbox_msg_t mbox_fifo_read(struct omap_mbox *mbox)
  115. {
  116. struct omap_mbox_fifo *fifo = &mbox->rx_fifo;
  117. return (mbox_msg_t) mbox_read_reg(mbox->parent, fifo->msg);
  118. }
  119. static void mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg)
  120. {
  121. struct omap_mbox_fifo *fifo = &mbox->tx_fifo;
  122. mbox_write_reg(mbox->parent, msg, fifo->msg);
  123. }
  124. static int mbox_fifo_empty(struct omap_mbox *mbox)
  125. {
  126. struct omap_mbox_fifo *fifo = &mbox->rx_fifo;
  127. return (mbox_read_reg(mbox->parent, fifo->msg_stat) == 0);
  128. }
  129. static int mbox_fifo_full(struct omap_mbox *mbox)
  130. {
  131. struct omap_mbox_fifo *fifo = &mbox->tx_fifo;
  132. return mbox_read_reg(mbox->parent, fifo->fifo_stat);
  133. }
  134. /* Mailbox IRQ handle functions */
  135. static void ack_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
  136. {
  137. struct omap_mbox_fifo *fifo = (irq == IRQ_TX) ?
  138. &mbox->tx_fifo : &mbox->rx_fifo;
  139. u32 bit = fifo->intr_bit;
  140. u32 irqstatus = fifo->irqstatus;
  141. mbox_write_reg(mbox->parent, bit, irqstatus);
  142. /* Flush posted write for irq status to avoid spurious interrupts */
  143. mbox_read_reg(mbox->parent, irqstatus);
  144. }
  145. static int is_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
  146. {
  147. struct omap_mbox_fifo *fifo = (irq == IRQ_TX) ?
  148. &mbox->tx_fifo : &mbox->rx_fifo;
  149. u32 bit = fifo->intr_bit;
  150. u32 irqenable = fifo->irqenable;
  151. u32 irqstatus = fifo->irqstatus;
  152. u32 enable = mbox_read_reg(mbox->parent, irqenable);
  153. u32 status = mbox_read_reg(mbox->parent, irqstatus);
  154. return (int)(enable & status & bit);
  155. }
  156. /*
  157. * message sender
  158. */
  159. int omap_mbox_msg_send(struct omap_mbox *mbox, mbox_msg_t msg)
  160. {
  161. struct omap_mbox_queue *mq = mbox->txq;
  162. int ret = 0, len;
  163. spin_lock_bh(&mq->lock);
  164. if (kfifo_avail(&mq->fifo) < sizeof(msg)) {
  165. ret = -ENOMEM;
  166. goto out;
  167. }
  168. if (kfifo_is_empty(&mq->fifo) && !mbox_fifo_full(mbox)) {
  169. mbox_fifo_write(mbox, msg);
  170. goto out;
  171. }
  172. len = kfifo_in(&mq->fifo, (unsigned char *)&msg, sizeof(msg));
  173. WARN_ON(len != sizeof(msg));
  174. tasklet_schedule(&mbox->txq->tasklet);
  175. out:
  176. spin_unlock_bh(&mq->lock);
  177. return ret;
  178. }
  179. EXPORT_SYMBOL(omap_mbox_msg_send);
  180. void omap_mbox_save_ctx(struct omap_mbox *mbox)
  181. {
  182. int i;
  183. int nr_regs;
  184. if (mbox->intr_type)
  185. nr_regs = OMAP4_MBOX_NR_REGS;
  186. else
  187. nr_regs = MBOX_NR_REGS;
  188. for (i = 0; i < nr_regs; i++) {
  189. mbox->ctx[i] = mbox_read_reg(mbox->parent, i * sizeof(u32));
  190. dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__,
  191. i, mbox->ctx[i]);
  192. }
  193. }
  194. EXPORT_SYMBOL(omap_mbox_save_ctx);
  195. void omap_mbox_restore_ctx(struct omap_mbox *mbox)
  196. {
  197. int i;
  198. int nr_regs;
  199. if (mbox->intr_type)
  200. nr_regs = OMAP4_MBOX_NR_REGS;
  201. else
  202. nr_regs = MBOX_NR_REGS;
  203. for (i = 0; i < nr_regs; i++) {
  204. mbox_write_reg(mbox->parent, mbox->ctx[i], i * sizeof(u32));
  205. dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__,
  206. i, mbox->ctx[i]);
  207. }
  208. }
  209. EXPORT_SYMBOL(omap_mbox_restore_ctx);
  210. void omap_mbox_enable_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
  211. {
  212. u32 l;
  213. struct omap_mbox_fifo *fifo = (irq == IRQ_TX) ?
  214. &mbox->tx_fifo : &mbox->rx_fifo;
  215. u32 bit = fifo->intr_bit;
  216. u32 irqenable = fifo->irqenable;
  217. l = mbox_read_reg(mbox->parent, irqenable);
  218. l |= bit;
  219. mbox_write_reg(mbox->parent, l, irqenable);
  220. }
  221. EXPORT_SYMBOL(omap_mbox_enable_irq);
  222. void omap_mbox_disable_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
  223. {
  224. struct omap_mbox_fifo *fifo = (irq == IRQ_TX) ?
  225. &mbox->tx_fifo : &mbox->rx_fifo;
  226. u32 bit = fifo->intr_bit;
  227. u32 irqdisable = fifo->irqdisable;
  228. /*
  229. * Read and update the interrupt configuration register for pre-OMAP4.
  230. * OMAP4 and later SoCs have a dedicated interrupt disabling register.
  231. */
  232. if (!mbox->intr_type)
  233. bit = mbox_read_reg(mbox->parent, irqdisable) & ~bit;
  234. mbox_write_reg(mbox->parent, bit, irqdisable);
  235. }
  236. EXPORT_SYMBOL(omap_mbox_disable_irq);
  237. static void mbox_tx_tasklet(unsigned long tx_data)
  238. {
  239. struct omap_mbox *mbox = (struct omap_mbox *)tx_data;
  240. struct omap_mbox_queue *mq = mbox->txq;
  241. mbox_msg_t msg;
  242. int ret;
  243. while (kfifo_len(&mq->fifo)) {
  244. if (mbox_fifo_full(mbox)) {
  245. omap_mbox_enable_irq(mbox, IRQ_TX);
  246. break;
  247. }
  248. ret = kfifo_out(&mq->fifo, (unsigned char *)&msg,
  249. sizeof(msg));
  250. WARN_ON(ret != sizeof(msg));
  251. mbox_fifo_write(mbox, msg);
  252. }
  253. }
  254. /*
  255. * Message receiver(workqueue)
  256. */
  257. static void mbox_rx_work(struct work_struct *work)
  258. {
  259. struct omap_mbox_queue *mq =
  260. container_of(work, struct omap_mbox_queue, work);
  261. mbox_msg_t msg;
  262. int len;
  263. while (kfifo_len(&mq->fifo) >= sizeof(msg)) {
  264. len = kfifo_out(&mq->fifo, (unsigned char *)&msg, sizeof(msg));
  265. WARN_ON(len != sizeof(msg));
  266. blocking_notifier_call_chain(&mq->mbox->notifier, len,
  267. (void *)msg);
  268. spin_lock_irq(&mq->lock);
  269. if (mq->full) {
  270. mq->full = false;
  271. omap_mbox_enable_irq(mq->mbox, IRQ_RX);
  272. }
  273. spin_unlock_irq(&mq->lock);
  274. }
  275. }
  276. /*
  277. * Mailbox interrupt handler
  278. */
  279. static void __mbox_tx_interrupt(struct omap_mbox *mbox)
  280. {
  281. omap_mbox_disable_irq(mbox, IRQ_TX);
  282. ack_mbox_irq(mbox, IRQ_TX);
  283. tasklet_schedule(&mbox->txq->tasklet);
  284. }
  285. static void __mbox_rx_interrupt(struct omap_mbox *mbox)
  286. {
  287. struct omap_mbox_queue *mq = mbox->rxq;
  288. mbox_msg_t msg;
  289. int len;
  290. while (!mbox_fifo_empty(mbox)) {
  291. if (unlikely(kfifo_avail(&mq->fifo) < sizeof(msg))) {
  292. omap_mbox_disable_irq(mbox, IRQ_RX);
  293. mq->full = true;
  294. goto nomem;
  295. }
  296. msg = mbox_fifo_read(mbox);
  297. len = kfifo_in(&mq->fifo, (unsigned char *)&msg, sizeof(msg));
  298. WARN_ON(len != sizeof(msg));
  299. }
  300. /* no more messages in the fifo. clear IRQ source. */
  301. ack_mbox_irq(mbox, IRQ_RX);
  302. nomem:
  303. schedule_work(&mbox->rxq->work);
  304. }
  305. static irqreturn_t mbox_interrupt(int irq, void *p)
  306. {
  307. struct omap_mbox *mbox = p;
  308. if (is_mbox_irq(mbox, IRQ_TX))
  309. __mbox_tx_interrupt(mbox);
  310. if (is_mbox_irq(mbox, IRQ_RX))
  311. __mbox_rx_interrupt(mbox);
  312. return IRQ_HANDLED;
  313. }
  314. static struct omap_mbox_queue *mbox_queue_alloc(struct omap_mbox *mbox,
  315. void (*work) (struct work_struct *),
  316. void (*tasklet)(unsigned long))
  317. {
  318. struct omap_mbox_queue *mq;
  319. mq = kzalloc(sizeof(struct omap_mbox_queue), GFP_KERNEL);
  320. if (!mq)
  321. return NULL;
  322. spin_lock_init(&mq->lock);
  323. if (kfifo_alloc(&mq->fifo, mbox_kfifo_size, GFP_KERNEL))
  324. goto error;
  325. if (work)
  326. INIT_WORK(&mq->work, work);
  327. if (tasklet)
  328. tasklet_init(&mq->tasklet, tasklet, (unsigned long)mbox);
  329. return mq;
  330. error:
  331. kfree(mq);
  332. return NULL;
  333. }
  334. static void mbox_queue_free(struct omap_mbox_queue *q)
  335. {
  336. kfifo_free(&q->fifo);
  337. kfree(q);
  338. }
  339. static int omap_mbox_startup(struct omap_mbox *mbox)
  340. {
  341. int ret = 0;
  342. struct omap_mbox_queue *mq;
  343. struct omap_mbox_device *mdev = mbox->parent;
  344. mutex_lock(&mdev->cfg_lock);
  345. ret = pm_runtime_get_sync(mdev->dev);
  346. if (unlikely(ret < 0))
  347. goto fail_startup;
  348. if (!mbox->use_count++) {
  349. mq = mbox_queue_alloc(mbox, NULL, mbox_tx_tasklet);
  350. if (!mq) {
  351. ret = -ENOMEM;
  352. goto fail_alloc_txq;
  353. }
  354. mbox->txq = mq;
  355. mq = mbox_queue_alloc(mbox, mbox_rx_work, NULL);
  356. if (!mq) {
  357. ret = -ENOMEM;
  358. goto fail_alloc_rxq;
  359. }
  360. mbox->rxq = mq;
  361. mq->mbox = mbox;
  362. ret = request_irq(mbox->irq, mbox_interrupt, IRQF_SHARED,
  363. mbox->name, mbox);
  364. if (unlikely(ret)) {
  365. pr_err("failed to register mailbox interrupt:%d\n",
  366. ret);
  367. goto fail_request_irq;
  368. }
  369. omap_mbox_enable_irq(mbox, IRQ_RX);
  370. }
  371. mutex_unlock(&mdev->cfg_lock);
  372. return 0;
  373. fail_request_irq:
  374. mbox_queue_free(mbox->rxq);
  375. fail_alloc_rxq:
  376. mbox_queue_free(mbox->txq);
  377. fail_alloc_txq:
  378. pm_runtime_put_sync(mdev->dev);
  379. mbox->use_count--;
  380. fail_startup:
  381. mutex_unlock(&mdev->cfg_lock);
  382. return ret;
  383. }
  384. static void omap_mbox_fini(struct omap_mbox *mbox)
  385. {
  386. struct omap_mbox_device *mdev = mbox->parent;
  387. mutex_lock(&mdev->cfg_lock);
  388. if (!--mbox->use_count) {
  389. omap_mbox_disable_irq(mbox, IRQ_RX);
  390. free_irq(mbox->irq, mbox);
  391. tasklet_kill(&mbox->txq->tasklet);
  392. flush_work(&mbox->rxq->work);
  393. mbox_queue_free(mbox->txq);
  394. mbox_queue_free(mbox->rxq);
  395. }
  396. pm_runtime_put_sync(mdev->dev);
  397. mutex_unlock(&mdev->cfg_lock);
  398. }
  399. static struct omap_mbox *omap_mbox_device_find(struct omap_mbox_device *mdev,
  400. const char *mbox_name)
  401. {
  402. struct omap_mbox *_mbox, *mbox = NULL;
  403. struct omap_mbox **mboxes = mdev->mboxes;
  404. int i;
  405. if (!mboxes)
  406. return NULL;
  407. for (i = 0; (_mbox = mboxes[i]); i++) {
  408. if (!strcmp(_mbox->name, mbox_name)) {
  409. mbox = _mbox;
  410. break;
  411. }
  412. }
  413. return mbox;
  414. }
  415. struct omap_mbox *omap_mbox_get(const char *name, struct notifier_block *nb)
  416. {
  417. struct omap_mbox *mbox = NULL;
  418. struct omap_mbox_device *mdev;
  419. int ret;
  420. mutex_lock(&omap_mbox_devices_lock);
  421. list_for_each_entry(mdev, &omap_mbox_devices, elem) {
  422. mbox = omap_mbox_device_find(mdev, name);
  423. if (mbox)
  424. break;
  425. }
  426. mutex_unlock(&omap_mbox_devices_lock);
  427. if (!mbox)
  428. return ERR_PTR(-ENOENT);
  429. if (nb)
  430. blocking_notifier_chain_register(&mbox->notifier, nb);
  431. ret = omap_mbox_startup(mbox);
  432. if (ret) {
  433. blocking_notifier_chain_unregister(&mbox->notifier, nb);
  434. return ERR_PTR(-ENODEV);
  435. }
  436. return mbox;
  437. }
  438. EXPORT_SYMBOL(omap_mbox_get);
  439. void omap_mbox_put(struct omap_mbox *mbox, struct notifier_block *nb)
  440. {
  441. blocking_notifier_chain_unregister(&mbox->notifier, nb);
  442. omap_mbox_fini(mbox);
  443. }
  444. EXPORT_SYMBOL(omap_mbox_put);
  445. static struct class omap_mbox_class = { .name = "mbox", };
  446. static int omap_mbox_register(struct omap_mbox_device *mdev)
  447. {
  448. int ret;
  449. int i;
  450. struct omap_mbox **mboxes;
  451. if (!mdev || !mdev->mboxes)
  452. return -EINVAL;
  453. mboxes = mdev->mboxes;
  454. for (i = 0; mboxes[i]; i++) {
  455. struct omap_mbox *mbox = mboxes[i];
  456. mbox->dev = device_create(&omap_mbox_class,
  457. mdev->dev, 0, mbox, "%s", mbox->name);
  458. if (IS_ERR(mbox->dev)) {
  459. ret = PTR_ERR(mbox->dev);
  460. goto err_out;
  461. }
  462. BLOCKING_INIT_NOTIFIER_HEAD(&mbox->notifier);
  463. }
  464. mutex_lock(&omap_mbox_devices_lock);
  465. list_add(&mdev->elem, &omap_mbox_devices);
  466. mutex_unlock(&omap_mbox_devices_lock);
  467. return 0;
  468. err_out:
  469. while (i--)
  470. device_unregister(mboxes[i]->dev);
  471. return ret;
  472. }
  473. static int omap_mbox_unregister(struct omap_mbox_device *mdev)
  474. {
  475. int i;
  476. struct omap_mbox **mboxes;
  477. if (!mdev || !mdev->mboxes)
  478. return -EINVAL;
  479. mutex_lock(&omap_mbox_devices_lock);
  480. list_del(&mdev->elem);
  481. mutex_unlock(&omap_mbox_devices_lock);
  482. mboxes = mdev->mboxes;
  483. for (i = 0; mboxes[i]; i++)
  484. device_unregister(mboxes[i]->dev);
  485. return 0;
  486. }
  487. static int omap_mbox_probe(struct platform_device *pdev)
  488. {
  489. struct resource *mem;
  490. int ret;
  491. struct omap_mbox **list, *mbox, *mboxblk;
  492. struct omap_mbox_pdata *pdata = pdev->dev.platform_data;
  493. struct omap_mbox_dev_info *info;
  494. struct omap_mbox_device *mdev;
  495. struct omap_mbox_fifo *fifo;
  496. u32 intr_type;
  497. u32 l;
  498. int i;
  499. if (!pdata || !pdata->info_cnt || !pdata->info) {
  500. pr_err("%s: platform not supported\n", __func__);
  501. return -ENODEV;
  502. }
  503. mdev = devm_kzalloc(&pdev->dev, sizeof(*mdev), GFP_KERNEL);
  504. if (!mdev)
  505. return -ENOMEM;
  506. mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  507. mdev->mbox_base = devm_ioremap_resource(&pdev->dev, mem);
  508. if (IS_ERR(mdev->mbox_base))
  509. return PTR_ERR(mdev->mbox_base);
  510. /* allocate one extra for marking end of list */
  511. list = devm_kzalloc(&pdev->dev, (pdata->info_cnt + 1) * sizeof(*list),
  512. GFP_KERNEL);
  513. if (!list)
  514. return -ENOMEM;
  515. mboxblk = devm_kzalloc(&pdev->dev, pdata->info_cnt * sizeof(*mbox),
  516. GFP_KERNEL);
  517. if (!mboxblk)
  518. return -ENOMEM;
  519. info = pdata->info;
  520. intr_type = pdata->intr_type;
  521. mbox = mboxblk;
  522. for (i = 0; i < pdata->info_cnt; i++, info++) {
  523. fifo = &mbox->tx_fifo;
  524. fifo->msg = MAILBOX_MESSAGE(info->tx_id);
  525. fifo->fifo_stat = MAILBOX_FIFOSTATUS(info->tx_id);
  526. fifo->intr_bit = MAILBOX_IRQ_NOTFULL(info->tx_id);
  527. fifo->irqenable = MAILBOX_IRQENABLE(intr_type, info->usr_id);
  528. fifo->irqstatus = MAILBOX_IRQSTATUS(intr_type, info->usr_id);
  529. fifo->irqdisable = MAILBOX_IRQDISABLE(intr_type, info->usr_id);
  530. fifo = &mbox->rx_fifo;
  531. fifo->msg = MAILBOX_MESSAGE(info->rx_id);
  532. fifo->msg_stat = MAILBOX_MSGSTATUS(info->rx_id);
  533. fifo->intr_bit = MAILBOX_IRQ_NEWMSG(info->rx_id);
  534. fifo->irqenable = MAILBOX_IRQENABLE(intr_type, info->usr_id);
  535. fifo->irqstatus = MAILBOX_IRQSTATUS(intr_type, info->usr_id);
  536. fifo->irqdisable = MAILBOX_IRQDISABLE(intr_type, info->usr_id);
  537. mbox->intr_type = intr_type;
  538. mbox->parent = mdev;
  539. mbox->name = info->name;
  540. mbox->irq = platform_get_irq(pdev, info->irq_id);
  541. if (mbox->irq < 0)
  542. return mbox->irq;
  543. list[i] = mbox++;
  544. }
  545. mutex_init(&mdev->cfg_lock);
  546. mdev->dev = &pdev->dev;
  547. mdev->num_users = pdata->num_users;
  548. mdev->num_fifos = pdata->num_fifos;
  549. mdev->mboxes = list;
  550. ret = omap_mbox_register(mdev);
  551. if (ret)
  552. return ret;
  553. platform_set_drvdata(pdev, mdev);
  554. pm_runtime_enable(mdev->dev);
  555. ret = pm_runtime_get_sync(mdev->dev);
  556. if (ret < 0) {
  557. pm_runtime_put_noidle(mdev->dev);
  558. goto unregister;
  559. }
  560. /*
  561. * just print the raw revision register, the format is not
  562. * uniform across all SoCs
  563. */
  564. l = mbox_read_reg(mdev, MAILBOX_REVISION);
  565. dev_info(mdev->dev, "omap mailbox rev 0x%x\n", l);
  566. ret = pm_runtime_put_sync(mdev->dev);
  567. if (ret < 0)
  568. goto unregister;
  569. return 0;
  570. unregister:
  571. pm_runtime_disable(mdev->dev);
  572. omap_mbox_unregister(mdev);
  573. return ret;
  574. }
  575. static int omap_mbox_remove(struct platform_device *pdev)
  576. {
  577. struct omap_mbox_device *mdev = platform_get_drvdata(pdev);
  578. pm_runtime_disable(mdev->dev);
  579. omap_mbox_unregister(mdev);
  580. return 0;
  581. }
  582. static struct platform_driver omap_mbox_driver = {
  583. .probe = omap_mbox_probe,
  584. .remove = omap_mbox_remove,
  585. .driver = {
  586. .name = "omap-mailbox",
  587. .owner = THIS_MODULE,
  588. },
  589. };
  590. static int __init omap_mbox_init(void)
  591. {
  592. int err;
  593. err = class_register(&omap_mbox_class);
  594. if (err)
  595. return err;
  596. /* kfifo size sanity check: alignment and minimal size */
  597. mbox_kfifo_size = ALIGN(mbox_kfifo_size, sizeof(mbox_msg_t));
  598. mbox_kfifo_size = max_t(unsigned int, mbox_kfifo_size,
  599. sizeof(mbox_msg_t));
  600. return platform_driver_register(&omap_mbox_driver);
  601. }
  602. subsys_initcall(omap_mbox_init);
  603. static void __exit omap_mbox_exit(void)
  604. {
  605. platform_driver_unregister(&omap_mbox_driver);
  606. class_unregister(&omap_mbox_class);
  607. }
  608. module_exit(omap_mbox_exit);
  609. MODULE_LICENSE("GPL v2");
  610. MODULE_DESCRIPTION("omap mailbox: interrupt driven messaging");
  611. MODULE_AUTHOR("Toshihiro Kobayashi");
  612. MODULE_AUTHOR("Hiroshi DOYU");