Kconfig 1.8 KB

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  1. config IRQCHIP
  2. def_bool y
  3. depends on OF_IRQ
  4. config ARM_GIC
  5. bool
  6. select IRQ_DOMAIN
  7. select MULTI_IRQ_HANDLER
  8. config GIC_NON_BANKED
  9. bool
  10. config ARM_GIC_V3
  11. bool
  12. select IRQ_DOMAIN
  13. select MULTI_IRQ_HANDLER
  14. config ARM_NVIC
  15. bool
  16. select IRQ_DOMAIN
  17. select GENERIC_IRQ_CHIP
  18. config ARM_VIC
  19. bool
  20. select IRQ_DOMAIN
  21. select MULTI_IRQ_HANDLER
  22. config ARM_VIC_NR
  23. int
  24. default 4 if ARCH_S5PV210
  25. default 2
  26. depends on ARM_VIC
  27. help
  28. The maximum number of VICs available in the system, for
  29. power management.
  30. config ATMEL_AIC_IRQ
  31. bool
  32. select GENERIC_IRQ_CHIP
  33. select IRQ_DOMAIN
  34. select MULTI_IRQ_HANDLER
  35. select SPARSE_IRQ
  36. config ATMEL_AIC5_IRQ
  37. bool
  38. select GENERIC_IRQ_CHIP
  39. select IRQ_DOMAIN
  40. select MULTI_IRQ_HANDLER
  41. select SPARSE_IRQ
  42. config BRCMSTB_L2_IRQ
  43. bool
  44. depends on ARM
  45. select GENERIC_IRQ_CHIP
  46. select IRQ_DOMAIN
  47. config DW_APB_ICTL
  48. bool
  49. select IRQ_DOMAIN
  50. config IMGPDC_IRQ
  51. bool
  52. select GENERIC_IRQ_CHIP
  53. select IRQ_DOMAIN
  54. config CLPS711X_IRQCHIP
  55. bool
  56. depends on ARCH_CLPS711X
  57. select IRQ_DOMAIN
  58. select MULTI_IRQ_HANDLER
  59. select SPARSE_IRQ
  60. default y
  61. config OR1K_PIC
  62. bool
  63. select IRQ_DOMAIN
  64. config ORION_IRQCHIP
  65. bool
  66. select IRQ_DOMAIN
  67. select MULTI_IRQ_HANDLER
  68. config RENESAS_INTC_IRQPIN
  69. bool
  70. select IRQ_DOMAIN
  71. config RENESAS_IRQC
  72. bool
  73. select IRQ_DOMAIN
  74. config TB10X_IRQC
  75. bool
  76. select IRQ_DOMAIN
  77. select GENERIC_IRQ_CHIP
  78. config VERSATILE_FPGA_IRQ
  79. bool
  80. select IRQ_DOMAIN
  81. config VERSATILE_FPGA_IRQ_NR
  82. int
  83. default 4
  84. depends on VERSATILE_FPGA_IRQ
  85. config XTENSA_MX
  86. bool
  87. select IRQ_DOMAIN
  88. config IRQ_CROSSBAR
  89. bool
  90. help
  91. Support for a CROSSBAR ip that preceeds the main interrupt controller.
  92. The primary irqchip invokes the crossbar's callback which inturn allocates
  93. a free irq and configures the IP. Thus the peripheral interrupts are
  94. routed to one of the free irqchip interrupt lines.