main.c 37 KB

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  1. /*
  2. * Copyright (c) 2013, Mellanox Technologies inc. All rights reserved.
  3. *
  4. * This software is available to you under a choice of one of two
  5. * licenses. You may choose to be licensed under the terms of the GNU
  6. * General Public License (GPL) Version 2, available from the file
  7. * COPYING in the main directory of this source tree, or the
  8. * OpenIB.org BSD license below:
  9. *
  10. * Redistribution and use in source and binary forms, with or
  11. * without modification, are permitted provided that the following
  12. * conditions are met:
  13. *
  14. * - Redistributions of source code must retain the above
  15. * copyright notice, this list of conditions and the following
  16. * disclaimer.
  17. *
  18. * - Redistributions in binary form must reproduce the above
  19. * copyright notice, this list of conditions and the following
  20. * disclaimer in the documentation and/or other materials
  21. * provided with the distribution.
  22. *
  23. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30. * SOFTWARE.
  31. */
  32. #include <asm-generic/kmap_types.h>
  33. #include <linux/module.h>
  34. #include <linux/init.h>
  35. #include <linux/errno.h>
  36. #include <linux/pci.h>
  37. #include <linux/dma-mapping.h>
  38. #include <linux/slab.h>
  39. #include <linux/io-mapping.h>
  40. #include <linux/sched.h>
  41. #include <rdma/ib_user_verbs.h>
  42. #include <rdma/ib_smi.h>
  43. #include <rdma/ib_umem.h>
  44. #include "user.h"
  45. #include "mlx5_ib.h"
  46. #define DRIVER_NAME "mlx5_ib"
  47. #define DRIVER_VERSION "2.2-1"
  48. #define DRIVER_RELDATE "Feb 2014"
  49. MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
  50. MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
  51. MODULE_LICENSE("Dual BSD/GPL");
  52. MODULE_VERSION(DRIVER_VERSION);
  53. static int deprecated_prof_sel = 2;
  54. module_param_named(prof_sel, deprecated_prof_sel, int, 0444);
  55. MODULE_PARM_DESC(prof_sel, "profile selector. Deprecated here. Moved to module mlx5_core");
  56. static char mlx5_version[] =
  57. DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
  58. DRIVER_VERSION " (" DRIVER_RELDATE ")\n";
  59. int mlx5_vector2eqn(struct mlx5_ib_dev *dev, int vector, int *eqn, int *irqn)
  60. {
  61. struct mlx5_eq_table *table = &dev->mdev->priv.eq_table;
  62. struct mlx5_eq *eq, *n;
  63. int err = -ENOENT;
  64. spin_lock(&table->lock);
  65. list_for_each_entry_safe(eq, n, &dev->eqs_list, list) {
  66. if (eq->index == vector) {
  67. *eqn = eq->eqn;
  68. *irqn = eq->irqn;
  69. err = 0;
  70. break;
  71. }
  72. }
  73. spin_unlock(&table->lock);
  74. return err;
  75. }
  76. static int alloc_comp_eqs(struct mlx5_ib_dev *dev)
  77. {
  78. struct mlx5_eq_table *table = &dev->mdev->priv.eq_table;
  79. char name[MLX5_MAX_EQ_NAME];
  80. struct mlx5_eq *eq, *n;
  81. int ncomp_vec;
  82. int nent;
  83. int err;
  84. int i;
  85. INIT_LIST_HEAD(&dev->eqs_list);
  86. ncomp_vec = table->num_comp_vectors;
  87. nent = MLX5_COMP_EQ_SIZE;
  88. for (i = 0; i < ncomp_vec; i++) {
  89. eq = kzalloc(sizeof(*eq), GFP_KERNEL);
  90. if (!eq) {
  91. err = -ENOMEM;
  92. goto clean;
  93. }
  94. snprintf(name, MLX5_MAX_EQ_NAME, "mlx5_comp%d", i);
  95. err = mlx5_create_map_eq(dev->mdev, eq,
  96. i + MLX5_EQ_VEC_COMP_BASE, nent, 0,
  97. name, &dev->mdev->priv.uuari.uars[0]);
  98. if (err) {
  99. kfree(eq);
  100. goto clean;
  101. }
  102. mlx5_ib_dbg(dev, "allocated completion EQN %d\n", eq->eqn);
  103. eq->index = i;
  104. spin_lock(&table->lock);
  105. list_add_tail(&eq->list, &dev->eqs_list);
  106. spin_unlock(&table->lock);
  107. }
  108. dev->num_comp_vectors = ncomp_vec;
  109. return 0;
  110. clean:
  111. spin_lock(&table->lock);
  112. list_for_each_entry_safe(eq, n, &dev->eqs_list, list) {
  113. list_del(&eq->list);
  114. spin_unlock(&table->lock);
  115. if (mlx5_destroy_unmap_eq(dev->mdev, eq))
  116. mlx5_ib_warn(dev, "failed to destroy EQ 0x%x\n", eq->eqn);
  117. kfree(eq);
  118. spin_lock(&table->lock);
  119. }
  120. spin_unlock(&table->lock);
  121. return err;
  122. }
  123. static void free_comp_eqs(struct mlx5_ib_dev *dev)
  124. {
  125. struct mlx5_eq_table *table = &dev->mdev->priv.eq_table;
  126. struct mlx5_eq *eq, *n;
  127. spin_lock(&table->lock);
  128. list_for_each_entry_safe(eq, n, &dev->eqs_list, list) {
  129. list_del(&eq->list);
  130. spin_unlock(&table->lock);
  131. if (mlx5_destroy_unmap_eq(dev->mdev, eq))
  132. mlx5_ib_warn(dev, "failed to destroy EQ 0x%x\n", eq->eqn);
  133. kfree(eq);
  134. spin_lock(&table->lock);
  135. }
  136. spin_unlock(&table->lock);
  137. }
  138. static int mlx5_ib_query_device(struct ib_device *ibdev,
  139. struct ib_device_attr *props)
  140. {
  141. struct mlx5_ib_dev *dev = to_mdev(ibdev);
  142. struct ib_smp *in_mad = NULL;
  143. struct ib_smp *out_mad = NULL;
  144. int err = -ENOMEM;
  145. int max_rq_sg;
  146. int max_sq_sg;
  147. u64 flags;
  148. in_mad = kzalloc(sizeof(*in_mad), GFP_KERNEL);
  149. out_mad = kmalloc(sizeof(*out_mad), GFP_KERNEL);
  150. if (!in_mad || !out_mad)
  151. goto out;
  152. init_query_mad(in_mad);
  153. in_mad->attr_id = IB_SMP_ATTR_NODE_INFO;
  154. err = mlx5_MAD_IFC(to_mdev(ibdev), 1, 1, 1, NULL, NULL, in_mad, out_mad);
  155. if (err)
  156. goto out;
  157. memset(props, 0, sizeof(*props));
  158. props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
  159. (fw_rev_min(dev->mdev) << 16) |
  160. fw_rev_sub(dev->mdev);
  161. props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
  162. IB_DEVICE_PORT_ACTIVE_EVENT |
  163. IB_DEVICE_SYS_IMAGE_GUID |
  164. IB_DEVICE_RC_RNR_NAK_GEN;
  165. flags = dev->mdev->caps.flags;
  166. if (flags & MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR)
  167. props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
  168. if (flags & MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR)
  169. props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
  170. if (flags & MLX5_DEV_CAP_FLAG_APM)
  171. props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
  172. props->device_cap_flags |= IB_DEVICE_LOCAL_DMA_LKEY;
  173. if (flags & MLX5_DEV_CAP_FLAG_XRC)
  174. props->device_cap_flags |= IB_DEVICE_XRC;
  175. props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
  176. if (flags & MLX5_DEV_CAP_FLAG_SIG_HAND_OVER) {
  177. props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
  178. /* At this stage no support for signature handover */
  179. props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
  180. IB_PROT_T10DIF_TYPE_2 |
  181. IB_PROT_T10DIF_TYPE_3;
  182. props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
  183. IB_GUARD_T10DIF_CSUM;
  184. }
  185. if (flags & MLX5_DEV_CAP_FLAG_BLOCK_MCAST)
  186. props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
  187. props->vendor_id = be32_to_cpup((__be32 *)(out_mad->data + 36)) &
  188. 0xffffff;
  189. props->vendor_part_id = be16_to_cpup((__be16 *)(out_mad->data + 30));
  190. props->hw_ver = be32_to_cpup((__be32 *)(out_mad->data + 32));
  191. memcpy(&props->sys_image_guid, out_mad->data + 4, 8);
  192. props->max_mr_size = ~0ull;
  193. props->page_size_cap = dev->mdev->caps.min_page_sz;
  194. props->max_qp = 1 << dev->mdev->caps.log_max_qp;
  195. props->max_qp_wr = dev->mdev->caps.max_wqes;
  196. max_rq_sg = dev->mdev->caps.max_rq_desc_sz / sizeof(struct mlx5_wqe_data_seg);
  197. max_sq_sg = (dev->mdev->caps.max_sq_desc_sz - sizeof(struct mlx5_wqe_ctrl_seg)) /
  198. sizeof(struct mlx5_wqe_data_seg);
  199. props->max_sge = min(max_rq_sg, max_sq_sg);
  200. props->max_cq = 1 << dev->mdev->caps.log_max_cq;
  201. props->max_cqe = dev->mdev->caps.max_cqes - 1;
  202. props->max_mr = 1 << dev->mdev->caps.log_max_mkey;
  203. props->max_pd = 1 << dev->mdev->caps.log_max_pd;
  204. props->max_qp_rd_atom = dev->mdev->caps.max_ra_req_qp;
  205. props->max_qp_init_rd_atom = dev->mdev->caps.max_ra_res_qp;
  206. props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
  207. props->max_srq = 1 << dev->mdev->caps.log_max_srq;
  208. props->max_srq_wr = dev->mdev->caps.max_srq_wqes - 1;
  209. props->max_srq_sge = max_rq_sg - 1;
  210. props->max_fast_reg_page_list_len = (unsigned int)-1;
  211. props->local_ca_ack_delay = dev->mdev->caps.local_ca_ack_delay;
  212. props->atomic_cap = IB_ATOMIC_NONE;
  213. props->masked_atomic_cap = IB_ATOMIC_NONE;
  214. props->max_pkeys = be16_to_cpup((__be16 *)(out_mad->data + 28));
  215. props->max_mcast_grp = 1 << dev->mdev->caps.log_max_mcg;
  216. props->max_mcast_qp_attach = dev->mdev->caps.max_qp_mcg;
  217. props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
  218. props->max_mcast_grp;
  219. props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
  220. out:
  221. kfree(in_mad);
  222. kfree(out_mad);
  223. return err;
  224. }
  225. int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
  226. struct ib_port_attr *props)
  227. {
  228. struct mlx5_ib_dev *dev = to_mdev(ibdev);
  229. struct ib_smp *in_mad = NULL;
  230. struct ib_smp *out_mad = NULL;
  231. int ext_active_speed;
  232. int err = -ENOMEM;
  233. if (port < 1 || port > dev->mdev->caps.num_ports) {
  234. mlx5_ib_warn(dev, "invalid port number %d\n", port);
  235. return -EINVAL;
  236. }
  237. in_mad = kzalloc(sizeof(*in_mad), GFP_KERNEL);
  238. out_mad = kmalloc(sizeof(*out_mad), GFP_KERNEL);
  239. if (!in_mad || !out_mad)
  240. goto out;
  241. memset(props, 0, sizeof(*props));
  242. init_query_mad(in_mad);
  243. in_mad->attr_id = IB_SMP_ATTR_PORT_INFO;
  244. in_mad->attr_mod = cpu_to_be32(port);
  245. err = mlx5_MAD_IFC(dev, 1, 1, port, NULL, NULL, in_mad, out_mad);
  246. if (err) {
  247. mlx5_ib_warn(dev, "err %d\n", err);
  248. goto out;
  249. }
  250. props->lid = be16_to_cpup((__be16 *)(out_mad->data + 16));
  251. props->lmc = out_mad->data[34] & 0x7;
  252. props->sm_lid = be16_to_cpup((__be16 *)(out_mad->data + 18));
  253. props->sm_sl = out_mad->data[36] & 0xf;
  254. props->state = out_mad->data[32] & 0xf;
  255. props->phys_state = out_mad->data[33] >> 4;
  256. props->port_cap_flags = be32_to_cpup((__be32 *)(out_mad->data + 20));
  257. props->gid_tbl_len = out_mad->data[50];
  258. props->max_msg_sz = 1 << to_mdev(ibdev)->mdev->caps.log_max_msg;
  259. props->pkey_tbl_len = to_mdev(ibdev)->mdev->caps.port[port - 1].pkey_table_len;
  260. props->bad_pkey_cntr = be16_to_cpup((__be16 *)(out_mad->data + 46));
  261. props->qkey_viol_cntr = be16_to_cpup((__be16 *)(out_mad->data + 48));
  262. props->active_width = out_mad->data[31] & 0xf;
  263. props->active_speed = out_mad->data[35] >> 4;
  264. props->max_mtu = out_mad->data[41] & 0xf;
  265. props->active_mtu = out_mad->data[36] >> 4;
  266. props->subnet_timeout = out_mad->data[51] & 0x1f;
  267. props->max_vl_num = out_mad->data[37] >> 4;
  268. props->init_type_reply = out_mad->data[41] >> 4;
  269. /* Check if extended speeds (EDR/FDR/...) are supported */
  270. if (props->port_cap_flags & IB_PORT_EXTENDED_SPEEDS_SUP) {
  271. ext_active_speed = out_mad->data[62] >> 4;
  272. switch (ext_active_speed) {
  273. case 1:
  274. props->active_speed = 16; /* FDR */
  275. break;
  276. case 2:
  277. props->active_speed = 32; /* EDR */
  278. break;
  279. }
  280. }
  281. /* If reported active speed is QDR, check if is FDR-10 */
  282. if (props->active_speed == 4) {
  283. if (dev->mdev->caps.ext_port_cap[port - 1] &
  284. MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO) {
  285. init_query_mad(in_mad);
  286. in_mad->attr_id = MLX5_ATTR_EXTENDED_PORT_INFO;
  287. in_mad->attr_mod = cpu_to_be32(port);
  288. err = mlx5_MAD_IFC(dev, 1, 1, port,
  289. NULL, NULL, in_mad, out_mad);
  290. if (err)
  291. goto out;
  292. /* Checking LinkSpeedActive for FDR-10 */
  293. if (out_mad->data[15] & 0x1)
  294. props->active_speed = 8;
  295. }
  296. }
  297. out:
  298. kfree(in_mad);
  299. kfree(out_mad);
  300. return err;
  301. }
  302. static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
  303. union ib_gid *gid)
  304. {
  305. struct ib_smp *in_mad = NULL;
  306. struct ib_smp *out_mad = NULL;
  307. int err = -ENOMEM;
  308. in_mad = kzalloc(sizeof(*in_mad), GFP_KERNEL);
  309. out_mad = kmalloc(sizeof(*out_mad), GFP_KERNEL);
  310. if (!in_mad || !out_mad)
  311. goto out;
  312. init_query_mad(in_mad);
  313. in_mad->attr_id = IB_SMP_ATTR_PORT_INFO;
  314. in_mad->attr_mod = cpu_to_be32(port);
  315. err = mlx5_MAD_IFC(to_mdev(ibdev), 1, 1, port, NULL, NULL, in_mad, out_mad);
  316. if (err)
  317. goto out;
  318. memcpy(gid->raw, out_mad->data + 8, 8);
  319. init_query_mad(in_mad);
  320. in_mad->attr_id = IB_SMP_ATTR_GUID_INFO;
  321. in_mad->attr_mod = cpu_to_be32(index / 8);
  322. err = mlx5_MAD_IFC(to_mdev(ibdev), 1, 1, port, NULL, NULL, in_mad, out_mad);
  323. if (err)
  324. goto out;
  325. memcpy(gid->raw + 8, out_mad->data + (index % 8) * 8, 8);
  326. out:
  327. kfree(in_mad);
  328. kfree(out_mad);
  329. return err;
  330. }
  331. static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
  332. u16 *pkey)
  333. {
  334. struct ib_smp *in_mad = NULL;
  335. struct ib_smp *out_mad = NULL;
  336. int err = -ENOMEM;
  337. in_mad = kzalloc(sizeof(*in_mad), GFP_KERNEL);
  338. out_mad = kmalloc(sizeof(*out_mad), GFP_KERNEL);
  339. if (!in_mad || !out_mad)
  340. goto out;
  341. init_query_mad(in_mad);
  342. in_mad->attr_id = IB_SMP_ATTR_PKEY_TABLE;
  343. in_mad->attr_mod = cpu_to_be32(index / 32);
  344. err = mlx5_MAD_IFC(to_mdev(ibdev), 1, 1, port, NULL, NULL, in_mad, out_mad);
  345. if (err)
  346. goto out;
  347. *pkey = be16_to_cpu(((__be16 *)out_mad->data)[index % 32]);
  348. out:
  349. kfree(in_mad);
  350. kfree(out_mad);
  351. return err;
  352. }
  353. struct mlx5_reg_node_desc {
  354. u8 desc[64];
  355. };
  356. static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
  357. struct ib_device_modify *props)
  358. {
  359. struct mlx5_ib_dev *dev = to_mdev(ibdev);
  360. struct mlx5_reg_node_desc in;
  361. struct mlx5_reg_node_desc out;
  362. int err;
  363. if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
  364. return -EOPNOTSUPP;
  365. if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
  366. return 0;
  367. /*
  368. * If possible, pass node desc to FW, so it can generate
  369. * a 144 trap. If cmd fails, just ignore.
  370. */
  371. memcpy(&in, props->node_desc, 64);
  372. err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
  373. sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
  374. if (err)
  375. return err;
  376. memcpy(ibdev->node_desc, props->node_desc, 64);
  377. return err;
  378. }
  379. static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
  380. struct ib_port_modify *props)
  381. {
  382. struct mlx5_ib_dev *dev = to_mdev(ibdev);
  383. struct ib_port_attr attr;
  384. u32 tmp;
  385. int err;
  386. mutex_lock(&dev->cap_mask_mutex);
  387. err = mlx5_ib_query_port(ibdev, port, &attr);
  388. if (err)
  389. goto out;
  390. tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
  391. ~props->clr_port_cap_mask;
  392. err = mlx5_set_port_caps(dev->mdev, port, tmp);
  393. out:
  394. mutex_unlock(&dev->cap_mask_mutex);
  395. return err;
  396. }
  397. static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
  398. struct ib_udata *udata)
  399. {
  400. struct mlx5_ib_dev *dev = to_mdev(ibdev);
  401. struct mlx5_ib_alloc_ucontext_req_v2 req;
  402. struct mlx5_ib_alloc_ucontext_resp resp;
  403. struct mlx5_ib_ucontext *context;
  404. struct mlx5_uuar_info *uuari;
  405. struct mlx5_uar *uars;
  406. int gross_uuars;
  407. int num_uars;
  408. int ver;
  409. int uuarn;
  410. int err;
  411. int i;
  412. size_t reqlen;
  413. if (!dev->ib_active)
  414. return ERR_PTR(-EAGAIN);
  415. memset(&req, 0, sizeof(req));
  416. reqlen = udata->inlen - sizeof(struct ib_uverbs_cmd_hdr);
  417. if (reqlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
  418. ver = 0;
  419. else if (reqlen == sizeof(struct mlx5_ib_alloc_ucontext_req_v2))
  420. ver = 2;
  421. else
  422. return ERR_PTR(-EINVAL);
  423. err = ib_copy_from_udata(&req, udata, reqlen);
  424. if (err)
  425. return ERR_PTR(err);
  426. if (req.flags || req.reserved)
  427. return ERR_PTR(-EINVAL);
  428. if (req.total_num_uuars > MLX5_MAX_UUARS)
  429. return ERR_PTR(-ENOMEM);
  430. if (req.total_num_uuars == 0)
  431. return ERR_PTR(-EINVAL);
  432. req.total_num_uuars = ALIGN(req.total_num_uuars,
  433. MLX5_NON_FP_BF_REGS_PER_PAGE);
  434. if (req.num_low_latency_uuars > req.total_num_uuars - 1)
  435. return ERR_PTR(-EINVAL);
  436. num_uars = req.total_num_uuars / MLX5_NON_FP_BF_REGS_PER_PAGE;
  437. gross_uuars = num_uars * MLX5_BF_REGS_PER_PAGE;
  438. resp.qp_tab_size = 1 << dev->mdev->caps.log_max_qp;
  439. resp.bf_reg_size = dev->mdev->caps.bf_reg_size;
  440. resp.cache_line_size = L1_CACHE_BYTES;
  441. resp.max_sq_desc_sz = dev->mdev->caps.max_sq_desc_sz;
  442. resp.max_rq_desc_sz = dev->mdev->caps.max_rq_desc_sz;
  443. resp.max_send_wqebb = dev->mdev->caps.max_wqes;
  444. resp.max_recv_wr = dev->mdev->caps.max_wqes;
  445. resp.max_srq_recv_wr = dev->mdev->caps.max_srq_wqes;
  446. context = kzalloc(sizeof(*context), GFP_KERNEL);
  447. if (!context)
  448. return ERR_PTR(-ENOMEM);
  449. uuari = &context->uuari;
  450. mutex_init(&uuari->lock);
  451. uars = kcalloc(num_uars, sizeof(*uars), GFP_KERNEL);
  452. if (!uars) {
  453. err = -ENOMEM;
  454. goto out_ctx;
  455. }
  456. uuari->bitmap = kcalloc(BITS_TO_LONGS(gross_uuars),
  457. sizeof(*uuari->bitmap),
  458. GFP_KERNEL);
  459. if (!uuari->bitmap) {
  460. err = -ENOMEM;
  461. goto out_uar_ctx;
  462. }
  463. /*
  464. * clear all fast path uuars
  465. */
  466. for (i = 0; i < gross_uuars; i++) {
  467. uuarn = i & 3;
  468. if (uuarn == 2 || uuarn == 3)
  469. set_bit(i, uuari->bitmap);
  470. }
  471. uuari->count = kcalloc(gross_uuars, sizeof(*uuari->count), GFP_KERNEL);
  472. if (!uuari->count) {
  473. err = -ENOMEM;
  474. goto out_bitmap;
  475. }
  476. for (i = 0; i < num_uars; i++) {
  477. err = mlx5_cmd_alloc_uar(dev->mdev, &uars[i].index);
  478. if (err)
  479. goto out_count;
  480. }
  481. INIT_LIST_HEAD(&context->db_page_list);
  482. mutex_init(&context->db_page_mutex);
  483. resp.tot_uuars = req.total_num_uuars;
  484. resp.num_ports = dev->mdev->caps.num_ports;
  485. err = ib_copy_to_udata(udata, &resp,
  486. sizeof(resp) - sizeof(resp.reserved));
  487. if (err)
  488. goto out_uars;
  489. uuari->ver = ver;
  490. uuari->num_low_latency_uuars = req.num_low_latency_uuars;
  491. uuari->uars = uars;
  492. uuari->num_uars = num_uars;
  493. return &context->ibucontext;
  494. out_uars:
  495. for (i--; i >= 0; i--)
  496. mlx5_cmd_free_uar(dev->mdev, uars[i].index);
  497. out_count:
  498. kfree(uuari->count);
  499. out_bitmap:
  500. kfree(uuari->bitmap);
  501. out_uar_ctx:
  502. kfree(uars);
  503. out_ctx:
  504. kfree(context);
  505. return ERR_PTR(err);
  506. }
  507. static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
  508. {
  509. struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
  510. struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
  511. struct mlx5_uuar_info *uuari = &context->uuari;
  512. int i;
  513. for (i = 0; i < uuari->num_uars; i++) {
  514. if (mlx5_cmd_free_uar(dev->mdev, uuari->uars[i].index))
  515. mlx5_ib_warn(dev, "failed to free UAR 0x%x\n", uuari->uars[i].index);
  516. }
  517. kfree(uuari->count);
  518. kfree(uuari->bitmap);
  519. kfree(uuari->uars);
  520. kfree(context);
  521. return 0;
  522. }
  523. static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, int index)
  524. {
  525. return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + index;
  526. }
  527. static int get_command(unsigned long offset)
  528. {
  529. return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
  530. }
  531. static int get_arg(unsigned long offset)
  532. {
  533. return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
  534. }
  535. static int get_index(unsigned long offset)
  536. {
  537. return get_arg(offset);
  538. }
  539. static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
  540. {
  541. struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
  542. struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
  543. struct mlx5_uuar_info *uuari = &context->uuari;
  544. unsigned long command;
  545. unsigned long idx;
  546. phys_addr_t pfn;
  547. command = get_command(vma->vm_pgoff);
  548. switch (command) {
  549. case MLX5_IB_MMAP_REGULAR_PAGE:
  550. if (vma->vm_end - vma->vm_start != PAGE_SIZE)
  551. return -EINVAL;
  552. idx = get_index(vma->vm_pgoff);
  553. pfn = uar_index2pfn(dev, uuari->uars[idx].index);
  554. mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn 0x%llx\n", idx,
  555. (unsigned long long)pfn);
  556. if (idx >= uuari->num_uars)
  557. return -EINVAL;
  558. vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
  559. if (io_remap_pfn_range(vma, vma->vm_start, pfn,
  560. PAGE_SIZE, vma->vm_page_prot))
  561. return -EAGAIN;
  562. mlx5_ib_dbg(dev, "mapped WC at 0x%lx, PA 0x%llx\n",
  563. vma->vm_start,
  564. (unsigned long long)pfn << PAGE_SHIFT);
  565. break;
  566. case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
  567. return -ENOSYS;
  568. default:
  569. return -EINVAL;
  570. }
  571. return 0;
  572. }
  573. static int alloc_pa_mkey(struct mlx5_ib_dev *dev, u32 *key, u32 pdn)
  574. {
  575. struct mlx5_create_mkey_mbox_in *in;
  576. struct mlx5_mkey_seg *seg;
  577. struct mlx5_core_mr mr;
  578. int err;
  579. in = kzalloc(sizeof(*in), GFP_KERNEL);
  580. if (!in)
  581. return -ENOMEM;
  582. seg = &in->seg;
  583. seg->flags = MLX5_PERM_LOCAL_READ | MLX5_ACCESS_MODE_PA;
  584. seg->flags_pd = cpu_to_be32(pdn | MLX5_MKEY_LEN64);
  585. seg->qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
  586. seg->start_addr = 0;
  587. err = mlx5_core_create_mkey(dev->mdev, &mr, in, sizeof(*in),
  588. NULL, NULL, NULL);
  589. if (err) {
  590. mlx5_ib_warn(dev, "failed to create mkey, %d\n", err);
  591. goto err_in;
  592. }
  593. kfree(in);
  594. *key = mr.key;
  595. return 0;
  596. err_in:
  597. kfree(in);
  598. return err;
  599. }
  600. static void free_pa_mkey(struct mlx5_ib_dev *dev, u32 key)
  601. {
  602. struct mlx5_core_mr mr;
  603. int err;
  604. memset(&mr, 0, sizeof(mr));
  605. mr.key = key;
  606. err = mlx5_core_destroy_mkey(dev->mdev, &mr);
  607. if (err)
  608. mlx5_ib_warn(dev, "failed to destroy mkey 0x%x\n", key);
  609. }
  610. static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
  611. struct ib_ucontext *context,
  612. struct ib_udata *udata)
  613. {
  614. struct mlx5_ib_alloc_pd_resp resp;
  615. struct mlx5_ib_pd *pd;
  616. int err;
  617. pd = kmalloc(sizeof(*pd), GFP_KERNEL);
  618. if (!pd)
  619. return ERR_PTR(-ENOMEM);
  620. err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn);
  621. if (err) {
  622. kfree(pd);
  623. return ERR_PTR(err);
  624. }
  625. if (context) {
  626. resp.pdn = pd->pdn;
  627. if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
  628. mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn);
  629. kfree(pd);
  630. return ERR_PTR(-EFAULT);
  631. }
  632. } else {
  633. err = alloc_pa_mkey(to_mdev(ibdev), &pd->pa_lkey, pd->pdn);
  634. if (err) {
  635. mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn);
  636. kfree(pd);
  637. return ERR_PTR(err);
  638. }
  639. }
  640. return &pd->ibpd;
  641. }
  642. static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
  643. {
  644. struct mlx5_ib_dev *mdev = to_mdev(pd->device);
  645. struct mlx5_ib_pd *mpd = to_mpd(pd);
  646. if (!pd->uobject)
  647. free_pa_mkey(mdev, mpd->pa_lkey);
  648. mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn);
  649. kfree(mpd);
  650. return 0;
  651. }
  652. static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
  653. {
  654. struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
  655. int err;
  656. err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num);
  657. if (err)
  658. mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
  659. ibqp->qp_num, gid->raw);
  660. return err;
  661. }
  662. static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
  663. {
  664. struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
  665. int err;
  666. err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num);
  667. if (err)
  668. mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
  669. ibqp->qp_num, gid->raw);
  670. return err;
  671. }
  672. static int init_node_data(struct mlx5_ib_dev *dev)
  673. {
  674. struct ib_smp *in_mad = NULL;
  675. struct ib_smp *out_mad = NULL;
  676. int err = -ENOMEM;
  677. in_mad = kzalloc(sizeof(*in_mad), GFP_KERNEL);
  678. out_mad = kmalloc(sizeof(*out_mad), GFP_KERNEL);
  679. if (!in_mad || !out_mad)
  680. goto out;
  681. init_query_mad(in_mad);
  682. in_mad->attr_id = IB_SMP_ATTR_NODE_DESC;
  683. err = mlx5_MAD_IFC(dev, 1, 1, 1, NULL, NULL, in_mad, out_mad);
  684. if (err)
  685. goto out;
  686. memcpy(dev->ib_dev.node_desc, out_mad->data, 64);
  687. in_mad->attr_id = IB_SMP_ATTR_NODE_INFO;
  688. err = mlx5_MAD_IFC(dev, 1, 1, 1, NULL, NULL, in_mad, out_mad);
  689. if (err)
  690. goto out;
  691. dev->mdev->rev_id = be32_to_cpup((__be32 *)(out_mad->data + 32));
  692. memcpy(&dev->ib_dev.node_guid, out_mad->data + 12, 8);
  693. out:
  694. kfree(in_mad);
  695. kfree(out_mad);
  696. return err;
  697. }
  698. static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr,
  699. char *buf)
  700. {
  701. struct mlx5_ib_dev *dev =
  702. container_of(device, struct mlx5_ib_dev, ib_dev.dev);
  703. return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
  704. }
  705. static ssize_t show_reg_pages(struct device *device,
  706. struct device_attribute *attr, char *buf)
  707. {
  708. struct mlx5_ib_dev *dev =
  709. container_of(device, struct mlx5_ib_dev, ib_dev.dev);
  710. return sprintf(buf, "%d\n", dev->mdev->priv.reg_pages);
  711. }
  712. static ssize_t show_hca(struct device *device, struct device_attribute *attr,
  713. char *buf)
  714. {
  715. struct mlx5_ib_dev *dev =
  716. container_of(device, struct mlx5_ib_dev, ib_dev.dev);
  717. return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
  718. }
  719. static ssize_t show_fw_ver(struct device *device, struct device_attribute *attr,
  720. char *buf)
  721. {
  722. struct mlx5_ib_dev *dev =
  723. container_of(device, struct mlx5_ib_dev, ib_dev.dev);
  724. return sprintf(buf, "%d.%d.%d\n", fw_rev_maj(dev->mdev),
  725. fw_rev_min(dev->mdev), fw_rev_sub(dev->mdev));
  726. }
  727. static ssize_t show_rev(struct device *device, struct device_attribute *attr,
  728. char *buf)
  729. {
  730. struct mlx5_ib_dev *dev =
  731. container_of(device, struct mlx5_ib_dev, ib_dev.dev);
  732. return sprintf(buf, "%x\n", dev->mdev->rev_id);
  733. }
  734. static ssize_t show_board(struct device *device, struct device_attribute *attr,
  735. char *buf)
  736. {
  737. struct mlx5_ib_dev *dev =
  738. container_of(device, struct mlx5_ib_dev, ib_dev.dev);
  739. return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
  740. dev->mdev->board_id);
  741. }
  742. static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
  743. static DEVICE_ATTR(fw_ver, S_IRUGO, show_fw_ver, NULL);
  744. static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
  745. static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
  746. static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL);
  747. static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL);
  748. static struct device_attribute *mlx5_class_attributes[] = {
  749. &dev_attr_hw_rev,
  750. &dev_attr_fw_ver,
  751. &dev_attr_hca_type,
  752. &dev_attr_board_id,
  753. &dev_attr_fw_pages,
  754. &dev_attr_reg_pages,
  755. };
  756. static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context,
  757. enum mlx5_dev_event event, unsigned long param)
  758. {
  759. struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context;
  760. struct ib_event ibev;
  761. u8 port = 0;
  762. switch (event) {
  763. case MLX5_DEV_EVENT_SYS_ERROR:
  764. ibdev->ib_active = false;
  765. ibev.event = IB_EVENT_DEVICE_FATAL;
  766. break;
  767. case MLX5_DEV_EVENT_PORT_UP:
  768. ibev.event = IB_EVENT_PORT_ACTIVE;
  769. port = (u8)param;
  770. break;
  771. case MLX5_DEV_EVENT_PORT_DOWN:
  772. ibev.event = IB_EVENT_PORT_ERR;
  773. port = (u8)param;
  774. break;
  775. case MLX5_DEV_EVENT_PORT_INITIALIZED:
  776. /* not used by ULPs */
  777. return;
  778. case MLX5_DEV_EVENT_LID_CHANGE:
  779. ibev.event = IB_EVENT_LID_CHANGE;
  780. port = (u8)param;
  781. break;
  782. case MLX5_DEV_EVENT_PKEY_CHANGE:
  783. ibev.event = IB_EVENT_PKEY_CHANGE;
  784. port = (u8)param;
  785. break;
  786. case MLX5_DEV_EVENT_GUID_CHANGE:
  787. ibev.event = IB_EVENT_GID_CHANGE;
  788. port = (u8)param;
  789. break;
  790. case MLX5_DEV_EVENT_CLIENT_REREG:
  791. ibev.event = IB_EVENT_CLIENT_REREGISTER;
  792. port = (u8)param;
  793. break;
  794. }
  795. ibev.device = &ibdev->ib_dev;
  796. ibev.element.port_num = port;
  797. if (port < 1 || port > ibdev->num_ports) {
  798. mlx5_ib_warn(ibdev, "warning: event on port %d\n", port);
  799. return;
  800. }
  801. if (ibdev->ib_active)
  802. ib_dispatch_event(&ibev);
  803. }
  804. static void get_ext_port_caps(struct mlx5_ib_dev *dev)
  805. {
  806. int port;
  807. for (port = 1; port <= dev->mdev->caps.num_ports; port++)
  808. mlx5_query_ext_port_caps(dev, port);
  809. }
  810. static int get_port_caps(struct mlx5_ib_dev *dev)
  811. {
  812. struct ib_device_attr *dprops = NULL;
  813. struct ib_port_attr *pprops = NULL;
  814. int err = 0;
  815. int port;
  816. pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
  817. if (!pprops)
  818. goto out;
  819. dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
  820. if (!dprops)
  821. goto out;
  822. err = mlx5_ib_query_device(&dev->ib_dev, dprops);
  823. if (err) {
  824. mlx5_ib_warn(dev, "query_device failed %d\n", err);
  825. goto out;
  826. }
  827. for (port = 1; port <= dev->mdev->caps.num_ports; port++) {
  828. err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
  829. if (err) {
  830. mlx5_ib_warn(dev, "query_port %d failed %d\n", port, err);
  831. break;
  832. }
  833. dev->mdev->caps.port[port - 1].pkey_table_len = dprops->max_pkeys;
  834. dev->mdev->caps.port[port - 1].gid_table_len = pprops->gid_tbl_len;
  835. mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n",
  836. dprops->max_pkeys, pprops->gid_tbl_len);
  837. }
  838. out:
  839. kfree(pprops);
  840. kfree(dprops);
  841. return err;
  842. }
  843. static void destroy_umrc_res(struct mlx5_ib_dev *dev)
  844. {
  845. int err;
  846. err = mlx5_mr_cache_cleanup(dev);
  847. if (err)
  848. mlx5_ib_warn(dev, "mr cache cleanup failed\n");
  849. mlx5_ib_destroy_qp(dev->umrc.qp);
  850. ib_destroy_cq(dev->umrc.cq);
  851. ib_dereg_mr(dev->umrc.mr);
  852. ib_dealloc_pd(dev->umrc.pd);
  853. }
  854. enum {
  855. MAX_UMR_WR = 128,
  856. };
  857. static int create_umr_res(struct mlx5_ib_dev *dev)
  858. {
  859. struct ib_qp_init_attr *init_attr = NULL;
  860. struct ib_qp_attr *attr = NULL;
  861. struct ib_pd *pd;
  862. struct ib_cq *cq;
  863. struct ib_qp *qp;
  864. struct ib_mr *mr;
  865. int ret;
  866. attr = kzalloc(sizeof(*attr), GFP_KERNEL);
  867. init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
  868. if (!attr || !init_attr) {
  869. ret = -ENOMEM;
  870. goto error_0;
  871. }
  872. pd = ib_alloc_pd(&dev->ib_dev);
  873. if (IS_ERR(pd)) {
  874. mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
  875. ret = PTR_ERR(pd);
  876. goto error_0;
  877. }
  878. mr = ib_get_dma_mr(pd, IB_ACCESS_LOCAL_WRITE);
  879. if (IS_ERR(mr)) {
  880. mlx5_ib_dbg(dev, "Couldn't create DMA MR for sync UMR QP\n");
  881. ret = PTR_ERR(mr);
  882. goto error_1;
  883. }
  884. cq = ib_create_cq(&dev->ib_dev, mlx5_umr_cq_handler, NULL, NULL, 128,
  885. 0);
  886. if (IS_ERR(cq)) {
  887. mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
  888. ret = PTR_ERR(cq);
  889. goto error_2;
  890. }
  891. ib_req_notify_cq(cq, IB_CQ_NEXT_COMP);
  892. init_attr->send_cq = cq;
  893. init_attr->recv_cq = cq;
  894. init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
  895. init_attr->cap.max_send_wr = MAX_UMR_WR;
  896. init_attr->cap.max_send_sge = 1;
  897. init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
  898. init_attr->port_num = 1;
  899. qp = mlx5_ib_create_qp(pd, init_attr, NULL);
  900. if (IS_ERR(qp)) {
  901. mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
  902. ret = PTR_ERR(qp);
  903. goto error_3;
  904. }
  905. qp->device = &dev->ib_dev;
  906. qp->real_qp = qp;
  907. qp->uobject = NULL;
  908. qp->qp_type = MLX5_IB_QPT_REG_UMR;
  909. attr->qp_state = IB_QPS_INIT;
  910. attr->port_num = 1;
  911. ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
  912. IB_QP_PORT, NULL);
  913. if (ret) {
  914. mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
  915. goto error_4;
  916. }
  917. memset(attr, 0, sizeof(*attr));
  918. attr->qp_state = IB_QPS_RTR;
  919. attr->path_mtu = IB_MTU_256;
  920. ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
  921. if (ret) {
  922. mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
  923. goto error_4;
  924. }
  925. memset(attr, 0, sizeof(*attr));
  926. attr->qp_state = IB_QPS_RTS;
  927. ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
  928. if (ret) {
  929. mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
  930. goto error_4;
  931. }
  932. dev->umrc.qp = qp;
  933. dev->umrc.cq = cq;
  934. dev->umrc.mr = mr;
  935. dev->umrc.pd = pd;
  936. sema_init(&dev->umrc.sem, MAX_UMR_WR);
  937. ret = mlx5_mr_cache_init(dev);
  938. if (ret) {
  939. mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
  940. goto error_4;
  941. }
  942. kfree(attr);
  943. kfree(init_attr);
  944. return 0;
  945. error_4:
  946. mlx5_ib_destroy_qp(qp);
  947. error_3:
  948. ib_destroy_cq(cq);
  949. error_2:
  950. ib_dereg_mr(mr);
  951. error_1:
  952. ib_dealloc_pd(pd);
  953. error_0:
  954. kfree(attr);
  955. kfree(init_attr);
  956. return ret;
  957. }
  958. static int create_dev_resources(struct mlx5_ib_resources *devr)
  959. {
  960. struct ib_srq_init_attr attr;
  961. struct mlx5_ib_dev *dev;
  962. int ret = 0;
  963. dev = container_of(devr, struct mlx5_ib_dev, devr);
  964. devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
  965. if (IS_ERR(devr->p0)) {
  966. ret = PTR_ERR(devr->p0);
  967. goto error0;
  968. }
  969. devr->p0->device = &dev->ib_dev;
  970. devr->p0->uobject = NULL;
  971. atomic_set(&devr->p0->usecnt, 0);
  972. devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, 1, 0, NULL, NULL);
  973. if (IS_ERR(devr->c0)) {
  974. ret = PTR_ERR(devr->c0);
  975. goto error1;
  976. }
  977. devr->c0->device = &dev->ib_dev;
  978. devr->c0->uobject = NULL;
  979. devr->c0->comp_handler = NULL;
  980. devr->c0->event_handler = NULL;
  981. devr->c0->cq_context = NULL;
  982. atomic_set(&devr->c0->usecnt, 0);
  983. devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
  984. if (IS_ERR(devr->x0)) {
  985. ret = PTR_ERR(devr->x0);
  986. goto error2;
  987. }
  988. devr->x0->device = &dev->ib_dev;
  989. devr->x0->inode = NULL;
  990. atomic_set(&devr->x0->usecnt, 0);
  991. mutex_init(&devr->x0->tgt_qp_mutex);
  992. INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
  993. devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
  994. if (IS_ERR(devr->x1)) {
  995. ret = PTR_ERR(devr->x1);
  996. goto error3;
  997. }
  998. devr->x1->device = &dev->ib_dev;
  999. devr->x1->inode = NULL;
  1000. atomic_set(&devr->x1->usecnt, 0);
  1001. mutex_init(&devr->x1->tgt_qp_mutex);
  1002. INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
  1003. memset(&attr, 0, sizeof(attr));
  1004. attr.attr.max_sge = 1;
  1005. attr.attr.max_wr = 1;
  1006. attr.srq_type = IB_SRQT_XRC;
  1007. attr.ext.xrc.cq = devr->c0;
  1008. attr.ext.xrc.xrcd = devr->x0;
  1009. devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
  1010. if (IS_ERR(devr->s0)) {
  1011. ret = PTR_ERR(devr->s0);
  1012. goto error4;
  1013. }
  1014. devr->s0->device = &dev->ib_dev;
  1015. devr->s0->pd = devr->p0;
  1016. devr->s0->uobject = NULL;
  1017. devr->s0->event_handler = NULL;
  1018. devr->s0->srq_context = NULL;
  1019. devr->s0->srq_type = IB_SRQT_XRC;
  1020. devr->s0->ext.xrc.xrcd = devr->x0;
  1021. devr->s0->ext.xrc.cq = devr->c0;
  1022. atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
  1023. atomic_inc(&devr->s0->ext.xrc.cq->usecnt);
  1024. atomic_inc(&devr->p0->usecnt);
  1025. atomic_set(&devr->s0->usecnt, 0);
  1026. return 0;
  1027. error4:
  1028. mlx5_ib_dealloc_xrcd(devr->x1);
  1029. error3:
  1030. mlx5_ib_dealloc_xrcd(devr->x0);
  1031. error2:
  1032. mlx5_ib_destroy_cq(devr->c0);
  1033. error1:
  1034. mlx5_ib_dealloc_pd(devr->p0);
  1035. error0:
  1036. return ret;
  1037. }
  1038. static void destroy_dev_resources(struct mlx5_ib_resources *devr)
  1039. {
  1040. mlx5_ib_destroy_srq(devr->s0);
  1041. mlx5_ib_dealloc_xrcd(devr->x0);
  1042. mlx5_ib_dealloc_xrcd(devr->x1);
  1043. mlx5_ib_destroy_cq(devr->c0);
  1044. mlx5_ib_dealloc_pd(devr->p0);
  1045. }
  1046. static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
  1047. {
  1048. struct mlx5_ib_dev *dev;
  1049. int err;
  1050. int i;
  1051. printk_once(KERN_INFO "%s", mlx5_version);
  1052. dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
  1053. if (!dev)
  1054. return NULL;
  1055. dev->mdev = mdev;
  1056. err = get_port_caps(dev);
  1057. if (err)
  1058. goto err_dealloc;
  1059. get_ext_port_caps(dev);
  1060. err = alloc_comp_eqs(dev);
  1061. if (err)
  1062. goto err_dealloc;
  1063. MLX5_INIT_DOORBELL_LOCK(&dev->uar_lock);
  1064. strlcpy(dev->ib_dev.name, "mlx5_%d", IB_DEVICE_NAME_MAX);
  1065. dev->ib_dev.owner = THIS_MODULE;
  1066. dev->ib_dev.node_type = RDMA_NODE_IB_CA;
  1067. dev->ib_dev.local_dma_lkey = mdev->caps.reserved_lkey;
  1068. dev->num_ports = mdev->caps.num_ports;
  1069. dev->ib_dev.phys_port_cnt = dev->num_ports;
  1070. dev->ib_dev.num_comp_vectors = dev->num_comp_vectors;
  1071. dev->ib_dev.dma_device = &mdev->pdev->dev;
  1072. dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION;
  1073. dev->ib_dev.uverbs_cmd_mask =
  1074. (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
  1075. (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
  1076. (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
  1077. (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
  1078. (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
  1079. (1ull << IB_USER_VERBS_CMD_REG_MR) |
  1080. (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
  1081. (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
  1082. (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
  1083. (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
  1084. (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
  1085. (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
  1086. (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
  1087. (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
  1088. (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
  1089. (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
  1090. (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
  1091. (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
  1092. (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
  1093. (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
  1094. (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
  1095. (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
  1096. (1ull << IB_USER_VERBS_CMD_OPEN_QP);
  1097. dev->ib_dev.query_device = mlx5_ib_query_device;
  1098. dev->ib_dev.query_port = mlx5_ib_query_port;
  1099. dev->ib_dev.query_gid = mlx5_ib_query_gid;
  1100. dev->ib_dev.query_pkey = mlx5_ib_query_pkey;
  1101. dev->ib_dev.modify_device = mlx5_ib_modify_device;
  1102. dev->ib_dev.modify_port = mlx5_ib_modify_port;
  1103. dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext;
  1104. dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext;
  1105. dev->ib_dev.mmap = mlx5_ib_mmap;
  1106. dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd;
  1107. dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd;
  1108. dev->ib_dev.create_ah = mlx5_ib_create_ah;
  1109. dev->ib_dev.query_ah = mlx5_ib_query_ah;
  1110. dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah;
  1111. dev->ib_dev.create_srq = mlx5_ib_create_srq;
  1112. dev->ib_dev.modify_srq = mlx5_ib_modify_srq;
  1113. dev->ib_dev.query_srq = mlx5_ib_query_srq;
  1114. dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq;
  1115. dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv;
  1116. dev->ib_dev.create_qp = mlx5_ib_create_qp;
  1117. dev->ib_dev.modify_qp = mlx5_ib_modify_qp;
  1118. dev->ib_dev.query_qp = mlx5_ib_query_qp;
  1119. dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp;
  1120. dev->ib_dev.post_send = mlx5_ib_post_send;
  1121. dev->ib_dev.post_recv = mlx5_ib_post_recv;
  1122. dev->ib_dev.create_cq = mlx5_ib_create_cq;
  1123. dev->ib_dev.modify_cq = mlx5_ib_modify_cq;
  1124. dev->ib_dev.resize_cq = mlx5_ib_resize_cq;
  1125. dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq;
  1126. dev->ib_dev.poll_cq = mlx5_ib_poll_cq;
  1127. dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq;
  1128. dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr;
  1129. dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr;
  1130. dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr;
  1131. dev->ib_dev.destroy_mr = mlx5_ib_destroy_mr;
  1132. dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach;
  1133. dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach;
  1134. dev->ib_dev.process_mad = mlx5_ib_process_mad;
  1135. dev->ib_dev.create_mr = mlx5_ib_create_mr;
  1136. dev->ib_dev.alloc_fast_reg_mr = mlx5_ib_alloc_fast_reg_mr;
  1137. dev->ib_dev.alloc_fast_reg_page_list = mlx5_ib_alloc_fast_reg_page_list;
  1138. dev->ib_dev.free_fast_reg_page_list = mlx5_ib_free_fast_reg_page_list;
  1139. dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status;
  1140. if (mdev->caps.flags & MLX5_DEV_CAP_FLAG_XRC) {
  1141. dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd;
  1142. dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd;
  1143. dev->ib_dev.uverbs_cmd_mask |=
  1144. (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
  1145. (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
  1146. }
  1147. err = init_node_data(dev);
  1148. if (err)
  1149. goto err_eqs;
  1150. mutex_init(&dev->cap_mask_mutex);
  1151. spin_lock_init(&dev->mr_lock);
  1152. err = create_dev_resources(&dev->devr);
  1153. if (err)
  1154. goto err_eqs;
  1155. err = ib_register_device(&dev->ib_dev, NULL);
  1156. if (err)
  1157. goto err_rsrc;
  1158. err = create_umr_res(dev);
  1159. if (err)
  1160. goto err_dev;
  1161. for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) {
  1162. err = device_create_file(&dev->ib_dev.dev,
  1163. mlx5_class_attributes[i]);
  1164. if (err)
  1165. goto err_umrc;
  1166. }
  1167. dev->ib_active = true;
  1168. return dev;
  1169. err_umrc:
  1170. destroy_umrc_res(dev);
  1171. err_dev:
  1172. ib_unregister_device(&dev->ib_dev);
  1173. err_rsrc:
  1174. destroy_dev_resources(&dev->devr);
  1175. err_eqs:
  1176. free_comp_eqs(dev);
  1177. err_dealloc:
  1178. ib_dealloc_device((struct ib_device *)dev);
  1179. return NULL;
  1180. }
  1181. static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
  1182. {
  1183. struct mlx5_ib_dev *dev = context;
  1184. destroy_umrc_res(dev);
  1185. ib_unregister_device(&dev->ib_dev);
  1186. destroy_dev_resources(&dev->devr);
  1187. free_comp_eqs(dev);
  1188. ib_dealloc_device(&dev->ib_dev);
  1189. }
  1190. static struct mlx5_interface mlx5_ib_interface = {
  1191. .add = mlx5_ib_add,
  1192. .remove = mlx5_ib_remove,
  1193. .event = mlx5_ib_event,
  1194. };
  1195. static int __init mlx5_ib_init(void)
  1196. {
  1197. if (deprecated_prof_sel != 2)
  1198. pr_warn("prof_sel is deprecated for mlx5_ib, set it for mlx5_core\n");
  1199. return mlx5_register_interface(&mlx5_ib_interface);
  1200. }
  1201. static void __exit mlx5_ib_cleanup(void)
  1202. {
  1203. mlx5_unregister_interface(&mlx5_ib_interface);
  1204. }
  1205. module_init(mlx5_ib_init);
  1206. module_exit(mlx5_ib_cleanup);