sti_mixer.c 6.2 KB

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  1. /*
  2. * Copyright (C) STMicroelectronics SA 2014
  3. * Authors: Benjamin Gaignard <benjamin.gaignard@st.com>
  4. * Fabien Dessenne <fabien.dessenne@st.com>
  5. * for STMicroelectronics.
  6. * License terms: GNU General Public License (GPL), version 2
  7. */
  8. #include "sti_compositor.h"
  9. #include "sti_mixer.h"
  10. #include "sti_vtg.h"
  11. /* Identity: G=Y , B=Cb , R=Cr */
  12. static const u32 mixerColorSpaceMatIdentity[] = {
  13. 0x10000000, 0x00000000, 0x10000000, 0x00001000,
  14. 0x00000000, 0x00000000, 0x00000000, 0x00000000
  15. };
  16. /* regs offset */
  17. #define GAM_MIXER_CTL 0x00
  18. #define GAM_MIXER_BKC 0x04
  19. #define GAM_MIXER_BCO 0x0C
  20. #define GAM_MIXER_BCS 0x10
  21. #define GAM_MIXER_AVO 0x28
  22. #define GAM_MIXER_AVS 0x2C
  23. #define GAM_MIXER_CRB 0x34
  24. #define GAM_MIXER_ACT 0x38
  25. #define GAM_MIXER_MBP 0x3C
  26. #define GAM_MIXER_MX0 0x80
  27. /* id for depth of CRB reg */
  28. #define GAM_DEPTH_VID0_ID 1
  29. #define GAM_DEPTH_VID1_ID 2
  30. #define GAM_DEPTH_GDP0_ID 3
  31. #define GAM_DEPTH_GDP1_ID 4
  32. #define GAM_DEPTH_GDP2_ID 5
  33. #define GAM_DEPTH_GDP3_ID 6
  34. #define GAM_DEPTH_MASK_ID 7
  35. /* mask in CTL reg */
  36. #define GAM_CTL_BACK_MASK BIT(0)
  37. #define GAM_CTL_VID0_MASK BIT(1)
  38. #define GAM_CTL_VID1_MASK BIT(2)
  39. #define GAM_CTL_GDP0_MASK BIT(3)
  40. #define GAM_CTL_GDP1_MASK BIT(4)
  41. #define GAM_CTL_GDP2_MASK BIT(5)
  42. #define GAM_CTL_GDP3_MASK BIT(6)
  43. const char *sti_mixer_to_str(struct sti_mixer *mixer)
  44. {
  45. switch (mixer->id) {
  46. case STI_MIXER_MAIN:
  47. return "MAIN_MIXER";
  48. case STI_MIXER_AUX:
  49. return "AUX_MIXER";
  50. default:
  51. return "<UNKNOWN MIXER>";
  52. }
  53. }
  54. static inline u32 sti_mixer_reg_read(struct sti_mixer *mixer, u32 reg_id)
  55. {
  56. return readl(mixer->regs + reg_id);
  57. }
  58. static inline void sti_mixer_reg_write(struct sti_mixer *mixer,
  59. u32 reg_id, u32 val)
  60. {
  61. writel(val, mixer->regs + reg_id);
  62. }
  63. void sti_mixer_set_background_status(struct sti_mixer *mixer, bool enable)
  64. {
  65. u32 val = sti_mixer_reg_read(mixer, GAM_MIXER_CTL);
  66. val &= ~GAM_CTL_BACK_MASK;
  67. val |= enable;
  68. sti_mixer_reg_write(mixer, GAM_MIXER_CTL, val);
  69. }
  70. static void sti_mixer_set_background_color(struct sti_mixer *mixer,
  71. u8 red, u8 green, u8 blue)
  72. {
  73. u32 val = (red << 16) | (green << 8) | blue;
  74. sti_mixer_reg_write(mixer, GAM_MIXER_BKC, val);
  75. }
  76. static void sti_mixer_set_background_area(struct sti_mixer *mixer,
  77. struct drm_display_mode *mode)
  78. {
  79. u32 ydo, xdo, yds, xds;
  80. ydo = sti_vtg_get_line_number(*mode, 0);
  81. yds = sti_vtg_get_line_number(*mode, mode->vdisplay - 1);
  82. xdo = sti_vtg_get_pixel_number(*mode, 0);
  83. xds = sti_vtg_get_pixel_number(*mode, mode->hdisplay - 1);
  84. sti_mixer_reg_write(mixer, GAM_MIXER_BCO, ydo << 16 | xdo);
  85. sti_mixer_reg_write(mixer, GAM_MIXER_BCS, yds << 16 | xds);
  86. }
  87. int sti_mixer_set_layer_depth(struct sti_mixer *mixer, struct sti_layer *layer)
  88. {
  89. int layer_id = 0, depth = layer->zorder;
  90. u32 mask, val;
  91. if (depth >= GAM_MIXER_NB_DEPTH_LEVEL)
  92. return 1;
  93. switch (layer->desc) {
  94. case STI_GDP_0:
  95. layer_id = GAM_DEPTH_GDP0_ID;
  96. break;
  97. case STI_GDP_1:
  98. layer_id = GAM_DEPTH_GDP1_ID;
  99. break;
  100. case STI_GDP_2:
  101. layer_id = GAM_DEPTH_GDP2_ID;
  102. break;
  103. case STI_GDP_3:
  104. layer_id = GAM_DEPTH_GDP3_ID;
  105. break;
  106. case STI_VID_0:
  107. layer_id = GAM_DEPTH_VID0_ID;
  108. break;
  109. case STI_VID_1:
  110. layer_id = GAM_DEPTH_VID1_ID;
  111. break;
  112. default:
  113. DRM_ERROR("Unknown layer %d\n", layer->desc);
  114. return 1;
  115. }
  116. mask = GAM_DEPTH_MASK_ID << (3 * depth);
  117. layer_id = layer_id << (3 * depth);
  118. DRM_DEBUG_DRIVER("%s %s depth=%d\n", sti_mixer_to_str(mixer),
  119. sti_layer_to_str(layer), depth);
  120. dev_dbg(mixer->dev, "GAM_MIXER_CRB val 0x%x mask 0x%x\n",
  121. layer_id, mask);
  122. val = sti_mixer_reg_read(mixer, GAM_MIXER_CRB);
  123. val &= ~mask;
  124. val |= layer_id;
  125. sti_mixer_reg_write(mixer, GAM_MIXER_CRB, val);
  126. dev_dbg(mixer->dev, "Read GAM_MIXER_CRB 0x%x\n",
  127. sti_mixer_reg_read(mixer, GAM_MIXER_CRB));
  128. return 0;
  129. }
  130. int sti_mixer_active_video_area(struct sti_mixer *mixer,
  131. struct drm_display_mode *mode)
  132. {
  133. u32 ydo, xdo, yds, xds;
  134. ydo = sti_vtg_get_line_number(*mode, 0);
  135. yds = sti_vtg_get_line_number(*mode, mode->vdisplay - 1);
  136. xdo = sti_vtg_get_pixel_number(*mode, 0);
  137. xds = sti_vtg_get_pixel_number(*mode, mode->hdisplay - 1);
  138. DRM_DEBUG_DRIVER("%s active video area xdo:%d ydo:%d xds:%d yds:%d\n",
  139. sti_mixer_to_str(mixer), xdo, ydo, xds, yds);
  140. sti_mixer_reg_write(mixer, GAM_MIXER_AVO, ydo << 16 | xdo);
  141. sti_mixer_reg_write(mixer, GAM_MIXER_AVS, yds << 16 | xds);
  142. sti_mixer_set_background_color(mixer, 0xFF, 0, 0);
  143. sti_mixer_set_background_area(mixer, mode);
  144. sti_mixer_set_background_status(mixer, true);
  145. return 0;
  146. }
  147. static u32 sti_mixer_get_layer_mask(struct sti_layer *layer)
  148. {
  149. switch (layer->desc) {
  150. case STI_BACK:
  151. return GAM_CTL_BACK_MASK;
  152. case STI_GDP_0:
  153. return GAM_CTL_GDP0_MASK;
  154. case STI_GDP_1:
  155. return GAM_CTL_GDP1_MASK;
  156. case STI_GDP_2:
  157. return GAM_CTL_GDP2_MASK;
  158. case STI_GDP_3:
  159. return GAM_CTL_GDP3_MASK;
  160. case STI_VID_0:
  161. return GAM_CTL_VID0_MASK;
  162. case STI_VID_1:
  163. return GAM_CTL_VID1_MASK;
  164. default:
  165. return 0;
  166. }
  167. }
  168. int sti_mixer_set_layer_status(struct sti_mixer *mixer,
  169. struct sti_layer *layer, bool status)
  170. {
  171. u32 mask, val;
  172. DRM_DEBUG_DRIVER("%s %s %s\n", status ? "enable" : "disable",
  173. sti_mixer_to_str(mixer), sti_layer_to_str(layer));
  174. mask = sti_mixer_get_layer_mask(layer);
  175. if (!mask) {
  176. DRM_ERROR("Can not find layer mask\n");
  177. return -EINVAL;
  178. }
  179. val = sti_mixer_reg_read(mixer, GAM_MIXER_CTL);
  180. val &= ~mask;
  181. val |= status ? mask : 0;
  182. sti_mixer_reg_write(mixer, GAM_MIXER_CTL, val);
  183. return 0;
  184. }
  185. void sti_mixer_set_matrix(struct sti_mixer *mixer)
  186. {
  187. unsigned int i;
  188. for (i = 0; i < ARRAY_SIZE(mixerColorSpaceMatIdentity); i++)
  189. sti_mixer_reg_write(mixer, GAM_MIXER_MX0 + (i * 4),
  190. mixerColorSpaceMatIdentity[i]);
  191. }
  192. struct sti_mixer *sti_mixer_create(struct device *dev, int id,
  193. void __iomem *baseaddr)
  194. {
  195. struct sti_mixer *mixer = devm_kzalloc(dev, sizeof(*mixer), GFP_KERNEL);
  196. struct device_node *np = dev->of_node;
  197. dev_dbg(dev, "%s\n", __func__);
  198. if (!mixer) {
  199. DRM_ERROR("Failed to allocated memory for mixer\n");
  200. return NULL;
  201. }
  202. mixer->regs = baseaddr;
  203. mixer->dev = dev;
  204. mixer->id = id;
  205. if (of_device_is_compatible(np, "st,stih416-compositor"))
  206. sti_mixer_set_matrix(mixer);
  207. DRM_DEBUG_DRIVER("%s created. Regs=%p\n",
  208. sti_mixer_to_str(mixer), mixer->regs);
  209. return mixer;
  210. }