sti_hdmi.c 21 KB

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  1. /*
  2. * Copyright (C) STMicroelectronics SA 2014
  3. * Author: Vincent Abriou <vincent.abriou@st.com> for STMicroelectronics.
  4. * License terms: GNU General Public License (GPL), version 2
  5. */
  6. #include <linux/clk.h>
  7. #include <linux/component.h>
  8. #include <linux/hdmi.h>
  9. #include <linux/module.h>
  10. #include <linux/of_gpio.h>
  11. #include <linux/platform_device.h>
  12. #include <linux/reset.h>
  13. #include <drm/drmP.h>
  14. #include <drm/drm_crtc_helper.h>
  15. #include <drm/drm_edid.h>
  16. #include "sti_hdmi.h"
  17. #include "sti_hdmi_tx3g4c28phy.h"
  18. #include "sti_hdmi_tx3g0c55phy.h"
  19. #include "sti_vtg.h"
  20. #define HDMI_CFG 0x0000
  21. #define HDMI_INT_EN 0x0004
  22. #define HDMI_INT_STA 0x0008
  23. #define HDMI_INT_CLR 0x000C
  24. #define HDMI_STA 0x0010
  25. #define HDMI_ACTIVE_VID_XMIN 0x0100
  26. #define HDMI_ACTIVE_VID_XMAX 0x0104
  27. #define HDMI_ACTIVE_VID_YMIN 0x0108
  28. #define HDMI_ACTIVE_VID_YMAX 0x010C
  29. #define HDMI_DFLT_CHL0_DAT 0x0110
  30. #define HDMI_DFLT_CHL1_DAT 0x0114
  31. #define HDMI_DFLT_CHL2_DAT 0x0118
  32. #define HDMI_SW_DI_1_HEAD_WORD 0x0210
  33. #define HDMI_SW_DI_1_PKT_WORD0 0x0214
  34. #define HDMI_SW_DI_1_PKT_WORD1 0x0218
  35. #define HDMI_SW_DI_1_PKT_WORD2 0x021C
  36. #define HDMI_SW_DI_1_PKT_WORD3 0x0220
  37. #define HDMI_SW_DI_1_PKT_WORD4 0x0224
  38. #define HDMI_SW_DI_1_PKT_WORD5 0x0228
  39. #define HDMI_SW_DI_1_PKT_WORD6 0x022C
  40. #define HDMI_SW_DI_CFG 0x0230
  41. #define HDMI_IFRAME_SLOT_AVI 1
  42. #define XCAT(prefix, x, suffix) prefix ## x ## suffix
  43. #define HDMI_SW_DI_N_HEAD_WORD(x) XCAT(HDMI_SW_DI_, x, _HEAD_WORD)
  44. #define HDMI_SW_DI_N_PKT_WORD0(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD0)
  45. #define HDMI_SW_DI_N_PKT_WORD1(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD1)
  46. #define HDMI_SW_DI_N_PKT_WORD2(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD2)
  47. #define HDMI_SW_DI_N_PKT_WORD3(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD3)
  48. #define HDMI_SW_DI_N_PKT_WORD4(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD4)
  49. #define HDMI_SW_DI_N_PKT_WORD5(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD5)
  50. #define HDMI_SW_DI_N_PKT_WORD6(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD6)
  51. #define HDMI_IFRAME_DISABLED 0x0
  52. #define HDMI_IFRAME_SINGLE_SHOT 0x1
  53. #define HDMI_IFRAME_FIELD 0x2
  54. #define HDMI_IFRAME_FRAME 0x3
  55. #define HDMI_IFRAME_MASK 0x3
  56. #define HDMI_IFRAME_CFG_DI_N(x, n) ((x) << ((n-1)*4)) /* n from 1 to 6 */
  57. #define HDMI_CFG_DEVICE_EN BIT(0)
  58. #define HDMI_CFG_HDMI_NOT_DVI BIT(1)
  59. #define HDMI_CFG_HDCP_EN BIT(2)
  60. #define HDMI_CFG_ESS_NOT_OESS BIT(3)
  61. #define HDMI_CFG_H_SYNC_POL_NEG BIT(4)
  62. #define HDMI_CFG_SINK_TERM_DET_EN BIT(5)
  63. #define HDMI_CFG_V_SYNC_POL_NEG BIT(6)
  64. #define HDMI_CFG_422_EN BIT(8)
  65. #define HDMI_CFG_FIFO_OVERRUN_CLR BIT(12)
  66. #define HDMI_CFG_FIFO_UNDERRUN_CLR BIT(13)
  67. #define HDMI_CFG_SW_RST_EN BIT(31)
  68. #define HDMI_INT_GLOBAL BIT(0)
  69. #define HDMI_INT_SW_RST BIT(1)
  70. #define HDMI_INT_PIX_CAP BIT(3)
  71. #define HDMI_INT_HOT_PLUG BIT(4)
  72. #define HDMI_INT_DLL_LCK BIT(5)
  73. #define HDMI_INT_NEW_FRAME BIT(6)
  74. #define HDMI_INT_GENCTRL_PKT BIT(7)
  75. #define HDMI_INT_SINK_TERM_PRESENT BIT(11)
  76. #define HDMI_DEFAULT_INT (HDMI_INT_SINK_TERM_PRESENT \
  77. | HDMI_INT_DLL_LCK \
  78. | HDMI_INT_HOT_PLUG \
  79. | HDMI_INT_GLOBAL)
  80. #define HDMI_WORKING_INT (HDMI_INT_SINK_TERM_PRESENT \
  81. | HDMI_INT_GENCTRL_PKT \
  82. | HDMI_INT_NEW_FRAME \
  83. | HDMI_INT_DLL_LCK \
  84. | HDMI_INT_HOT_PLUG \
  85. | HDMI_INT_PIX_CAP \
  86. | HDMI_INT_SW_RST \
  87. | HDMI_INT_GLOBAL)
  88. #define HDMI_STA_SW_RST BIT(1)
  89. struct sti_hdmi_connector {
  90. struct drm_connector drm_connector;
  91. struct drm_encoder *encoder;
  92. struct sti_hdmi *hdmi;
  93. };
  94. #define to_sti_hdmi_connector(x) \
  95. container_of(x, struct sti_hdmi_connector, drm_connector)
  96. u32 hdmi_read(struct sti_hdmi *hdmi, int offset)
  97. {
  98. return readl(hdmi->regs + offset);
  99. }
  100. void hdmi_write(struct sti_hdmi *hdmi, u32 val, int offset)
  101. {
  102. writel(val, hdmi->regs + offset);
  103. }
  104. /**
  105. * HDMI interrupt handler threaded
  106. *
  107. * @irq: irq number
  108. * @arg: connector structure
  109. */
  110. static irqreturn_t hdmi_irq_thread(int irq, void *arg)
  111. {
  112. struct sti_hdmi *hdmi = arg;
  113. /* Hot plug/unplug IRQ */
  114. if (hdmi->irq_status & HDMI_INT_HOT_PLUG) {
  115. /* read gpio to get the status */
  116. hdmi->hpd = gpio_get_value(hdmi->hpd_gpio);
  117. if (hdmi->drm_dev)
  118. drm_helper_hpd_irq_event(hdmi->drm_dev);
  119. }
  120. /* Sw reset and PLL lock are exclusive so we can use the same
  121. * event to signal them
  122. */
  123. if (hdmi->irq_status & (HDMI_INT_SW_RST | HDMI_INT_DLL_LCK)) {
  124. hdmi->event_received = true;
  125. wake_up_interruptible(&hdmi->wait_event);
  126. }
  127. return IRQ_HANDLED;
  128. }
  129. /**
  130. * HDMI interrupt handler
  131. *
  132. * @irq: irq number
  133. * @arg: connector structure
  134. */
  135. static irqreturn_t hdmi_irq(int irq, void *arg)
  136. {
  137. struct sti_hdmi *hdmi = arg;
  138. /* read interrupt status */
  139. hdmi->irq_status = hdmi_read(hdmi, HDMI_INT_STA);
  140. /* clear interrupt status */
  141. hdmi_write(hdmi, hdmi->irq_status, HDMI_INT_CLR);
  142. /* force sync bus write */
  143. hdmi_read(hdmi, HDMI_INT_STA);
  144. return IRQ_WAKE_THREAD;
  145. }
  146. /**
  147. * Set hdmi active area depending on the drm display mode selected
  148. *
  149. * @hdmi: pointer on the hdmi internal structure
  150. */
  151. static void hdmi_active_area(struct sti_hdmi *hdmi)
  152. {
  153. u32 xmin, xmax;
  154. u32 ymin, ymax;
  155. xmin = sti_vtg_get_pixel_number(hdmi->mode, 0);
  156. xmax = sti_vtg_get_pixel_number(hdmi->mode, hdmi->mode.hdisplay - 1);
  157. ymin = sti_vtg_get_line_number(hdmi->mode, 0);
  158. ymax = sti_vtg_get_line_number(hdmi->mode, hdmi->mode.vdisplay - 1);
  159. hdmi_write(hdmi, xmin, HDMI_ACTIVE_VID_XMIN);
  160. hdmi_write(hdmi, xmax, HDMI_ACTIVE_VID_XMAX);
  161. hdmi_write(hdmi, ymin, HDMI_ACTIVE_VID_YMIN);
  162. hdmi_write(hdmi, ymax, HDMI_ACTIVE_VID_YMAX);
  163. }
  164. /**
  165. * Overall hdmi configuration
  166. *
  167. * @hdmi: pointer on the hdmi internal structure
  168. */
  169. static void hdmi_config(struct sti_hdmi *hdmi)
  170. {
  171. u32 conf;
  172. DRM_DEBUG_DRIVER("\n");
  173. /* Clear overrun and underrun fifo */
  174. conf = HDMI_CFG_FIFO_OVERRUN_CLR | HDMI_CFG_FIFO_UNDERRUN_CLR;
  175. /* Enable HDMI mode not DVI */
  176. conf |= HDMI_CFG_HDMI_NOT_DVI | HDMI_CFG_ESS_NOT_OESS;
  177. /* Enable sink term detection */
  178. conf |= HDMI_CFG_SINK_TERM_DET_EN;
  179. /* Set Hsync polarity */
  180. if (hdmi->mode.flags & DRM_MODE_FLAG_NHSYNC) {
  181. DRM_DEBUG_DRIVER("H Sync Negative\n");
  182. conf |= HDMI_CFG_H_SYNC_POL_NEG;
  183. }
  184. /* Set Vsync polarity */
  185. if (hdmi->mode.flags & DRM_MODE_FLAG_NVSYNC) {
  186. DRM_DEBUG_DRIVER("V Sync Negative\n");
  187. conf |= HDMI_CFG_V_SYNC_POL_NEG;
  188. }
  189. /* Enable HDMI */
  190. conf |= HDMI_CFG_DEVICE_EN;
  191. hdmi_write(hdmi, conf, HDMI_CFG);
  192. }
  193. /**
  194. * Prepare and configure the AVI infoframe
  195. *
  196. * AVI infoframe are transmitted at least once per two video field and
  197. * contains information about HDMI transmission mode such as color space,
  198. * colorimetry, ...
  199. *
  200. * @hdmi: pointer on the hdmi internal structure
  201. *
  202. * Return negative value if error occurs
  203. */
  204. static int hdmi_avi_infoframe_config(struct sti_hdmi *hdmi)
  205. {
  206. struct drm_display_mode *mode = &hdmi->mode;
  207. struct hdmi_avi_infoframe infoframe;
  208. u8 buffer[HDMI_INFOFRAME_SIZE(AVI)];
  209. u8 *frame = buffer + HDMI_INFOFRAME_HEADER_SIZE;
  210. u32 val;
  211. int ret;
  212. DRM_DEBUG_DRIVER("\n");
  213. ret = drm_hdmi_avi_infoframe_from_display_mode(&infoframe, mode);
  214. if (ret < 0) {
  215. DRM_ERROR("failed to setup AVI infoframe: %d\n", ret);
  216. return ret;
  217. }
  218. /* fixed infoframe configuration not linked to the mode */
  219. infoframe.colorspace = HDMI_COLORSPACE_RGB;
  220. infoframe.quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
  221. infoframe.colorimetry = HDMI_COLORIMETRY_NONE;
  222. ret = hdmi_avi_infoframe_pack(&infoframe, buffer, sizeof(buffer));
  223. if (ret < 0) {
  224. DRM_ERROR("failed to pack AVI infoframe: %d\n", ret);
  225. return ret;
  226. }
  227. /* Disable transmission slot for AVI infoframe */
  228. val = hdmi_read(hdmi, HDMI_SW_DI_CFG);
  229. val &= ~HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, HDMI_IFRAME_SLOT_AVI);
  230. hdmi_write(hdmi, val, HDMI_SW_DI_CFG);
  231. /* Infoframe header */
  232. val = buffer[0x0];
  233. val |= buffer[0x1] << 8;
  234. val |= buffer[0x2] << 16;
  235. hdmi_write(hdmi, val, HDMI_SW_DI_N_HEAD_WORD(HDMI_IFRAME_SLOT_AVI));
  236. /* Infoframe packet bytes */
  237. val = frame[0x0];
  238. val |= frame[0x1] << 8;
  239. val |= frame[0x2] << 16;
  240. val |= frame[0x3] << 24;
  241. hdmi_write(hdmi, val, HDMI_SW_DI_N_PKT_WORD0(HDMI_IFRAME_SLOT_AVI));
  242. val = frame[0x4];
  243. val |= frame[0x5] << 8;
  244. val |= frame[0x6] << 16;
  245. val |= frame[0x7] << 24;
  246. hdmi_write(hdmi, val, HDMI_SW_DI_N_PKT_WORD1(HDMI_IFRAME_SLOT_AVI));
  247. val = frame[0x8];
  248. val |= frame[0x9] << 8;
  249. val |= frame[0xA] << 16;
  250. val |= frame[0xB] << 24;
  251. hdmi_write(hdmi, val, HDMI_SW_DI_N_PKT_WORD2(HDMI_IFRAME_SLOT_AVI));
  252. val = frame[0xC];
  253. val |= frame[0xD] << 8;
  254. hdmi_write(hdmi, val, HDMI_SW_DI_N_PKT_WORD3(HDMI_IFRAME_SLOT_AVI));
  255. /* Enable transmission slot for AVI infoframe
  256. * According to the hdmi specification, AVI infoframe should be
  257. * transmitted at least once per two video fields
  258. */
  259. val = hdmi_read(hdmi, HDMI_SW_DI_CFG);
  260. val |= HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_FIELD, HDMI_IFRAME_SLOT_AVI);
  261. hdmi_write(hdmi, val, HDMI_SW_DI_CFG);
  262. return 0;
  263. }
  264. /**
  265. * Software reset of the hdmi subsystem
  266. *
  267. * @hdmi: pointer on the hdmi internal structure
  268. *
  269. */
  270. #define HDMI_TIMEOUT_SWRESET 100 /*milliseconds */
  271. static void hdmi_swreset(struct sti_hdmi *hdmi)
  272. {
  273. u32 val;
  274. DRM_DEBUG_DRIVER("\n");
  275. /* Enable hdmi_audio clock only during hdmi reset */
  276. if (clk_prepare_enable(hdmi->clk_audio))
  277. DRM_INFO("Failed to prepare/enable hdmi_audio clk\n");
  278. /* Sw reset */
  279. hdmi->event_received = false;
  280. val = hdmi_read(hdmi, HDMI_CFG);
  281. val |= HDMI_CFG_SW_RST_EN;
  282. hdmi_write(hdmi, val, HDMI_CFG);
  283. /* Wait reset completed */
  284. wait_event_interruptible_timeout(hdmi->wait_event,
  285. hdmi->event_received == true,
  286. msecs_to_jiffies
  287. (HDMI_TIMEOUT_SWRESET));
  288. /*
  289. * HDMI_STA_SW_RST bit is set to '1' when SW_RST bit in HDMI_CFG is
  290. * set to '1' and clk_audio is running.
  291. */
  292. if ((hdmi_read(hdmi, HDMI_STA) & HDMI_STA_SW_RST) == 0)
  293. DRM_DEBUG_DRIVER("Warning: HDMI sw reset timeout occurs\n");
  294. val = hdmi_read(hdmi, HDMI_CFG);
  295. val &= ~HDMI_CFG_SW_RST_EN;
  296. hdmi_write(hdmi, val, HDMI_CFG);
  297. /* Disable hdmi_audio clock. Not used anymore for drm purpose */
  298. clk_disable_unprepare(hdmi->clk_audio);
  299. }
  300. static void sti_hdmi_disable(struct drm_bridge *bridge)
  301. {
  302. struct sti_hdmi *hdmi = bridge->driver_private;
  303. u32 val = hdmi_read(hdmi, HDMI_CFG);
  304. if (!hdmi->enabled)
  305. return;
  306. DRM_DEBUG_DRIVER("\n");
  307. /* Disable HDMI */
  308. val &= ~HDMI_CFG_DEVICE_EN;
  309. hdmi_write(hdmi, val, HDMI_CFG);
  310. hdmi_write(hdmi, 0xffffffff, HDMI_INT_CLR);
  311. /* Stop the phy */
  312. hdmi->phy_ops->stop(hdmi);
  313. /* Set the default channel data to be a dark red */
  314. hdmi_write(hdmi, 0x0000, HDMI_DFLT_CHL0_DAT);
  315. hdmi_write(hdmi, 0x0000, HDMI_DFLT_CHL1_DAT);
  316. hdmi_write(hdmi, 0x0060, HDMI_DFLT_CHL2_DAT);
  317. /* Disable/unprepare hdmi clock */
  318. clk_disable_unprepare(hdmi->clk_phy);
  319. clk_disable_unprepare(hdmi->clk_tmds);
  320. clk_disable_unprepare(hdmi->clk_pix);
  321. hdmi->enabled = false;
  322. }
  323. static void sti_hdmi_pre_enable(struct drm_bridge *bridge)
  324. {
  325. struct sti_hdmi *hdmi = bridge->driver_private;
  326. DRM_DEBUG_DRIVER("\n");
  327. if (hdmi->enabled)
  328. return;
  329. /* Prepare/enable clocks */
  330. if (clk_prepare_enable(hdmi->clk_pix))
  331. DRM_ERROR("Failed to prepare/enable hdmi_pix clk\n");
  332. if (clk_prepare_enable(hdmi->clk_tmds))
  333. DRM_ERROR("Failed to prepare/enable hdmi_tmds clk\n");
  334. if (clk_prepare_enable(hdmi->clk_phy))
  335. DRM_ERROR("Failed to prepare/enable hdmi_rejec_pll clk\n");
  336. hdmi->enabled = true;
  337. /* Program hdmi serializer and start phy */
  338. if (!hdmi->phy_ops->start(hdmi)) {
  339. DRM_ERROR("Unable to start hdmi phy\n");
  340. return;
  341. }
  342. /* Program hdmi active area */
  343. hdmi_active_area(hdmi);
  344. /* Enable working interrupts */
  345. hdmi_write(hdmi, HDMI_WORKING_INT, HDMI_INT_EN);
  346. /* Program hdmi config */
  347. hdmi_config(hdmi);
  348. /* Program AVI infoframe */
  349. if (hdmi_avi_infoframe_config(hdmi))
  350. DRM_ERROR("Unable to configure AVI infoframe\n");
  351. /* Sw reset */
  352. hdmi_swreset(hdmi);
  353. }
  354. static void sti_hdmi_set_mode(struct drm_bridge *bridge,
  355. struct drm_display_mode *mode,
  356. struct drm_display_mode *adjusted_mode)
  357. {
  358. struct sti_hdmi *hdmi = bridge->driver_private;
  359. int ret;
  360. DRM_DEBUG_DRIVER("\n");
  361. /* Copy the drm display mode in the connector local structure */
  362. memcpy(&hdmi->mode, mode, sizeof(struct drm_display_mode));
  363. /* Update clock framerate according to the selected mode */
  364. ret = clk_set_rate(hdmi->clk_pix, mode->clock * 1000);
  365. if (ret < 0) {
  366. DRM_ERROR("Cannot set rate (%dHz) for hdmi_pix clk\n",
  367. mode->clock * 1000);
  368. return;
  369. }
  370. ret = clk_set_rate(hdmi->clk_phy, mode->clock * 1000);
  371. if (ret < 0) {
  372. DRM_ERROR("Cannot set rate (%dHz) for hdmi_rejection_pll clk\n",
  373. mode->clock * 1000);
  374. return;
  375. }
  376. }
  377. static void sti_hdmi_bridge_nope(struct drm_bridge *bridge)
  378. {
  379. /* do nothing */
  380. }
  381. static void sti_hdmi_brigde_destroy(struct drm_bridge *bridge)
  382. {
  383. drm_bridge_cleanup(bridge);
  384. kfree(bridge);
  385. }
  386. static const struct drm_bridge_funcs sti_hdmi_bridge_funcs = {
  387. .pre_enable = sti_hdmi_pre_enable,
  388. .enable = sti_hdmi_bridge_nope,
  389. .disable = sti_hdmi_disable,
  390. .post_disable = sti_hdmi_bridge_nope,
  391. .mode_set = sti_hdmi_set_mode,
  392. .destroy = sti_hdmi_brigde_destroy,
  393. };
  394. static int sti_hdmi_connector_get_modes(struct drm_connector *connector)
  395. {
  396. struct i2c_adapter *i2c_adap;
  397. struct edid *edid;
  398. int count;
  399. DRM_DEBUG_DRIVER("\n");
  400. i2c_adap = i2c_get_adapter(1);
  401. if (!i2c_adap)
  402. goto fail;
  403. edid = drm_get_edid(connector, i2c_adap);
  404. if (!edid)
  405. goto fail;
  406. count = drm_add_edid_modes(connector, edid);
  407. drm_mode_connector_update_edid_property(connector, edid);
  408. kfree(edid);
  409. return count;
  410. fail:
  411. DRM_ERROR("Can not read HDMI EDID\n");
  412. return 0;
  413. }
  414. #define CLK_TOLERANCE_HZ 50
  415. static int sti_hdmi_connector_mode_valid(struct drm_connector *connector,
  416. struct drm_display_mode *mode)
  417. {
  418. int target = mode->clock * 1000;
  419. int target_min = target - CLK_TOLERANCE_HZ;
  420. int target_max = target + CLK_TOLERANCE_HZ;
  421. int result;
  422. struct sti_hdmi_connector *hdmi_connector
  423. = to_sti_hdmi_connector(connector);
  424. struct sti_hdmi *hdmi = hdmi_connector->hdmi;
  425. result = clk_round_rate(hdmi->clk_pix, target);
  426. DRM_DEBUG_DRIVER("target rate = %d => available rate = %d\n",
  427. target, result);
  428. if ((result < target_min) || (result > target_max)) {
  429. DRM_DEBUG_DRIVER("hdmi pixclk=%d not supported\n", target);
  430. return MODE_BAD;
  431. }
  432. return MODE_OK;
  433. }
  434. struct drm_encoder *sti_hdmi_best_encoder(struct drm_connector *connector)
  435. {
  436. struct sti_hdmi_connector *hdmi_connector
  437. = to_sti_hdmi_connector(connector);
  438. /* Best encoder is the one associated during connector creation */
  439. return hdmi_connector->encoder;
  440. }
  441. static struct drm_connector_helper_funcs sti_hdmi_connector_helper_funcs = {
  442. .get_modes = sti_hdmi_connector_get_modes,
  443. .mode_valid = sti_hdmi_connector_mode_valid,
  444. .best_encoder = sti_hdmi_best_encoder,
  445. };
  446. /* get detection status of display device */
  447. static enum drm_connector_status
  448. sti_hdmi_connector_detect(struct drm_connector *connector, bool force)
  449. {
  450. struct sti_hdmi_connector *hdmi_connector
  451. = to_sti_hdmi_connector(connector);
  452. struct sti_hdmi *hdmi = hdmi_connector->hdmi;
  453. DRM_DEBUG_DRIVER("\n");
  454. if (hdmi->hpd) {
  455. DRM_DEBUG_DRIVER("hdmi cable connected\n");
  456. return connector_status_connected;
  457. }
  458. DRM_DEBUG_DRIVER("hdmi cable disconnected\n");
  459. return connector_status_disconnected;
  460. }
  461. static void sti_hdmi_connector_destroy(struct drm_connector *connector)
  462. {
  463. struct sti_hdmi_connector *hdmi_connector
  464. = to_sti_hdmi_connector(connector);
  465. drm_connector_unregister(connector);
  466. drm_connector_cleanup(connector);
  467. kfree(hdmi_connector);
  468. }
  469. static struct drm_connector_funcs sti_hdmi_connector_funcs = {
  470. .dpms = drm_helper_connector_dpms,
  471. .fill_modes = drm_helper_probe_single_connector_modes,
  472. .detect = sti_hdmi_connector_detect,
  473. .destroy = sti_hdmi_connector_destroy,
  474. };
  475. static struct drm_encoder *sti_hdmi_find_encoder(struct drm_device *dev)
  476. {
  477. struct drm_encoder *encoder;
  478. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  479. if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS)
  480. return encoder;
  481. }
  482. return NULL;
  483. }
  484. static int sti_hdmi_bind(struct device *dev, struct device *master, void *data)
  485. {
  486. struct sti_hdmi *hdmi = dev_get_drvdata(dev);
  487. struct drm_device *drm_dev = data;
  488. struct drm_encoder *encoder;
  489. struct sti_hdmi_connector *connector;
  490. struct drm_connector *drm_connector;
  491. struct drm_bridge *bridge;
  492. struct i2c_adapter *i2c_adap;
  493. int err;
  494. i2c_adap = i2c_get_adapter(1);
  495. if (!i2c_adap)
  496. return -EPROBE_DEFER;
  497. /* Set the drm device handle */
  498. hdmi->drm_dev = drm_dev;
  499. encoder = sti_hdmi_find_encoder(drm_dev);
  500. if (!encoder)
  501. return -ENOMEM;
  502. connector = devm_kzalloc(dev, sizeof(*connector), GFP_KERNEL);
  503. if (!connector)
  504. return -ENOMEM;
  505. connector->hdmi = hdmi;
  506. bridge = devm_kzalloc(dev, sizeof(*bridge), GFP_KERNEL);
  507. if (!bridge)
  508. return -ENOMEM;
  509. bridge->driver_private = hdmi;
  510. drm_bridge_init(drm_dev, bridge, &sti_hdmi_bridge_funcs);
  511. encoder->bridge = bridge;
  512. connector->encoder = encoder;
  513. drm_connector = (struct drm_connector *)connector;
  514. drm_connector->polled = DRM_CONNECTOR_POLL_HPD;
  515. drm_connector_init(drm_dev, drm_connector,
  516. &sti_hdmi_connector_funcs, DRM_MODE_CONNECTOR_HDMIA);
  517. drm_connector_helper_add(drm_connector,
  518. &sti_hdmi_connector_helper_funcs);
  519. err = drm_connector_register(drm_connector);
  520. if (err)
  521. goto err_connector;
  522. err = drm_mode_connector_attach_encoder(drm_connector, encoder);
  523. if (err) {
  524. DRM_ERROR("Failed to attach a connector to a encoder\n");
  525. goto err_sysfs;
  526. }
  527. /* Enable default interrupts */
  528. hdmi_write(hdmi, HDMI_DEFAULT_INT, HDMI_INT_EN);
  529. return 0;
  530. err_sysfs:
  531. drm_connector_unregister(drm_connector);
  532. err_connector:
  533. drm_bridge_cleanup(bridge);
  534. drm_connector_cleanup(drm_connector);
  535. return -EINVAL;
  536. }
  537. static void sti_hdmi_unbind(struct device *dev,
  538. struct device *master, void *data)
  539. {
  540. /* do nothing */
  541. }
  542. static const struct component_ops sti_hdmi_ops = {
  543. .bind = sti_hdmi_bind,
  544. .unbind = sti_hdmi_unbind,
  545. };
  546. static const struct of_device_id hdmi_of_match[] = {
  547. {
  548. .compatible = "st,stih416-hdmi",
  549. .data = &tx3g0c55phy_ops,
  550. }, {
  551. .compatible = "st,stih407-hdmi",
  552. .data = &tx3g4c28phy_ops,
  553. }, {
  554. /* end node */
  555. }
  556. };
  557. MODULE_DEVICE_TABLE(of, hdmi_of_match);
  558. static int sti_hdmi_probe(struct platform_device *pdev)
  559. {
  560. struct device *dev = &pdev->dev;
  561. struct sti_hdmi *hdmi;
  562. struct device_node *np = dev->of_node;
  563. struct resource *res;
  564. int ret;
  565. DRM_INFO("%s\n", __func__);
  566. hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
  567. if (!hdmi)
  568. return -ENOMEM;
  569. hdmi->dev = pdev->dev;
  570. /* Get resources */
  571. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi-reg");
  572. if (!res) {
  573. DRM_ERROR("Invalid hdmi resource\n");
  574. return -ENOMEM;
  575. }
  576. hdmi->regs = devm_ioremap_nocache(dev, res->start, resource_size(res));
  577. if (!hdmi->regs)
  578. return -ENOMEM;
  579. if (of_device_is_compatible(np, "st,stih416-hdmi")) {
  580. res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
  581. "syscfg");
  582. if (!res) {
  583. DRM_ERROR("Invalid syscfg resource\n");
  584. return -ENOMEM;
  585. }
  586. hdmi->syscfg = devm_ioremap_nocache(dev, res->start,
  587. resource_size(res));
  588. if (!hdmi->syscfg)
  589. return -ENOMEM;
  590. }
  591. hdmi->phy_ops = (struct hdmi_phy_ops *)
  592. of_match_node(hdmi_of_match, np)->data;
  593. /* Get clock resources */
  594. hdmi->clk_pix = devm_clk_get(dev, "pix");
  595. if (IS_ERR(hdmi->clk_pix)) {
  596. DRM_ERROR("Cannot get hdmi_pix clock\n");
  597. return PTR_ERR(hdmi->clk_pix);
  598. }
  599. hdmi->clk_tmds = devm_clk_get(dev, "tmds");
  600. if (IS_ERR(hdmi->clk_tmds)) {
  601. DRM_ERROR("Cannot get hdmi_tmds clock\n");
  602. return PTR_ERR(hdmi->clk_tmds);
  603. }
  604. hdmi->clk_phy = devm_clk_get(dev, "phy");
  605. if (IS_ERR(hdmi->clk_phy)) {
  606. DRM_ERROR("Cannot get hdmi_phy clock\n");
  607. return PTR_ERR(hdmi->clk_phy);
  608. }
  609. hdmi->clk_audio = devm_clk_get(dev, "audio");
  610. if (IS_ERR(hdmi->clk_audio)) {
  611. DRM_ERROR("Cannot get hdmi_audio clock\n");
  612. return PTR_ERR(hdmi->clk_audio);
  613. }
  614. hdmi->hpd_gpio = of_get_named_gpio(np, "hdmi,hpd-gpio", 0);
  615. if (hdmi->hpd_gpio < 0) {
  616. DRM_ERROR("Failed to get hdmi hpd-gpio\n");
  617. return -EIO;
  618. }
  619. hdmi->hpd = gpio_get_value(hdmi->hpd_gpio);
  620. init_waitqueue_head(&hdmi->wait_event);
  621. hdmi->irq = platform_get_irq_byname(pdev, "irq");
  622. ret = devm_request_threaded_irq(dev, hdmi->irq, hdmi_irq,
  623. hdmi_irq_thread, IRQF_ONESHOT, dev_name(dev), hdmi);
  624. if (ret) {
  625. DRM_ERROR("Failed to register HDMI interrupt\n");
  626. return ret;
  627. }
  628. hdmi->reset = devm_reset_control_get(dev, "hdmi");
  629. /* Take hdmi out of reset */
  630. if (!IS_ERR(hdmi->reset))
  631. reset_control_deassert(hdmi->reset);
  632. platform_set_drvdata(pdev, hdmi);
  633. return component_add(&pdev->dev, &sti_hdmi_ops);
  634. }
  635. static int sti_hdmi_remove(struct platform_device *pdev)
  636. {
  637. component_del(&pdev->dev, &sti_hdmi_ops);
  638. return 0;
  639. }
  640. struct platform_driver sti_hdmi_driver = {
  641. .driver = {
  642. .name = "sti-hdmi",
  643. .owner = THIS_MODULE,
  644. .of_match_table = hdmi_of_match,
  645. },
  646. .probe = sti_hdmi_probe,
  647. .remove = sti_hdmi_remove,
  648. };
  649. module_platform_driver(sti_hdmi_driver);
  650. MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@st.com>");
  651. MODULE_DESCRIPTION("STMicroelectronics SoC DRM driver");
  652. MODULE_LICENSE("GPL");