msm_drv.c 24 KB

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  1. /*
  2. * Copyright (C) 2013 Red Hat
  3. * Author: Rob Clark <robdclark@gmail.com>
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License version 2 as published by
  7. * the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program. If not, see <http://www.gnu.org/licenses/>.
  16. */
  17. #include "msm_drv.h"
  18. #include "msm_gpu.h"
  19. #include "msm_kms.h"
  20. static void msm_fb_output_poll_changed(struct drm_device *dev)
  21. {
  22. struct msm_drm_private *priv = dev->dev_private;
  23. if (priv->fbdev)
  24. drm_fb_helper_hotplug_event(priv->fbdev);
  25. }
  26. static const struct drm_mode_config_funcs mode_config_funcs = {
  27. .fb_create = msm_framebuffer_create,
  28. .output_poll_changed = msm_fb_output_poll_changed,
  29. };
  30. int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu)
  31. {
  32. struct msm_drm_private *priv = dev->dev_private;
  33. int idx = priv->num_mmus++;
  34. if (WARN_ON(idx >= ARRAY_SIZE(priv->mmus)))
  35. return -EINVAL;
  36. priv->mmus[idx] = mmu;
  37. return idx;
  38. }
  39. #ifdef CONFIG_DRM_MSM_REGISTER_LOGGING
  40. static bool reglog = false;
  41. MODULE_PARM_DESC(reglog, "Enable register read/write logging");
  42. module_param(reglog, bool, 0600);
  43. #else
  44. #define reglog 0
  45. #endif
  46. static char *vram = "16m";
  47. MODULE_PARM_DESC(vram, "Configure VRAM size (for devices without IOMMU/GPUMMU");
  48. module_param(vram, charp, 0);
  49. /*
  50. * Util/helpers:
  51. */
  52. void __iomem *msm_ioremap(struct platform_device *pdev, const char *name,
  53. const char *dbgname)
  54. {
  55. struct resource *res;
  56. unsigned long size;
  57. void __iomem *ptr;
  58. if (name)
  59. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
  60. else
  61. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  62. if (!res) {
  63. dev_err(&pdev->dev, "failed to get memory resource: %s\n", name);
  64. return ERR_PTR(-EINVAL);
  65. }
  66. size = resource_size(res);
  67. ptr = devm_ioremap_nocache(&pdev->dev, res->start, size);
  68. if (!ptr) {
  69. dev_err(&pdev->dev, "failed to ioremap: %s\n", name);
  70. return ERR_PTR(-ENOMEM);
  71. }
  72. if (reglog)
  73. printk(KERN_DEBUG "IO:region %s %08x %08lx\n", dbgname, (u32)ptr, size);
  74. return ptr;
  75. }
  76. void msm_writel(u32 data, void __iomem *addr)
  77. {
  78. if (reglog)
  79. printk(KERN_DEBUG "IO:W %08x %08x\n", (u32)addr, data);
  80. writel(data, addr);
  81. }
  82. u32 msm_readl(const void __iomem *addr)
  83. {
  84. u32 val = readl(addr);
  85. if (reglog)
  86. printk(KERN_ERR "IO:R %08x %08x\n", (u32)addr, val);
  87. return val;
  88. }
  89. /*
  90. * DRM operations:
  91. */
  92. static int msm_unload(struct drm_device *dev)
  93. {
  94. struct msm_drm_private *priv = dev->dev_private;
  95. struct msm_kms *kms = priv->kms;
  96. struct msm_gpu *gpu = priv->gpu;
  97. drm_kms_helper_poll_fini(dev);
  98. drm_mode_config_cleanup(dev);
  99. drm_vblank_cleanup(dev);
  100. pm_runtime_get_sync(dev->dev);
  101. drm_irq_uninstall(dev);
  102. pm_runtime_put_sync(dev->dev);
  103. flush_workqueue(priv->wq);
  104. destroy_workqueue(priv->wq);
  105. if (kms) {
  106. pm_runtime_disable(dev->dev);
  107. kms->funcs->destroy(kms);
  108. }
  109. if (gpu) {
  110. mutex_lock(&dev->struct_mutex);
  111. gpu->funcs->pm_suspend(gpu);
  112. gpu->funcs->destroy(gpu);
  113. mutex_unlock(&dev->struct_mutex);
  114. }
  115. if (priv->vram.paddr) {
  116. DEFINE_DMA_ATTRS(attrs);
  117. dma_set_attr(DMA_ATTR_NO_KERNEL_MAPPING, &attrs);
  118. drm_mm_takedown(&priv->vram.mm);
  119. dma_free_attrs(dev->dev, priv->vram.size, NULL,
  120. priv->vram.paddr, &attrs);
  121. }
  122. component_unbind_all(dev->dev, dev);
  123. dev->dev_private = NULL;
  124. kfree(priv);
  125. return 0;
  126. }
  127. static int get_mdp_ver(struct platform_device *pdev)
  128. {
  129. #ifdef CONFIG_OF
  130. static const struct of_device_id match_types[] = { {
  131. .compatible = "qcom,mdss_mdp",
  132. .data = (void *)5,
  133. }, {
  134. /* end node */
  135. } };
  136. struct device *dev = &pdev->dev;
  137. const struct of_device_id *match;
  138. match = of_match_node(match_types, dev->of_node);
  139. if (match)
  140. return (int)match->data;
  141. #endif
  142. return 4;
  143. }
  144. static int msm_load(struct drm_device *dev, unsigned long flags)
  145. {
  146. struct platform_device *pdev = dev->platformdev;
  147. struct msm_drm_private *priv;
  148. struct msm_kms *kms;
  149. int ret;
  150. priv = kzalloc(sizeof(*priv), GFP_KERNEL);
  151. if (!priv) {
  152. dev_err(dev->dev, "failed to allocate private data\n");
  153. return -ENOMEM;
  154. }
  155. dev->dev_private = priv;
  156. priv->wq = alloc_ordered_workqueue("msm", 0);
  157. init_waitqueue_head(&priv->fence_event);
  158. INIT_LIST_HEAD(&priv->inactive_list);
  159. INIT_LIST_HEAD(&priv->fence_cbs);
  160. drm_mode_config_init(dev);
  161. /* if we have no IOMMU, then we need to use carveout allocator.
  162. * Grab the entire CMA chunk carved out in early startup in
  163. * mach-msm:
  164. */
  165. if (!iommu_present(&platform_bus_type)) {
  166. DEFINE_DMA_ATTRS(attrs);
  167. unsigned long size;
  168. void *p;
  169. DBG("using %s VRAM carveout", vram);
  170. size = memparse(vram, NULL);
  171. priv->vram.size = size;
  172. drm_mm_init(&priv->vram.mm, 0, (size >> PAGE_SHIFT) - 1);
  173. dma_set_attr(DMA_ATTR_NO_KERNEL_MAPPING, &attrs);
  174. dma_set_attr(DMA_ATTR_WRITE_COMBINE, &attrs);
  175. /* note that for no-kernel-mapping, the vaddr returned
  176. * is bogus, but non-null if allocation succeeded:
  177. */
  178. p = dma_alloc_attrs(dev->dev, size,
  179. &priv->vram.paddr, GFP_KERNEL, &attrs);
  180. if (!p) {
  181. dev_err(dev->dev, "failed to allocate VRAM\n");
  182. priv->vram.paddr = 0;
  183. ret = -ENOMEM;
  184. goto fail;
  185. }
  186. dev_info(dev->dev, "VRAM: %08x->%08x\n",
  187. (uint32_t)priv->vram.paddr,
  188. (uint32_t)(priv->vram.paddr + size));
  189. }
  190. platform_set_drvdata(pdev, dev);
  191. /* Bind all our sub-components: */
  192. ret = component_bind_all(dev->dev, dev);
  193. if (ret)
  194. return ret;
  195. switch (get_mdp_ver(pdev)) {
  196. case 4:
  197. kms = mdp4_kms_init(dev);
  198. break;
  199. case 5:
  200. kms = mdp5_kms_init(dev);
  201. break;
  202. default:
  203. kms = ERR_PTR(-ENODEV);
  204. break;
  205. }
  206. if (IS_ERR(kms)) {
  207. /*
  208. * NOTE: once we have GPU support, having no kms should not
  209. * be considered fatal.. ideally we would still support gpu
  210. * and (for example) use dmabuf/prime to share buffers with
  211. * imx drm driver on iMX5
  212. */
  213. dev_err(dev->dev, "failed to load kms\n");
  214. ret = PTR_ERR(kms);
  215. goto fail;
  216. }
  217. priv->kms = kms;
  218. if (kms) {
  219. pm_runtime_enable(dev->dev);
  220. ret = kms->funcs->hw_init(kms);
  221. if (ret) {
  222. dev_err(dev->dev, "kms hw init failed: %d\n", ret);
  223. goto fail;
  224. }
  225. }
  226. dev->mode_config.min_width = 0;
  227. dev->mode_config.min_height = 0;
  228. dev->mode_config.max_width = 2048;
  229. dev->mode_config.max_height = 2048;
  230. dev->mode_config.funcs = &mode_config_funcs;
  231. ret = drm_vblank_init(dev, 1);
  232. if (ret < 0) {
  233. dev_err(dev->dev, "failed to initialize vblank\n");
  234. goto fail;
  235. }
  236. pm_runtime_get_sync(dev->dev);
  237. ret = drm_irq_install(dev, platform_get_irq(dev->platformdev, 0));
  238. pm_runtime_put_sync(dev->dev);
  239. if (ret < 0) {
  240. dev_err(dev->dev, "failed to install IRQ handler\n");
  241. goto fail;
  242. }
  243. #ifdef CONFIG_DRM_MSM_FBDEV
  244. priv->fbdev = msm_fbdev_init(dev);
  245. #endif
  246. ret = msm_debugfs_late_init(dev);
  247. if (ret)
  248. goto fail;
  249. drm_kms_helper_poll_init(dev);
  250. return 0;
  251. fail:
  252. msm_unload(dev);
  253. return ret;
  254. }
  255. static void load_gpu(struct drm_device *dev)
  256. {
  257. static DEFINE_MUTEX(init_lock);
  258. struct msm_drm_private *priv = dev->dev_private;
  259. struct msm_gpu *gpu;
  260. mutex_lock(&init_lock);
  261. if (priv->gpu)
  262. goto out;
  263. gpu = a3xx_gpu_init(dev);
  264. if (IS_ERR(gpu)) {
  265. dev_warn(dev->dev, "failed to load a3xx gpu\n");
  266. gpu = NULL;
  267. /* not fatal */
  268. }
  269. if (gpu) {
  270. int ret;
  271. mutex_lock(&dev->struct_mutex);
  272. gpu->funcs->pm_resume(gpu);
  273. mutex_unlock(&dev->struct_mutex);
  274. ret = gpu->funcs->hw_init(gpu);
  275. if (ret) {
  276. dev_err(dev->dev, "gpu hw init failed: %d\n", ret);
  277. gpu->funcs->destroy(gpu);
  278. gpu = NULL;
  279. } else {
  280. /* give inactive pm a chance to kick in: */
  281. msm_gpu_retire(gpu);
  282. }
  283. }
  284. priv->gpu = gpu;
  285. out:
  286. mutex_unlock(&init_lock);
  287. }
  288. static int msm_open(struct drm_device *dev, struct drm_file *file)
  289. {
  290. struct msm_file_private *ctx;
  291. /* For now, load gpu on open.. to avoid the requirement of having
  292. * firmware in the initrd.
  293. */
  294. load_gpu(dev);
  295. ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
  296. if (!ctx)
  297. return -ENOMEM;
  298. file->driver_priv = ctx;
  299. return 0;
  300. }
  301. static void msm_preclose(struct drm_device *dev, struct drm_file *file)
  302. {
  303. struct msm_drm_private *priv = dev->dev_private;
  304. struct msm_file_private *ctx = file->driver_priv;
  305. struct msm_kms *kms = priv->kms;
  306. if (kms)
  307. kms->funcs->preclose(kms, file);
  308. mutex_lock(&dev->struct_mutex);
  309. if (ctx == priv->lastctx)
  310. priv->lastctx = NULL;
  311. mutex_unlock(&dev->struct_mutex);
  312. kfree(ctx);
  313. }
  314. static void msm_lastclose(struct drm_device *dev)
  315. {
  316. struct msm_drm_private *priv = dev->dev_private;
  317. if (priv->fbdev)
  318. drm_fb_helper_restore_fbdev_mode_unlocked(priv->fbdev);
  319. }
  320. static irqreturn_t msm_irq(int irq, void *arg)
  321. {
  322. struct drm_device *dev = arg;
  323. struct msm_drm_private *priv = dev->dev_private;
  324. struct msm_kms *kms = priv->kms;
  325. BUG_ON(!kms);
  326. return kms->funcs->irq(kms);
  327. }
  328. static void msm_irq_preinstall(struct drm_device *dev)
  329. {
  330. struct msm_drm_private *priv = dev->dev_private;
  331. struct msm_kms *kms = priv->kms;
  332. BUG_ON(!kms);
  333. kms->funcs->irq_preinstall(kms);
  334. }
  335. static int msm_irq_postinstall(struct drm_device *dev)
  336. {
  337. struct msm_drm_private *priv = dev->dev_private;
  338. struct msm_kms *kms = priv->kms;
  339. BUG_ON(!kms);
  340. return kms->funcs->irq_postinstall(kms);
  341. }
  342. static void msm_irq_uninstall(struct drm_device *dev)
  343. {
  344. struct msm_drm_private *priv = dev->dev_private;
  345. struct msm_kms *kms = priv->kms;
  346. BUG_ON(!kms);
  347. kms->funcs->irq_uninstall(kms);
  348. }
  349. static int msm_enable_vblank(struct drm_device *dev, int crtc_id)
  350. {
  351. struct msm_drm_private *priv = dev->dev_private;
  352. struct msm_kms *kms = priv->kms;
  353. if (!kms)
  354. return -ENXIO;
  355. DBG("dev=%p, crtc=%d", dev, crtc_id);
  356. return kms->funcs->enable_vblank(kms, priv->crtcs[crtc_id]);
  357. }
  358. static void msm_disable_vblank(struct drm_device *dev, int crtc_id)
  359. {
  360. struct msm_drm_private *priv = dev->dev_private;
  361. struct msm_kms *kms = priv->kms;
  362. if (!kms)
  363. return;
  364. DBG("dev=%p, crtc=%d", dev, crtc_id);
  365. kms->funcs->disable_vblank(kms, priv->crtcs[crtc_id]);
  366. }
  367. /*
  368. * DRM debugfs:
  369. */
  370. #ifdef CONFIG_DEBUG_FS
  371. static int msm_gpu_show(struct drm_device *dev, struct seq_file *m)
  372. {
  373. struct msm_drm_private *priv = dev->dev_private;
  374. struct msm_gpu *gpu = priv->gpu;
  375. if (gpu) {
  376. seq_printf(m, "%s Status:\n", gpu->name);
  377. gpu->funcs->show(gpu, m);
  378. }
  379. return 0;
  380. }
  381. static int msm_gem_show(struct drm_device *dev, struct seq_file *m)
  382. {
  383. struct msm_drm_private *priv = dev->dev_private;
  384. struct msm_gpu *gpu = priv->gpu;
  385. if (gpu) {
  386. seq_printf(m, "Active Objects (%s):\n", gpu->name);
  387. msm_gem_describe_objects(&gpu->active_list, m);
  388. }
  389. seq_printf(m, "Inactive Objects:\n");
  390. msm_gem_describe_objects(&priv->inactive_list, m);
  391. return 0;
  392. }
  393. static int msm_mm_show(struct drm_device *dev, struct seq_file *m)
  394. {
  395. return drm_mm_dump_table(m, &dev->vma_offset_manager->vm_addr_space_mm);
  396. }
  397. static int msm_fb_show(struct drm_device *dev, struct seq_file *m)
  398. {
  399. struct msm_drm_private *priv = dev->dev_private;
  400. struct drm_framebuffer *fb, *fbdev_fb = NULL;
  401. if (priv->fbdev) {
  402. seq_printf(m, "fbcon ");
  403. fbdev_fb = priv->fbdev->fb;
  404. msm_framebuffer_describe(fbdev_fb, m);
  405. }
  406. mutex_lock(&dev->mode_config.fb_lock);
  407. list_for_each_entry(fb, &dev->mode_config.fb_list, head) {
  408. if (fb == fbdev_fb)
  409. continue;
  410. seq_printf(m, "user ");
  411. msm_framebuffer_describe(fb, m);
  412. }
  413. mutex_unlock(&dev->mode_config.fb_lock);
  414. return 0;
  415. }
  416. static int show_locked(struct seq_file *m, void *arg)
  417. {
  418. struct drm_info_node *node = (struct drm_info_node *) m->private;
  419. struct drm_device *dev = node->minor->dev;
  420. int (*show)(struct drm_device *dev, struct seq_file *m) =
  421. node->info_ent->data;
  422. int ret;
  423. ret = mutex_lock_interruptible(&dev->struct_mutex);
  424. if (ret)
  425. return ret;
  426. ret = show(dev, m);
  427. mutex_unlock(&dev->struct_mutex);
  428. return ret;
  429. }
  430. static struct drm_info_list msm_debugfs_list[] = {
  431. {"gpu", show_locked, 0, msm_gpu_show},
  432. {"gem", show_locked, 0, msm_gem_show},
  433. { "mm", show_locked, 0, msm_mm_show },
  434. { "fb", show_locked, 0, msm_fb_show },
  435. };
  436. static int late_init_minor(struct drm_minor *minor)
  437. {
  438. int ret;
  439. if (!minor)
  440. return 0;
  441. ret = msm_rd_debugfs_init(minor);
  442. if (ret) {
  443. dev_err(minor->dev->dev, "could not install rd debugfs\n");
  444. return ret;
  445. }
  446. ret = msm_perf_debugfs_init(minor);
  447. if (ret) {
  448. dev_err(minor->dev->dev, "could not install perf debugfs\n");
  449. return ret;
  450. }
  451. return 0;
  452. }
  453. int msm_debugfs_late_init(struct drm_device *dev)
  454. {
  455. int ret;
  456. ret = late_init_minor(dev->primary);
  457. if (ret)
  458. return ret;
  459. ret = late_init_minor(dev->render);
  460. if (ret)
  461. return ret;
  462. ret = late_init_minor(dev->control);
  463. return ret;
  464. }
  465. static int msm_debugfs_init(struct drm_minor *minor)
  466. {
  467. struct drm_device *dev = minor->dev;
  468. int ret;
  469. ret = drm_debugfs_create_files(msm_debugfs_list,
  470. ARRAY_SIZE(msm_debugfs_list),
  471. minor->debugfs_root, minor);
  472. if (ret) {
  473. dev_err(dev->dev, "could not install msm_debugfs_list\n");
  474. return ret;
  475. }
  476. return 0;
  477. }
  478. static void msm_debugfs_cleanup(struct drm_minor *minor)
  479. {
  480. drm_debugfs_remove_files(msm_debugfs_list,
  481. ARRAY_SIZE(msm_debugfs_list), minor);
  482. if (!minor->dev->dev_private)
  483. return;
  484. msm_rd_debugfs_cleanup(minor);
  485. msm_perf_debugfs_cleanup(minor);
  486. }
  487. #endif
  488. /*
  489. * Fences:
  490. */
  491. int msm_wait_fence_interruptable(struct drm_device *dev, uint32_t fence,
  492. struct timespec *timeout)
  493. {
  494. struct msm_drm_private *priv = dev->dev_private;
  495. int ret;
  496. if (!priv->gpu)
  497. return 0;
  498. if (fence > priv->gpu->submitted_fence) {
  499. DRM_ERROR("waiting on invalid fence: %u (of %u)\n",
  500. fence, priv->gpu->submitted_fence);
  501. return -EINVAL;
  502. }
  503. if (!timeout) {
  504. /* no-wait: */
  505. ret = fence_completed(dev, fence) ? 0 : -EBUSY;
  506. } else {
  507. unsigned long timeout_jiffies = timespec_to_jiffies(timeout);
  508. unsigned long start_jiffies = jiffies;
  509. unsigned long remaining_jiffies;
  510. if (time_after(start_jiffies, timeout_jiffies))
  511. remaining_jiffies = 0;
  512. else
  513. remaining_jiffies = timeout_jiffies - start_jiffies;
  514. ret = wait_event_interruptible_timeout(priv->fence_event,
  515. fence_completed(dev, fence),
  516. remaining_jiffies);
  517. if (ret == 0) {
  518. DBG("timeout waiting for fence: %u (completed: %u)",
  519. fence, priv->completed_fence);
  520. ret = -ETIMEDOUT;
  521. } else if (ret != -ERESTARTSYS) {
  522. ret = 0;
  523. }
  524. }
  525. return ret;
  526. }
  527. /* called from workqueue */
  528. void msm_update_fence(struct drm_device *dev, uint32_t fence)
  529. {
  530. struct msm_drm_private *priv = dev->dev_private;
  531. mutex_lock(&dev->struct_mutex);
  532. priv->completed_fence = max(fence, priv->completed_fence);
  533. while (!list_empty(&priv->fence_cbs)) {
  534. struct msm_fence_cb *cb;
  535. cb = list_first_entry(&priv->fence_cbs,
  536. struct msm_fence_cb, work.entry);
  537. if (cb->fence > priv->completed_fence)
  538. break;
  539. list_del_init(&cb->work.entry);
  540. queue_work(priv->wq, &cb->work);
  541. }
  542. mutex_unlock(&dev->struct_mutex);
  543. wake_up_all(&priv->fence_event);
  544. }
  545. void __msm_fence_worker(struct work_struct *work)
  546. {
  547. struct msm_fence_cb *cb = container_of(work, struct msm_fence_cb, work);
  548. cb->func(cb);
  549. }
  550. /*
  551. * DRM ioctls:
  552. */
  553. static int msm_ioctl_get_param(struct drm_device *dev, void *data,
  554. struct drm_file *file)
  555. {
  556. struct msm_drm_private *priv = dev->dev_private;
  557. struct drm_msm_param *args = data;
  558. struct msm_gpu *gpu;
  559. /* for now, we just have 3d pipe.. eventually this would need to
  560. * be more clever to dispatch to appropriate gpu module:
  561. */
  562. if (args->pipe != MSM_PIPE_3D0)
  563. return -EINVAL;
  564. gpu = priv->gpu;
  565. if (!gpu)
  566. return -ENXIO;
  567. return gpu->funcs->get_param(gpu, args->param, &args->value);
  568. }
  569. static int msm_ioctl_gem_new(struct drm_device *dev, void *data,
  570. struct drm_file *file)
  571. {
  572. struct drm_msm_gem_new *args = data;
  573. if (args->flags & ~MSM_BO_FLAGS) {
  574. DRM_ERROR("invalid flags: %08x\n", args->flags);
  575. return -EINVAL;
  576. }
  577. return msm_gem_new_handle(dev, file, args->size,
  578. args->flags, &args->handle);
  579. }
  580. #define TS(t) ((struct timespec){ .tv_sec = (t).tv_sec, .tv_nsec = (t).tv_nsec })
  581. static int msm_ioctl_gem_cpu_prep(struct drm_device *dev, void *data,
  582. struct drm_file *file)
  583. {
  584. struct drm_msm_gem_cpu_prep *args = data;
  585. struct drm_gem_object *obj;
  586. int ret;
  587. if (args->op & ~MSM_PREP_FLAGS) {
  588. DRM_ERROR("invalid op: %08x\n", args->op);
  589. return -EINVAL;
  590. }
  591. obj = drm_gem_object_lookup(dev, file, args->handle);
  592. if (!obj)
  593. return -ENOENT;
  594. ret = msm_gem_cpu_prep(obj, args->op, &TS(args->timeout));
  595. drm_gem_object_unreference_unlocked(obj);
  596. return ret;
  597. }
  598. static int msm_ioctl_gem_cpu_fini(struct drm_device *dev, void *data,
  599. struct drm_file *file)
  600. {
  601. struct drm_msm_gem_cpu_fini *args = data;
  602. struct drm_gem_object *obj;
  603. int ret;
  604. obj = drm_gem_object_lookup(dev, file, args->handle);
  605. if (!obj)
  606. return -ENOENT;
  607. ret = msm_gem_cpu_fini(obj);
  608. drm_gem_object_unreference_unlocked(obj);
  609. return ret;
  610. }
  611. static int msm_ioctl_gem_info(struct drm_device *dev, void *data,
  612. struct drm_file *file)
  613. {
  614. struct drm_msm_gem_info *args = data;
  615. struct drm_gem_object *obj;
  616. int ret = 0;
  617. if (args->pad)
  618. return -EINVAL;
  619. obj = drm_gem_object_lookup(dev, file, args->handle);
  620. if (!obj)
  621. return -ENOENT;
  622. args->offset = msm_gem_mmap_offset(obj);
  623. drm_gem_object_unreference_unlocked(obj);
  624. return ret;
  625. }
  626. static int msm_ioctl_wait_fence(struct drm_device *dev, void *data,
  627. struct drm_file *file)
  628. {
  629. struct drm_msm_wait_fence *args = data;
  630. if (args->pad) {
  631. DRM_ERROR("invalid pad: %08x\n", args->pad);
  632. return -EINVAL;
  633. }
  634. return msm_wait_fence_interruptable(dev, args->fence,
  635. &TS(args->timeout));
  636. }
  637. static const struct drm_ioctl_desc msm_ioctls[] = {
  638. DRM_IOCTL_DEF_DRV(MSM_GET_PARAM, msm_ioctl_get_param, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
  639. DRM_IOCTL_DEF_DRV(MSM_GEM_NEW, msm_ioctl_gem_new, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
  640. DRM_IOCTL_DEF_DRV(MSM_GEM_INFO, msm_ioctl_gem_info, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
  641. DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_PREP, msm_ioctl_gem_cpu_prep, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
  642. DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_FINI, msm_ioctl_gem_cpu_fini, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
  643. DRM_IOCTL_DEF_DRV(MSM_GEM_SUBMIT, msm_ioctl_gem_submit, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
  644. DRM_IOCTL_DEF_DRV(MSM_WAIT_FENCE, msm_ioctl_wait_fence, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
  645. };
  646. static const struct vm_operations_struct vm_ops = {
  647. .fault = msm_gem_fault,
  648. .open = drm_gem_vm_open,
  649. .close = drm_gem_vm_close,
  650. };
  651. static const struct file_operations fops = {
  652. .owner = THIS_MODULE,
  653. .open = drm_open,
  654. .release = drm_release,
  655. .unlocked_ioctl = drm_ioctl,
  656. #ifdef CONFIG_COMPAT
  657. .compat_ioctl = drm_compat_ioctl,
  658. #endif
  659. .poll = drm_poll,
  660. .read = drm_read,
  661. .llseek = no_llseek,
  662. .mmap = msm_gem_mmap,
  663. };
  664. static struct drm_driver msm_driver = {
  665. .driver_features = DRIVER_HAVE_IRQ |
  666. DRIVER_GEM |
  667. DRIVER_PRIME |
  668. DRIVER_RENDER |
  669. DRIVER_MODESET,
  670. .load = msm_load,
  671. .unload = msm_unload,
  672. .open = msm_open,
  673. .preclose = msm_preclose,
  674. .lastclose = msm_lastclose,
  675. .irq_handler = msm_irq,
  676. .irq_preinstall = msm_irq_preinstall,
  677. .irq_postinstall = msm_irq_postinstall,
  678. .irq_uninstall = msm_irq_uninstall,
  679. .get_vblank_counter = drm_vblank_count,
  680. .enable_vblank = msm_enable_vblank,
  681. .disable_vblank = msm_disable_vblank,
  682. .gem_free_object = msm_gem_free_object,
  683. .gem_vm_ops = &vm_ops,
  684. .dumb_create = msm_gem_dumb_create,
  685. .dumb_map_offset = msm_gem_dumb_map_offset,
  686. .dumb_destroy = drm_gem_dumb_destroy,
  687. .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
  688. .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
  689. .gem_prime_export = drm_gem_prime_export,
  690. .gem_prime_import = drm_gem_prime_import,
  691. .gem_prime_pin = msm_gem_prime_pin,
  692. .gem_prime_unpin = msm_gem_prime_unpin,
  693. .gem_prime_get_sg_table = msm_gem_prime_get_sg_table,
  694. .gem_prime_import_sg_table = msm_gem_prime_import_sg_table,
  695. .gem_prime_vmap = msm_gem_prime_vmap,
  696. .gem_prime_vunmap = msm_gem_prime_vunmap,
  697. #ifdef CONFIG_DEBUG_FS
  698. .debugfs_init = msm_debugfs_init,
  699. .debugfs_cleanup = msm_debugfs_cleanup,
  700. #endif
  701. .ioctls = msm_ioctls,
  702. .num_ioctls = DRM_MSM_NUM_IOCTLS,
  703. .fops = &fops,
  704. .name = "msm",
  705. .desc = "MSM Snapdragon DRM",
  706. .date = "20130625",
  707. .major = 1,
  708. .minor = 0,
  709. };
  710. #ifdef CONFIG_PM_SLEEP
  711. static int msm_pm_suspend(struct device *dev)
  712. {
  713. struct drm_device *ddev = dev_get_drvdata(dev);
  714. drm_kms_helper_poll_disable(ddev);
  715. return 0;
  716. }
  717. static int msm_pm_resume(struct device *dev)
  718. {
  719. struct drm_device *ddev = dev_get_drvdata(dev);
  720. drm_kms_helper_poll_enable(ddev);
  721. return 0;
  722. }
  723. #endif
  724. static const struct dev_pm_ops msm_pm_ops = {
  725. SET_SYSTEM_SLEEP_PM_OPS(msm_pm_suspend, msm_pm_resume)
  726. };
  727. /*
  728. * Componentized driver support:
  729. */
  730. #ifdef CONFIG_OF
  731. /* NOTE: the CONFIG_OF case duplicates the same code as exynos or imx
  732. * (or probably any other).. so probably some room for some helpers
  733. */
  734. static int compare_of(struct device *dev, void *data)
  735. {
  736. return dev->of_node == data;
  737. }
  738. static int add_components(struct device *dev, struct component_match **matchptr,
  739. const char *name)
  740. {
  741. struct device_node *np = dev->of_node;
  742. unsigned i;
  743. for (i = 0; ; i++) {
  744. struct device_node *node;
  745. node = of_parse_phandle(np, name, i);
  746. if (!node)
  747. break;
  748. component_match_add(dev, matchptr, compare_of, node);
  749. }
  750. return 0;
  751. }
  752. #else
  753. static int compare_dev(struct device *dev, void *data)
  754. {
  755. return dev == data;
  756. }
  757. #endif
  758. static int msm_drm_bind(struct device *dev)
  759. {
  760. return drm_platform_init(&msm_driver, to_platform_device(dev));
  761. }
  762. static void msm_drm_unbind(struct device *dev)
  763. {
  764. drm_put_dev(platform_get_drvdata(to_platform_device(dev)));
  765. }
  766. static const struct component_master_ops msm_drm_ops = {
  767. .bind = msm_drm_bind,
  768. .unbind = msm_drm_unbind,
  769. };
  770. /*
  771. * Platform driver:
  772. */
  773. static int msm_pdev_probe(struct platform_device *pdev)
  774. {
  775. struct component_match *match = NULL;
  776. #ifdef CONFIG_OF
  777. add_components(&pdev->dev, &match, "connectors");
  778. add_components(&pdev->dev, &match, "gpus");
  779. #else
  780. /* For non-DT case, it kinda sucks. We don't actually have a way
  781. * to know whether or not we are waiting for certain devices (or if
  782. * they are simply not present). But for non-DT we only need to
  783. * care about apq8064/apq8060/etc (all mdp4/a3xx):
  784. */
  785. static const char *devnames[] = {
  786. "hdmi_msm.0", "kgsl-3d0.0",
  787. };
  788. int i;
  789. DBG("Adding components..");
  790. for (i = 0; i < ARRAY_SIZE(devnames); i++) {
  791. struct device *dev;
  792. dev = bus_find_device_by_name(&platform_bus_type,
  793. NULL, devnames[i]);
  794. if (!dev) {
  795. dev_info(&pdev->dev, "still waiting for %s\n", devnames[i]);
  796. return -EPROBE_DEFER;
  797. }
  798. component_match_add(&pdev->dev, &match, compare_dev, dev);
  799. }
  800. #endif
  801. pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
  802. return component_master_add_with_match(&pdev->dev, &msm_drm_ops, match);
  803. }
  804. static int msm_pdev_remove(struct platform_device *pdev)
  805. {
  806. component_master_del(&pdev->dev, &msm_drm_ops);
  807. return 0;
  808. }
  809. static const struct platform_device_id msm_id[] = {
  810. { "mdp", 0 },
  811. { }
  812. };
  813. static const struct of_device_id dt_match[] = {
  814. { .compatible = "qcom,mdp" }, /* mdp4 */
  815. { .compatible = "qcom,mdss_mdp" }, /* mdp5 */
  816. {}
  817. };
  818. MODULE_DEVICE_TABLE(of, dt_match);
  819. static struct platform_driver msm_platform_driver = {
  820. .probe = msm_pdev_probe,
  821. .remove = msm_pdev_remove,
  822. .driver = {
  823. .owner = THIS_MODULE,
  824. .name = "msm",
  825. .of_match_table = dt_match,
  826. .pm = &msm_pm_ops,
  827. },
  828. .id_table = msm_id,
  829. };
  830. static int __init msm_drm_register(void)
  831. {
  832. DBG("init");
  833. hdmi_register();
  834. a3xx_register();
  835. return platform_driver_register(&msm_platform_driver);
  836. }
  837. static void __exit msm_drm_unregister(void)
  838. {
  839. DBG("fini");
  840. platform_driver_unregister(&msm_platform_driver);
  841. hdmi_unregister();
  842. a3xx_unregister();
  843. }
  844. module_init(msm_drm_register);
  845. module_exit(msm_drm_unregister);
  846. MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
  847. MODULE_DESCRIPTION("MSM DRM Driver");
  848. MODULE_LICENSE("GPL");