mdp4_kms.h 6.3 KB

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  1. /*
  2. * Copyright (C) 2013 Red Hat
  3. * Author: Rob Clark <robdclark@gmail.com>
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License version 2 as published by
  7. * the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program. If not, see <http://www.gnu.org/licenses/>.
  16. */
  17. #ifndef __MDP4_KMS_H__
  18. #define __MDP4_KMS_H__
  19. #include "msm_drv.h"
  20. #include "msm_kms.h"
  21. #include "mdp/mdp_kms.h"
  22. #include "mdp4.xml.h"
  23. struct mdp4_kms {
  24. struct mdp_kms base;
  25. struct drm_device *dev;
  26. int rev;
  27. /* mapper-id used to request GEM buffer mapped for scanout: */
  28. int id;
  29. void __iomem *mmio;
  30. struct regulator *dsi_pll_vdda;
  31. struct regulator *dsi_pll_vddio;
  32. struct regulator *vdd;
  33. struct clk *clk;
  34. struct clk *pclk;
  35. struct clk *lut_clk;
  36. struct clk *axi_clk;
  37. struct mdp_irq error_handler;
  38. /* empty/blank cursor bo to use when cursor is "disabled" */
  39. struct drm_gem_object *blank_cursor_bo;
  40. uint32_t blank_cursor_iova;
  41. };
  42. #define to_mdp4_kms(x) container_of(x, struct mdp4_kms, base)
  43. /* platform config data (ie. from DT, or pdata) */
  44. struct mdp4_platform_config {
  45. struct iommu_domain *iommu;
  46. uint32_t max_clk;
  47. };
  48. static inline void mdp4_write(struct mdp4_kms *mdp4_kms, u32 reg, u32 data)
  49. {
  50. msm_writel(data, mdp4_kms->mmio + reg);
  51. }
  52. static inline u32 mdp4_read(struct mdp4_kms *mdp4_kms, u32 reg)
  53. {
  54. return msm_readl(mdp4_kms->mmio + reg);
  55. }
  56. static inline uint32_t pipe2flush(enum mdp4_pipe pipe)
  57. {
  58. switch (pipe) {
  59. case VG1: return MDP4_OVERLAY_FLUSH_VG1;
  60. case VG2: return MDP4_OVERLAY_FLUSH_VG2;
  61. case RGB1: return MDP4_OVERLAY_FLUSH_RGB1;
  62. case RGB2: return MDP4_OVERLAY_FLUSH_RGB1;
  63. default: return 0;
  64. }
  65. }
  66. static inline uint32_t ovlp2flush(int ovlp)
  67. {
  68. switch (ovlp) {
  69. case 0: return MDP4_OVERLAY_FLUSH_OVLP0;
  70. case 1: return MDP4_OVERLAY_FLUSH_OVLP1;
  71. default: return 0;
  72. }
  73. }
  74. static inline uint32_t dma2irq(enum mdp4_dma dma)
  75. {
  76. switch (dma) {
  77. case DMA_P: return MDP4_IRQ_DMA_P_DONE;
  78. case DMA_S: return MDP4_IRQ_DMA_S_DONE;
  79. case DMA_E: return MDP4_IRQ_DMA_E_DONE;
  80. default: return 0;
  81. }
  82. }
  83. static inline uint32_t dma2err(enum mdp4_dma dma)
  84. {
  85. switch (dma) {
  86. case DMA_P: return MDP4_IRQ_PRIMARY_INTF_UDERRUN;
  87. case DMA_S: return 0; // ???
  88. case DMA_E: return MDP4_IRQ_EXTERNAL_INTF_UDERRUN;
  89. default: return 0;
  90. }
  91. }
  92. static inline uint32_t mixercfg(int mixer, enum mdp4_pipe pipe,
  93. enum mdp_mixer_stage_id stage)
  94. {
  95. uint32_t mixer_cfg = 0;
  96. switch (pipe) {
  97. case VG1:
  98. mixer_cfg = MDP4_LAYERMIXER_IN_CFG_PIPE0(stage) |
  99. COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE0_MIXER1);
  100. break;
  101. case VG2:
  102. mixer_cfg = MDP4_LAYERMIXER_IN_CFG_PIPE1(stage) |
  103. COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE1_MIXER1);
  104. break;
  105. case RGB1:
  106. mixer_cfg = MDP4_LAYERMIXER_IN_CFG_PIPE2(stage) |
  107. COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE2_MIXER1);
  108. break;
  109. case RGB2:
  110. mixer_cfg = MDP4_LAYERMIXER_IN_CFG_PIPE3(stage) |
  111. COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE3_MIXER1);
  112. break;
  113. case RGB3:
  114. mixer_cfg = MDP4_LAYERMIXER_IN_CFG_PIPE4(stage) |
  115. COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE4_MIXER1);
  116. break;
  117. case VG3:
  118. mixer_cfg = MDP4_LAYERMIXER_IN_CFG_PIPE5(stage) |
  119. COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE5_MIXER1);
  120. break;
  121. case VG4:
  122. mixer_cfg = MDP4_LAYERMIXER_IN_CFG_PIPE6(stage) |
  123. COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE6_MIXER1);
  124. break;
  125. default:
  126. WARN_ON("invalid pipe");
  127. break;
  128. }
  129. return mixer_cfg;
  130. }
  131. int mdp4_disable(struct mdp4_kms *mdp4_kms);
  132. int mdp4_enable(struct mdp4_kms *mdp4_kms);
  133. void mdp4_set_irqmask(struct mdp_kms *mdp_kms, uint32_t irqmask);
  134. void mdp4_irq_preinstall(struct msm_kms *kms);
  135. int mdp4_irq_postinstall(struct msm_kms *kms);
  136. void mdp4_irq_uninstall(struct msm_kms *kms);
  137. irqreturn_t mdp4_irq(struct msm_kms *kms);
  138. int mdp4_enable_vblank(struct msm_kms *kms, struct drm_crtc *crtc);
  139. void mdp4_disable_vblank(struct msm_kms *kms, struct drm_crtc *crtc);
  140. static inline
  141. uint32_t mdp4_get_formats(enum mdp4_pipe pipe_id, uint32_t *pixel_formats,
  142. uint32_t max_formats)
  143. {
  144. /* TODO when we have YUV, we need to filter supported formats
  145. * based on pipe_id..
  146. */
  147. return mdp_get_formats(pixel_formats, max_formats);
  148. }
  149. void mdp4_plane_install_properties(struct drm_plane *plane,
  150. struct drm_mode_object *obj);
  151. void mdp4_plane_set_scanout(struct drm_plane *plane,
  152. struct drm_framebuffer *fb);
  153. int mdp4_plane_mode_set(struct drm_plane *plane,
  154. struct drm_crtc *crtc, struct drm_framebuffer *fb,
  155. int crtc_x, int crtc_y,
  156. unsigned int crtc_w, unsigned int crtc_h,
  157. uint32_t src_x, uint32_t src_y,
  158. uint32_t src_w, uint32_t src_h);
  159. enum mdp4_pipe mdp4_plane_pipe(struct drm_plane *plane);
  160. struct drm_plane *mdp4_plane_init(struct drm_device *dev,
  161. enum mdp4_pipe pipe_id, bool private_plane);
  162. uint32_t mdp4_crtc_vblank(struct drm_crtc *crtc);
  163. void mdp4_crtc_cancel_pending_flip(struct drm_crtc *crtc, struct drm_file *file);
  164. void mdp4_crtc_set_config(struct drm_crtc *crtc, uint32_t config);
  165. void mdp4_crtc_set_intf(struct drm_crtc *crtc, enum mdp4_intf intf);
  166. void mdp4_crtc_attach(struct drm_crtc *crtc, struct drm_plane *plane);
  167. void mdp4_crtc_detach(struct drm_crtc *crtc, struct drm_plane *plane);
  168. struct drm_crtc *mdp4_crtc_init(struct drm_device *dev,
  169. struct drm_plane *plane, int id, int ovlp_id,
  170. enum mdp4_dma dma_id);
  171. long mdp4_dtv_round_pixclk(struct drm_encoder *encoder, unsigned long rate);
  172. struct drm_encoder *mdp4_dtv_encoder_init(struct drm_device *dev);
  173. #ifdef CONFIG_MSM_BUS_SCALING
  174. static inline int match_dev_name(struct device *dev, void *data)
  175. {
  176. return !strcmp(dev_name(dev), data);
  177. }
  178. /* bus scaling data is associated with extra pointless platform devices,
  179. * "dtv", etc.. this is a bit of a hack, but we need a way for encoders
  180. * to find their pdata to make the bus-scaling stuff work.
  181. */
  182. static inline void *mdp4_find_pdata(const char *devname)
  183. {
  184. struct device *dev;
  185. dev = bus_find_device(&platform_bus_type, NULL,
  186. (void *)devname, match_dev_name);
  187. return dev ? dev->platform_data : NULL;
  188. }
  189. #endif
  190. #endif /* __MDP4_KMS_H__ */