platsmp.c 3.4 KB

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  1. /*
  2. * This file contains Xilinx specific SMP code, used to start up
  3. * the second processor.
  4. *
  5. * Copyright (C) 2011-2013 Xilinx
  6. *
  7. * based on linux/arch/arm/mach-realview/platsmp.c
  8. *
  9. * Copyright (C) 2002 ARM Ltd.
  10. *
  11. * This software is licensed under the terms of the GNU General Public
  12. * License version 2, as published by the Free Software Foundation, and
  13. * may be copied, distributed, and modified under those terms.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. */
  20. #include <linux/export.h>
  21. #include <linux/jiffies.h>
  22. #include <linux/init.h>
  23. #include <linux/io.h>
  24. #include <asm/cacheflush.h>
  25. #include <asm/smp_scu.h>
  26. #include <linux/irqchip/arm-gic.h>
  27. #include "common.h"
  28. /*
  29. * Store number of cores in the system
  30. * Because of scu_get_core_count() must be in __init section and can't
  31. * be called from zynq_cpun_start() because it is not in __init section.
  32. */
  33. static int ncores;
  34. int zynq_cpun_start(u32 address, int cpu)
  35. {
  36. u32 trampoline_code_size = &zynq_secondary_trampoline_end -
  37. &zynq_secondary_trampoline;
  38. /* MS: Expectation that SLCR are directly map and accessible */
  39. /* Not possible to jump to non aligned address */
  40. if (!(address & 3) && (!address || (address >= trampoline_code_size))) {
  41. /* Store pointer to ioremap area which points to address 0x0 */
  42. static u8 __iomem *zero;
  43. u32 trampoline_size = &zynq_secondary_trampoline_jump -
  44. &zynq_secondary_trampoline;
  45. zynq_slcr_cpu_stop(cpu);
  46. if (address) {
  47. if (__pa(PAGE_OFFSET)) {
  48. zero = ioremap(0, trampoline_code_size);
  49. if (!zero) {
  50. pr_warn("BOOTUP jump vectors not accessible\n");
  51. return -1;
  52. }
  53. } else {
  54. zero = (__force u8 __iomem *)PAGE_OFFSET;
  55. }
  56. /*
  57. * This is elegant way how to jump to any address
  58. * 0x0: Load address at 0x8 to r0
  59. * 0x4: Jump by mov instruction
  60. * 0x8: Jumping address
  61. */
  62. memcpy((__force void *)zero, &zynq_secondary_trampoline,
  63. trampoline_size);
  64. writel(address, zero + trampoline_size);
  65. flush_cache_all();
  66. outer_flush_range(0, trampoline_code_size);
  67. smp_wmb();
  68. if (__pa(PAGE_OFFSET))
  69. iounmap(zero);
  70. }
  71. zynq_slcr_cpu_start(cpu);
  72. return 0;
  73. }
  74. pr_warn("Can't start CPU%d: Wrong starting address %x\n", cpu, address);
  75. return -1;
  76. }
  77. EXPORT_SYMBOL(zynq_cpun_start);
  78. static int zynq_boot_secondary(unsigned int cpu,
  79. struct task_struct *idle)
  80. {
  81. return zynq_cpun_start(virt_to_phys(zynq_secondary_startup), cpu);
  82. }
  83. /*
  84. * Initialise the CPU possible map early - this describes the CPUs
  85. * which may be present or become present in the system.
  86. */
  87. static void __init zynq_smp_init_cpus(void)
  88. {
  89. int i;
  90. ncores = scu_get_core_count(zynq_scu_base);
  91. for (i = 0; i < ncores && i < CONFIG_NR_CPUS; i++)
  92. set_cpu_possible(i, true);
  93. }
  94. static void __init zynq_smp_prepare_cpus(unsigned int max_cpus)
  95. {
  96. scu_enable(zynq_scu_base);
  97. }
  98. #ifdef CONFIG_HOTPLUG_CPU
  99. static int zynq_cpu_kill(unsigned cpu)
  100. {
  101. zynq_slcr_cpu_stop(cpu);
  102. return 1;
  103. }
  104. #endif
  105. struct smp_operations zynq_smp_ops __initdata = {
  106. .smp_init_cpus = zynq_smp_init_cpus,
  107. .smp_prepare_cpus = zynq_smp_prepare_cpus,
  108. .smp_boot_secondary = zynq_boot_secondary,
  109. #ifdef CONFIG_HOTPLUG_CPU
  110. .cpu_die = zynq_platform_cpu_die,
  111. .cpu_kill = zynq_cpu_kill,
  112. #endif
  113. };