r8152.c 91 KB

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  1. /*
  2. * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
  3. *
  4. * This program is free software; you can redistribute it and/or
  5. * modify it under the terms of the GNU General Public License
  6. * version 2 as published by the Free Software Foundation.
  7. *
  8. */
  9. #include <linux/signal.h>
  10. #include <linux/slab.h>
  11. #include <linux/module.h>
  12. #include <linux/netdevice.h>
  13. #include <linux/etherdevice.h>
  14. #include <linux/mii.h>
  15. #include <linux/ethtool.h>
  16. #include <linux/usb.h>
  17. #include <linux/crc32.h>
  18. #include <linux/if_vlan.h>
  19. #include <linux/uaccess.h>
  20. #include <linux/list.h>
  21. #include <linux/ip.h>
  22. #include <linux/ipv6.h>
  23. #include <net/ip6_checksum.h>
  24. #include <uapi/linux/mdio.h>
  25. #include <linux/mdio.h>
  26. #include <linux/usb/cdc.h>
  27. /* Version Information */
  28. #define DRIVER_VERSION "v1.08.0 (2015/01/13)"
  29. #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
  30. #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
  31. #define MODULENAME "r8152"
  32. #define R8152_PHY_ID 32
  33. #define PLA_IDR 0xc000
  34. #define PLA_RCR 0xc010
  35. #define PLA_RMS 0xc016
  36. #define PLA_RXFIFO_CTRL0 0xc0a0
  37. #define PLA_RXFIFO_CTRL1 0xc0a4
  38. #define PLA_RXFIFO_CTRL2 0xc0a8
  39. #define PLA_FMC 0xc0b4
  40. #define PLA_CFG_WOL 0xc0b6
  41. #define PLA_TEREDO_CFG 0xc0bc
  42. #define PLA_MAR 0xcd00
  43. #define PLA_BACKUP 0xd000
  44. #define PAL_BDC_CR 0xd1a0
  45. #define PLA_TEREDO_TIMER 0xd2cc
  46. #define PLA_REALWOW_TIMER 0xd2e8
  47. #define PLA_LEDSEL 0xdd90
  48. #define PLA_LED_FEATURE 0xdd92
  49. #define PLA_PHYAR 0xde00
  50. #define PLA_BOOT_CTRL 0xe004
  51. #define PLA_GPHY_INTR_IMR 0xe022
  52. #define PLA_EEE_CR 0xe040
  53. #define PLA_EEEP_CR 0xe080
  54. #define PLA_MAC_PWR_CTRL 0xe0c0
  55. #define PLA_MAC_PWR_CTRL2 0xe0ca
  56. #define PLA_MAC_PWR_CTRL3 0xe0cc
  57. #define PLA_MAC_PWR_CTRL4 0xe0ce
  58. #define PLA_WDT6_CTRL 0xe428
  59. #define PLA_TCR0 0xe610
  60. #define PLA_TCR1 0xe612
  61. #define PLA_MTPS 0xe615
  62. #define PLA_TXFIFO_CTRL 0xe618
  63. #define PLA_RSTTALLY 0xe800
  64. #define PLA_CR 0xe813
  65. #define PLA_CRWECR 0xe81c
  66. #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */
  67. #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */
  68. #define PLA_CONFIG5 0xe822
  69. #define PLA_PHY_PWR 0xe84c
  70. #define PLA_OOB_CTRL 0xe84f
  71. #define PLA_CPCR 0xe854
  72. #define PLA_MISC_0 0xe858
  73. #define PLA_MISC_1 0xe85a
  74. #define PLA_OCP_GPHY_BASE 0xe86c
  75. #define PLA_TALLYCNT 0xe890
  76. #define PLA_SFF_STS_7 0xe8de
  77. #define PLA_PHYSTATUS 0xe908
  78. #define PLA_BP_BA 0xfc26
  79. #define PLA_BP_0 0xfc28
  80. #define PLA_BP_1 0xfc2a
  81. #define PLA_BP_2 0xfc2c
  82. #define PLA_BP_3 0xfc2e
  83. #define PLA_BP_4 0xfc30
  84. #define PLA_BP_5 0xfc32
  85. #define PLA_BP_6 0xfc34
  86. #define PLA_BP_7 0xfc36
  87. #define PLA_BP_EN 0xfc38
  88. #define USB_U2P3_CTRL 0xb460
  89. #define USB_DEV_STAT 0xb808
  90. #define USB_USB_CTRL 0xd406
  91. #define USB_PHY_CTRL 0xd408
  92. #define USB_TX_AGG 0xd40a
  93. #define USB_RX_BUF_TH 0xd40c
  94. #define USB_USB_TIMER 0xd428
  95. #define USB_RX_EARLY_AGG 0xd42c
  96. #define USB_PM_CTRL_STATUS 0xd432
  97. #define USB_TX_DMA 0xd434
  98. #define USB_TOLERANCE 0xd490
  99. #define USB_LPM_CTRL 0xd41a
  100. #define USB_UPS_CTRL 0xd800
  101. #define USB_MISC_0 0xd81a
  102. #define USB_POWER_CUT 0xd80a
  103. #define USB_AFE_CTRL2 0xd824
  104. #define USB_WDT11_CTRL 0xe43c
  105. #define USB_BP_BA 0xfc26
  106. #define USB_BP_0 0xfc28
  107. #define USB_BP_1 0xfc2a
  108. #define USB_BP_2 0xfc2c
  109. #define USB_BP_3 0xfc2e
  110. #define USB_BP_4 0xfc30
  111. #define USB_BP_5 0xfc32
  112. #define USB_BP_6 0xfc34
  113. #define USB_BP_7 0xfc36
  114. #define USB_BP_EN 0xfc38
  115. /* OCP Registers */
  116. #define OCP_ALDPS_CONFIG 0x2010
  117. #define OCP_EEE_CONFIG1 0x2080
  118. #define OCP_EEE_CONFIG2 0x2092
  119. #define OCP_EEE_CONFIG3 0x2094
  120. #define OCP_BASE_MII 0xa400
  121. #define OCP_EEE_AR 0xa41a
  122. #define OCP_EEE_DATA 0xa41c
  123. #define OCP_PHY_STATUS 0xa420
  124. #define OCP_POWER_CFG 0xa430
  125. #define OCP_EEE_CFG 0xa432
  126. #define OCP_SRAM_ADDR 0xa436
  127. #define OCP_SRAM_DATA 0xa438
  128. #define OCP_DOWN_SPEED 0xa442
  129. #define OCP_EEE_ABLE 0xa5c4
  130. #define OCP_EEE_ADV 0xa5d0
  131. #define OCP_EEE_LPABLE 0xa5d2
  132. #define OCP_ADC_CFG 0xbc06
  133. /* SRAM Register */
  134. #define SRAM_LPF_CFG 0x8012
  135. #define SRAM_10M_AMP1 0x8080
  136. #define SRAM_10M_AMP2 0x8082
  137. #define SRAM_IMPEDANCE 0x8084
  138. /* PLA_RCR */
  139. #define RCR_AAP 0x00000001
  140. #define RCR_APM 0x00000002
  141. #define RCR_AM 0x00000004
  142. #define RCR_AB 0x00000008
  143. #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
  144. /* PLA_RXFIFO_CTRL0 */
  145. #define RXFIFO_THR1_NORMAL 0x00080002
  146. #define RXFIFO_THR1_OOB 0x01800003
  147. /* PLA_RXFIFO_CTRL1 */
  148. #define RXFIFO_THR2_FULL 0x00000060
  149. #define RXFIFO_THR2_HIGH 0x00000038
  150. #define RXFIFO_THR2_OOB 0x0000004a
  151. #define RXFIFO_THR2_NORMAL 0x00a0
  152. /* PLA_RXFIFO_CTRL2 */
  153. #define RXFIFO_THR3_FULL 0x00000078
  154. #define RXFIFO_THR3_HIGH 0x00000048
  155. #define RXFIFO_THR3_OOB 0x0000005a
  156. #define RXFIFO_THR3_NORMAL 0x0110
  157. /* PLA_TXFIFO_CTRL */
  158. #define TXFIFO_THR_NORMAL 0x00400008
  159. #define TXFIFO_THR_NORMAL2 0x01000008
  160. /* PLA_FMC */
  161. #define FMC_FCR_MCU_EN 0x0001
  162. /* PLA_EEEP_CR */
  163. #define EEEP_CR_EEEP_TX 0x0002
  164. /* PLA_WDT6_CTRL */
  165. #define WDT6_SET_MODE 0x0010
  166. /* PLA_TCR0 */
  167. #define TCR0_TX_EMPTY 0x0800
  168. #define TCR0_AUTO_FIFO 0x0080
  169. /* PLA_TCR1 */
  170. #define VERSION_MASK 0x7cf0
  171. /* PLA_MTPS */
  172. #define MTPS_JUMBO (12 * 1024 / 64)
  173. #define MTPS_DEFAULT (6 * 1024 / 64)
  174. /* PLA_RSTTALLY */
  175. #define TALLY_RESET 0x0001
  176. /* PLA_CR */
  177. #define CR_RST 0x10
  178. #define CR_RE 0x08
  179. #define CR_TE 0x04
  180. /* PLA_CRWECR */
  181. #define CRWECR_NORAML 0x00
  182. #define CRWECR_CONFIG 0xc0
  183. /* PLA_OOB_CTRL */
  184. #define NOW_IS_OOB 0x80
  185. #define TXFIFO_EMPTY 0x20
  186. #define RXFIFO_EMPTY 0x10
  187. #define LINK_LIST_READY 0x02
  188. #define DIS_MCU_CLROOB 0x01
  189. #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY)
  190. /* PLA_MISC_1 */
  191. #define RXDY_GATED_EN 0x0008
  192. /* PLA_SFF_STS_7 */
  193. #define RE_INIT_LL 0x8000
  194. #define MCU_BORW_EN 0x4000
  195. /* PLA_CPCR */
  196. #define CPCR_RX_VLAN 0x0040
  197. /* PLA_CFG_WOL */
  198. #define MAGIC_EN 0x0001
  199. /* PLA_TEREDO_CFG */
  200. #define TEREDO_SEL 0x8000
  201. #define TEREDO_WAKE_MASK 0x7f00
  202. #define TEREDO_RS_EVENT_MASK 0x00fe
  203. #define OOB_TEREDO_EN 0x0001
  204. /* PAL_BDC_CR */
  205. #define ALDPS_PROXY_MODE 0x0001
  206. /* PLA_CONFIG34 */
  207. #define LINK_ON_WAKE_EN 0x0010
  208. #define LINK_OFF_WAKE_EN 0x0008
  209. /* PLA_CONFIG5 */
  210. #define BWF_EN 0x0040
  211. #define MWF_EN 0x0020
  212. #define UWF_EN 0x0010
  213. #define LAN_WAKE_EN 0x0002
  214. /* PLA_LED_FEATURE */
  215. #define LED_MODE_MASK 0x0700
  216. /* PLA_PHY_PWR */
  217. #define TX_10M_IDLE_EN 0x0080
  218. #define PFM_PWM_SWITCH 0x0040
  219. /* PLA_MAC_PWR_CTRL */
  220. #define D3_CLK_GATED_EN 0x00004000
  221. #define MCU_CLK_RATIO 0x07010f07
  222. #define MCU_CLK_RATIO_MASK 0x0f0f0f0f
  223. #define ALDPS_SPDWN_RATIO 0x0f87
  224. /* PLA_MAC_PWR_CTRL2 */
  225. #define EEE_SPDWN_RATIO 0x8007
  226. /* PLA_MAC_PWR_CTRL3 */
  227. #define PKT_AVAIL_SPDWN_EN 0x0100
  228. #define SUSPEND_SPDWN_EN 0x0004
  229. #define U1U2_SPDWN_EN 0x0002
  230. #define L1_SPDWN_EN 0x0001
  231. /* PLA_MAC_PWR_CTRL4 */
  232. #define PWRSAVE_SPDWN_EN 0x1000
  233. #define RXDV_SPDWN_EN 0x0800
  234. #define TX10MIDLE_EN 0x0100
  235. #define TP100_SPDWN_EN 0x0020
  236. #define TP500_SPDWN_EN 0x0010
  237. #define TP1000_SPDWN_EN 0x0008
  238. #define EEE_SPDWN_EN 0x0001
  239. /* PLA_GPHY_INTR_IMR */
  240. #define GPHY_STS_MSK 0x0001
  241. #define SPEED_DOWN_MSK 0x0002
  242. #define SPDWN_RXDV_MSK 0x0004
  243. #define SPDWN_LINKCHG_MSK 0x0008
  244. /* PLA_PHYAR */
  245. #define PHYAR_FLAG 0x80000000
  246. /* PLA_EEE_CR */
  247. #define EEE_RX_EN 0x0001
  248. #define EEE_TX_EN 0x0002
  249. /* PLA_BOOT_CTRL */
  250. #define AUTOLOAD_DONE 0x0002
  251. /* USB_DEV_STAT */
  252. #define STAT_SPEED_MASK 0x0006
  253. #define STAT_SPEED_HIGH 0x0000
  254. #define STAT_SPEED_FULL 0x0002
  255. /* USB_TX_AGG */
  256. #define TX_AGG_MAX_THRESHOLD 0x03
  257. /* USB_RX_BUF_TH */
  258. #define RX_THR_SUPPER 0x0c350180
  259. #define RX_THR_HIGH 0x7a120180
  260. #define RX_THR_SLOW 0xffff0180
  261. /* USB_TX_DMA */
  262. #define TEST_MODE_DISABLE 0x00000001
  263. #define TX_SIZE_ADJUST1 0x00000100
  264. /* USB_UPS_CTRL */
  265. #define POWER_CUT 0x0100
  266. /* USB_PM_CTRL_STATUS */
  267. #define RESUME_INDICATE 0x0001
  268. /* USB_USB_CTRL */
  269. #define RX_AGG_DISABLE 0x0010
  270. /* USB_U2P3_CTRL */
  271. #define U2P3_ENABLE 0x0001
  272. /* USB_POWER_CUT */
  273. #define PWR_EN 0x0001
  274. #define PHASE2_EN 0x0008
  275. /* USB_MISC_0 */
  276. #define PCUT_STATUS 0x0001
  277. /* USB_RX_EARLY_AGG */
  278. #define EARLY_AGG_SUPPER 0x0e832981
  279. #define EARLY_AGG_HIGH 0x0e837a12
  280. #define EARLY_AGG_SLOW 0x0e83ffff
  281. /* USB_WDT11_CTRL */
  282. #define TIMER11_EN 0x0001
  283. /* USB_LPM_CTRL */
  284. #define LPM_TIMER_MASK 0x0c
  285. #define LPM_TIMER_500MS 0x04 /* 500 ms */
  286. #define LPM_TIMER_500US 0x0c /* 500 us */
  287. /* USB_AFE_CTRL2 */
  288. #define SEN_VAL_MASK 0xf800
  289. #define SEN_VAL_NORMAL 0xa000
  290. #define SEL_RXIDLE 0x0100
  291. /* OCP_ALDPS_CONFIG */
  292. #define ENPWRSAVE 0x8000
  293. #define ENPDNPS 0x0200
  294. #define LINKENA 0x0100
  295. #define DIS_SDSAVE 0x0010
  296. /* OCP_PHY_STATUS */
  297. #define PHY_STAT_MASK 0x0007
  298. #define PHY_STAT_LAN_ON 3
  299. #define PHY_STAT_PWRDN 5
  300. /* OCP_POWER_CFG */
  301. #define EEE_CLKDIV_EN 0x8000
  302. #define EN_ALDPS 0x0004
  303. #define EN_10M_PLLOFF 0x0001
  304. /* OCP_EEE_CONFIG1 */
  305. #define RG_TXLPI_MSK_HFDUP 0x8000
  306. #define RG_MATCLR_EN 0x4000
  307. #define EEE_10_CAP 0x2000
  308. #define EEE_NWAY_EN 0x1000
  309. #define TX_QUIET_EN 0x0200
  310. #define RX_QUIET_EN 0x0100
  311. #define sd_rise_time_mask 0x0070
  312. #define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */
  313. #define RG_RXLPI_MSK_HFDUP 0x0008
  314. #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
  315. /* OCP_EEE_CONFIG2 */
  316. #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
  317. #define RG_DACQUIET_EN 0x0400
  318. #define RG_LDVQUIET_EN 0x0200
  319. #define RG_CKRSEL 0x0020
  320. #define RG_EEEPRG_EN 0x0010
  321. /* OCP_EEE_CONFIG3 */
  322. #define fast_snr_mask 0xff80
  323. #define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */
  324. #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
  325. #define MSK_PH 0x0006 /* bit 0 ~ 3 */
  326. /* OCP_EEE_AR */
  327. /* bit[15:14] function */
  328. #define FUN_ADDR 0x0000
  329. #define FUN_DATA 0x4000
  330. /* bit[4:0] device addr */
  331. /* OCP_EEE_CFG */
  332. #define CTAP_SHORT_EN 0x0040
  333. #define EEE10_EN 0x0010
  334. /* OCP_DOWN_SPEED */
  335. #define EN_10M_BGOFF 0x0080
  336. /* OCP_ADC_CFG */
  337. #define CKADSEL_L 0x0100
  338. #define ADC_EN 0x0080
  339. #define EN_EMI_L 0x0040
  340. /* SRAM_LPF_CFG */
  341. #define LPF_AUTO_TUNE 0x8000
  342. /* SRAM_10M_AMP1 */
  343. #define GDAC_IB_UPALL 0x0008
  344. /* SRAM_10M_AMP2 */
  345. #define AMP_DN 0x0200
  346. /* SRAM_IMPEDANCE */
  347. #define RX_DRIVING_MASK 0x6000
  348. enum rtl_register_content {
  349. _1000bps = 0x10,
  350. _100bps = 0x08,
  351. _10bps = 0x04,
  352. LINK_STATUS = 0x02,
  353. FULL_DUP = 0x01,
  354. };
  355. #define RTL8152_MAX_TX 4
  356. #define RTL8152_MAX_RX 10
  357. #define INTBUFSIZE 2
  358. #define CRC_SIZE 4
  359. #define TX_ALIGN 4
  360. #define RX_ALIGN 8
  361. #define INTR_LINK 0x0004
  362. #define RTL8152_REQT_READ 0xc0
  363. #define RTL8152_REQT_WRITE 0x40
  364. #define RTL8152_REQ_GET_REGS 0x05
  365. #define RTL8152_REQ_SET_REGS 0x05
  366. #define BYTE_EN_DWORD 0xff
  367. #define BYTE_EN_WORD 0x33
  368. #define BYTE_EN_BYTE 0x11
  369. #define BYTE_EN_SIX_BYTES 0x3f
  370. #define BYTE_EN_START_MASK 0x0f
  371. #define BYTE_EN_END_MASK 0xf0
  372. #define RTL8153_MAX_PACKET 9216 /* 9K */
  373. #define RTL8153_MAX_MTU (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - VLAN_HLEN)
  374. #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + VLAN_HLEN)
  375. #define RTL8153_RMS RTL8153_MAX_PACKET
  376. #define RTL8152_TX_TIMEOUT (5 * HZ)
  377. #define RTL8152_NAPI_WEIGHT 64
  378. /* rtl8152 flags */
  379. enum rtl8152_flags {
  380. RTL8152_UNPLUG = 0,
  381. RTL8152_SET_RX_MODE,
  382. WORK_ENABLE,
  383. RTL8152_LINK_CHG,
  384. SELECTIVE_SUSPEND,
  385. PHY_RESET,
  386. SCHEDULE_NAPI,
  387. };
  388. /* Define these values to match your device */
  389. #define VENDOR_ID_REALTEK 0x0bda
  390. #define VENDOR_ID_SAMSUNG 0x04e8
  391. #define MCU_TYPE_PLA 0x0100
  392. #define MCU_TYPE_USB 0x0000
  393. struct tally_counter {
  394. __le64 tx_packets;
  395. __le64 rx_packets;
  396. __le64 tx_errors;
  397. __le32 rx_errors;
  398. __le16 rx_missed;
  399. __le16 align_errors;
  400. __le32 tx_one_collision;
  401. __le32 tx_multi_collision;
  402. __le64 rx_unicast;
  403. __le64 rx_broadcast;
  404. __le32 rx_multicast;
  405. __le16 tx_aborted;
  406. __le16 tx_underrun;
  407. };
  408. struct rx_desc {
  409. __le32 opts1;
  410. #define RX_LEN_MASK 0x7fff
  411. __le32 opts2;
  412. #define RD_UDP_CS BIT(23)
  413. #define RD_TCP_CS BIT(22)
  414. #define RD_IPV6_CS BIT(20)
  415. #define RD_IPV4_CS BIT(19)
  416. __le32 opts3;
  417. #define IPF BIT(23) /* IP checksum fail */
  418. #define UDPF BIT(22) /* UDP checksum fail */
  419. #define TCPF BIT(21) /* TCP checksum fail */
  420. #define RX_VLAN_TAG BIT(16)
  421. __le32 opts4;
  422. __le32 opts5;
  423. __le32 opts6;
  424. };
  425. struct tx_desc {
  426. __le32 opts1;
  427. #define TX_FS BIT(31) /* First segment of a packet */
  428. #define TX_LS BIT(30) /* Final segment of a packet */
  429. #define GTSENDV4 BIT(28)
  430. #define GTSENDV6 BIT(27)
  431. #define GTTCPHO_SHIFT 18
  432. #define GTTCPHO_MAX 0x7fU
  433. #define TX_LEN_MAX 0x3ffffU
  434. __le32 opts2;
  435. #define UDP_CS BIT(31) /* Calculate UDP/IP checksum */
  436. #define TCP_CS BIT(30) /* Calculate TCP/IP checksum */
  437. #define IPV4_CS BIT(29) /* Calculate IPv4 checksum */
  438. #define IPV6_CS BIT(28) /* Calculate IPv6 checksum */
  439. #define MSS_SHIFT 17
  440. #define MSS_MAX 0x7ffU
  441. #define TCPHO_SHIFT 17
  442. #define TCPHO_MAX 0x7ffU
  443. #define TX_VLAN_TAG BIT(16)
  444. };
  445. struct r8152;
  446. struct rx_agg {
  447. struct list_head list;
  448. struct urb *urb;
  449. struct r8152 *context;
  450. void *buffer;
  451. void *head;
  452. };
  453. struct tx_agg {
  454. struct list_head list;
  455. struct urb *urb;
  456. struct r8152 *context;
  457. void *buffer;
  458. void *head;
  459. u32 skb_num;
  460. u32 skb_len;
  461. };
  462. struct r8152 {
  463. unsigned long flags;
  464. struct usb_device *udev;
  465. struct napi_struct napi;
  466. struct usb_interface *intf;
  467. struct net_device *netdev;
  468. struct urb *intr_urb;
  469. struct tx_agg tx_info[RTL8152_MAX_TX];
  470. struct rx_agg rx_info[RTL8152_MAX_RX];
  471. struct list_head rx_done, tx_free;
  472. struct sk_buff_head tx_queue, rx_queue;
  473. spinlock_t rx_lock, tx_lock;
  474. struct delayed_work schedule;
  475. struct mii_if_info mii;
  476. struct mutex control; /* use for hw setting */
  477. struct rtl_ops {
  478. void (*init)(struct r8152 *);
  479. int (*enable)(struct r8152 *);
  480. void (*disable)(struct r8152 *);
  481. void (*up)(struct r8152 *);
  482. void (*down)(struct r8152 *);
  483. void (*unload)(struct r8152 *);
  484. int (*eee_get)(struct r8152 *, struct ethtool_eee *);
  485. int (*eee_set)(struct r8152 *, struct ethtool_eee *);
  486. } rtl_ops;
  487. int intr_interval;
  488. u32 saved_wolopts;
  489. u32 msg_enable;
  490. u32 tx_qlen;
  491. u16 ocp_base;
  492. u8 *intr_buff;
  493. u8 version;
  494. };
  495. enum rtl_version {
  496. RTL_VER_UNKNOWN = 0,
  497. RTL_VER_01,
  498. RTL_VER_02,
  499. RTL_VER_03,
  500. RTL_VER_04,
  501. RTL_VER_05,
  502. RTL_VER_MAX
  503. };
  504. enum tx_csum_stat {
  505. TX_CSUM_SUCCESS = 0,
  506. TX_CSUM_TSO,
  507. TX_CSUM_NONE
  508. };
  509. /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  510. * The RTL chips use a 64 element hash table based on the Ethernet CRC.
  511. */
  512. static const int multicast_filter_limit = 32;
  513. static unsigned int agg_buf_sz = 16384;
  514. #define RTL_LIMITED_TSO_SIZE (agg_buf_sz - sizeof(struct tx_desc) - \
  515. VLAN_ETH_HLEN - VLAN_HLEN)
  516. static
  517. int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
  518. {
  519. int ret;
  520. void *tmp;
  521. tmp = kmalloc(size, GFP_KERNEL);
  522. if (!tmp)
  523. return -ENOMEM;
  524. ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
  525. RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
  526. value, index, tmp, size, 500);
  527. memcpy(data, tmp, size);
  528. kfree(tmp);
  529. return ret;
  530. }
  531. static
  532. int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
  533. {
  534. int ret;
  535. void *tmp;
  536. tmp = kmemdup(data, size, GFP_KERNEL);
  537. if (!tmp)
  538. return -ENOMEM;
  539. ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
  540. RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
  541. value, index, tmp, size, 500);
  542. kfree(tmp);
  543. return ret;
  544. }
  545. static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
  546. void *data, u16 type)
  547. {
  548. u16 limit = 64;
  549. int ret = 0;
  550. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  551. return -ENODEV;
  552. /* both size and indix must be 4 bytes align */
  553. if ((size & 3) || !size || (index & 3) || !data)
  554. return -EPERM;
  555. if ((u32)index + (u32)size > 0xffff)
  556. return -EPERM;
  557. while (size) {
  558. if (size > limit) {
  559. ret = get_registers(tp, index, type, limit, data);
  560. if (ret < 0)
  561. break;
  562. index += limit;
  563. data += limit;
  564. size -= limit;
  565. } else {
  566. ret = get_registers(tp, index, type, size, data);
  567. if (ret < 0)
  568. break;
  569. index += size;
  570. data += size;
  571. size = 0;
  572. break;
  573. }
  574. }
  575. if (ret == -ENODEV)
  576. set_bit(RTL8152_UNPLUG, &tp->flags);
  577. return ret;
  578. }
  579. static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
  580. u16 size, void *data, u16 type)
  581. {
  582. int ret;
  583. u16 byteen_start, byteen_end, byen;
  584. u16 limit = 512;
  585. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  586. return -ENODEV;
  587. /* both size and indix must be 4 bytes align */
  588. if ((size & 3) || !size || (index & 3) || !data)
  589. return -EPERM;
  590. if ((u32)index + (u32)size > 0xffff)
  591. return -EPERM;
  592. byteen_start = byteen & BYTE_EN_START_MASK;
  593. byteen_end = byteen & BYTE_EN_END_MASK;
  594. byen = byteen_start | (byteen_start << 4);
  595. ret = set_registers(tp, index, type | byen, 4, data);
  596. if (ret < 0)
  597. goto error1;
  598. index += 4;
  599. data += 4;
  600. size -= 4;
  601. if (size) {
  602. size -= 4;
  603. while (size) {
  604. if (size > limit) {
  605. ret = set_registers(tp, index,
  606. type | BYTE_EN_DWORD,
  607. limit, data);
  608. if (ret < 0)
  609. goto error1;
  610. index += limit;
  611. data += limit;
  612. size -= limit;
  613. } else {
  614. ret = set_registers(tp, index,
  615. type | BYTE_EN_DWORD,
  616. size, data);
  617. if (ret < 0)
  618. goto error1;
  619. index += size;
  620. data += size;
  621. size = 0;
  622. break;
  623. }
  624. }
  625. byen = byteen_end | (byteen_end >> 4);
  626. ret = set_registers(tp, index, type | byen, 4, data);
  627. if (ret < 0)
  628. goto error1;
  629. }
  630. error1:
  631. if (ret == -ENODEV)
  632. set_bit(RTL8152_UNPLUG, &tp->flags);
  633. return ret;
  634. }
  635. static inline
  636. int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
  637. {
  638. return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
  639. }
  640. static inline
  641. int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
  642. {
  643. return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
  644. }
  645. static inline
  646. int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
  647. {
  648. return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB);
  649. }
  650. static inline
  651. int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
  652. {
  653. return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
  654. }
  655. static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
  656. {
  657. __le32 data;
  658. generic_ocp_read(tp, index, sizeof(data), &data, type);
  659. return __le32_to_cpu(data);
  660. }
  661. static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
  662. {
  663. __le32 tmp = __cpu_to_le32(data);
  664. generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
  665. }
  666. static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
  667. {
  668. u32 data;
  669. __le32 tmp;
  670. u8 shift = index & 2;
  671. index &= ~3;
  672. generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
  673. data = __le32_to_cpu(tmp);
  674. data >>= (shift * 8);
  675. data &= 0xffff;
  676. return (u16)data;
  677. }
  678. static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
  679. {
  680. u32 mask = 0xffff;
  681. __le32 tmp;
  682. u16 byen = BYTE_EN_WORD;
  683. u8 shift = index & 2;
  684. data &= mask;
  685. if (index & 2) {
  686. byen <<= shift;
  687. mask <<= (shift * 8);
  688. data <<= (shift * 8);
  689. index &= ~3;
  690. }
  691. tmp = __cpu_to_le32(data);
  692. generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
  693. }
  694. static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
  695. {
  696. u32 data;
  697. __le32 tmp;
  698. u8 shift = index & 3;
  699. index &= ~3;
  700. generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
  701. data = __le32_to_cpu(tmp);
  702. data >>= (shift * 8);
  703. data &= 0xff;
  704. return (u8)data;
  705. }
  706. static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
  707. {
  708. u32 mask = 0xff;
  709. __le32 tmp;
  710. u16 byen = BYTE_EN_BYTE;
  711. u8 shift = index & 3;
  712. data &= mask;
  713. if (index & 3) {
  714. byen <<= shift;
  715. mask <<= (shift * 8);
  716. data <<= (shift * 8);
  717. index &= ~3;
  718. }
  719. tmp = __cpu_to_le32(data);
  720. generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
  721. }
  722. static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
  723. {
  724. u16 ocp_base, ocp_index;
  725. ocp_base = addr & 0xf000;
  726. if (ocp_base != tp->ocp_base) {
  727. ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
  728. tp->ocp_base = ocp_base;
  729. }
  730. ocp_index = (addr & 0x0fff) | 0xb000;
  731. return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
  732. }
  733. static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
  734. {
  735. u16 ocp_base, ocp_index;
  736. ocp_base = addr & 0xf000;
  737. if (ocp_base != tp->ocp_base) {
  738. ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
  739. tp->ocp_base = ocp_base;
  740. }
  741. ocp_index = (addr & 0x0fff) | 0xb000;
  742. ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
  743. }
  744. static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
  745. {
  746. ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
  747. }
  748. static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
  749. {
  750. return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
  751. }
  752. static void sram_write(struct r8152 *tp, u16 addr, u16 data)
  753. {
  754. ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
  755. ocp_reg_write(tp, OCP_SRAM_DATA, data);
  756. }
  757. static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
  758. {
  759. struct r8152 *tp = netdev_priv(netdev);
  760. int ret;
  761. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  762. return -ENODEV;
  763. if (phy_id != R8152_PHY_ID)
  764. return -EINVAL;
  765. ret = r8152_mdio_read(tp, reg);
  766. return ret;
  767. }
  768. static
  769. void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
  770. {
  771. struct r8152 *tp = netdev_priv(netdev);
  772. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  773. return;
  774. if (phy_id != R8152_PHY_ID)
  775. return;
  776. r8152_mdio_write(tp, reg, val);
  777. }
  778. static int
  779. r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
  780. static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
  781. {
  782. struct r8152 *tp = netdev_priv(netdev);
  783. struct sockaddr *addr = p;
  784. int ret = -EADDRNOTAVAIL;
  785. if (!is_valid_ether_addr(addr->sa_data))
  786. goto out1;
  787. ret = usb_autopm_get_interface(tp->intf);
  788. if (ret < 0)
  789. goto out1;
  790. mutex_lock(&tp->control);
  791. memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
  792. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
  793. pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
  794. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
  795. mutex_unlock(&tp->control);
  796. usb_autopm_put_interface(tp->intf);
  797. out1:
  798. return ret;
  799. }
  800. static int set_ethernet_addr(struct r8152 *tp)
  801. {
  802. struct net_device *dev = tp->netdev;
  803. struct sockaddr sa;
  804. int ret;
  805. if (tp->version == RTL_VER_01)
  806. ret = pla_ocp_read(tp, PLA_IDR, 8, sa.sa_data);
  807. else
  808. ret = pla_ocp_read(tp, PLA_BACKUP, 8, sa.sa_data);
  809. if (ret < 0) {
  810. netif_err(tp, probe, dev, "Get ether addr fail\n");
  811. } else if (!is_valid_ether_addr(sa.sa_data)) {
  812. netif_err(tp, probe, dev, "Invalid ether addr %pM\n",
  813. sa.sa_data);
  814. eth_hw_addr_random(dev);
  815. ether_addr_copy(sa.sa_data, dev->dev_addr);
  816. ret = rtl8152_set_mac_address(dev, &sa);
  817. netif_info(tp, probe, dev, "Random ether addr %pM\n",
  818. sa.sa_data);
  819. } else {
  820. if (tp->version == RTL_VER_01)
  821. ether_addr_copy(dev->dev_addr, sa.sa_data);
  822. else
  823. ret = rtl8152_set_mac_address(dev, &sa);
  824. }
  825. return ret;
  826. }
  827. static void read_bulk_callback(struct urb *urb)
  828. {
  829. struct net_device *netdev;
  830. int status = urb->status;
  831. struct rx_agg *agg;
  832. struct r8152 *tp;
  833. agg = urb->context;
  834. if (!agg)
  835. return;
  836. tp = agg->context;
  837. if (!tp)
  838. return;
  839. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  840. return;
  841. if (!test_bit(WORK_ENABLE, &tp->flags))
  842. return;
  843. netdev = tp->netdev;
  844. /* When link down, the driver would cancel all bulks. */
  845. /* This avoid the re-submitting bulk */
  846. if (!netif_carrier_ok(netdev))
  847. return;
  848. usb_mark_last_busy(tp->udev);
  849. switch (status) {
  850. case 0:
  851. if (urb->actual_length < ETH_ZLEN)
  852. break;
  853. spin_lock(&tp->rx_lock);
  854. list_add_tail(&agg->list, &tp->rx_done);
  855. spin_unlock(&tp->rx_lock);
  856. napi_schedule(&tp->napi);
  857. return;
  858. case -ESHUTDOWN:
  859. set_bit(RTL8152_UNPLUG, &tp->flags);
  860. netif_device_detach(tp->netdev);
  861. return;
  862. case -ENOENT:
  863. return; /* the urb is in unlink state */
  864. case -ETIME:
  865. if (net_ratelimit())
  866. netdev_warn(netdev, "maybe reset is needed?\n");
  867. break;
  868. default:
  869. if (net_ratelimit())
  870. netdev_warn(netdev, "Rx status %d\n", status);
  871. break;
  872. }
  873. r8152_submit_rx(tp, agg, GFP_ATOMIC);
  874. }
  875. static void write_bulk_callback(struct urb *urb)
  876. {
  877. struct net_device_stats *stats;
  878. struct net_device *netdev;
  879. struct tx_agg *agg;
  880. struct r8152 *tp;
  881. int status = urb->status;
  882. agg = urb->context;
  883. if (!agg)
  884. return;
  885. tp = agg->context;
  886. if (!tp)
  887. return;
  888. netdev = tp->netdev;
  889. stats = &netdev->stats;
  890. if (status) {
  891. if (net_ratelimit())
  892. netdev_warn(netdev, "Tx status %d\n", status);
  893. stats->tx_errors += agg->skb_num;
  894. } else {
  895. stats->tx_packets += agg->skb_num;
  896. stats->tx_bytes += agg->skb_len;
  897. }
  898. spin_lock(&tp->tx_lock);
  899. list_add_tail(&agg->list, &tp->tx_free);
  900. spin_unlock(&tp->tx_lock);
  901. usb_autopm_put_interface_async(tp->intf);
  902. if (!netif_carrier_ok(netdev))
  903. return;
  904. if (!test_bit(WORK_ENABLE, &tp->flags))
  905. return;
  906. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  907. return;
  908. if (!skb_queue_empty(&tp->tx_queue))
  909. napi_schedule(&tp->napi);
  910. }
  911. static void intr_callback(struct urb *urb)
  912. {
  913. struct r8152 *tp;
  914. __le16 *d;
  915. int status = urb->status;
  916. int res;
  917. tp = urb->context;
  918. if (!tp)
  919. return;
  920. if (!test_bit(WORK_ENABLE, &tp->flags))
  921. return;
  922. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  923. return;
  924. switch (status) {
  925. case 0: /* success */
  926. break;
  927. case -ECONNRESET: /* unlink */
  928. case -ESHUTDOWN:
  929. netif_device_detach(tp->netdev);
  930. case -ENOENT:
  931. case -EPROTO:
  932. netif_info(tp, intr, tp->netdev,
  933. "Stop submitting intr, status %d\n", status);
  934. return;
  935. case -EOVERFLOW:
  936. netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n");
  937. goto resubmit;
  938. /* -EPIPE: should clear the halt */
  939. default:
  940. netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
  941. goto resubmit;
  942. }
  943. d = urb->transfer_buffer;
  944. if (INTR_LINK & __le16_to_cpu(d[0])) {
  945. if (!netif_carrier_ok(tp->netdev)) {
  946. set_bit(RTL8152_LINK_CHG, &tp->flags);
  947. schedule_delayed_work(&tp->schedule, 0);
  948. }
  949. } else {
  950. if (netif_carrier_ok(tp->netdev)) {
  951. set_bit(RTL8152_LINK_CHG, &tp->flags);
  952. schedule_delayed_work(&tp->schedule, 0);
  953. }
  954. }
  955. resubmit:
  956. res = usb_submit_urb(urb, GFP_ATOMIC);
  957. if (res == -ENODEV) {
  958. set_bit(RTL8152_UNPLUG, &tp->flags);
  959. netif_device_detach(tp->netdev);
  960. } else if (res) {
  961. netif_err(tp, intr, tp->netdev,
  962. "can't resubmit intr, status %d\n", res);
  963. }
  964. }
  965. static inline void *rx_agg_align(void *data)
  966. {
  967. return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
  968. }
  969. static inline void *tx_agg_align(void *data)
  970. {
  971. return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
  972. }
  973. static void free_all_mem(struct r8152 *tp)
  974. {
  975. int i;
  976. for (i = 0; i < RTL8152_MAX_RX; i++) {
  977. usb_free_urb(tp->rx_info[i].urb);
  978. tp->rx_info[i].urb = NULL;
  979. kfree(tp->rx_info[i].buffer);
  980. tp->rx_info[i].buffer = NULL;
  981. tp->rx_info[i].head = NULL;
  982. }
  983. for (i = 0; i < RTL8152_MAX_TX; i++) {
  984. usb_free_urb(tp->tx_info[i].urb);
  985. tp->tx_info[i].urb = NULL;
  986. kfree(tp->tx_info[i].buffer);
  987. tp->tx_info[i].buffer = NULL;
  988. tp->tx_info[i].head = NULL;
  989. }
  990. usb_free_urb(tp->intr_urb);
  991. tp->intr_urb = NULL;
  992. kfree(tp->intr_buff);
  993. tp->intr_buff = NULL;
  994. }
  995. static int alloc_all_mem(struct r8152 *tp)
  996. {
  997. struct net_device *netdev = tp->netdev;
  998. struct usb_interface *intf = tp->intf;
  999. struct usb_host_interface *alt = intf->cur_altsetting;
  1000. struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
  1001. struct urb *urb;
  1002. int node, i;
  1003. u8 *buf;
  1004. node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
  1005. spin_lock_init(&tp->rx_lock);
  1006. spin_lock_init(&tp->tx_lock);
  1007. INIT_LIST_HEAD(&tp->tx_free);
  1008. skb_queue_head_init(&tp->tx_queue);
  1009. skb_queue_head_init(&tp->rx_queue);
  1010. for (i = 0; i < RTL8152_MAX_RX; i++) {
  1011. buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
  1012. if (!buf)
  1013. goto err1;
  1014. if (buf != rx_agg_align(buf)) {
  1015. kfree(buf);
  1016. buf = kmalloc_node(agg_buf_sz + RX_ALIGN, GFP_KERNEL,
  1017. node);
  1018. if (!buf)
  1019. goto err1;
  1020. }
  1021. urb = usb_alloc_urb(0, GFP_KERNEL);
  1022. if (!urb) {
  1023. kfree(buf);
  1024. goto err1;
  1025. }
  1026. INIT_LIST_HEAD(&tp->rx_info[i].list);
  1027. tp->rx_info[i].context = tp;
  1028. tp->rx_info[i].urb = urb;
  1029. tp->rx_info[i].buffer = buf;
  1030. tp->rx_info[i].head = rx_agg_align(buf);
  1031. }
  1032. for (i = 0; i < RTL8152_MAX_TX; i++) {
  1033. buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
  1034. if (!buf)
  1035. goto err1;
  1036. if (buf != tx_agg_align(buf)) {
  1037. kfree(buf);
  1038. buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL,
  1039. node);
  1040. if (!buf)
  1041. goto err1;
  1042. }
  1043. urb = usb_alloc_urb(0, GFP_KERNEL);
  1044. if (!urb) {
  1045. kfree(buf);
  1046. goto err1;
  1047. }
  1048. INIT_LIST_HEAD(&tp->tx_info[i].list);
  1049. tp->tx_info[i].context = tp;
  1050. tp->tx_info[i].urb = urb;
  1051. tp->tx_info[i].buffer = buf;
  1052. tp->tx_info[i].head = tx_agg_align(buf);
  1053. list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
  1054. }
  1055. tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
  1056. if (!tp->intr_urb)
  1057. goto err1;
  1058. tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
  1059. if (!tp->intr_buff)
  1060. goto err1;
  1061. tp->intr_interval = (int)ep_intr->desc.bInterval;
  1062. usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3),
  1063. tp->intr_buff, INTBUFSIZE, intr_callback,
  1064. tp, tp->intr_interval);
  1065. return 0;
  1066. err1:
  1067. free_all_mem(tp);
  1068. return -ENOMEM;
  1069. }
  1070. static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
  1071. {
  1072. struct tx_agg *agg = NULL;
  1073. unsigned long flags;
  1074. if (list_empty(&tp->tx_free))
  1075. return NULL;
  1076. spin_lock_irqsave(&tp->tx_lock, flags);
  1077. if (!list_empty(&tp->tx_free)) {
  1078. struct list_head *cursor;
  1079. cursor = tp->tx_free.next;
  1080. list_del_init(cursor);
  1081. agg = list_entry(cursor, struct tx_agg, list);
  1082. }
  1083. spin_unlock_irqrestore(&tp->tx_lock, flags);
  1084. return agg;
  1085. }
  1086. /* r8152_csum_workaround()
  1087. * The hw limites the value the transport offset. When the offset is out of the
  1088. * range, calculate the checksum by sw.
  1089. */
  1090. static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb,
  1091. struct sk_buff_head *list)
  1092. {
  1093. if (skb_shinfo(skb)->gso_size) {
  1094. netdev_features_t features = tp->netdev->features;
  1095. struct sk_buff_head seg_list;
  1096. struct sk_buff *segs, *nskb;
  1097. features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
  1098. segs = skb_gso_segment(skb, features);
  1099. if (IS_ERR(segs) || !segs)
  1100. goto drop;
  1101. __skb_queue_head_init(&seg_list);
  1102. do {
  1103. nskb = segs;
  1104. segs = segs->next;
  1105. nskb->next = NULL;
  1106. __skb_queue_tail(&seg_list, nskb);
  1107. } while (segs);
  1108. skb_queue_splice(&seg_list, list);
  1109. dev_kfree_skb(skb);
  1110. } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
  1111. if (skb_checksum_help(skb) < 0)
  1112. goto drop;
  1113. __skb_queue_head(list, skb);
  1114. } else {
  1115. struct net_device_stats *stats;
  1116. drop:
  1117. stats = &tp->netdev->stats;
  1118. stats->tx_dropped++;
  1119. dev_kfree_skb(skb);
  1120. }
  1121. }
  1122. /* msdn_giant_send_check()
  1123. * According to the document of microsoft, the TCP Pseudo Header excludes the
  1124. * packet length for IPv6 TCP large packets.
  1125. */
  1126. static int msdn_giant_send_check(struct sk_buff *skb)
  1127. {
  1128. const struct ipv6hdr *ipv6h;
  1129. struct tcphdr *th;
  1130. int ret;
  1131. ret = skb_cow_head(skb, 0);
  1132. if (ret)
  1133. return ret;
  1134. ipv6h = ipv6_hdr(skb);
  1135. th = tcp_hdr(skb);
  1136. th->check = 0;
  1137. th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
  1138. return ret;
  1139. }
  1140. static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb)
  1141. {
  1142. if (skb_vlan_tag_present(skb)) {
  1143. u32 opts2;
  1144. opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb));
  1145. desc->opts2 |= cpu_to_le32(opts2);
  1146. }
  1147. }
  1148. static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb)
  1149. {
  1150. u32 opts2 = le32_to_cpu(desc->opts2);
  1151. if (opts2 & RX_VLAN_TAG)
  1152. __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
  1153. swab16(opts2 & 0xffff));
  1154. }
  1155. static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc,
  1156. struct sk_buff *skb, u32 len, u32 transport_offset)
  1157. {
  1158. u32 mss = skb_shinfo(skb)->gso_size;
  1159. u32 opts1, opts2 = 0;
  1160. int ret = TX_CSUM_SUCCESS;
  1161. WARN_ON_ONCE(len > TX_LEN_MAX);
  1162. opts1 = len | TX_FS | TX_LS;
  1163. if (mss) {
  1164. if (transport_offset > GTTCPHO_MAX) {
  1165. netif_warn(tp, tx_err, tp->netdev,
  1166. "Invalid transport offset 0x%x for TSO\n",
  1167. transport_offset);
  1168. ret = TX_CSUM_TSO;
  1169. goto unavailable;
  1170. }
  1171. switch (vlan_get_protocol(skb)) {
  1172. case htons(ETH_P_IP):
  1173. opts1 |= GTSENDV4;
  1174. break;
  1175. case htons(ETH_P_IPV6):
  1176. if (msdn_giant_send_check(skb)) {
  1177. ret = TX_CSUM_TSO;
  1178. goto unavailable;
  1179. }
  1180. opts1 |= GTSENDV6;
  1181. break;
  1182. default:
  1183. WARN_ON_ONCE(1);
  1184. break;
  1185. }
  1186. opts1 |= transport_offset << GTTCPHO_SHIFT;
  1187. opts2 |= min(mss, MSS_MAX) << MSS_SHIFT;
  1188. } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
  1189. u8 ip_protocol;
  1190. if (transport_offset > TCPHO_MAX) {
  1191. netif_warn(tp, tx_err, tp->netdev,
  1192. "Invalid transport offset 0x%x\n",
  1193. transport_offset);
  1194. ret = TX_CSUM_NONE;
  1195. goto unavailable;
  1196. }
  1197. switch (vlan_get_protocol(skb)) {
  1198. case htons(ETH_P_IP):
  1199. opts2 |= IPV4_CS;
  1200. ip_protocol = ip_hdr(skb)->protocol;
  1201. break;
  1202. case htons(ETH_P_IPV6):
  1203. opts2 |= IPV6_CS;
  1204. ip_protocol = ipv6_hdr(skb)->nexthdr;
  1205. break;
  1206. default:
  1207. ip_protocol = IPPROTO_RAW;
  1208. break;
  1209. }
  1210. if (ip_protocol == IPPROTO_TCP)
  1211. opts2 |= TCP_CS;
  1212. else if (ip_protocol == IPPROTO_UDP)
  1213. opts2 |= UDP_CS;
  1214. else
  1215. WARN_ON_ONCE(1);
  1216. opts2 |= transport_offset << TCPHO_SHIFT;
  1217. }
  1218. desc->opts2 = cpu_to_le32(opts2);
  1219. desc->opts1 = cpu_to_le32(opts1);
  1220. unavailable:
  1221. return ret;
  1222. }
  1223. static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
  1224. {
  1225. struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
  1226. int remain, ret;
  1227. u8 *tx_data;
  1228. __skb_queue_head_init(&skb_head);
  1229. spin_lock(&tx_queue->lock);
  1230. skb_queue_splice_init(tx_queue, &skb_head);
  1231. spin_unlock(&tx_queue->lock);
  1232. tx_data = agg->head;
  1233. agg->skb_num = 0;
  1234. agg->skb_len = 0;
  1235. remain = agg_buf_sz;
  1236. while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
  1237. struct tx_desc *tx_desc;
  1238. struct sk_buff *skb;
  1239. unsigned int len;
  1240. u32 offset;
  1241. skb = __skb_dequeue(&skb_head);
  1242. if (!skb)
  1243. break;
  1244. len = skb->len + sizeof(*tx_desc);
  1245. if (len > remain) {
  1246. __skb_queue_head(&skb_head, skb);
  1247. break;
  1248. }
  1249. tx_data = tx_agg_align(tx_data);
  1250. tx_desc = (struct tx_desc *)tx_data;
  1251. offset = (u32)skb_transport_offset(skb);
  1252. if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) {
  1253. r8152_csum_workaround(tp, skb, &skb_head);
  1254. continue;
  1255. }
  1256. rtl_tx_vlan_tag(tx_desc, skb);
  1257. tx_data += sizeof(*tx_desc);
  1258. len = skb->len;
  1259. if (skb_copy_bits(skb, 0, tx_data, len) < 0) {
  1260. struct net_device_stats *stats = &tp->netdev->stats;
  1261. stats->tx_dropped++;
  1262. dev_kfree_skb_any(skb);
  1263. tx_data -= sizeof(*tx_desc);
  1264. continue;
  1265. }
  1266. tx_data += len;
  1267. agg->skb_len += len;
  1268. agg->skb_num++;
  1269. dev_kfree_skb_any(skb);
  1270. remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
  1271. }
  1272. if (!skb_queue_empty(&skb_head)) {
  1273. spin_lock(&tx_queue->lock);
  1274. skb_queue_splice(&skb_head, tx_queue);
  1275. spin_unlock(&tx_queue->lock);
  1276. }
  1277. netif_tx_lock(tp->netdev);
  1278. if (netif_queue_stopped(tp->netdev) &&
  1279. skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
  1280. netif_wake_queue(tp->netdev);
  1281. netif_tx_unlock(tp->netdev);
  1282. ret = usb_autopm_get_interface_async(tp->intf);
  1283. if (ret < 0)
  1284. goto out_tx_fill;
  1285. usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
  1286. agg->head, (int)(tx_data - (u8 *)agg->head),
  1287. (usb_complete_t)write_bulk_callback, agg);
  1288. ret = usb_submit_urb(agg->urb, GFP_ATOMIC);
  1289. if (ret < 0)
  1290. usb_autopm_put_interface_async(tp->intf);
  1291. out_tx_fill:
  1292. return ret;
  1293. }
  1294. static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc)
  1295. {
  1296. u8 checksum = CHECKSUM_NONE;
  1297. u32 opts2, opts3;
  1298. if (tp->version == RTL_VER_01)
  1299. goto return_result;
  1300. opts2 = le32_to_cpu(rx_desc->opts2);
  1301. opts3 = le32_to_cpu(rx_desc->opts3);
  1302. if (opts2 & RD_IPV4_CS) {
  1303. if (opts3 & IPF)
  1304. checksum = CHECKSUM_NONE;
  1305. else if ((opts2 & RD_UDP_CS) && (opts3 & UDPF))
  1306. checksum = CHECKSUM_NONE;
  1307. else if ((opts2 & RD_TCP_CS) && (opts3 & TCPF))
  1308. checksum = CHECKSUM_NONE;
  1309. else
  1310. checksum = CHECKSUM_UNNECESSARY;
  1311. } else if (RD_IPV6_CS) {
  1312. if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
  1313. checksum = CHECKSUM_UNNECESSARY;
  1314. else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
  1315. checksum = CHECKSUM_UNNECESSARY;
  1316. }
  1317. return_result:
  1318. return checksum;
  1319. }
  1320. static int rx_bottom(struct r8152 *tp, int budget)
  1321. {
  1322. unsigned long flags;
  1323. struct list_head *cursor, *next, rx_queue;
  1324. int ret = 0, work_done = 0;
  1325. if (!skb_queue_empty(&tp->rx_queue)) {
  1326. while (work_done < budget) {
  1327. struct sk_buff *skb = __skb_dequeue(&tp->rx_queue);
  1328. struct net_device *netdev = tp->netdev;
  1329. struct net_device_stats *stats = &netdev->stats;
  1330. unsigned int pkt_len;
  1331. if (!skb)
  1332. break;
  1333. pkt_len = skb->len;
  1334. napi_gro_receive(&tp->napi, skb);
  1335. work_done++;
  1336. stats->rx_packets++;
  1337. stats->rx_bytes += pkt_len;
  1338. }
  1339. }
  1340. if (list_empty(&tp->rx_done))
  1341. goto out1;
  1342. INIT_LIST_HEAD(&rx_queue);
  1343. spin_lock_irqsave(&tp->rx_lock, flags);
  1344. list_splice_init(&tp->rx_done, &rx_queue);
  1345. spin_unlock_irqrestore(&tp->rx_lock, flags);
  1346. list_for_each_safe(cursor, next, &rx_queue) {
  1347. struct rx_desc *rx_desc;
  1348. struct rx_agg *agg;
  1349. int len_used = 0;
  1350. struct urb *urb;
  1351. u8 *rx_data;
  1352. list_del_init(cursor);
  1353. agg = list_entry(cursor, struct rx_agg, list);
  1354. urb = agg->urb;
  1355. if (urb->actual_length < ETH_ZLEN)
  1356. goto submit;
  1357. rx_desc = agg->head;
  1358. rx_data = agg->head;
  1359. len_used += sizeof(struct rx_desc);
  1360. while (urb->actual_length > len_used) {
  1361. struct net_device *netdev = tp->netdev;
  1362. struct net_device_stats *stats = &netdev->stats;
  1363. unsigned int pkt_len;
  1364. struct sk_buff *skb;
  1365. pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
  1366. if (pkt_len < ETH_ZLEN)
  1367. break;
  1368. len_used += pkt_len;
  1369. if (urb->actual_length < len_used)
  1370. break;
  1371. pkt_len -= CRC_SIZE;
  1372. rx_data += sizeof(struct rx_desc);
  1373. skb = netdev_alloc_skb_ip_align(netdev, pkt_len);
  1374. if (!skb) {
  1375. stats->rx_dropped++;
  1376. goto find_next_rx;
  1377. }
  1378. skb->ip_summed = r8152_rx_csum(tp, rx_desc);
  1379. memcpy(skb->data, rx_data, pkt_len);
  1380. skb_put(skb, pkt_len);
  1381. skb->protocol = eth_type_trans(skb, netdev);
  1382. rtl_rx_vlan_tag(rx_desc, skb);
  1383. if (work_done < budget) {
  1384. napi_gro_receive(&tp->napi, skb);
  1385. work_done++;
  1386. stats->rx_packets++;
  1387. stats->rx_bytes += pkt_len;
  1388. } else {
  1389. __skb_queue_tail(&tp->rx_queue, skb);
  1390. }
  1391. find_next_rx:
  1392. rx_data = rx_agg_align(rx_data + pkt_len + CRC_SIZE);
  1393. rx_desc = (struct rx_desc *)rx_data;
  1394. len_used = (int)(rx_data - (u8 *)agg->head);
  1395. len_used += sizeof(struct rx_desc);
  1396. }
  1397. submit:
  1398. if (!ret) {
  1399. ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
  1400. } else {
  1401. urb->actual_length = 0;
  1402. list_add_tail(&agg->list, next);
  1403. }
  1404. }
  1405. if (!list_empty(&rx_queue)) {
  1406. spin_lock_irqsave(&tp->rx_lock, flags);
  1407. list_splice_tail(&rx_queue, &tp->rx_done);
  1408. spin_unlock_irqrestore(&tp->rx_lock, flags);
  1409. }
  1410. out1:
  1411. return work_done;
  1412. }
  1413. static void tx_bottom(struct r8152 *tp)
  1414. {
  1415. int res;
  1416. do {
  1417. struct tx_agg *agg;
  1418. if (skb_queue_empty(&tp->tx_queue))
  1419. break;
  1420. agg = r8152_get_tx_agg(tp);
  1421. if (!agg)
  1422. break;
  1423. res = r8152_tx_agg_fill(tp, agg);
  1424. if (res) {
  1425. struct net_device *netdev = tp->netdev;
  1426. if (res == -ENODEV) {
  1427. set_bit(RTL8152_UNPLUG, &tp->flags);
  1428. netif_device_detach(netdev);
  1429. } else {
  1430. struct net_device_stats *stats = &netdev->stats;
  1431. unsigned long flags;
  1432. netif_warn(tp, tx_err, netdev,
  1433. "failed tx_urb %d\n", res);
  1434. stats->tx_dropped += agg->skb_num;
  1435. spin_lock_irqsave(&tp->tx_lock, flags);
  1436. list_add_tail(&agg->list, &tp->tx_free);
  1437. spin_unlock_irqrestore(&tp->tx_lock, flags);
  1438. }
  1439. }
  1440. } while (res == 0);
  1441. }
  1442. static void bottom_half(struct r8152 *tp)
  1443. {
  1444. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  1445. return;
  1446. if (!test_bit(WORK_ENABLE, &tp->flags))
  1447. return;
  1448. /* When link down, the driver would cancel all bulks. */
  1449. /* This avoid the re-submitting bulk */
  1450. if (!netif_carrier_ok(tp->netdev))
  1451. return;
  1452. clear_bit(SCHEDULE_NAPI, &tp->flags);
  1453. tx_bottom(tp);
  1454. }
  1455. static int r8152_poll(struct napi_struct *napi, int budget)
  1456. {
  1457. struct r8152 *tp = container_of(napi, struct r8152, napi);
  1458. int work_done;
  1459. work_done = rx_bottom(tp, budget);
  1460. bottom_half(tp);
  1461. if (work_done < budget) {
  1462. napi_complete(napi);
  1463. if (!list_empty(&tp->rx_done))
  1464. napi_schedule(napi);
  1465. }
  1466. return work_done;
  1467. }
  1468. static
  1469. int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
  1470. {
  1471. int ret;
  1472. /* The rx would be stopped, so skip submitting */
  1473. if (test_bit(RTL8152_UNPLUG, &tp->flags) ||
  1474. !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev))
  1475. return 0;
  1476. usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
  1477. agg->head, agg_buf_sz,
  1478. (usb_complete_t)read_bulk_callback, agg);
  1479. ret = usb_submit_urb(agg->urb, mem_flags);
  1480. if (ret == -ENODEV) {
  1481. set_bit(RTL8152_UNPLUG, &tp->flags);
  1482. netif_device_detach(tp->netdev);
  1483. } else if (ret) {
  1484. struct urb *urb = agg->urb;
  1485. unsigned long flags;
  1486. urb->actual_length = 0;
  1487. spin_lock_irqsave(&tp->rx_lock, flags);
  1488. list_add_tail(&agg->list, &tp->rx_done);
  1489. spin_unlock_irqrestore(&tp->rx_lock, flags);
  1490. netif_err(tp, rx_err, tp->netdev,
  1491. "Couldn't submit rx[%p], ret = %d\n", agg, ret);
  1492. napi_schedule(&tp->napi);
  1493. }
  1494. return ret;
  1495. }
  1496. static void rtl_drop_queued_tx(struct r8152 *tp)
  1497. {
  1498. struct net_device_stats *stats = &tp->netdev->stats;
  1499. struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
  1500. struct sk_buff *skb;
  1501. if (skb_queue_empty(tx_queue))
  1502. return;
  1503. __skb_queue_head_init(&skb_head);
  1504. spin_lock_bh(&tx_queue->lock);
  1505. skb_queue_splice_init(tx_queue, &skb_head);
  1506. spin_unlock_bh(&tx_queue->lock);
  1507. while ((skb = __skb_dequeue(&skb_head))) {
  1508. dev_kfree_skb(skb);
  1509. stats->tx_dropped++;
  1510. }
  1511. }
  1512. static void rtl8152_tx_timeout(struct net_device *netdev)
  1513. {
  1514. struct r8152 *tp = netdev_priv(netdev);
  1515. int i;
  1516. netif_warn(tp, tx_err, netdev, "Tx timeout\n");
  1517. for (i = 0; i < RTL8152_MAX_TX; i++)
  1518. usb_unlink_urb(tp->tx_info[i].urb);
  1519. }
  1520. static void rtl8152_set_rx_mode(struct net_device *netdev)
  1521. {
  1522. struct r8152 *tp = netdev_priv(netdev);
  1523. if (netif_carrier_ok(netdev)) {
  1524. set_bit(RTL8152_SET_RX_MODE, &tp->flags);
  1525. schedule_delayed_work(&tp->schedule, 0);
  1526. }
  1527. }
  1528. static void _rtl8152_set_rx_mode(struct net_device *netdev)
  1529. {
  1530. struct r8152 *tp = netdev_priv(netdev);
  1531. u32 mc_filter[2]; /* Multicast hash filter */
  1532. __le32 tmp[2];
  1533. u32 ocp_data;
  1534. clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
  1535. netif_stop_queue(netdev);
  1536. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  1537. ocp_data &= ~RCR_ACPT_ALL;
  1538. ocp_data |= RCR_AB | RCR_APM;
  1539. if (netdev->flags & IFF_PROMISC) {
  1540. /* Unconditionally log net taps. */
  1541. netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
  1542. ocp_data |= RCR_AM | RCR_AAP;
  1543. mc_filter[1] = 0xffffffff;
  1544. mc_filter[0] = 0xffffffff;
  1545. } else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
  1546. (netdev->flags & IFF_ALLMULTI)) {
  1547. /* Too many to filter perfectly -- accept all multicasts. */
  1548. ocp_data |= RCR_AM;
  1549. mc_filter[1] = 0xffffffff;
  1550. mc_filter[0] = 0xffffffff;
  1551. } else {
  1552. struct netdev_hw_addr *ha;
  1553. mc_filter[1] = 0;
  1554. mc_filter[0] = 0;
  1555. netdev_for_each_mc_addr(ha, netdev) {
  1556. int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
  1557. mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
  1558. ocp_data |= RCR_AM;
  1559. }
  1560. }
  1561. tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
  1562. tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
  1563. pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
  1564. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  1565. netif_wake_queue(netdev);
  1566. }
  1567. static netdev_features_t
  1568. rtl8152_features_check(struct sk_buff *skb, struct net_device *dev,
  1569. netdev_features_t features)
  1570. {
  1571. u32 mss = skb_shinfo(skb)->gso_size;
  1572. int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX;
  1573. int offset = skb_transport_offset(skb);
  1574. if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && offset > max_offset)
  1575. features &= ~(NETIF_F_ALL_CSUM | NETIF_F_GSO_MASK);
  1576. else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz)
  1577. features &= ~NETIF_F_GSO_MASK;
  1578. return features;
  1579. }
  1580. static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
  1581. struct net_device *netdev)
  1582. {
  1583. struct r8152 *tp = netdev_priv(netdev);
  1584. skb_tx_timestamp(skb);
  1585. skb_queue_tail(&tp->tx_queue, skb);
  1586. if (!list_empty(&tp->tx_free)) {
  1587. if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
  1588. set_bit(SCHEDULE_NAPI, &tp->flags);
  1589. schedule_delayed_work(&tp->schedule, 0);
  1590. } else {
  1591. usb_mark_last_busy(tp->udev);
  1592. napi_schedule(&tp->napi);
  1593. }
  1594. } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) {
  1595. netif_stop_queue(netdev);
  1596. }
  1597. return NETDEV_TX_OK;
  1598. }
  1599. static void r8152b_reset_packet_filter(struct r8152 *tp)
  1600. {
  1601. u32 ocp_data;
  1602. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
  1603. ocp_data &= ~FMC_FCR_MCU_EN;
  1604. ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
  1605. ocp_data |= FMC_FCR_MCU_EN;
  1606. ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
  1607. }
  1608. static void rtl8152_nic_reset(struct r8152 *tp)
  1609. {
  1610. int i;
  1611. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
  1612. for (i = 0; i < 1000; i++) {
  1613. if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
  1614. break;
  1615. usleep_range(100, 400);
  1616. }
  1617. }
  1618. static void set_tx_qlen(struct r8152 *tp)
  1619. {
  1620. struct net_device *netdev = tp->netdev;
  1621. tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + VLAN_HLEN +
  1622. sizeof(struct tx_desc));
  1623. }
  1624. static inline u8 rtl8152_get_speed(struct r8152 *tp)
  1625. {
  1626. return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
  1627. }
  1628. static void rtl_set_eee_plus(struct r8152 *tp)
  1629. {
  1630. u32 ocp_data;
  1631. u8 speed;
  1632. speed = rtl8152_get_speed(tp);
  1633. if (speed & _10bps) {
  1634. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
  1635. ocp_data |= EEEP_CR_EEEP_TX;
  1636. ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
  1637. } else {
  1638. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
  1639. ocp_data &= ~EEEP_CR_EEEP_TX;
  1640. ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
  1641. }
  1642. }
  1643. static void rxdy_gated_en(struct r8152 *tp, bool enable)
  1644. {
  1645. u32 ocp_data;
  1646. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
  1647. if (enable)
  1648. ocp_data |= RXDY_GATED_EN;
  1649. else
  1650. ocp_data &= ~RXDY_GATED_EN;
  1651. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
  1652. }
  1653. static int rtl_start_rx(struct r8152 *tp)
  1654. {
  1655. int i, ret = 0;
  1656. napi_disable(&tp->napi);
  1657. INIT_LIST_HEAD(&tp->rx_done);
  1658. for (i = 0; i < RTL8152_MAX_RX; i++) {
  1659. INIT_LIST_HEAD(&tp->rx_info[i].list);
  1660. ret = r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL);
  1661. if (ret)
  1662. break;
  1663. }
  1664. napi_enable(&tp->napi);
  1665. if (ret && ++i < RTL8152_MAX_RX) {
  1666. struct list_head rx_queue;
  1667. unsigned long flags;
  1668. INIT_LIST_HEAD(&rx_queue);
  1669. do {
  1670. struct rx_agg *agg = &tp->rx_info[i++];
  1671. struct urb *urb = agg->urb;
  1672. urb->actual_length = 0;
  1673. list_add_tail(&agg->list, &rx_queue);
  1674. } while (i < RTL8152_MAX_RX);
  1675. spin_lock_irqsave(&tp->rx_lock, flags);
  1676. list_splice_tail(&rx_queue, &tp->rx_done);
  1677. spin_unlock_irqrestore(&tp->rx_lock, flags);
  1678. }
  1679. return ret;
  1680. }
  1681. static int rtl_stop_rx(struct r8152 *tp)
  1682. {
  1683. int i;
  1684. for (i = 0; i < RTL8152_MAX_RX; i++)
  1685. usb_kill_urb(tp->rx_info[i].urb);
  1686. while (!skb_queue_empty(&tp->rx_queue))
  1687. dev_kfree_skb(__skb_dequeue(&tp->rx_queue));
  1688. return 0;
  1689. }
  1690. static int rtl_enable(struct r8152 *tp)
  1691. {
  1692. u32 ocp_data;
  1693. r8152b_reset_packet_filter(tp);
  1694. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
  1695. ocp_data |= CR_RE | CR_TE;
  1696. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
  1697. rxdy_gated_en(tp, false);
  1698. return 0;
  1699. }
  1700. static int rtl8152_enable(struct r8152 *tp)
  1701. {
  1702. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  1703. return -ENODEV;
  1704. set_tx_qlen(tp);
  1705. rtl_set_eee_plus(tp);
  1706. return rtl_enable(tp);
  1707. }
  1708. static void r8153_set_rx_agg(struct r8152 *tp)
  1709. {
  1710. u8 speed;
  1711. speed = rtl8152_get_speed(tp);
  1712. if (speed & _1000bps) {
  1713. if (tp->udev->speed == USB_SPEED_SUPER) {
  1714. ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH,
  1715. RX_THR_SUPPER);
  1716. ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG,
  1717. EARLY_AGG_SUPPER);
  1718. } else {
  1719. ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH,
  1720. RX_THR_HIGH);
  1721. ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG,
  1722. EARLY_AGG_HIGH);
  1723. }
  1724. } else {
  1725. ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_SLOW);
  1726. ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG,
  1727. EARLY_AGG_SLOW);
  1728. }
  1729. }
  1730. static int rtl8153_enable(struct r8152 *tp)
  1731. {
  1732. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  1733. return -ENODEV;
  1734. set_tx_qlen(tp);
  1735. rtl_set_eee_plus(tp);
  1736. r8153_set_rx_agg(tp);
  1737. return rtl_enable(tp);
  1738. }
  1739. static void rtl_disable(struct r8152 *tp)
  1740. {
  1741. u32 ocp_data;
  1742. int i;
  1743. if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
  1744. rtl_drop_queued_tx(tp);
  1745. return;
  1746. }
  1747. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  1748. ocp_data &= ~RCR_ACPT_ALL;
  1749. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  1750. rtl_drop_queued_tx(tp);
  1751. for (i = 0; i < RTL8152_MAX_TX; i++)
  1752. usb_kill_urb(tp->tx_info[i].urb);
  1753. rxdy_gated_en(tp, true);
  1754. for (i = 0; i < 1000; i++) {
  1755. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  1756. if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
  1757. break;
  1758. usleep_range(1000, 2000);
  1759. }
  1760. for (i = 0; i < 1000; i++) {
  1761. if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
  1762. break;
  1763. usleep_range(1000, 2000);
  1764. }
  1765. rtl_stop_rx(tp);
  1766. rtl8152_nic_reset(tp);
  1767. }
  1768. static void r8152_power_cut_en(struct r8152 *tp, bool enable)
  1769. {
  1770. u32 ocp_data;
  1771. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
  1772. if (enable)
  1773. ocp_data |= POWER_CUT;
  1774. else
  1775. ocp_data &= ~POWER_CUT;
  1776. ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
  1777. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
  1778. ocp_data &= ~RESUME_INDICATE;
  1779. ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
  1780. }
  1781. static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
  1782. {
  1783. u32 ocp_data;
  1784. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
  1785. if (enable)
  1786. ocp_data |= CPCR_RX_VLAN;
  1787. else
  1788. ocp_data &= ~CPCR_RX_VLAN;
  1789. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
  1790. }
  1791. static int rtl8152_set_features(struct net_device *dev,
  1792. netdev_features_t features)
  1793. {
  1794. netdev_features_t changed = features ^ dev->features;
  1795. struct r8152 *tp = netdev_priv(dev);
  1796. int ret;
  1797. ret = usb_autopm_get_interface(tp->intf);
  1798. if (ret < 0)
  1799. goto out;
  1800. mutex_lock(&tp->control);
  1801. if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
  1802. if (features & NETIF_F_HW_VLAN_CTAG_RX)
  1803. rtl_rx_vlan_en(tp, true);
  1804. else
  1805. rtl_rx_vlan_en(tp, false);
  1806. }
  1807. mutex_unlock(&tp->control);
  1808. usb_autopm_put_interface(tp->intf);
  1809. out:
  1810. return ret;
  1811. }
  1812. #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
  1813. static u32 __rtl_get_wol(struct r8152 *tp)
  1814. {
  1815. u32 ocp_data;
  1816. u32 wolopts = 0;
  1817. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG5);
  1818. if (!(ocp_data & LAN_WAKE_EN))
  1819. return 0;
  1820. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
  1821. if (ocp_data & LINK_ON_WAKE_EN)
  1822. wolopts |= WAKE_PHY;
  1823. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
  1824. if (ocp_data & UWF_EN)
  1825. wolopts |= WAKE_UCAST;
  1826. if (ocp_data & BWF_EN)
  1827. wolopts |= WAKE_BCAST;
  1828. if (ocp_data & MWF_EN)
  1829. wolopts |= WAKE_MCAST;
  1830. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
  1831. if (ocp_data & MAGIC_EN)
  1832. wolopts |= WAKE_MAGIC;
  1833. return wolopts;
  1834. }
  1835. static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
  1836. {
  1837. u32 ocp_data;
  1838. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
  1839. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
  1840. ocp_data &= ~LINK_ON_WAKE_EN;
  1841. if (wolopts & WAKE_PHY)
  1842. ocp_data |= LINK_ON_WAKE_EN;
  1843. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
  1844. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
  1845. ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN | LAN_WAKE_EN);
  1846. if (wolopts & WAKE_UCAST)
  1847. ocp_data |= UWF_EN;
  1848. if (wolopts & WAKE_BCAST)
  1849. ocp_data |= BWF_EN;
  1850. if (wolopts & WAKE_MCAST)
  1851. ocp_data |= MWF_EN;
  1852. if (wolopts & WAKE_ANY)
  1853. ocp_data |= LAN_WAKE_EN;
  1854. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
  1855. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
  1856. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
  1857. ocp_data &= ~MAGIC_EN;
  1858. if (wolopts & WAKE_MAGIC)
  1859. ocp_data |= MAGIC_EN;
  1860. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
  1861. if (wolopts & WAKE_ANY)
  1862. device_set_wakeup_enable(&tp->udev->dev, true);
  1863. else
  1864. device_set_wakeup_enable(&tp->udev->dev, false);
  1865. }
  1866. static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
  1867. {
  1868. if (enable) {
  1869. u32 ocp_data;
  1870. __rtl_set_wol(tp, WAKE_ANY);
  1871. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
  1872. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
  1873. ocp_data |= LINK_OFF_WAKE_EN;
  1874. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
  1875. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
  1876. } else {
  1877. __rtl_set_wol(tp, tp->saved_wolopts);
  1878. }
  1879. }
  1880. static void rtl_phy_reset(struct r8152 *tp)
  1881. {
  1882. u16 data;
  1883. int i;
  1884. clear_bit(PHY_RESET, &tp->flags);
  1885. data = r8152_mdio_read(tp, MII_BMCR);
  1886. /* don't reset again before the previous one complete */
  1887. if (data & BMCR_RESET)
  1888. return;
  1889. data |= BMCR_RESET;
  1890. r8152_mdio_write(tp, MII_BMCR, data);
  1891. for (i = 0; i < 50; i++) {
  1892. msleep(20);
  1893. if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
  1894. break;
  1895. }
  1896. }
  1897. static void r8153_teredo_off(struct r8152 *tp)
  1898. {
  1899. u32 ocp_data;
  1900. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
  1901. ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | OOB_TEREDO_EN);
  1902. ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
  1903. ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
  1904. ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
  1905. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
  1906. }
  1907. static void r8152b_disable_aldps(struct r8152 *tp)
  1908. {
  1909. ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | DIS_SDSAVE);
  1910. msleep(20);
  1911. }
  1912. static inline void r8152b_enable_aldps(struct r8152 *tp)
  1913. {
  1914. ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
  1915. LINKENA | DIS_SDSAVE);
  1916. }
  1917. static void rtl8152_disable(struct r8152 *tp)
  1918. {
  1919. r8152b_disable_aldps(tp);
  1920. rtl_disable(tp);
  1921. r8152b_enable_aldps(tp);
  1922. }
  1923. static void r8152b_hw_phy_cfg(struct r8152 *tp)
  1924. {
  1925. u16 data;
  1926. data = r8152_mdio_read(tp, MII_BMCR);
  1927. if (data & BMCR_PDOWN) {
  1928. data &= ~BMCR_PDOWN;
  1929. r8152_mdio_write(tp, MII_BMCR, data);
  1930. }
  1931. set_bit(PHY_RESET, &tp->flags);
  1932. }
  1933. static void r8152b_exit_oob(struct r8152 *tp)
  1934. {
  1935. u32 ocp_data;
  1936. int i;
  1937. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  1938. ocp_data &= ~RCR_ACPT_ALL;
  1939. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  1940. rxdy_gated_en(tp, true);
  1941. r8153_teredo_off(tp);
  1942. r8152b_hw_phy_cfg(tp);
  1943. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
  1944. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
  1945. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  1946. ocp_data &= ~NOW_IS_OOB;
  1947. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  1948. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  1949. ocp_data &= ~MCU_BORW_EN;
  1950. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  1951. for (i = 0; i < 1000; i++) {
  1952. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  1953. if (ocp_data & LINK_LIST_READY)
  1954. break;
  1955. usleep_range(1000, 2000);
  1956. }
  1957. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  1958. ocp_data |= RE_INIT_LL;
  1959. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  1960. for (i = 0; i < 1000; i++) {
  1961. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  1962. if (ocp_data & LINK_LIST_READY)
  1963. break;
  1964. usleep_range(1000, 2000);
  1965. }
  1966. rtl8152_nic_reset(tp);
  1967. /* rx share fifo credit full threshold */
  1968. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
  1969. if (tp->udev->speed == USB_SPEED_FULL ||
  1970. tp->udev->speed == USB_SPEED_LOW) {
  1971. /* rx share fifo credit near full threshold */
  1972. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
  1973. RXFIFO_THR2_FULL);
  1974. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
  1975. RXFIFO_THR3_FULL);
  1976. } else {
  1977. /* rx share fifo credit near full threshold */
  1978. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
  1979. RXFIFO_THR2_HIGH);
  1980. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
  1981. RXFIFO_THR3_HIGH);
  1982. }
  1983. /* TX share fifo free credit full threshold */
  1984. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
  1985. ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
  1986. ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
  1987. ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
  1988. TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
  1989. rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
  1990. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
  1991. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
  1992. ocp_data |= TCR0_AUTO_FIFO;
  1993. ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
  1994. }
  1995. static void r8152b_enter_oob(struct r8152 *tp)
  1996. {
  1997. u32 ocp_data;
  1998. int i;
  1999. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2000. ocp_data &= ~NOW_IS_OOB;
  2001. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  2002. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
  2003. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
  2004. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
  2005. rtl_disable(tp);
  2006. for (i = 0; i < 1000; i++) {
  2007. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2008. if (ocp_data & LINK_LIST_READY)
  2009. break;
  2010. usleep_range(1000, 2000);
  2011. }
  2012. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  2013. ocp_data |= RE_INIT_LL;
  2014. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  2015. for (i = 0; i < 1000; i++) {
  2016. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2017. if (ocp_data & LINK_LIST_READY)
  2018. break;
  2019. usleep_range(1000, 2000);
  2020. }
  2021. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
  2022. rtl_rx_vlan_en(tp, true);
  2023. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
  2024. ocp_data |= ALDPS_PROXY_MODE;
  2025. ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
  2026. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2027. ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
  2028. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  2029. rxdy_gated_en(tp, false);
  2030. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  2031. ocp_data |= RCR_APM | RCR_AM | RCR_AB;
  2032. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  2033. }
  2034. static void r8153_hw_phy_cfg(struct r8152 *tp)
  2035. {
  2036. u32 ocp_data;
  2037. u16 data;
  2038. ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
  2039. data = r8152_mdio_read(tp, MII_BMCR);
  2040. if (data & BMCR_PDOWN) {
  2041. data &= ~BMCR_PDOWN;
  2042. r8152_mdio_write(tp, MII_BMCR, data);
  2043. }
  2044. if (tp->version == RTL_VER_03) {
  2045. data = ocp_reg_read(tp, OCP_EEE_CFG);
  2046. data &= ~CTAP_SHORT_EN;
  2047. ocp_reg_write(tp, OCP_EEE_CFG, data);
  2048. }
  2049. data = ocp_reg_read(tp, OCP_POWER_CFG);
  2050. data |= EEE_CLKDIV_EN;
  2051. ocp_reg_write(tp, OCP_POWER_CFG, data);
  2052. data = ocp_reg_read(tp, OCP_DOWN_SPEED);
  2053. data |= EN_10M_BGOFF;
  2054. ocp_reg_write(tp, OCP_DOWN_SPEED, data);
  2055. data = ocp_reg_read(tp, OCP_POWER_CFG);
  2056. data |= EN_10M_PLLOFF;
  2057. ocp_reg_write(tp, OCP_POWER_CFG, data);
  2058. sram_write(tp, SRAM_IMPEDANCE, 0x0b13);
  2059. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
  2060. ocp_data |= PFM_PWM_SWITCH;
  2061. ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
  2062. /* Enable LPF corner auto tune */
  2063. sram_write(tp, SRAM_LPF_CFG, 0xf70f);
  2064. /* Adjust 10M Amplitude */
  2065. sram_write(tp, SRAM_10M_AMP1, 0x00af);
  2066. sram_write(tp, SRAM_10M_AMP2, 0x0208);
  2067. set_bit(PHY_RESET, &tp->flags);
  2068. }
  2069. static void r8153_u1u2en(struct r8152 *tp, bool enable)
  2070. {
  2071. u8 u1u2[8];
  2072. if (enable)
  2073. memset(u1u2, 0xff, sizeof(u1u2));
  2074. else
  2075. memset(u1u2, 0x00, sizeof(u1u2));
  2076. usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
  2077. }
  2078. static void r8153_u2p3en(struct r8152 *tp, bool enable)
  2079. {
  2080. u32 ocp_data;
  2081. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
  2082. if (enable)
  2083. ocp_data |= U2P3_ENABLE;
  2084. else
  2085. ocp_data &= ~U2P3_ENABLE;
  2086. ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
  2087. }
  2088. static void r8153_power_cut_en(struct r8152 *tp, bool enable)
  2089. {
  2090. u32 ocp_data;
  2091. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
  2092. if (enable)
  2093. ocp_data |= PWR_EN | PHASE2_EN;
  2094. else
  2095. ocp_data &= ~(PWR_EN | PHASE2_EN);
  2096. ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
  2097. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
  2098. ocp_data &= ~PCUT_STATUS;
  2099. ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
  2100. }
  2101. static void r8153_first_init(struct r8152 *tp)
  2102. {
  2103. u32 ocp_data;
  2104. int i;
  2105. rxdy_gated_en(tp, true);
  2106. r8153_teredo_off(tp);
  2107. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  2108. ocp_data &= ~RCR_ACPT_ALL;
  2109. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  2110. r8153_hw_phy_cfg(tp);
  2111. rtl8152_nic_reset(tp);
  2112. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2113. ocp_data &= ~NOW_IS_OOB;
  2114. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  2115. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  2116. ocp_data &= ~MCU_BORW_EN;
  2117. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  2118. for (i = 0; i < 1000; i++) {
  2119. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2120. if (ocp_data & LINK_LIST_READY)
  2121. break;
  2122. usleep_range(1000, 2000);
  2123. }
  2124. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  2125. ocp_data |= RE_INIT_LL;
  2126. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  2127. for (i = 0; i < 1000; i++) {
  2128. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2129. if (ocp_data & LINK_LIST_READY)
  2130. break;
  2131. usleep_range(1000, 2000);
  2132. }
  2133. rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
  2134. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS);
  2135. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
  2136. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
  2137. ocp_data |= TCR0_AUTO_FIFO;
  2138. ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
  2139. rtl8152_nic_reset(tp);
  2140. /* rx share fifo credit full threshold */
  2141. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
  2142. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
  2143. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
  2144. /* TX share fifo free credit full threshold */
  2145. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
  2146. /* rx aggregation */
  2147. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
  2148. ocp_data &= ~RX_AGG_DISABLE;
  2149. ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
  2150. }
  2151. static void r8153_enter_oob(struct r8152 *tp)
  2152. {
  2153. u32 ocp_data;
  2154. int i;
  2155. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2156. ocp_data &= ~NOW_IS_OOB;
  2157. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  2158. rtl_disable(tp);
  2159. for (i = 0; i < 1000; i++) {
  2160. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2161. if (ocp_data & LINK_LIST_READY)
  2162. break;
  2163. usleep_range(1000, 2000);
  2164. }
  2165. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  2166. ocp_data |= RE_INIT_LL;
  2167. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  2168. for (i = 0; i < 1000; i++) {
  2169. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2170. if (ocp_data & LINK_LIST_READY)
  2171. break;
  2172. usleep_range(1000, 2000);
  2173. }
  2174. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS);
  2175. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
  2176. ocp_data &= ~TEREDO_WAKE_MASK;
  2177. ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
  2178. rtl_rx_vlan_en(tp, true);
  2179. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
  2180. ocp_data |= ALDPS_PROXY_MODE;
  2181. ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
  2182. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2183. ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
  2184. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  2185. rxdy_gated_en(tp, false);
  2186. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  2187. ocp_data |= RCR_APM | RCR_AM | RCR_AB;
  2188. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  2189. }
  2190. static void r8153_disable_aldps(struct r8152 *tp)
  2191. {
  2192. u16 data;
  2193. data = ocp_reg_read(tp, OCP_POWER_CFG);
  2194. data &= ~EN_ALDPS;
  2195. ocp_reg_write(tp, OCP_POWER_CFG, data);
  2196. msleep(20);
  2197. }
  2198. static void r8153_enable_aldps(struct r8152 *tp)
  2199. {
  2200. u16 data;
  2201. data = ocp_reg_read(tp, OCP_POWER_CFG);
  2202. data |= EN_ALDPS;
  2203. ocp_reg_write(tp, OCP_POWER_CFG, data);
  2204. }
  2205. static void rtl8153_disable(struct r8152 *tp)
  2206. {
  2207. r8153_disable_aldps(tp);
  2208. rtl_disable(tp);
  2209. r8153_enable_aldps(tp);
  2210. }
  2211. static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex)
  2212. {
  2213. u16 bmcr, anar, gbcr;
  2214. int ret = 0;
  2215. cancel_delayed_work_sync(&tp->schedule);
  2216. anar = r8152_mdio_read(tp, MII_ADVERTISE);
  2217. anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
  2218. ADVERTISE_100HALF | ADVERTISE_100FULL);
  2219. if (tp->mii.supports_gmii) {
  2220. gbcr = r8152_mdio_read(tp, MII_CTRL1000);
  2221. gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
  2222. } else {
  2223. gbcr = 0;
  2224. }
  2225. if (autoneg == AUTONEG_DISABLE) {
  2226. if (speed == SPEED_10) {
  2227. bmcr = 0;
  2228. anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
  2229. } else if (speed == SPEED_100) {
  2230. bmcr = BMCR_SPEED100;
  2231. anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
  2232. } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
  2233. bmcr = BMCR_SPEED1000;
  2234. gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
  2235. } else {
  2236. ret = -EINVAL;
  2237. goto out;
  2238. }
  2239. if (duplex == DUPLEX_FULL)
  2240. bmcr |= BMCR_FULLDPLX;
  2241. } else {
  2242. if (speed == SPEED_10) {
  2243. if (duplex == DUPLEX_FULL)
  2244. anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
  2245. else
  2246. anar |= ADVERTISE_10HALF;
  2247. } else if (speed == SPEED_100) {
  2248. if (duplex == DUPLEX_FULL) {
  2249. anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
  2250. anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
  2251. } else {
  2252. anar |= ADVERTISE_10HALF;
  2253. anar |= ADVERTISE_100HALF;
  2254. }
  2255. } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
  2256. if (duplex == DUPLEX_FULL) {
  2257. anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
  2258. anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
  2259. gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
  2260. } else {
  2261. anar |= ADVERTISE_10HALF;
  2262. anar |= ADVERTISE_100HALF;
  2263. gbcr |= ADVERTISE_1000HALF;
  2264. }
  2265. } else {
  2266. ret = -EINVAL;
  2267. goto out;
  2268. }
  2269. bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
  2270. }
  2271. if (test_bit(PHY_RESET, &tp->flags))
  2272. bmcr |= BMCR_RESET;
  2273. if (tp->mii.supports_gmii)
  2274. r8152_mdio_write(tp, MII_CTRL1000, gbcr);
  2275. r8152_mdio_write(tp, MII_ADVERTISE, anar);
  2276. r8152_mdio_write(tp, MII_BMCR, bmcr);
  2277. if (test_bit(PHY_RESET, &tp->flags)) {
  2278. int i;
  2279. clear_bit(PHY_RESET, &tp->flags);
  2280. for (i = 0; i < 50; i++) {
  2281. msleep(20);
  2282. if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
  2283. break;
  2284. }
  2285. }
  2286. out:
  2287. return ret;
  2288. }
  2289. static void rtl8152_up(struct r8152 *tp)
  2290. {
  2291. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  2292. return;
  2293. r8152b_disable_aldps(tp);
  2294. r8152b_exit_oob(tp);
  2295. r8152b_enable_aldps(tp);
  2296. }
  2297. static void rtl8152_down(struct r8152 *tp)
  2298. {
  2299. if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
  2300. rtl_drop_queued_tx(tp);
  2301. return;
  2302. }
  2303. r8152_power_cut_en(tp, false);
  2304. r8152b_disable_aldps(tp);
  2305. r8152b_enter_oob(tp);
  2306. r8152b_enable_aldps(tp);
  2307. }
  2308. static void rtl8153_up(struct r8152 *tp)
  2309. {
  2310. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  2311. return;
  2312. r8153_disable_aldps(tp);
  2313. r8153_first_init(tp);
  2314. r8153_enable_aldps(tp);
  2315. }
  2316. static void rtl8153_down(struct r8152 *tp)
  2317. {
  2318. if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
  2319. rtl_drop_queued_tx(tp);
  2320. return;
  2321. }
  2322. r8153_u1u2en(tp, false);
  2323. r8153_power_cut_en(tp, false);
  2324. r8153_disable_aldps(tp);
  2325. r8153_enter_oob(tp);
  2326. r8153_enable_aldps(tp);
  2327. }
  2328. static void set_carrier(struct r8152 *tp)
  2329. {
  2330. struct net_device *netdev = tp->netdev;
  2331. u8 speed;
  2332. clear_bit(RTL8152_LINK_CHG, &tp->flags);
  2333. speed = rtl8152_get_speed(tp);
  2334. if (speed & LINK_STATUS) {
  2335. if (!netif_carrier_ok(netdev)) {
  2336. tp->rtl_ops.enable(tp);
  2337. set_bit(RTL8152_SET_RX_MODE, &tp->flags);
  2338. netif_carrier_on(netdev);
  2339. rtl_start_rx(tp);
  2340. }
  2341. } else {
  2342. if (netif_carrier_ok(netdev)) {
  2343. netif_carrier_off(netdev);
  2344. napi_disable(&tp->napi);
  2345. tp->rtl_ops.disable(tp);
  2346. napi_enable(&tp->napi);
  2347. }
  2348. }
  2349. }
  2350. static void rtl_work_func_t(struct work_struct *work)
  2351. {
  2352. struct r8152 *tp = container_of(work, struct r8152, schedule.work);
  2353. /* If the device is unplugged or !netif_running(), the workqueue
  2354. * doesn't need to wake the device, and could return directly.
  2355. */
  2356. if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev))
  2357. return;
  2358. if (usb_autopm_get_interface(tp->intf) < 0)
  2359. return;
  2360. if (!test_bit(WORK_ENABLE, &tp->flags))
  2361. goto out1;
  2362. if (!mutex_trylock(&tp->control)) {
  2363. schedule_delayed_work(&tp->schedule, 0);
  2364. goto out1;
  2365. }
  2366. if (test_bit(RTL8152_LINK_CHG, &tp->flags))
  2367. set_carrier(tp);
  2368. if (test_bit(RTL8152_SET_RX_MODE, &tp->flags))
  2369. _rtl8152_set_rx_mode(tp->netdev);
  2370. /* don't schedule napi before linking */
  2371. if (test_bit(SCHEDULE_NAPI, &tp->flags) &&
  2372. netif_carrier_ok(tp->netdev)) {
  2373. clear_bit(SCHEDULE_NAPI, &tp->flags);
  2374. napi_schedule(&tp->napi);
  2375. }
  2376. if (test_bit(PHY_RESET, &tp->flags))
  2377. rtl_phy_reset(tp);
  2378. mutex_unlock(&tp->control);
  2379. out1:
  2380. usb_autopm_put_interface(tp->intf);
  2381. }
  2382. static int rtl8152_open(struct net_device *netdev)
  2383. {
  2384. struct r8152 *tp = netdev_priv(netdev);
  2385. int res = 0;
  2386. res = alloc_all_mem(tp);
  2387. if (res)
  2388. goto out;
  2389. netif_carrier_off(netdev);
  2390. res = usb_autopm_get_interface(tp->intf);
  2391. if (res < 0) {
  2392. free_all_mem(tp);
  2393. goto out;
  2394. }
  2395. mutex_lock(&tp->control);
  2396. /* The WORK_ENABLE may be set when autoresume occurs */
  2397. if (test_bit(WORK_ENABLE, &tp->flags)) {
  2398. clear_bit(WORK_ENABLE, &tp->flags);
  2399. usb_kill_urb(tp->intr_urb);
  2400. cancel_delayed_work_sync(&tp->schedule);
  2401. /* disable the tx/rx, if the workqueue has enabled them. */
  2402. if (netif_carrier_ok(netdev))
  2403. tp->rtl_ops.disable(tp);
  2404. }
  2405. tp->rtl_ops.up(tp);
  2406. rtl8152_set_speed(tp, AUTONEG_ENABLE,
  2407. tp->mii.supports_gmii ? SPEED_1000 : SPEED_100,
  2408. DUPLEX_FULL);
  2409. netif_carrier_off(netdev);
  2410. netif_start_queue(netdev);
  2411. set_bit(WORK_ENABLE, &tp->flags);
  2412. res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
  2413. if (res) {
  2414. if (res == -ENODEV)
  2415. netif_device_detach(tp->netdev);
  2416. netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
  2417. res);
  2418. free_all_mem(tp);
  2419. } else {
  2420. napi_enable(&tp->napi);
  2421. }
  2422. mutex_unlock(&tp->control);
  2423. usb_autopm_put_interface(tp->intf);
  2424. out:
  2425. return res;
  2426. }
  2427. static int rtl8152_close(struct net_device *netdev)
  2428. {
  2429. struct r8152 *tp = netdev_priv(netdev);
  2430. int res = 0;
  2431. napi_disable(&tp->napi);
  2432. clear_bit(WORK_ENABLE, &tp->flags);
  2433. usb_kill_urb(tp->intr_urb);
  2434. cancel_delayed_work_sync(&tp->schedule);
  2435. netif_stop_queue(netdev);
  2436. res = usb_autopm_get_interface(tp->intf);
  2437. if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) {
  2438. rtl_drop_queued_tx(tp);
  2439. rtl_stop_rx(tp);
  2440. } else {
  2441. mutex_lock(&tp->control);
  2442. /* The autosuspend may have been enabled and wouldn't
  2443. * be disable when autoresume occurs, because the
  2444. * netif_running() would be false.
  2445. */
  2446. rtl_runtime_suspend_enable(tp, false);
  2447. tp->rtl_ops.down(tp);
  2448. mutex_unlock(&tp->control);
  2449. usb_autopm_put_interface(tp->intf);
  2450. }
  2451. free_all_mem(tp);
  2452. return res;
  2453. }
  2454. static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg)
  2455. {
  2456. ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev);
  2457. ocp_reg_write(tp, OCP_EEE_DATA, reg);
  2458. ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev);
  2459. }
  2460. static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg)
  2461. {
  2462. u16 data;
  2463. r8152_mmd_indirect(tp, dev, reg);
  2464. data = ocp_reg_read(tp, OCP_EEE_DATA);
  2465. ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
  2466. return data;
  2467. }
  2468. static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)
  2469. {
  2470. r8152_mmd_indirect(tp, dev, reg);
  2471. ocp_reg_write(tp, OCP_EEE_DATA, data);
  2472. ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
  2473. }
  2474. static void r8152_eee_en(struct r8152 *tp, bool enable)
  2475. {
  2476. u16 config1, config2, config3;
  2477. u32 ocp_data;
  2478. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
  2479. config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;
  2480. config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);
  2481. config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;
  2482. if (enable) {
  2483. ocp_data |= EEE_RX_EN | EEE_TX_EN;
  2484. config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;
  2485. config1 |= sd_rise_time(1);
  2486. config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;
  2487. config3 |= fast_snr(42);
  2488. } else {
  2489. ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
  2490. config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
  2491. RX_QUIET_EN);
  2492. config1 |= sd_rise_time(7);
  2493. config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);
  2494. config3 |= fast_snr(511);
  2495. }
  2496. ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
  2497. ocp_reg_write(tp, OCP_EEE_CONFIG1, config1);
  2498. ocp_reg_write(tp, OCP_EEE_CONFIG2, config2);
  2499. ocp_reg_write(tp, OCP_EEE_CONFIG3, config3);
  2500. }
  2501. static void r8152b_enable_eee(struct r8152 *tp)
  2502. {
  2503. r8152_eee_en(tp, true);
  2504. r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, MDIO_EEE_100TX);
  2505. }
  2506. static void r8153_eee_en(struct r8152 *tp, bool enable)
  2507. {
  2508. u32 ocp_data;
  2509. u16 config;
  2510. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
  2511. config = ocp_reg_read(tp, OCP_EEE_CFG);
  2512. if (enable) {
  2513. ocp_data |= EEE_RX_EN | EEE_TX_EN;
  2514. config |= EEE10_EN;
  2515. } else {
  2516. ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
  2517. config &= ~EEE10_EN;
  2518. }
  2519. ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
  2520. ocp_reg_write(tp, OCP_EEE_CFG, config);
  2521. }
  2522. static void r8153_enable_eee(struct r8152 *tp)
  2523. {
  2524. r8153_eee_en(tp, true);
  2525. ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX);
  2526. }
  2527. static void r8152b_enable_fc(struct r8152 *tp)
  2528. {
  2529. u16 anar;
  2530. anar = r8152_mdio_read(tp, MII_ADVERTISE);
  2531. anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
  2532. r8152_mdio_write(tp, MII_ADVERTISE, anar);
  2533. }
  2534. static void rtl_tally_reset(struct r8152 *tp)
  2535. {
  2536. u32 ocp_data;
  2537. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
  2538. ocp_data |= TALLY_RESET;
  2539. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
  2540. }
  2541. static void r8152b_init(struct r8152 *tp)
  2542. {
  2543. u32 ocp_data;
  2544. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  2545. return;
  2546. r8152b_disable_aldps(tp);
  2547. if (tp->version == RTL_VER_01) {
  2548. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
  2549. ocp_data &= ~LED_MODE_MASK;
  2550. ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
  2551. }
  2552. r8152_power_cut_en(tp, false);
  2553. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
  2554. ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
  2555. ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
  2556. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
  2557. ocp_data &= ~MCU_CLK_RATIO_MASK;
  2558. ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
  2559. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
  2560. ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
  2561. SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
  2562. ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
  2563. r8152b_enable_eee(tp);
  2564. r8152b_enable_aldps(tp);
  2565. r8152b_enable_fc(tp);
  2566. rtl_tally_reset(tp);
  2567. /* enable rx aggregation */
  2568. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
  2569. ocp_data &= ~RX_AGG_DISABLE;
  2570. ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
  2571. }
  2572. static void r8153_init(struct r8152 *tp)
  2573. {
  2574. u32 ocp_data;
  2575. int i;
  2576. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  2577. return;
  2578. r8153_disable_aldps(tp);
  2579. r8153_u1u2en(tp, false);
  2580. for (i = 0; i < 500; i++) {
  2581. if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
  2582. AUTOLOAD_DONE)
  2583. break;
  2584. msleep(20);
  2585. }
  2586. for (i = 0; i < 500; i++) {
  2587. ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK;
  2588. if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN)
  2589. break;
  2590. msleep(20);
  2591. }
  2592. r8153_u2p3en(tp, false);
  2593. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
  2594. ocp_data &= ~TIMER11_EN;
  2595. ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
  2596. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
  2597. ocp_data &= ~LED_MODE_MASK;
  2598. ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
  2599. ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL);
  2600. ocp_data &= ~LPM_TIMER_MASK;
  2601. if (tp->version == RTL_VER_04 && tp->udev->speed != USB_SPEED_SUPER)
  2602. ocp_data |= LPM_TIMER_500MS;
  2603. else
  2604. ocp_data |= LPM_TIMER_500US;
  2605. ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
  2606. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
  2607. ocp_data &= ~SEN_VAL_MASK;
  2608. ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
  2609. ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
  2610. r8153_power_cut_en(tp, false);
  2611. r8153_u1u2en(tp, true);
  2612. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ALDPS_SPDWN_RATIO);
  2613. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, EEE_SPDWN_RATIO);
  2614. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3,
  2615. PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN |
  2616. U1U2_SPDWN_EN | L1_SPDWN_EN);
  2617. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4,
  2618. PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN |
  2619. TP100_SPDWN_EN | TP500_SPDWN_EN | TP1000_SPDWN_EN |
  2620. EEE_SPDWN_EN);
  2621. r8153_enable_eee(tp);
  2622. r8153_enable_aldps(tp);
  2623. r8152b_enable_fc(tp);
  2624. rtl_tally_reset(tp);
  2625. }
  2626. static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
  2627. {
  2628. struct r8152 *tp = usb_get_intfdata(intf);
  2629. struct net_device *netdev = tp->netdev;
  2630. int ret = 0;
  2631. mutex_lock(&tp->control);
  2632. if (PMSG_IS_AUTO(message)) {
  2633. if (netif_running(netdev) && work_busy(&tp->schedule.work)) {
  2634. ret = -EBUSY;
  2635. goto out1;
  2636. }
  2637. set_bit(SELECTIVE_SUSPEND, &tp->flags);
  2638. } else {
  2639. netif_device_detach(netdev);
  2640. }
  2641. if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
  2642. clear_bit(WORK_ENABLE, &tp->flags);
  2643. usb_kill_urb(tp->intr_urb);
  2644. napi_disable(&tp->napi);
  2645. if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
  2646. rtl_stop_rx(tp);
  2647. rtl_runtime_suspend_enable(tp, true);
  2648. } else {
  2649. cancel_delayed_work_sync(&tp->schedule);
  2650. tp->rtl_ops.down(tp);
  2651. }
  2652. napi_enable(&tp->napi);
  2653. }
  2654. out1:
  2655. mutex_unlock(&tp->control);
  2656. return ret;
  2657. }
  2658. static int rtl8152_resume(struct usb_interface *intf)
  2659. {
  2660. struct r8152 *tp = usb_get_intfdata(intf);
  2661. mutex_lock(&tp->control);
  2662. if (!test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
  2663. tp->rtl_ops.init(tp);
  2664. netif_device_attach(tp->netdev);
  2665. }
  2666. if (netif_running(tp->netdev)) {
  2667. if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
  2668. rtl_runtime_suspend_enable(tp, false);
  2669. clear_bit(SELECTIVE_SUSPEND, &tp->flags);
  2670. set_bit(WORK_ENABLE, &tp->flags);
  2671. if (netif_carrier_ok(tp->netdev))
  2672. rtl_start_rx(tp);
  2673. } else {
  2674. tp->rtl_ops.up(tp);
  2675. rtl8152_set_speed(tp, AUTONEG_ENABLE,
  2676. tp->mii.supports_gmii ?
  2677. SPEED_1000 : SPEED_100,
  2678. DUPLEX_FULL);
  2679. netif_carrier_off(tp->netdev);
  2680. set_bit(WORK_ENABLE, &tp->flags);
  2681. }
  2682. usb_submit_urb(tp->intr_urb, GFP_KERNEL);
  2683. } else if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
  2684. clear_bit(SELECTIVE_SUSPEND, &tp->flags);
  2685. }
  2686. mutex_unlock(&tp->control);
  2687. return 0;
  2688. }
  2689. static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  2690. {
  2691. struct r8152 *tp = netdev_priv(dev);
  2692. if (usb_autopm_get_interface(tp->intf) < 0)
  2693. return;
  2694. mutex_lock(&tp->control);
  2695. wol->supported = WAKE_ANY;
  2696. wol->wolopts = __rtl_get_wol(tp);
  2697. mutex_unlock(&tp->control);
  2698. usb_autopm_put_interface(tp->intf);
  2699. }
  2700. static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  2701. {
  2702. struct r8152 *tp = netdev_priv(dev);
  2703. int ret;
  2704. ret = usb_autopm_get_interface(tp->intf);
  2705. if (ret < 0)
  2706. goto out_set_wol;
  2707. mutex_lock(&tp->control);
  2708. __rtl_set_wol(tp, wol->wolopts);
  2709. tp->saved_wolopts = wol->wolopts & WAKE_ANY;
  2710. mutex_unlock(&tp->control);
  2711. usb_autopm_put_interface(tp->intf);
  2712. out_set_wol:
  2713. return ret;
  2714. }
  2715. static u32 rtl8152_get_msglevel(struct net_device *dev)
  2716. {
  2717. struct r8152 *tp = netdev_priv(dev);
  2718. return tp->msg_enable;
  2719. }
  2720. static void rtl8152_set_msglevel(struct net_device *dev, u32 value)
  2721. {
  2722. struct r8152 *tp = netdev_priv(dev);
  2723. tp->msg_enable = value;
  2724. }
  2725. static void rtl8152_get_drvinfo(struct net_device *netdev,
  2726. struct ethtool_drvinfo *info)
  2727. {
  2728. struct r8152 *tp = netdev_priv(netdev);
  2729. strlcpy(info->driver, MODULENAME, sizeof(info->driver));
  2730. strlcpy(info->version, DRIVER_VERSION, sizeof(info->version));
  2731. usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
  2732. }
  2733. static
  2734. int rtl8152_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
  2735. {
  2736. struct r8152 *tp = netdev_priv(netdev);
  2737. int ret;
  2738. if (!tp->mii.mdio_read)
  2739. return -EOPNOTSUPP;
  2740. ret = usb_autopm_get_interface(tp->intf);
  2741. if (ret < 0)
  2742. goto out;
  2743. mutex_lock(&tp->control);
  2744. ret = mii_ethtool_gset(&tp->mii, cmd);
  2745. mutex_unlock(&tp->control);
  2746. usb_autopm_put_interface(tp->intf);
  2747. out:
  2748. return ret;
  2749. }
  2750. static int rtl8152_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  2751. {
  2752. struct r8152 *tp = netdev_priv(dev);
  2753. int ret;
  2754. ret = usb_autopm_get_interface(tp->intf);
  2755. if (ret < 0)
  2756. goto out;
  2757. mutex_lock(&tp->control);
  2758. ret = rtl8152_set_speed(tp, cmd->autoneg, cmd->speed, cmd->duplex);
  2759. mutex_unlock(&tp->control);
  2760. usb_autopm_put_interface(tp->intf);
  2761. out:
  2762. return ret;
  2763. }
  2764. static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = {
  2765. "tx_packets",
  2766. "rx_packets",
  2767. "tx_errors",
  2768. "rx_errors",
  2769. "rx_missed",
  2770. "align_errors",
  2771. "tx_single_collisions",
  2772. "tx_multi_collisions",
  2773. "rx_unicast",
  2774. "rx_broadcast",
  2775. "rx_multicast",
  2776. "tx_aborted",
  2777. "tx_underrun",
  2778. };
  2779. static int rtl8152_get_sset_count(struct net_device *dev, int sset)
  2780. {
  2781. switch (sset) {
  2782. case ETH_SS_STATS:
  2783. return ARRAY_SIZE(rtl8152_gstrings);
  2784. default:
  2785. return -EOPNOTSUPP;
  2786. }
  2787. }
  2788. static void rtl8152_get_ethtool_stats(struct net_device *dev,
  2789. struct ethtool_stats *stats, u64 *data)
  2790. {
  2791. struct r8152 *tp = netdev_priv(dev);
  2792. struct tally_counter tally;
  2793. if (usb_autopm_get_interface(tp->intf) < 0)
  2794. return;
  2795. generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA);
  2796. usb_autopm_put_interface(tp->intf);
  2797. data[0] = le64_to_cpu(tally.tx_packets);
  2798. data[1] = le64_to_cpu(tally.rx_packets);
  2799. data[2] = le64_to_cpu(tally.tx_errors);
  2800. data[3] = le32_to_cpu(tally.rx_errors);
  2801. data[4] = le16_to_cpu(tally.rx_missed);
  2802. data[5] = le16_to_cpu(tally.align_errors);
  2803. data[6] = le32_to_cpu(tally.tx_one_collision);
  2804. data[7] = le32_to_cpu(tally.tx_multi_collision);
  2805. data[8] = le64_to_cpu(tally.rx_unicast);
  2806. data[9] = le64_to_cpu(tally.rx_broadcast);
  2807. data[10] = le32_to_cpu(tally.rx_multicast);
  2808. data[11] = le16_to_cpu(tally.tx_aborted);
  2809. data[12] = le16_to_cpu(tally.tx_underrun);
  2810. }
  2811. static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data)
  2812. {
  2813. switch (stringset) {
  2814. case ETH_SS_STATS:
  2815. memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings));
  2816. break;
  2817. }
  2818. }
  2819. static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
  2820. {
  2821. u32 ocp_data, lp, adv, supported = 0;
  2822. u16 val;
  2823. val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
  2824. supported = mmd_eee_cap_to_ethtool_sup_t(val);
  2825. val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
  2826. adv = mmd_eee_adv_to_ethtool_adv_t(val);
  2827. val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
  2828. lp = mmd_eee_adv_to_ethtool_adv_t(val);
  2829. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
  2830. ocp_data &= EEE_RX_EN | EEE_TX_EN;
  2831. eee->eee_enabled = !!ocp_data;
  2832. eee->eee_active = !!(supported & adv & lp);
  2833. eee->supported = supported;
  2834. eee->advertised = adv;
  2835. eee->lp_advertised = lp;
  2836. return 0;
  2837. }
  2838. static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
  2839. {
  2840. u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
  2841. r8152_eee_en(tp, eee->eee_enabled);
  2842. if (!eee->eee_enabled)
  2843. val = 0;
  2844. r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
  2845. return 0;
  2846. }
  2847. static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
  2848. {
  2849. u32 ocp_data, lp, adv, supported = 0;
  2850. u16 val;
  2851. val = ocp_reg_read(tp, OCP_EEE_ABLE);
  2852. supported = mmd_eee_cap_to_ethtool_sup_t(val);
  2853. val = ocp_reg_read(tp, OCP_EEE_ADV);
  2854. adv = mmd_eee_adv_to_ethtool_adv_t(val);
  2855. val = ocp_reg_read(tp, OCP_EEE_LPABLE);
  2856. lp = mmd_eee_adv_to_ethtool_adv_t(val);
  2857. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
  2858. ocp_data &= EEE_RX_EN | EEE_TX_EN;
  2859. eee->eee_enabled = !!ocp_data;
  2860. eee->eee_active = !!(supported & adv & lp);
  2861. eee->supported = supported;
  2862. eee->advertised = adv;
  2863. eee->lp_advertised = lp;
  2864. return 0;
  2865. }
  2866. static int r8153_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
  2867. {
  2868. u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
  2869. r8153_eee_en(tp, eee->eee_enabled);
  2870. if (!eee->eee_enabled)
  2871. val = 0;
  2872. ocp_reg_write(tp, OCP_EEE_ADV, val);
  2873. return 0;
  2874. }
  2875. static int
  2876. rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata)
  2877. {
  2878. struct r8152 *tp = netdev_priv(net);
  2879. int ret;
  2880. ret = usb_autopm_get_interface(tp->intf);
  2881. if (ret < 0)
  2882. goto out;
  2883. mutex_lock(&tp->control);
  2884. ret = tp->rtl_ops.eee_get(tp, edata);
  2885. mutex_unlock(&tp->control);
  2886. usb_autopm_put_interface(tp->intf);
  2887. out:
  2888. return ret;
  2889. }
  2890. static int
  2891. rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata)
  2892. {
  2893. struct r8152 *tp = netdev_priv(net);
  2894. int ret;
  2895. ret = usb_autopm_get_interface(tp->intf);
  2896. if (ret < 0)
  2897. goto out;
  2898. mutex_lock(&tp->control);
  2899. ret = tp->rtl_ops.eee_set(tp, edata);
  2900. if (!ret)
  2901. ret = mii_nway_restart(&tp->mii);
  2902. mutex_unlock(&tp->control);
  2903. usb_autopm_put_interface(tp->intf);
  2904. out:
  2905. return ret;
  2906. }
  2907. static int rtl8152_nway_reset(struct net_device *dev)
  2908. {
  2909. struct r8152 *tp = netdev_priv(dev);
  2910. int ret;
  2911. ret = usb_autopm_get_interface(tp->intf);
  2912. if (ret < 0)
  2913. goto out;
  2914. mutex_lock(&tp->control);
  2915. ret = mii_nway_restart(&tp->mii);
  2916. mutex_unlock(&tp->control);
  2917. usb_autopm_put_interface(tp->intf);
  2918. out:
  2919. return ret;
  2920. }
  2921. static struct ethtool_ops ops = {
  2922. .get_drvinfo = rtl8152_get_drvinfo,
  2923. .get_settings = rtl8152_get_settings,
  2924. .set_settings = rtl8152_set_settings,
  2925. .get_link = ethtool_op_get_link,
  2926. .nway_reset = rtl8152_nway_reset,
  2927. .get_msglevel = rtl8152_get_msglevel,
  2928. .set_msglevel = rtl8152_set_msglevel,
  2929. .get_wol = rtl8152_get_wol,
  2930. .set_wol = rtl8152_set_wol,
  2931. .get_strings = rtl8152_get_strings,
  2932. .get_sset_count = rtl8152_get_sset_count,
  2933. .get_ethtool_stats = rtl8152_get_ethtool_stats,
  2934. .get_eee = rtl_ethtool_get_eee,
  2935. .set_eee = rtl_ethtool_set_eee,
  2936. };
  2937. static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
  2938. {
  2939. struct r8152 *tp = netdev_priv(netdev);
  2940. struct mii_ioctl_data *data = if_mii(rq);
  2941. int res;
  2942. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  2943. return -ENODEV;
  2944. res = usb_autopm_get_interface(tp->intf);
  2945. if (res < 0)
  2946. goto out;
  2947. switch (cmd) {
  2948. case SIOCGMIIPHY:
  2949. data->phy_id = R8152_PHY_ID; /* Internal PHY */
  2950. break;
  2951. case SIOCGMIIREG:
  2952. mutex_lock(&tp->control);
  2953. data->val_out = r8152_mdio_read(tp, data->reg_num);
  2954. mutex_unlock(&tp->control);
  2955. break;
  2956. case SIOCSMIIREG:
  2957. if (!capable(CAP_NET_ADMIN)) {
  2958. res = -EPERM;
  2959. break;
  2960. }
  2961. mutex_lock(&tp->control);
  2962. r8152_mdio_write(tp, data->reg_num, data->val_in);
  2963. mutex_unlock(&tp->control);
  2964. break;
  2965. default:
  2966. res = -EOPNOTSUPP;
  2967. }
  2968. usb_autopm_put_interface(tp->intf);
  2969. out:
  2970. return res;
  2971. }
  2972. static int rtl8152_change_mtu(struct net_device *dev, int new_mtu)
  2973. {
  2974. struct r8152 *tp = netdev_priv(dev);
  2975. switch (tp->version) {
  2976. case RTL_VER_01:
  2977. case RTL_VER_02:
  2978. return eth_change_mtu(dev, new_mtu);
  2979. default:
  2980. break;
  2981. }
  2982. if (new_mtu < 68 || new_mtu > RTL8153_MAX_MTU)
  2983. return -EINVAL;
  2984. dev->mtu = new_mtu;
  2985. return 0;
  2986. }
  2987. static const struct net_device_ops rtl8152_netdev_ops = {
  2988. .ndo_open = rtl8152_open,
  2989. .ndo_stop = rtl8152_close,
  2990. .ndo_do_ioctl = rtl8152_ioctl,
  2991. .ndo_start_xmit = rtl8152_start_xmit,
  2992. .ndo_tx_timeout = rtl8152_tx_timeout,
  2993. .ndo_set_features = rtl8152_set_features,
  2994. .ndo_set_rx_mode = rtl8152_set_rx_mode,
  2995. .ndo_set_mac_address = rtl8152_set_mac_address,
  2996. .ndo_change_mtu = rtl8152_change_mtu,
  2997. .ndo_validate_addr = eth_validate_addr,
  2998. .ndo_features_check = rtl8152_features_check,
  2999. };
  3000. static void r8152b_get_version(struct r8152 *tp)
  3001. {
  3002. u32 ocp_data;
  3003. u16 version;
  3004. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1);
  3005. version = (u16)(ocp_data & VERSION_MASK);
  3006. switch (version) {
  3007. case 0x4c00:
  3008. tp->version = RTL_VER_01;
  3009. break;
  3010. case 0x4c10:
  3011. tp->version = RTL_VER_02;
  3012. break;
  3013. case 0x5c00:
  3014. tp->version = RTL_VER_03;
  3015. tp->mii.supports_gmii = 1;
  3016. break;
  3017. case 0x5c10:
  3018. tp->version = RTL_VER_04;
  3019. tp->mii.supports_gmii = 1;
  3020. break;
  3021. case 0x5c20:
  3022. tp->version = RTL_VER_05;
  3023. tp->mii.supports_gmii = 1;
  3024. break;
  3025. default:
  3026. netif_info(tp, probe, tp->netdev,
  3027. "Unknown version 0x%04x\n", version);
  3028. break;
  3029. }
  3030. }
  3031. static void rtl8152_unload(struct r8152 *tp)
  3032. {
  3033. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  3034. return;
  3035. if (tp->version != RTL_VER_01)
  3036. r8152_power_cut_en(tp, true);
  3037. }
  3038. static void rtl8153_unload(struct r8152 *tp)
  3039. {
  3040. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  3041. return;
  3042. r8153_power_cut_en(tp, false);
  3043. }
  3044. static int rtl_ops_init(struct r8152 *tp)
  3045. {
  3046. struct rtl_ops *ops = &tp->rtl_ops;
  3047. int ret = 0;
  3048. switch (tp->version) {
  3049. case RTL_VER_01:
  3050. case RTL_VER_02:
  3051. ops->init = r8152b_init;
  3052. ops->enable = rtl8152_enable;
  3053. ops->disable = rtl8152_disable;
  3054. ops->up = rtl8152_up;
  3055. ops->down = rtl8152_down;
  3056. ops->unload = rtl8152_unload;
  3057. ops->eee_get = r8152_get_eee;
  3058. ops->eee_set = r8152_set_eee;
  3059. break;
  3060. case RTL_VER_03:
  3061. case RTL_VER_04:
  3062. case RTL_VER_05:
  3063. ops->init = r8153_init;
  3064. ops->enable = rtl8153_enable;
  3065. ops->disable = rtl8153_disable;
  3066. ops->up = rtl8153_up;
  3067. ops->down = rtl8153_down;
  3068. ops->unload = rtl8153_unload;
  3069. ops->eee_get = r8153_get_eee;
  3070. ops->eee_set = r8153_set_eee;
  3071. break;
  3072. default:
  3073. ret = -ENODEV;
  3074. netif_err(tp, probe, tp->netdev, "Unknown Device\n");
  3075. break;
  3076. }
  3077. return ret;
  3078. }
  3079. static int rtl8152_probe(struct usb_interface *intf,
  3080. const struct usb_device_id *id)
  3081. {
  3082. struct usb_device *udev = interface_to_usbdev(intf);
  3083. struct r8152 *tp;
  3084. struct net_device *netdev;
  3085. int ret;
  3086. if (udev->actconfig->desc.bConfigurationValue != 1) {
  3087. usb_driver_set_configuration(udev, 1);
  3088. return -ENODEV;
  3089. }
  3090. usb_reset_device(udev);
  3091. netdev = alloc_etherdev(sizeof(struct r8152));
  3092. if (!netdev) {
  3093. dev_err(&intf->dev, "Out of memory\n");
  3094. return -ENOMEM;
  3095. }
  3096. SET_NETDEV_DEV(netdev, &intf->dev);
  3097. tp = netdev_priv(netdev);
  3098. tp->msg_enable = 0x7FFF;
  3099. tp->udev = udev;
  3100. tp->netdev = netdev;
  3101. tp->intf = intf;
  3102. r8152b_get_version(tp);
  3103. ret = rtl_ops_init(tp);
  3104. if (ret)
  3105. goto out;
  3106. mutex_init(&tp->control);
  3107. INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
  3108. netdev->netdev_ops = &rtl8152_netdev_ops;
  3109. netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
  3110. netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
  3111. NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM |
  3112. NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX |
  3113. NETIF_F_HW_VLAN_CTAG_TX;
  3114. netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
  3115. NETIF_F_TSO | NETIF_F_FRAGLIST |
  3116. NETIF_F_IPV6_CSUM | NETIF_F_TSO6 |
  3117. NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX;
  3118. netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
  3119. NETIF_F_HIGHDMA | NETIF_F_FRAGLIST |
  3120. NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
  3121. netdev->ethtool_ops = &ops;
  3122. netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE);
  3123. tp->mii.dev = netdev;
  3124. tp->mii.mdio_read = read_mii_word;
  3125. tp->mii.mdio_write = write_mii_word;
  3126. tp->mii.phy_id_mask = 0x3f;
  3127. tp->mii.reg_num_mask = 0x1f;
  3128. tp->mii.phy_id = R8152_PHY_ID;
  3129. intf->needs_remote_wakeup = 1;
  3130. tp->rtl_ops.init(tp);
  3131. set_ethernet_addr(tp);
  3132. usb_set_intfdata(intf, tp);
  3133. netif_napi_add(netdev, &tp->napi, r8152_poll, RTL8152_NAPI_WEIGHT);
  3134. ret = register_netdev(netdev);
  3135. if (ret != 0) {
  3136. netif_err(tp, probe, netdev, "couldn't register the device\n");
  3137. goto out1;
  3138. }
  3139. tp->saved_wolopts = __rtl_get_wol(tp);
  3140. if (tp->saved_wolopts)
  3141. device_set_wakeup_enable(&udev->dev, true);
  3142. else
  3143. device_set_wakeup_enable(&udev->dev, false);
  3144. netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
  3145. return 0;
  3146. out1:
  3147. netif_napi_del(&tp->napi);
  3148. usb_set_intfdata(intf, NULL);
  3149. out:
  3150. free_netdev(netdev);
  3151. return ret;
  3152. }
  3153. static void rtl8152_disconnect(struct usb_interface *intf)
  3154. {
  3155. struct r8152 *tp = usb_get_intfdata(intf);
  3156. usb_set_intfdata(intf, NULL);
  3157. if (tp) {
  3158. struct usb_device *udev = tp->udev;
  3159. if (udev->state == USB_STATE_NOTATTACHED)
  3160. set_bit(RTL8152_UNPLUG, &tp->flags);
  3161. netif_napi_del(&tp->napi);
  3162. unregister_netdev(tp->netdev);
  3163. tp->rtl_ops.unload(tp);
  3164. free_netdev(tp->netdev);
  3165. }
  3166. }
  3167. #define REALTEK_USB_DEVICE(vend, prod) \
  3168. .match_flags = USB_DEVICE_ID_MATCH_DEVICE | \
  3169. USB_DEVICE_ID_MATCH_INT_CLASS, \
  3170. .idVendor = (vend), \
  3171. .idProduct = (prod), \
  3172. .bInterfaceClass = USB_CLASS_VENDOR_SPEC \
  3173. }, \
  3174. { \
  3175. .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | \
  3176. USB_DEVICE_ID_MATCH_DEVICE, \
  3177. .idVendor = (vend), \
  3178. .idProduct = (prod), \
  3179. .bInterfaceClass = USB_CLASS_COMM, \
  3180. .bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, \
  3181. .bInterfaceProtocol = USB_CDC_PROTO_NONE
  3182. /* table of devices that work with this driver */
  3183. static struct usb_device_id rtl8152_table[] = {
  3184. {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)},
  3185. {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)},
  3186. {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101)},
  3187. {}
  3188. };
  3189. MODULE_DEVICE_TABLE(usb, rtl8152_table);
  3190. static struct usb_driver rtl8152_driver = {
  3191. .name = MODULENAME,
  3192. .id_table = rtl8152_table,
  3193. .probe = rtl8152_probe,
  3194. .disconnect = rtl8152_disconnect,
  3195. .suspend = rtl8152_suspend,
  3196. .resume = rtl8152_resume,
  3197. .reset_resume = rtl8152_resume,
  3198. .supports_autosuspend = 1,
  3199. .disable_hub_initiated_lpm = 1,
  3200. };
  3201. module_usb_driver(rtl8152_driver);
  3202. MODULE_AUTHOR(DRIVER_AUTHOR);
  3203. MODULE_DESCRIPTION(DRIVER_DESC);
  3204. MODULE_LICENSE("GPL");