udc.c 45 KB

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  1. /*
  2. * udc.c - ChipIdea UDC driver
  3. *
  4. * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
  5. *
  6. * Author: David Lopo
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. #include <linux/delay.h>
  13. #include <linux/device.h>
  14. #include <linux/dmapool.h>
  15. #include <linux/err.h>
  16. #include <linux/irqreturn.h>
  17. #include <linux/kernel.h>
  18. #include <linux/slab.h>
  19. #include <linux/pm_runtime.h>
  20. #include <linux/usb/ch9.h>
  21. #include <linux/usb/gadget.h>
  22. #include <linux/usb/chipidea.h>
  23. #include "ci.h"
  24. #include "udc.h"
  25. #include "bits.h"
  26. #include "debug.h"
  27. #include "otg.h"
  28. /* control endpoint description */
  29. static const struct usb_endpoint_descriptor
  30. ctrl_endpt_out_desc = {
  31. .bLength = USB_DT_ENDPOINT_SIZE,
  32. .bDescriptorType = USB_DT_ENDPOINT,
  33. .bEndpointAddress = USB_DIR_OUT,
  34. .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
  35. .wMaxPacketSize = cpu_to_le16(CTRL_PAYLOAD_MAX),
  36. };
  37. static const struct usb_endpoint_descriptor
  38. ctrl_endpt_in_desc = {
  39. .bLength = USB_DT_ENDPOINT_SIZE,
  40. .bDescriptorType = USB_DT_ENDPOINT,
  41. .bEndpointAddress = USB_DIR_IN,
  42. .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
  43. .wMaxPacketSize = cpu_to_le16(CTRL_PAYLOAD_MAX),
  44. };
  45. /**
  46. * hw_ep_bit: calculates the bit number
  47. * @num: endpoint number
  48. * @dir: endpoint direction
  49. *
  50. * This function returns bit number
  51. */
  52. static inline int hw_ep_bit(int num, int dir)
  53. {
  54. return num + (dir ? 16 : 0);
  55. }
  56. static inline int ep_to_bit(struct ci_hdrc *ci, int n)
  57. {
  58. int fill = 16 - ci->hw_ep_max / 2;
  59. if (n >= ci->hw_ep_max / 2)
  60. n += fill;
  61. return n;
  62. }
  63. /**
  64. * hw_device_state: enables/disables interrupts (execute without interruption)
  65. * @dma: 0 => disable, !0 => enable and set dma engine
  66. *
  67. * This function returns an error code
  68. */
  69. static int hw_device_state(struct ci_hdrc *ci, u32 dma)
  70. {
  71. if (dma) {
  72. hw_write(ci, OP_ENDPTLISTADDR, ~0, dma);
  73. /* interrupt, error, port change, reset, sleep/suspend */
  74. hw_write(ci, OP_USBINTR, ~0,
  75. USBi_UI|USBi_UEI|USBi_PCI|USBi_URI|USBi_SLI);
  76. hw_write(ci, OP_USBCMD, USBCMD_RS, USBCMD_RS);
  77. } else {
  78. hw_write(ci, OP_USBINTR, ~0, 0);
  79. hw_write(ci, OP_USBCMD, USBCMD_RS, 0);
  80. }
  81. return 0;
  82. }
  83. /**
  84. * hw_ep_flush: flush endpoint fifo (execute without interruption)
  85. * @num: endpoint number
  86. * @dir: endpoint direction
  87. *
  88. * This function returns an error code
  89. */
  90. static int hw_ep_flush(struct ci_hdrc *ci, int num, int dir)
  91. {
  92. int n = hw_ep_bit(num, dir);
  93. do {
  94. /* flush any pending transfer */
  95. hw_write(ci, OP_ENDPTFLUSH, ~0, BIT(n));
  96. while (hw_read(ci, OP_ENDPTFLUSH, BIT(n)))
  97. cpu_relax();
  98. } while (hw_read(ci, OP_ENDPTSTAT, BIT(n)));
  99. return 0;
  100. }
  101. /**
  102. * hw_ep_disable: disables endpoint (execute without interruption)
  103. * @num: endpoint number
  104. * @dir: endpoint direction
  105. *
  106. * This function returns an error code
  107. */
  108. static int hw_ep_disable(struct ci_hdrc *ci, int num, int dir)
  109. {
  110. hw_ep_flush(ci, num, dir);
  111. hw_write(ci, OP_ENDPTCTRL + num,
  112. dir ? ENDPTCTRL_TXE : ENDPTCTRL_RXE, 0);
  113. return 0;
  114. }
  115. /**
  116. * hw_ep_enable: enables endpoint (execute without interruption)
  117. * @num: endpoint number
  118. * @dir: endpoint direction
  119. * @type: endpoint type
  120. *
  121. * This function returns an error code
  122. */
  123. static int hw_ep_enable(struct ci_hdrc *ci, int num, int dir, int type)
  124. {
  125. u32 mask, data;
  126. if (dir) {
  127. mask = ENDPTCTRL_TXT; /* type */
  128. data = type << __ffs(mask);
  129. mask |= ENDPTCTRL_TXS; /* unstall */
  130. mask |= ENDPTCTRL_TXR; /* reset data toggle */
  131. data |= ENDPTCTRL_TXR;
  132. mask |= ENDPTCTRL_TXE; /* enable */
  133. data |= ENDPTCTRL_TXE;
  134. } else {
  135. mask = ENDPTCTRL_RXT; /* type */
  136. data = type << __ffs(mask);
  137. mask |= ENDPTCTRL_RXS; /* unstall */
  138. mask |= ENDPTCTRL_RXR; /* reset data toggle */
  139. data |= ENDPTCTRL_RXR;
  140. mask |= ENDPTCTRL_RXE; /* enable */
  141. data |= ENDPTCTRL_RXE;
  142. }
  143. hw_write(ci, OP_ENDPTCTRL + num, mask, data);
  144. return 0;
  145. }
  146. /**
  147. * hw_ep_get_halt: return endpoint halt status
  148. * @num: endpoint number
  149. * @dir: endpoint direction
  150. *
  151. * This function returns 1 if endpoint halted
  152. */
  153. static int hw_ep_get_halt(struct ci_hdrc *ci, int num, int dir)
  154. {
  155. u32 mask = dir ? ENDPTCTRL_TXS : ENDPTCTRL_RXS;
  156. return hw_read(ci, OP_ENDPTCTRL + num, mask) ? 1 : 0;
  157. }
  158. /**
  159. * hw_ep_prime: primes endpoint (execute without interruption)
  160. * @num: endpoint number
  161. * @dir: endpoint direction
  162. * @is_ctrl: true if control endpoint
  163. *
  164. * This function returns an error code
  165. */
  166. static int hw_ep_prime(struct ci_hdrc *ci, int num, int dir, int is_ctrl)
  167. {
  168. int n = hw_ep_bit(num, dir);
  169. if (is_ctrl && dir == RX && hw_read(ci, OP_ENDPTSETUPSTAT, BIT(num)))
  170. return -EAGAIN;
  171. hw_write(ci, OP_ENDPTPRIME, ~0, BIT(n));
  172. while (hw_read(ci, OP_ENDPTPRIME, BIT(n)))
  173. cpu_relax();
  174. if (is_ctrl && dir == RX && hw_read(ci, OP_ENDPTSETUPSTAT, BIT(num)))
  175. return -EAGAIN;
  176. /* status shoult be tested according with manual but it doesn't work */
  177. return 0;
  178. }
  179. /**
  180. * hw_ep_set_halt: configures ep halt & resets data toggle after clear (execute
  181. * without interruption)
  182. * @num: endpoint number
  183. * @dir: endpoint direction
  184. * @value: true => stall, false => unstall
  185. *
  186. * This function returns an error code
  187. */
  188. static int hw_ep_set_halt(struct ci_hdrc *ci, int num, int dir, int value)
  189. {
  190. if (value != 0 && value != 1)
  191. return -EINVAL;
  192. do {
  193. enum ci_hw_regs reg = OP_ENDPTCTRL + num;
  194. u32 mask_xs = dir ? ENDPTCTRL_TXS : ENDPTCTRL_RXS;
  195. u32 mask_xr = dir ? ENDPTCTRL_TXR : ENDPTCTRL_RXR;
  196. /* data toggle - reserved for EP0 but it's in ESS */
  197. hw_write(ci, reg, mask_xs|mask_xr,
  198. value ? mask_xs : mask_xr);
  199. } while (value != hw_ep_get_halt(ci, num, dir));
  200. return 0;
  201. }
  202. /**
  203. * hw_is_port_high_speed: test if port is high speed
  204. *
  205. * This function returns true if high speed port
  206. */
  207. static int hw_port_is_high_speed(struct ci_hdrc *ci)
  208. {
  209. return ci->hw_bank.lpm ? hw_read(ci, OP_DEVLC, DEVLC_PSPD) :
  210. hw_read(ci, OP_PORTSC, PORTSC_HSP);
  211. }
  212. /**
  213. * hw_read_intr_enable: returns interrupt enable register
  214. *
  215. * This function returns register data
  216. */
  217. static u32 hw_read_intr_enable(struct ci_hdrc *ci)
  218. {
  219. return hw_read(ci, OP_USBINTR, ~0);
  220. }
  221. /**
  222. * hw_read_intr_status: returns interrupt status register
  223. *
  224. * This function returns register data
  225. */
  226. static u32 hw_read_intr_status(struct ci_hdrc *ci)
  227. {
  228. return hw_read(ci, OP_USBSTS, ~0);
  229. }
  230. /**
  231. * hw_test_and_clear_complete: test & clear complete status (execute without
  232. * interruption)
  233. * @n: endpoint number
  234. *
  235. * This function returns complete status
  236. */
  237. static int hw_test_and_clear_complete(struct ci_hdrc *ci, int n)
  238. {
  239. n = ep_to_bit(ci, n);
  240. return hw_test_and_clear(ci, OP_ENDPTCOMPLETE, BIT(n));
  241. }
  242. /**
  243. * hw_test_and_clear_intr_active: test & clear active interrupts (execute
  244. * without interruption)
  245. *
  246. * This function returns active interrutps
  247. */
  248. static u32 hw_test_and_clear_intr_active(struct ci_hdrc *ci)
  249. {
  250. u32 reg = hw_read_intr_status(ci) & hw_read_intr_enable(ci);
  251. hw_write(ci, OP_USBSTS, ~0, reg);
  252. return reg;
  253. }
  254. /**
  255. * hw_test_and_clear_setup_guard: test & clear setup guard (execute without
  256. * interruption)
  257. *
  258. * This function returns guard value
  259. */
  260. static int hw_test_and_clear_setup_guard(struct ci_hdrc *ci)
  261. {
  262. return hw_test_and_write(ci, OP_USBCMD, USBCMD_SUTW, 0);
  263. }
  264. /**
  265. * hw_test_and_set_setup_guard: test & set setup guard (execute without
  266. * interruption)
  267. *
  268. * This function returns guard value
  269. */
  270. static int hw_test_and_set_setup_guard(struct ci_hdrc *ci)
  271. {
  272. return hw_test_and_write(ci, OP_USBCMD, USBCMD_SUTW, USBCMD_SUTW);
  273. }
  274. /**
  275. * hw_usb_set_address: configures USB address (execute without interruption)
  276. * @value: new USB address
  277. *
  278. * This function explicitly sets the address, without the "USBADRA" (advance)
  279. * feature, which is not supported by older versions of the controller.
  280. */
  281. static void hw_usb_set_address(struct ci_hdrc *ci, u8 value)
  282. {
  283. hw_write(ci, OP_DEVICEADDR, DEVICEADDR_USBADR,
  284. value << __ffs(DEVICEADDR_USBADR));
  285. }
  286. /**
  287. * hw_usb_reset: restart device after a bus reset (execute without
  288. * interruption)
  289. *
  290. * This function returns an error code
  291. */
  292. static int hw_usb_reset(struct ci_hdrc *ci)
  293. {
  294. hw_usb_set_address(ci, 0);
  295. /* ESS flushes only at end?!? */
  296. hw_write(ci, OP_ENDPTFLUSH, ~0, ~0);
  297. /* clear setup token semaphores */
  298. hw_write(ci, OP_ENDPTSETUPSTAT, 0, 0);
  299. /* clear complete status */
  300. hw_write(ci, OP_ENDPTCOMPLETE, 0, 0);
  301. /* wait until all bits cleared */
  302. while (hw_read(ci, OP_ENDPTPRIME, ~0))
  303. udelay(10); /* not RTOS friendly */
  304. /* reset all endpoints ? */
  305. /* reset internal status and wait for further instructions
  306. no need to verify the port reset status (ESS does it) */
  307. return 0;
  308. }
  309. /******************************************************************************
  310. * UTIL block
  311. *****************************************************************************/
  312. static int add_td_to_list(struct ci_hw_ep *hwep, struct ci_hw_req *hwreq,
  313. unsigned length)
  314. {
  315. int i;
  316. u32 temp;
  317. struct td_node *lastnode, *node = kzalloc(sizeof(struct td_node),
  318. GFP_ATOMIC);
  319. if (node == NULL)
  320. return -ENOMEM;
  321. node->ptr = dma_pool_alloc(hwep->td_pool, GFP_ATOMIC,
  322. &node->dma);
  323. if (node->ptr == NULL) {
  324. kfree(node);
  325. return -ENOMEM;
  326. }
  327. memset(node->ptr, 0, sizeof(struct ci_hw_td));
  328. node->ptr->token = cpu_to_le32(length << __ffs(TD_TOTAL_BYTES));
  329. node->ptr->token &= cpu_to_le32(TD_TOTAL_BYTES);
  330. node->ptr->token |= cpu_to_le32(TD_STATUS_ACTIVE);
  331. if (hwep->type == USB_ENDPOINT_XFER_ISOC && hwep->dir == TX) {
  332. u32 mul = hwreq->req.length / hwep->ep.maxpacket;
  333. if (hwreq->req.length == 0
  334. || hwreq->req.length % hwep->ep.maxpacket)
  335. mul++;
  336. node->ptr->token |= mul << __ffs(TD_MULTO);
  337. }
  338. temp = (u32) (hwreq->req.dma + hwreq->req.actual);
  339. if (length) {
  340. node->ptr->page[0] = cpu_to_le32(temp);
  341. for (i = 1; i < TD_PAGE_COUNT; i++) {
  342. u32 page = temp + i * CI_HDRC_PAGE_SIZE;
  343. page &= ~TD_RESERVED_MASK;
  344. node->ptr->page[i] = cpu_to_le32(page);
  345. }
  346. }
  347. hwreq->req.actual += length;
  348. if (!list_empty(&hwreq->tds)) {
  349. /* get the last entry */
  350. lastnode = list_entry(hwreq->tds.prev,
  351. struct td_node, td);
  352. lastnode->ptr->next = cpu_to_le32(node->dma);
  353. }
  354. INIT_LIST_HEAD(&node->td);
  355. list_add_tail(&node->td, &hwreq->tds);
  356. return 0;
  357. }
  358. /**
  359. * _usb_addr: calculates endpoint address from direction & number
  360. * @ep: endpoint
  361. */
  362. static inline u8 _usb_addr(struct ci_hw_ep *ep)
  363. {
  364. return ((ep->dir == TX) ? USB_ENDPOINT_DIR_MASK : 0) | ep->num;
  365. }
  366. /**
  367. * _hardware_queue: configures a request at hardware level
  368. * @gadget: gadget
  369. * @hwep: endpoint
  370. *
  371. * This function returns an error code
  372. */
  373. static int _hardware_enqueue(struct ci_hw_ep *hwep, struct ci_hw_req *hwreq)
  374. {
  375. struct ci_hdrc *ci = hwep->ci;
  376. int ret = 0;
  377. unsigned rest = hwreq->req.length;
  378. int pages = TD_PAGE_COUNT;
  379. struct td_node *firstnode, *lastnode;
  380. /* don't queue twice */
  381. if (hwreq->req.status == -EALREADY)
  382. return -EALREADY;
  383. hwreq->req.status = -EALREADY;
  384. ret = usb_gadget_map_request(&ci->gadget, &hwreq->req, hwep->dir);
  385. if (ret)
  386. return ret;
  387. /*
  388. * The first buffer could be not page aligned.
  389. * In that case we have to span into one extra td.
  390. */
  391. if (hwreq->req.dma % PAGE_SIZE)
  392. pages--;
  393. if (rest == 0)
  394. add_td_to_list(hwep, hwreq, 0);
  395. while (rest > 0) {
  396. unsigned count = min(hwreq->req.length - hwreq->req.actual,
  397. (unsigned)(pages * CI_HDRC_PAGE_SIZE));
  398. add_td_to_list(hwep, hwreq, count);
  399. rest -= count;
  400. }
  401. if (hwreq->req.zero && hwreq->req.length
  402. && (hwreq->req.length % hwep->ep.maxpacket == 0))
  403. add_td_to_list(hwep, hwreq, 0);
  404. firstnode = list_first_entry(&hwreq->tds, struct td_node, td);
  405. lastnode = list_entry(hwreq->tds.prev,
  406. struct td_node, td);
  407. lastnode->ptr->next = cpu_to_le32(TD_TERMINATE);
  408. if (!hwreq->req.no_interrupt)
  409. lastnode->ptr->token |= cpu_to_le32(TD_IOC);
  410. wmb();
  411. hwreq->req.actual = 0;
  412. if (!list_empty(&hwep->qh.queue)) {
  413. struct ci_hw_req *hwreqprev;
  414. int n = hw_ep_bit(hwep->num, hwep->dir);
  415. int tmp_stat;
  416. struct td_node *prevlastnode;
  417. u32 next = firstnode->dma & TD_ADDR_MASK;
  418. hwreqprev = list_entry(hwep->qh.queue.prev,
  419. struct ci_hw_req, queue);
  420. prevlastnode = list_entry(hwreqprev->tds.prev,
  421. struct td_node, td);
  422. prevlastnode->ptr->next = cpu_to_le32(next);
  423. wmb();
  424. if (hw_read(ci, OP_ENDPTPRIME, BIT(n)))
  425. goto done;
  426. do {
  427. hw_write(ci, OP_USBCMD, USBCMD_ATDTW, USBCMD_ATDTW);
  428. tmp_stat = hw_read(ci, OP_ENDPTSTAT, BIT(n));
  429. } while (!hw_read(ci, OP_USBCMD, USBCMD_ATDTW));
  430. hw_write(ci, OP_USBCMD, USBCMD_ATDTW, 0);
  431. if (tmp_stat)
  432. goto done;
  433. }
  434. /* QH configuration */
  435. hwep->qh.ptr->td.next = cpu_to_le32(firstnode->dma);
  436. hwep->qh.ptr->td.token &=
  437. cpu_to_le32(~(TD_STATUS_HALTED|TD_STATUS_ACTIVE));
  438. if (hwep->type == USB_ENDPOINT_XFER_ISOC && hwep->dir == RX) {
  439. u32 mul = hwreq->req.length / hwep->ep.maxpacket;
  440. if (hwreq->req.length == 0
  441. || hwreq->req.length % hwep->ep.maxpacket)
  442. mul++;
  443. hwep->qh.ptr->cap |= mul << __ffs(QH_MULT);
  444. }
  445. wmb(); /* synchronize before ep prime */
  446. ret = hw_ep_prime(ci, hwep->num, hwep->dir,
  447. hwep->type == USB_ENDPOINT_XFER_CONTROL);
  448. done:
  449. return ret;
  450. }
  451. /*
  452. * free_pending_td: remove a pending request for the endpoint
  453. * @hwep: endpoint
  454. */
  455. static void free_pending_td(struct ci_hw_ep *hwep)
  456. {
  457. struct td_node *pending = hwep->pending_td;
  458. dma_pool_free(hwep->td_pool, pending->ptr, pending->dma);
  459. hwep->pending_td = NULL;
  460. kfree(pending);
  461. }
  462. /**
  463. * _hardware_dequeue: handles a request at hardware level
  464. * @gadget: gadget
  465. * @hwep: endpoint
  466. *
  467. * This function returns an error code
  468. */
  469. static int _hardware_dequeue(struct ci_hw_ep *hwep, struct ci_hw_req *hwreq)
  470. {
  471. u32 tmptoken;
  472. struct td_node *node, *tmpnode;
  473. unsigned remaining_length;
  474. unsigned actual = hwreq->req.length;
  475. if (hwreq->req.status != -EALREADY)
  476. return -EINVAL;
  477. hwreq->req.status = 0;
  478. list_for_each_entry_safe(node, tmpnode, &hwreq->tds, td) {
  479. tmptoken = le32_to_cpu(node->ptr->token);
  480. if ((TD_STATUS_ACTIVE & tmptoken) != 0) {
  481. hwreq->req.status = -EALREADY;
  482. return -EBUSY;
  483. }
  484. remaining_length = (tmptoken & TD_TOTAL_BYTES);
  485. remaining_length >>= __ffs(TD_TOTAL_BYTES);
  486. actual -= remaining_length;
  487. hwreq->req.status = tmptoken & TD_STATUS;
  488. if ((TD_STATUS_HALTED & hwreq->req.status)) {
  489. hwreq->req.status = -EPIPE;
  490. break;
  491. } else if ((TD_STATUS_DT_ERR & hwreq->req.status)) {
  492. hwreq->req.status = -EPROTO;
  493. break;
  494. } else if ((TD_STATUS_TR_ERR & hwreq->req.status)) {
  495. hwreq->req.status = -EILSEQ;
  496. break;
  497. }
  498. if (remaining_length) {
  499. if (hwep->dir) {
  500. hwreq->req.status = -EPROTO;
  501. break;
  502. }
  503. }
  504. /*
  505. * As the hardware could still address the freed td
  506. * which will run the udc unusable, the cleanup of the
  507. * td has to be delayed by one.
  508. */
  509. if (hwep->pending_td)
  510. free_pending_td(hwep);
  511. hwep->pending_td = node;
  512. list_del_init(&node->td);
  513. }
  514. usb_gadget_unmap_request(&hwep->ci->gadget, &hwreq->req, hwep->dir);
  515. hwreq->req.actual += actual;
  516. if (hwreq->req.status)
  517. return hwreq->req.status;
  518. return hwreq->req.actual;
  519. }
  520. /**
  521. * _ep_nuke: dequeues all endpoint requests
  522. * @hwep: endpoint
  523. *
  524. * This function returns an error code
  525. * Caller must hold lock
  526. */
  527. static int _ep_nuke(struct ci_hw_ep *hwep)
  528. __releases(hwep->lock)
  529. __acquires(hwep->lock)
  530. {
  531. struct td_node *node, *tmpnode;
  532. if (hwep == NULL)
  533. return -EINVAL;
  534. hw_ep_flush(hwep->ci, hwep->num, hwep->dir);
  535. while (!list_empty(&hwep->qh.queue)) {
  536. /* pop oldest request */
  537. struct ci_hw_req *hwreq = list_entry(hwep->qh.queue.next,
  538. struct ci_hw_req, queue);
  539. list_for_each_entry_safe(node, tmpnode, &hwreq->tds, td) {
  540. dma_pool_free(hwep->td_pool, node->ptr, node->dma);
  541. list_del_init(&node->td);
  542. node->ptr = NULL;
  543. kfree(node);
  544. }
  545. list_del_init(&hwreq->queue);
  546. hwreq->req.status = -ESHUTDOWN;
  547. if (hwreq->req.complete != NULL) {
  548. spin_unlock(hwep->lock);
  549. hwreq->req.complete(&hwep->ep, &hwreq->req);
  550. spin_lock(hwep->lock);
  551. }
  552. }
  553. if (hwep->pending_td)
  554. free_pending_td(hwep);
  555. return 0;
  556. }
  557. /**
  558. * _gadget_stop_activity: stops all USB activity, flushes & disables all endpts
  559. * @gadget: gadget
  560. *
  561. * This function returns an error code
  562. */
  563. static int _gadget_stop_activity(struct usb_gadget *gadget)
  564. {
  565. struct usb_ep *ep;
  566. struct ci_hdrc *ci = container_of(gadget, struct ci_hdrc, gadget);
  567. unsigned long flags;
  568. spin_lock_irqsave(&ci->lock, flags);
  569. ci->gadget.speed = USB_SPEED_UNKNOWN;
  570. ci->remote_wakeup = 0;
  571. ci->suspended = 0;
  572. spin_unlock_irqrestore(&ci->lock, flags);
  573. /* flush all endpoints */
  574. gadget_for_each_ep(ep, gadget) {
  575. usb_ep_fifo_flush(ep);
  576. }
  577. usb_ep_fifo_flush(&ci->ep0out->ep);
  578. usb_ep_fifo_flush(&ci->ep0in->ep);
  579. /* make sure to disable all endpoints */
  580. gadget_for_each_ep(ep, gadget) {
  581. usb_ep_disable(ep);
  582. }
  583. if (ci->status != NULL) {
  584. usb_ep_free_request(&ci->ep0in->ep, ci->status);
  585. ci->status = NULL;
  586. }
  587. return 0;
  588. }
  589. /******************************************************************************
  590. * ISR block
  591. *****************************************************************************/
  592. /**
  593. * isr_reset_handler: USB reset interrupt handler
  594. * @ci: UDC device
  595. *
  596. * This function resets USB engine after a bus reset occurred
  597. */
  598. static void isr_reset_handler(struct ci_hdrc *ci)
  599. __releases(ci->lock)
  600. __acquires(ci->lock)
  601. {
  602. int retval;
  603. spin_unlock(&ci->lock);
  604. if (ci->gadget.speed != USB_SPEED_UNKNOWN) {
  605. if (ci->driver)
  606. ci->driver->disconnect(&ci->gadget);
  607. }
  608. retval = _gadget_stop_activity(&ci->gadget);
  609. if (retval)
  610. goto done;
  611. retval = hw_usb_reset(ci);
  612. if (retval)
  613. goto done;
  614. ci->status = usb_ep_alloc_request(&ci->ep0in->ep, GFP_ATOMIC);
  615. if (ci->status == NULL)
  616. retval = -ENOMEM;
  617. done:
  618. spin_lock(&ci->lock);
  619. if (retval)
  620. dev_err(ci->dev, "error: %i\n", retval);
  621. }
  622. /**
  623. * isr_get_status_complete: get_status request complete function
  624. * @ep: endpoint
  625. * @req: request handled
  626. *
  627. * Caller must release lock
  628. */
  629. static void isr_get_status_complete(struct usb_ep *ep, struct usb_request *req)
  630. {
  631. if (ep == NULL || req == NULL)
  632. return;
  633. kfree(req->buf);
  634. usb_ep_free_request(ep, req);
  635. }
  636. /**
  637. * _ep_queue: queues (submits) an I/O request to an endpoint
  638. *
  639. * Caller must hold lock
  640. */
  641. static int _ep_queue(struct usb_ep *ep, struct usb_request *req,
  642. gfp_t __maybe_unused gfp_flags)
  643. {
  644. struct ci_hw_ep *hwep = container_of(ep, struct ci_hw_ep, ep);
  645. struct ci_hw_req *hwreq = container_of(req, struct ci_hw_req, req);
  646. struct ci_hdrc *ci = hwep->ci;
  647. int retval = 0;
  648. if (ep == NULL || req == NULL || hwep->ep.desc == NULL)
  649. return -EINVAL;
  650. if (hwep->type == USB_ENDPOINT_XFER_CONTROL) {
  651. if (req->length)
  652. hwep = (ci->ep0_dir == RX) ?
  653. ci->ep0out : ci->ep0in;
  654. if (!list_empty(&hwep->qh.queue)) {
  655. _ep_nuke(hwep);
  656. retval = -EOVERFLOW;
  657. dev_warn(hwep->ci->dev, "endpoint ctrl %X nuked\n",
  658. _usb_addr(hwep));
  659. }
  660. }
  661. if (usb_endpoint_xfer_isoc(hwep->ep.desc) &&
  662. hwreq->req.length > (1 + hwep->ep.mult) * hwep->ep.maxpacket) {
  663. dev_err(hwep->ci->dev, "request length too big for isochronous\n");
  664. return -EMSGSIZE;
  665. }
  666. /* first nuke then test link, e.g. previous status has not sent */
  667. if (!list_empty(&hwreq->queue)) {
  668. dev_err(hwep->ci->dev, "request already in queue\n");
  669. return -EBUSY;
  670. }
  671. /* push request */
  672. hwreq->req.status = -EINPROGRESS;
  673. hwreq->req.actual = 0;
  674. retval = _hardware_enqueue(hwep, hwreq);
  675. if (retval == -EALREADY)
  676. retval = 0;
  677. if (!retval)
  678. list_add_tail(&hwreq->queue, &hwep->qh.queue);
  679. return retval;
  680. }
  681. /**
  682. * isr_get_status_response: get_status request response
  683. * @ci: ci struct
  684. * @setup: setup request packet
  685. *
  686. * This function returns an error code
  687. */
  688. static int isr_get_status_response(struct ci_hdrc *ci,
  689. struct usb_ctrlrequest *setup)
  690. __releases(hwep->lock)
  691. __acquires(hwep->lock)
  692. {
  693. struct ci_hw_ep *hwep = ci->ep0in;
  694. struct usb_request *req = NULL;
  695. gfp_t gfp_flags = GFP_ATOMIC;
  696. int dir, num, retval;
  697. if (hwep == NULL || setup == NULL)
  698. return -EINVAL;
  699. spin_unlock(hwep->lock);
  700. req = usb_ep_alloc_request(&hwep->ep, gfp_flags);
  701. spin_lock(hwep->lock);
  702. if (req == NULL)
  703. return -ENOMEM;
  704. req->complete = isr_get_status_complete;
  705. req->length = 2;
  706. req->buf = kzalloc(req->length, gfp_flags);
  707. if (req->buf == NULL) {
  708. retval = -ENOMEM;
  709. goto err_free_req;
  710. }
  711. if ((setup->bRequestType & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
  712. /* Assume that device is bus powered for now. */
  713. *(u16 *)req->buf = ci->remote_wakeup << 1;
  714. retval = 0;
  715. } else if ((setup->bRequestType & USB_RECIP_MASK) \
  716. == USB_RECIP_ENDPOINT) {
  717. dir = (le16_to_cpu(setup->wIndex) & USB_ENDPOINT_DIR_MASK) ?
  718. TX : RX;
  719. num = le16_to_cpu(setup->wIndex) & USB_ENDPOINT_NUMBER_MASK;
  720. *(u16 *)req->buf = hw_ep_get_halt(ci, num, dir);
  721. }
  722. /* else do nothing; reserved for future use */
  723. retval = _ep_queue(&hwep->ep, req, gfp_flags);
  724. if (retval)
  725. goto err_free_buf;
  726. return 0;
  727. err_free_buf:
  728. kfree(req->buf);
  729. err_free_req:
  730. spin_unlock(hwep->lock);
  731. usb_ep_free_request(&hwep->ep, req);
  732. spin_lock(hwep->lock);
  733. return retval;
  734. }
  735. /**
  736. * isr_setup_status_complete: setup_status request complete function
  737. * @ep: endpoint
  738. * @req: request handled
  739. *
  740. * Caller must release lock. Put the port in test mode if test mode
  741. * feature is selected.
  742. */
  743. static void
  744. isr_setup_status_complete(struct usb_ep *ep, struct usb_request *req)
  745. {
  746. struct ci_hdrc *ci = req->context;
  747. unsigned long flags;
  748. if (ci->setaddr) {
  749. hw_usb_set_address(ci, ci->address);
  750. ci->setaddr = false;
  751. }
  752. spin_lock_irqsave(&ci->lock, flags);
  753. if (ci->test_mode)
  754. hw_port_test_set(ci, ci->test_mode);
  755. spin_unlock_irqrestore(&ci->lock, flags);
  756. }
  757. /**
  758. * isr_setup_status_phase: queues the status phase of a setup transation
  759. * @ci: ci struct
  760. *
  761. * This function returns an error code
  762. */
  763. static int isr_setup_status_phase(struct ci_hdrc *ci)
  764. {
  765. int retval;
  766. struct ci_hw_ep *hwep;
  767. hwep = (ci->ep0_dir == TX) ? ci->ep0out : ci->ep0in;
  768. ci->status->context = ci;
  769. ci->status->complete = isr_setup_status_complete;
  770. retval = _ep_queue(&hwep->ep, ci->status, GFP_ATOMIC);
  771. return retval;
  772. }
  773. /**
  774. * isr_tr_complete_low: transaction complete low level handler
  775. * @hwep: endpoint
  776. *
  777. * This function returns an error code
  778. * Caller must hold lock
  779. */
  780. static int isr_tr_complete_low(struct ci_hw_ep *hwep)
  781. __releases(hwep->lock)
  782. __acquires(hwep->lock)
  783. {
  784. struct ci_hw_req *hwreq, *hwreqtemp;
  785. struct ci_hw_ep *hweptemp = hwep;
  786. int retval = 0;
  787. list_for_each_entry_safe(hwreq, hwreqtemp, &hwep->qh.queue,
  788. queue) {
  789. retval = _hardware_dequeue(hwep, hwreq);
  790. if (retval < 0)
  791. break;
  792. list_del_init(&hwreq->queue);
  793. if (hwreq->req.complete != NULL) {
  794. spin_unlock(hwep->lock);
  795. if ((hwep->type == USB_ENDPOINT_XFER_CONTROL) &&
  796. hwreq->req.length)
  797. hweptemp = hwep->ci->ep0in;
  798. hwreq->req.complete(&hweptemp->ep, &hwreq->req);
  799. spin_lock(hwep->lock);
  800. }
  801. }
  802. if (retval == -EBUSY)
  803. retval = 0;
  804. return retval;
  805. }
  806. /**
  807. * isr_setup_packet_handler: setup packet handler
  808. * @ci: UDC descriptor
  809. *
  810. * This function handles setup packet
  811. */
  812. static void isr_setup_packet_handler(struct ci_hdrc *ci)
  813. __releases(ci->lock)
  814. __acquires(ci->lock)
  815. {
  816. struct ci_hw_ep *hwep = &ci->ci_hw_ep[0];
  817. struct usb_ctrlrequest req;
  818. int type, num, dir, err = -EINVAL;
  819. u8 tmode = 0;
  820. /*
  821. * Flush data and handshake transactions of previous
  822. * setup packet.
  823. */
  824. _ep_nuke(ci->ep0out);
  825. _ep_nuke(ci->ep0in);
  826. /* read_setup_packet */
  827. do {
  828. hw_test_and_set_setup_guard(ci);
  829. memcpy(&req, &hwep->qh.ptr->setup, sizeof(req));
  830. } while (!hw_test_and_clear_setup_guard(ci));
  831. type = req.bRequestType;
  832. ci->ep0_dir = (type & USB_DIR_IN) ? TX : RX;
  833. switch (req.bRequest) {
  834. case USB_REQ_CLEAR_FEATURE:
  835. if (type == (USB_DIR_OUT|USB_RECIP_ENDPOINT) &&
  836. le16_to_cpu(req.wValue) ==
  837. USB_ENDPOINT_HALT) {
  838. if (req.wLength != 0)
  839. break;
  840. num = le16_to_cpu(req.wIndex);
  841. dir = num & USB_ENDPOINT_DIR_MASK;
  842. num &= USB_ENDPOINT_NUMBER_MASK;
  843. if (dir) /* TX */
  844. num += ci->hw_ep_max / 2;
  845. if (!ci->ci_hw_ep[num].wedge) {
  846. spin_unlock(&ci->lock);
  847. err = usb_ep_clear_halt(
  848. &ci->ci_hw_ep[num].ep);
  849. spin_lock(&ci->lock);
  850. if (err)
  851. break;
  852. }
  853. err = isr_setup_status_phase(ci);
  854. } else if (type == (USB_DIR_OUT|USB_RECIP_DEVICE) &&
  855. le16_to_cpu(req.wValue) ==
  856. USB_DEVICE_REMOTE_WAKEUP) {
  857. if (req.wLength != 0)
  858. break;
  859. ci->remote_wakeup = 0;
  860. err = isr_setup_status_phase(ci);
  861. } else {
  862. goto delegate;
  863. }
  864. break;
  865. case USB_REQ_GET_STATUS:
  866. if (type != (USB_DIR_IN|USB_RECIP_DEVICE) &&
  867. type != (USB_DIR_IN|USB_RECIP_ENDPOINT) &&
  868. type != (USB_DIR_IN|USB_RECIP_INTERFACE))
  869. goto delegate;
  870. if (le16_to_cpu(req.wLength) != 2 ||
  871. le16_to_cpu(req.wValue) != 0)
  872. break;
  873. err = isr_get_status_response(ci, &req);
  874. break;
  875. case USB_REQ_SET_ADDRESS:
  876. if (type != (USB_DIR_OUT|USB_RECIP_DEVICE))
  877. goto delegate;
  878. if (le16_to_cpu(req.wLength) != 0 ||
  879. le16_to_cpu(req.wIndex) != 0)
  880. break;
  881. ci->address = (u8)le16_to_cpu(req.wValue);
  882. ci->setaddr = true;
  883. err = isr_setup_status_phase(ci);
  884. break;
  885. case USB_REQ_SET_FEATURE:
  886. if (type == (USB_DIR_OUT|USB_RECIP_ENDPOINT) &&
  887. le16_to_cpu(req.wValue) ==
  888. USB_ENDPOINT_HALT) {
  889. if (req.wLength != 0)
  890. break;
  891. num = le16_to_cpu(req.wIndex);
  892. dir = num & USB_ENDPOINT_DIR_MASK;
  893. num &= USB_ENDPOINT_NUMBER_MASK;
  894. if (dir) /* TX */
  895. num += ci->hw_ep_max / 2;
  896. spin_unlock(&ci->lock);
  897. err = usb_ep_set_halt(&ci->ci_hw_ep[num].ep);
  898. spin_lock(&ci->lock);
  899. if (!err)
  900. isr_setup_status_phase(ci);
  901. } else if (type == (USB_DIR_OUT|USB_RECIP_DEVICE)) {
  902. if (req.wLength != 0)
  903. break;
  904. switch (le16_to_cpu(req.wValue)) {
  905. case USB_DEVICE_REMOTE_WAKEUP:
  906. ci->remote_wakeup = 1;
  907. err = isr_setup_status_phase(ci);
  908. break;
  909. case USB_DEVICE_TEST_MODE:
  910. tmode = le16_to_cpu(req.wIndex) >> 8;
  911. switch (tmode) {
  912. case TEST_J:
  913. case TEST_K:
  914. case TEST_SE0_NAK:
  915. case TEST_PACKET:
  916. case TEST_FORCE_EN:
  917. ci->test_mode = tmode;
  918. err = isr_setup_status_phase(
  919. ci);
  920. break;
  921. default:
  922. break;
  923. }
  924. default:
  925. goto delegate;
  926. }
  927. } else {
  928. goto delegate;
  929. }
  930. break;
  931. default:
  932. delegate:
  933. if (req.wLength == 0) /* no data phase */
  934. ci->ep0_dir = TX;
  935. spin_unlock(&ci->lock);
  936. err = ci->driver->setup(&ci->gadget, &req);
  937. spin_lock(&ci->lock);
  938. break;
  939. }
  940. if (err < 0) {
  941. spin_unlock(&ci->lock);
  942. if (usb_ep_set_halt(&hwep->ep))
  943. dev_err(ci->dev, "error: ep_set_halt\n");
  944. spin_lock(&ci->lock);
  945. }
  946. }
  947. /**
  948. * isr_tr_complete_handler: transaction complete interrupt handler
  949. * @ci: UDC descriptor
  950. *
  951. * This function handles traffic events
  952. */
  953. static void isr_tr_complete_handler(struct ci_hdrc *ci)
  954. __releases(ci->lock)
  955. __acquires(ci->lock)
  956. {
  957. unsigned i;
  958. int err;
  959. for (i = 0; i < ci->hw_ep_max; i++) {
  960. struct ci_hw_ep *hwep = &ci->ci_hw_ep[i];
  961. if (hwep->ep.desc == NULL)
  962. continue; /* not configured */
  963. if (hw_test_and_clear_complete(ci, i)) {
  964. err = isr_tr_complete_low(hwep);
  965. if (hwep->type == USB_ENDPOINT_XFER_CONTROL) {
  966. if (err > 0) /* needs status phase */
  967. err = isr_setup_status_phase(ci);
  968. if (err < 0) {
  969. spin_unlock(&ci->lock);
  970. if (usb_ep_set_halt(&hwep->ep))
  971. dev_err(ci->dev,
  972. "error: ep_set_halt\n");
  973. spin_lock(&ci->lock);
  974. }
  975. }
  976. }
  977. /* Only handle setup packet below */
  978. if (i == 0 &&
  979. hw_test_and_clear(ci, OP_ENDPTSETUPSTAT, BIT(0)))
  980. isr_setup_packet_handler(ci);
  981. }
  982. }
  983. /******************************************************************************
  984. * ENDPT block
  985. *****************************************************************************/
  986. /**
  987. * ep_enable: configure endpoint, making it usable
  988. *
  989. * Check usb_ep_enable() at "usb_gadget.h" for details
  990. */
  991. static int ep_enable(struct usb_ep *ep,
  992. const struct usb_endpoint_descriptor *desc)
  993. {
  994. struct ci_hw_ep *hwep = container_of(ep, struct ci_hw_ep, ep);
  995. int retval = 0;
  996. unsigned long flags;
  997. u32 cap = 0;
  998. if (ep == NULL || desc == NULL)
  999. return -EINVAL;
  1000. spin_lock_irqsave(hwep->lock, flags);
  1001. /* only internal SW should enable ctrl endpts */
  1002. hwep->ep.desc = desc;
  1003. if (!list_empty(&hwep->qh.queue))
  1004. dev_warn(hwep->ci->dev, "enabling a non-empty endpoint!\n");
  1005. hwep->dir = usb_endpoint_dir_in(desc) ? TX : RX;
  1006. hwep->num = usb_endpoint_num(desc);
  1007. hwep->type = usb_endpoint_type(desc);
  1008. hwep->ep.maxpacket = usb_endpoint_maxp(desc) & 0x07ff;
  1009. hwep->ep.mult = QH_ISO_MULT(usb_endpoint_maxp(desc));
  1010. if (hwep->type == USB_ENDPOINT_XFER_CONTROL)
  1011. cap |= QH_IOS;
  1012. if (hwep->num)
  1013. cap |= QH_ZLT;
  1014. cap |= (hwep->ep.maxpacket << __ffs(QH_MAX_PKT)) & QH_MAX_PKT;
  1015. /*
  1016. * For ISO-TX, we set mult at QH as the largest value, and use
  1017. * MultO at TD as real mult value.
  1018. */
  1019. if (hwep->type == USB_ENDPOINT_XFER_ISOC && hwep->dir == TX)
  1020. cap |= 3 << __ffs(QH_MULT);
  1021. hwep->qh.ptr->cap = cpu_to_le32(cap);
  1022. hwep->qh.ptr->td.next |= cpu_to_le32(TD_TERMINATE); /* needed? */
  1023. if (hwep->num != 0 && hwep->type == USB_ENDPOINT_XFER_CONTROL) {
  1024. dev_err(hwep->ci->dev, "Set control xfer at non-ep0\n");
  1025. retval = -EINVAL;
  1026. }
  1027. /*
  1028. * Enable endpoints in the HW other than ep0 as ep0
  1029. * is always enabled
  1030. */
  1031. if (hwep->num)
  1032. retval |= hw_ep_enable(hwep->ci, hwep->num, hwep->dir,
  1033. hwep->type);
  1034. spin_unlock_irqrestore(hwep->lock, flags);
  1035. return retval;
  1036. }
  1037. /**
  1038. * ep_disable: endpoint is no longer usable
  1039. *
  1040. * Check usb_ep_disable() at "usb_gadget.h" for details
  1041. */
  1042. static int ep_disable(struct usb_ep *ep)
  1043. {
  1044. struct ci_hw_ep *hwep = container_of(ep, struct ci_hw_ep, ep);
  1045. int direction, retval = 0;
  1046. unsigned long flags;
  1047. if (ep == NULL)
  1048. return -EINVAL;
  1049. else if (hwep->ep.desc == NULL)
  1050. return -EBUSY;
  1051. spin_lock_irqsave(hwep->lock, flags);
  1052. /* only internal SW should disable ctrl endpts */
  1053. direction = hwep->dir;
  1054. do {
  1055. retval |= _ep_nuke(hwep);
  1056. retval |= hw_ep_disable(hwep->ci, hwep->num, hwep->dir);
  1057. if (hwep->type == USB_ENDPOINT_XFER_CONTROL)
  1058. hwep->dir = (hwep->dir == TX) ? RX : TX;
  1059. } while (hwep->dir != direction);
  1060. hwep->ep.desc = NULL;
  1061. spin_unlock_irqrestore(hwep->lock, flags);
  1062. return retval;
  1063. }
  1064. /**
  1065. * ep_alloc_request: allocate a request object to use with this endpoint
  1066. *
  1067. * Check usb_ep_alloc_request() at "usb_gadget.h" for details
  1068. */
  1069. static struct usb_request *ep_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
  1070. {
  1071. struct ci_hw_req *hwreq = NULL;
  1072. if (ep == NULL)
  1073. return NULL;
  1074. hwreq = kzalloc(sizeof(struct ci_hw_req), gfp_flags);
  1075. if (hwreq != NULL) {
  1076. INIT_LIST_HEAD(&hwreq->queue);
  1077. INIT_LIST_HEAD(&hwreq->tds);
  1078. }
  1079. return (hwreq == NULL) ? NULL : &hwreq->req;
  1080. }
  1081. /**
  1082. * ep_free_request: frees a request object
  1083. *
  1084. * Check usb_ep_free_request() at "usb_gadget.h" for details
  1085. */
  1086. static void ep_free_request(struct usb_ep *ep, struct usb_request *req)
  1087. {
  1088. struct ci_hw_ep *hwep = container_of(ep, struct ci_hw_ep, ep);
  1089. struct ci_hw_req *hwreq = container_of(req, struct ci_hw_req, req);
  1090. struct td_node *node, *tmpnode;
  1091. unsigned long flags;
  1092. if (ep == NULL || req == NULL) {
  1093. return;
  1094. } else if (!list_empty(&hwreq->queue)) {
  1095. dev_err(hwep->ci->dev, "freeing queued request\n");
  1096. return;
  1097. }
  1098. spin_lock_irqsave(hwep->lock, flags);
  1099. list_for_each_entry_safe(node, tmpnode, &hwreq->tds, td) {
  1100. dma_pool_free(hwep->td_pool, node->ptr, node->dma);
  1101. list_del_init(&node->td);
  1102. node->ptr = NULL;
  1103. kfree(node);
  1104. }
  1105. kfree(hwreq);
  1106. spin_unlock_irqrestore(hwep->lock, flags);
  1107. }
  1108. /**
  1109. * ep_queue: queues (submits) an I/O request to an endpoint
  1110. *
  1111. * Check usb_ep_queue()* at usb_gadget.h" for details
  1112. */
  1113. static int ep_queue(struct usb_ep *ep, struct usb_request *req,
  1114. gfp_t __maybe_unused gfp_flags)
  1115. {
  1116. struct ci_hw_ep *hwep = container_of(ep, struct ci_hw_ep, ep);
  1117. int retval = 0;
  1118. unsigned long flags;
  1119. if (ep == NULL || req == NULL || hwep->ep.desc == NULL)
  1120. return -EINVAL;
  1121. spin_lock_irqsave(hwep->lock, flags);
  1122. retval = _ep_queue(ep, req, gfp_flags);
  1123. spin_unlock_irqrestore(hwep->lock, flags);
  1124. return retval;
  1125. }
  1126. /**
  1127. * ep_dequeue: dequeues (cancels, unlinks) an I/O request from an endpoint
  1128. *
  1129. * Check usb_ep_dequeue() at "usb_gadget.h" for details
  1130. */
  1131. static int ep_dequeue(struct usb_ep *ep, struct usb_request *req)
  1132. {
  1133. struct ci_hw_ep *hwep = container_of(ep, struct ci_hw_ep, ep);
  1134. struct ci_hw_req *hwreq = container_of(req, struct ci_hw_req, req);
  1135. unsigned long flags;
  1136. if (ep == NULL || req == NULL || hwreq->req.status != -EALREADY ||
  1137. hwep->ep.desc == NULL || list_empty(&hwreq->queue) ||
  1138. list_empty(&hwep->qh.queue))
  1139. return -EINVAL;
  1140. spin_lock_irqsave(hwep->lock, flags);
  1141. hw_ep_flush(hwep->ci, hwep->num, hwep->dir);
  1142. /* pop request */
  1143. list_del_init(&hwreq->queue);
  1144. usb_gadget_unmap_request(&hwep->ci->gadget, req, hwep->dir);
  1145. req->status = -ECONNRESET;
  1146. if (hwreq->req.complete != NULL) {
  1147. spin_unlock(hwep->lock);
  1148. hwreq->req.complete(&hwep->ep, &hwreq->req);
  1149. spin_lock(hwep->lock);
  1150. }
  1151. spin_unlock_irqrestore(hwep->lock, flags);
  1152. return 0;
  1153. }
  1154. /**
  1155. * ep_set_halt: sets the endpoint halt feature
  1156. *
  1157. * Check usb_ep_set_halt() at "usb_gadget.h" for details
  1158. */
  1159. static int ep_set_halt(struct usb_ep *ep, int value)
  1160. {
  1161. struct ci_hw_ep *hwep = container_of(ep, struct ci_hw_ep, ep);
  1162. int direction, retval = 0;
  1163. unsigned long flags;
  1164. if (ep == NULL || hwep->ep.desc == NULL)
  1165. return -EINVAL;
  1166. if (usb_endpoint_xfer_isoc(hwep->ep.desc))
  1167. return -EOPNOTSUPP;
  1168. spin_lock_irqsave(hwep->lock, flags);
  1169. #ifndef STALL_IN
  1170. /* g_file_storage MS compliant but g_zero fails chapter 9 compliance */
  1171. if (value && hwep->type == USB_ENDPOINT_XFER_BULK && hwep->dir == TX &&
  1172. !list_empty(&hwep->qh.queue)) {
  1173. spin_unlock_irqrestore(hwep->lock, flags);
  1174. return -EAGAIN;
  1175. }
  1176. #endif
  1177. direction = hwep->dir;
  1178. do {
  1179. retval |= hw_ep_set_halt(hwep->ci, hwep->num, hwep->dir, value);
  1180. if (!value)
  1181. hwep->wedge = 0;
  1182. if (hwep->type == USB_ENDPOINT_XFER_CONTROL)
  1183. hwep->dir = (hwep->dir == TX) ? RX : TX;
  1184. } while (hwep->dir != direction);
  1185. spin_unlock_irqrestore(hwep->lock, flags);
  1186. return retval;
  1187. }
  1188. /**
  1189. * ep_set_wedge: sets the halt feature and ignores clear requests
  1190. *
  1191. * Check usb_ep_set_wedge() at "usb_gadget.h" for details
  1192. */
  1193. static int ep_set_wedge(struct usb_ep *ep)
  1194. {
  1195. struct ci_hw_ep *hwep = container_of(ep, struct ci_hw_ep, ep);
  1196. unsigned long flags;
  1197. if (ep == NULL || hwep->ep.desc == NULL)
  1198. return -EINVAL;
  1199. spin_lock_irqsave(hwep->lock, flags);
  1200. hwep->wedge = 1;
  1201. spin_unlock_irqrestore(hwep->lock, flags);
  1202. return usb_ep_set_halt(ep);
  1203. }
  1204. /**
  1205. * ep_fifo_flush: flushes contents of a fifo
  1206. *
  1207. * Check usb_ep_fifo_flush() at "usb_gadget.h" for details
  1208. */
  1209. static void ep_fifo_flush(struct usb_ep *ep)
  1210. {
  1211. struct ci_hw_ep *hwep = container_of(ep, struct ci_hw_ep, ep);
  1212. unsigned long flags;
  1213. if (ep == NULL) {
  1214. dev_err(hwep->ci->dev, "%02X: -EINVAL\n", _usb_addr(hwep));
  1215. return;
  1216. }
  1217. spin_lock_irqsave(hwep->lock, flags);
  1218. hw_ep_flush(hwep->ci, hwep->num, hwep->dir);
  1219. spin_unlock_irqrestore(hwep->lock, flags);
  1220. }
  1221. /**
  1222. * Endpoint-specific part of the API to the USB controller hardware
  1223. * Check "usb_gadget.h" for details
  1224. */
  1225. static const struct usb_ep_ops usb_ep_ops = {
  1226. .enable = ep_enable,
  1227. .disable = ep_disable,
  1228. .alloc_request = ep_alloc_request,
  1229. .free_request = ep_free_request,
  1230. .queue = ep_queue,
  1231. .dequeue = ep_dequeue,
  1232. .set_halt = ep_set_halt,
  1233. .set_wedge = ep_set_wedge,
  1234. .fifo_flush = ep_fifo_flush,
  1235. };
  1236. /******************************************************************************
  1237. * GADGET block
  1238. *****************************************************************************/
  1239. static int ci_udc_vbus_session(struct usb_gadget *_gadget, int is_active)
  1240. {
  1241. struct ci_hdrc *ci = container_of(_gadget, struct ci_hdrc, gadget);
  1242. unsigned long flags;
  1243. int gadget_ready = 0;
  1244. spin_lock_irqsave(&ci->lock, flags);
  1245. ci->vbus_active = is_active;
  1246. if (ci->driver)
  1247. gadget_ready = 1;
  1248. spin_unlock_irqrestore(&ci->lock, flags);
  1249. if (gadget_ready) {
  1250. if (is_active) {
  1251. pm_runtime_get_sync(&_gadget->dev);
  1252. hw_device_reset(ci, USBMODE_CM_DC);
  1253. hw_device_state(ci, ci->ep0out->qh.dma);
  1254. dev_dbg(ci->dev, "Connected to host\n");
  1255. } else {
  1256. if (ci->driver)
  1257. ci->driver->disconnect(&ci->gadget);
  1258. hw_device_state(ci, 0);
  1259. if (ci->platdata->notify_event)
  1260. ci->platdata->notify_event(ci,
  1261. CI_HDRC_CONTROLLER_STOPPED_EVENT);
  1262. _gadget_stop_activity(&ci->gadget);
  1263. pm_runtime_put_sync(&_gadget->dev);
  1264. dev_dbg(ci->dev, "Disconnected from host\n");
  1265. }
  1266. }
  1267. return 0;
  1268. }
  1269. static int ci_udc_wakeup(struct usb_gadget *_gadget)
  1270. {
  1271. struct ci_hdrc *ci = container_of(_gadget, struct ci_hdrc, gadget);
  1272. unsigned long flags;
  1273. int ret = 0;
  1274. spin_lock_irqsave(&ci->lock, flags);
  1275. if (!ci->remote_wakeup) {
  1276. ret = -EOPNOTSUPP;
  1277. goto out;
  1278. }
  1279. if (!hw_read(ci, OP_PORTSC, PORTSC_SUSP)) {
  1280. ret = -EINVAL;
  1281. goto out;
  1282. }
  1283. hw_write(ci, OP_PORTSC, PORTSC_FPR, PORTSC_FPR);
  1284. out:
  1285. spin_unlock_irqrestore(&ci->lock, flags);
  1286. return ret;
  1287. }
  1288. static int ci_udc_vbus_draw(struct usb_gadget *_gadget, unsigned ma)
  1289. {
  1290. struct ci_hdrc *ci = container_of(_gadget, struct ci_hdrc, gadget);
  1291. if (ci->transceiver)
  1292. return usb_phy_set_power(ci->transceiver, ma);
  1293. return -ENOTSUPP;
  1294. }
  1295. /* Change Data+ pullup status
  1296. * this func is used by usb_gadget_connect/disconnet
  1297. */
  1298. static int ci_udc_pullup(struct usb_gadget *_gadget, int is_on)
  1299. {
  1300. struct ci_hdrc *ci = container_of(_gadget, struct ci_hdrc, gadget);
  1301. if (!ci->vbus_active)
  1302. return -EOPNOTSUPP;
  1303. if (is_on)
  1304. hw_write(ci, OP_USBCMD, USBCMD_RS, USBCMD_RS);
  1305. else
  1306. hw_write(ci, OP_USBCMD, USBCMD_RS, 0);
  1307. return 0;
  1308. }
  1309. static int ci_udc_start(struct usb_gadget *gadget,
  1310. struct usb_gadget_driver *driver);
  1311. static int ci_udc_stop(struct usb_gadget *gadget,
  1312. struct usb_gadget_driver *driver);
  1313. /**
  1314. * Device operations part of the API to the USB controller hardware,
  1315. * which don't involve endpoints (or i/o)
  1316. * Check "usb_gadget.h" for details
  1317. */
  1318. static const struct usb_gadget_ops usb_gadget_ops = {
  1319. .vbus_session = ci_udc_vbus_session,
  1320. .wakeup = ci_udc_wakeup,
  1321. .pullup = ci_udc_pullup,
  1322. .vbus_draw = ci_udc_vbus_draw,
  1323. .udc_start = ci_udc_start,
  1324. .udc_stop = ci_udc_stop,
  1325. };
  1326. static int init_eps(struct ci_hdrc *ci)
  1327. {
  1328. int retval = 0, i, j;
  1329. for (i = 0; i < ci->hw_ep_max/2; i++)
  1330. for (j = RX; j <= TX; j++) {
  1331. int k = i + j * ci->hw_ep_max/2;
  1332. struct ci_hw_ep *hwep = &ci->ci_hw_ep[k];
  1333. scnprintf(hwep->name, sizeof(hwep->name), "ep%i%s", i,
  1334. (j == TX) ? "in" : "out");
  1335. hwep->ci = ci;
  1336. hwep->lock = &ci->lock;
  1337. hwep->td_pool = ci->td_pool;
  1338. hwep->ep.name = hwep->name;
  1339. hwep->ep.ops = &usb_ep_ops;
  1340. /*
  1341. * for ep0: maxP defined in desc, for other
  1342. * eps, maxP is set by epautoconfig() called
  1343. * by gadget layer
  1344. */
  1345. usb_ep_set_maxpacket_limit(&hwep->ep, (unsigned short)~0);
  1346. INIT_LIST_HEAD(&hwep->qh.queue);
  1347. hwep->qh.ptr = dma_pool_alloc(ci->qh_pool, GFP_KERNEL,
  1348. &hwep->qh.dma);
  1349. if (hwep->qh.ptr == NULL)
  1350. retval = -ENOMEM;
  1351. else
  1352. memset(hwep->qh.ptr, 0, sizeof(*hwep->qh.ptr));
  1353. /*
  1354. * set up shorthands for ep0 out and in endpoints,
  1355. * don't add to gadget's ep_list
  1356. */
  1357. if (i == 0) {
  1358. if (j == RX)
  1359. ci->ep0out = hwep;
  1360. else
  1361. ci->ep0in = hwep;
  1362. usb_ep_set_maxpacket_limit(&hwep->ep, CTRL_PAYLOAD_MAX);
  1363. continue;
  1364. }
  1365. list_add_tail(&hwep->ep.ep_list, &ci->gadget.ep_list);
  1366. }
  1367. return retval;
  1368. }
  1369. static void destroy_eps(struct ci_hdrc *ci)
  1370. {
  1371. int i;
  1372. for (i = 0; i < ci->hw_ep_max; i++) {
  1373. struct ci_hw_ep *hwep = &ci->ci_hw_ep[i];
  1374. if (hwep->pending_td)
  1375. free_pending_td(hwep);
  1376. dma_pool_free(ci->qh_pool, hwep->qh.ptr, hwep->qh.dma);
  1377. }
  1378. }
  1379. /**
  1380. * ci_udc_start: register a gadget driver
  1381. * @gadget: our gadget
  1382. * @driver: the driver being registered
  1383. *
  1384. * Interrupts are enabled here.
  1385. */
  1386. static int ci_udc_start(struct usb_gadget *gadget,
  1387. struct usb_gadget_driver *driver)
  1388. {
  1389. struct ci_hdrc *ci = container_of(gadget, struct ci_hdrc, gadget);
  1390. unsigned long flags;
  1391. int retval = -ENOMEM;
  1392. if (driver->disconnect == NULL)
  1393. return -EINVAL;
  1394. ci->ep0out->ep.desc = &ctrl_endpt_out_desc;
  1395. retval = usb_ep_enable(&ci->ep0out->ep);
  1396. if (retval)
  1397. return retval;
  1398. ci->ep0in->ep.desc = &ctrl_endpt_in_desc;
  1399. retval = usb_ep_enable(&ci->ep0in->ep);
  1400. if (retval)
  1401. return retval;
  1402. ci->driver = driver;
  1403. pm_runtime_get_sync(&ci->gadget.dev);
  1404. if (ci->vbus_active) {
  1405. spin_lock_irqsave(&ci->lock, flags);
  1406. hw_device_reset(ci, USBMODE_CM_DC);
  1407. } else {
  1408. pm_runtime_put_sync(&ci->gadget.dev);
  1409. return retval;
  1410. }
  1411. retval = hw_device_state(ci, ci->ep0out->qh.dma);
  1412. spin_unlock_irqrestore(&ci->lock, flags);
  1413. if (retval)
  1414. pm_runtime_put_sync(&ci->gadget.dev);
  1415. return retval;
  1416. }
  1417. /**
  1418. * ci_udc_stop: unregister a gadget driver
  1419. */
  1420. static int ci_udc_stop(struct usb_gadget *gadget,
  1421. struct usb_gadget_driver *driver)
  1422. {
  1423. struct ci_hdrc *ci = container_of(gadget, struct ci_hdrc, gadget);
  1424. unsigned long flags;
  1425. spin_lock_irqsave(&ci->lock, flags);
  1426. if (ci->vbus_active) {
  1427. hw_device_state(ci, 0);
  1428. if (ci->platdata->notify_event)
  1429. ci->platdata->notify_event(ci,
  1430. CI_HDRC_CONTROLLER_STOPPED_EVENT);
  1431. spin_unlock_irqrestore(&ci->lock, flags);
  1432. _gadget_stop_activity(&ci->gadget);
  1433. spin_lock_irqsave(&ci->lock, flags);
  1434. pm_runtime_put(&ci->gadget.dev);
  1435. }
  1436. ci->driver = NULL;
  1437. spin_unlock_irqrestore(&ci->lock, flags);
  1438. return 0;
  1439. }
  1440. /******************************************************************************
  1441. * BUS block
  1442. *****************************************************************************/
  1443. /**
  1444. * udc_irq: ci interrupt handler
  1445. *
  1446. * This function returns IRQ_HANDLED if the IRQ has been handled
  1447. * It locks access to registers
  1448. */
  1449. static irqreturn_t udc_irq(struct ci_hdrc *ci)
  1450. {
  1451. irqreturn_t retval;
  1452. u32 intr;
  1453. if (ci == NULL)
  1454. return IRQ_HANDLED;
  1455. spin_lock(&ci->lock);
  1456. if (ci->platdata->flags & CI_HDRC_REGS_SHARED) {
  1457. if (hw_read(ci, OP_USBMODE, USBMODE_CM) !=
  1458. USBMODE_CM_DC) {
  1459. spin_unlock(&ci->lock);
  1460. return IRQ_NONE;
  1461. }
  1462. }
  1463. intr = hw_test_and_clear_intr_active(ci);
  1464. if (intr) {
  1465. /* order defines priority - do NOT change it */
  1466. if (USBi_URI & intr)
  1467. isr_reset_handler(ci);
  1468. if (USBi_PCI & intr) {
  1469. ci->gadget.speed = hw_port_is_high_speed(ci) ?
  1470. USB_SPEED_HIGH : USB_SPEED_FULL;
  1471. if (ci->suspended && ci->driver->resume) {
  1472. spin_unlock(&ci->lock);
  1473. ci->driver->resume(&ci->gadget);
  1474. spin_lock(&ci->lock);
  1475. ci->suspended = 0;
  1476. }
  1477. }
  1478. if (USBi_UI & intr)
  1479. isr_tr_complete_handler(ci);
  1480. if (USBi_SLI & intr) {
  1481. if (ci->gadget.speed != USB_SPEED_UNKNOWN &&
  1482. ci->driver->suspend) {
  1483. ci->suspended = 1;
  1484. spin_unlock(&ci->lock);
  1485. ci->driver->suspend(&ci->gadget);
  1486. spin_lock(&ci->lock);
  1487. }
  1488. }
  1489. retval = IRQ_HANDLED;
  1490. } else {
  1491. retval = IRQ_NONE;
  1492. }
  1493. spin_unlock(&ci->lock);
  1494. return retval;
  1495. }
  1496. /**
  1497. * udc_start: initialize gadget role
  1498. * @ci: chipidea controller
  1499. */
  1500. static int udc_start(struct ci_hdrc *ci)
  1501. {
  1502. struct device *dev = ci->dev;
  1503. int retval = 0;
  1504. spin_lock_init(&ci->lock);
  1505. ci->gadget.ops = &usb_gadget_ops;
  1506. ci->gadget.speed = USB_SPEED_UNKNOWN;
  1507. ci->gadget.max_speed = USB_SPEED_HIGH;
  1508. ci->gadget.is_otg = 0;
  1509. ci->gadget.name = ci->platdata->name;
  1510. INIT_LIST_HEAD(&ci->gadget.ep_list);
  1511. /* alloc resources */
  1512. ci->qh_pool = dma_pool_create("ci_hw_qh", dev,
  1513. sizeof(struct ci_hw_qh),
  1514. 64, CI_HDRC_PAGE_SIZE);
  1515. if (ci->qh_pool == NULL)
  1516. return -ENOMEM;
  1517. ci->td_pool = dma_pool_create("ci_hw_td", dev,
  1518. sizeof(struct ci_hw_td),
  1519. 64, CI_HDRC_PAGE_SIZE);
  1520. if (ci->td_pool == NULL) {
  1521. retval = -ENOMEM;
  1522. goto free_qh_pool;
  1523. }
  1524. retval = init_eps(ci);
  1525. if (retval)
  1526. goto free_pools;
  1527. ci->gadget.ep0 = &ci->ep0in->ep;
  1528. retval = usb_add_gadget_udc(dev, &ci->gadget);
  1529. if (retval)
  1530. goto destroy_eps;
  1531. pm_runtime_no_callbacks(&ci->gadget.dev);
  1532. pm_runtime_enable(&ci->gadget.dev);
  1533. return retval;
  1534. destroy_eps:
  1535. destroy_eps(ci);
  1536. free_pools:
  1537. dma_pool_destroy(ci->td_pool);
  1538. free_qh_pool:
  1539. dma_pool_destroy(ci->qh_pool);
  1540. return retval;
  1541. }
  1542. /**
  1543. * ci_hdrc_gadget_destroy: parent remove must call this to remove UDC
  1544. *
  1545. * No interrupts active, the IRQ has been released
  1546. */
  1547. void ci_hdrc_gadget_destroy(struct ci_hdrc *ci)
  1548. {
  1549. if (!ci->roles[CI_ROLE_GADGET])
  1550. return;
  1551. usb_del_gadget_udc(&ci->gadget);
  1552. destroy_eps(ci);
  1553. dma_pool_destroy(ci->td_pool);
  1554. dma_pool_destroy(ci->qh_pool);
  1555. }
  1556. static int udc_id_switch_for_device(struct ci_hdrc *ci)
  1557. {
  1558. if (ci->is_otg)
  1559. /* Clear and enable BSV irq */
  1560. hw_write_otgsc(ci, OTGSC_BSVIS | OTGSC_BSVIE,
  1561. OTGSC_BSVIS | OTGSC_BSVIE);
  1562. return 0;
  1563. }
  1564. static void udc_id_switch_for_host(struct ci_hdrc *ci)
  1565. {
  1566. /*
  1567. * host doesn't care B_SESSION_VALID event
  1568. * so clear and disbale BSV irq
  1569. */
  1570. if (ci->is_otg)
  1571. hw_write_otgsc(ci, OTGSC_BSVIE | OTGSC_BSVIS, OTGSC_BSVIS);
  1572. }
  1573. /**
  1574. * ci_hdrc_gadget_init - initialize device related bits
  1575. * ci: the controller
  1576. *
  1577. * This function initializes the gadget, if the device is "device capable".
  1578. */
  1579. int ci_hdrc_gadget_init(struct ci_hdrc *ci)
  1580. {
  1581. struct ci_role_driver *rdrv;
  1582. if (!hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DC))
  1583. return -ENXIO;
  1584. rdrv = devm_kzalloc(ci->dev, sizeof(struct ci_role_driver), GFP_KERNEL);
  1585. if (!rdrv)
  1586. return -ENOMEM;
  1587. rdrv->start = udc_id_switch_for_device;
  1588. rdrv->stop = udc_id_switch_for_host;
  1589. rdrv->irq = udc_irq;
  1590. rdrv->name = "gadget";
  1591. ci->roles[CI_ROLE_GADGET] = rdrv;
  1592. return udc_start(ci);
  1593. }