ehci-fsl.c 19 KB

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  1. /*
  2. * Copyright 2005-2009 MontaVista Software, Inc.
  3. * Copyright 2008,2012 Freescale Semiconductor, Inc.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License as published by the
  7. * Free Software Foundation; either version 2 of the License, or (at your
  8. * option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  12. * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  13. * for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software Foundation,
  17. * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18. *
  19. * Ported to 834x by Randy Vinson <rvinson@mvista.com> using code provided
  20. * by Hunter Wu.
  21. * Power Management support by Dave Liu <daveliu@freescale.com>,
  22. * Jerry Huang <Chang-Ming.Huang@freescale.com> and
  23. * Anton Vorontsov <avorontsov@ru.mvista.com>.
  24. */
  25. #include <linux/kernel.h>
  26. #include <linux/types.h>
  27. #include <linux/delay.h>
  28. #include <linux/pm.h>
  29. #include <linux/err.h>
  30. #include <linux/platform_device.h>
  31. #include <linux/fsl_devices.h>
  32. #include "ehci-fsl.h"
  33. /* configure so an HC device and id are always provided */
  34. /* always called with process context; sleeping is OK */
  35. /**
  36. * usb_hcd_fsl_probe - initialize FSL-based HCDs
  37. * @drvier: Driver to be used for this HCD
  38. * @pdev: USB Host Controller being probed
  39. * Context: !in_interrupt()
  40. *
  41. * Allocates basic resources for this USB host controller.
  42. *
  43. */
  44. static int usb_hcd_fsl_probe(const struct hc_driver *driver,
  45. struct platform_device *pdev)
  46. {
  47. struct fsl_usb2_platform_data *pdata;
  48. struct usb_hcd *hcd;
  49. struct resource *res;
  50. int irq;
  51. int retval;
  52. pr_debug("initializing FSL-SOC USB Controller\n");
  53. /* Need platform data for setup */
  54. pdata = dev_get_platdata(&pdev->dev);
  55. if (!pdata) {
  56. dev_err(&pdev->dev,
  57. "No platform data for %s.\n", dev_name(&pdev->dev));
  58. return -ENODEV;
  59. }
  60. /*
  61. * This is a host mode driver, verify that we're supposed to be
  62. * in host mode.
  63. */
  64. if (!((pdata->operating_mode == FSL_USB2_DR_HOST) ||
  65. (pdata->operating_mode == FSL_USB2_MPH_HOST) ||
  66. (pdata->operating_mode == FSL_USB2_DR_OTG))) {
  67. dev_err(&pdev->dev,
  68. "Non Host Mode configured for %s. Wrong driver linked.\n",
  69. dev_name(&pdev->dev));
  70. return -ENODEV;
  71. }
  72. res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  73. if (!res) {
  74. dev_err(&pdev->dev,
  75. "Found HC with no IRQ. Check %s setup!\n",
  76. dev_name(&pdev->dev));
  77. return -ENODEV;
  78. }
  79. irq = res->start;
  80. hcd = usb_create_hcd(driver, &pdev->dev, dev_name(&pdev->dev));
  81. if (!hcd) {
  82. retval = -ENOMEM;
  83. goto err1;
  84. }
  85. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  86. if (!res) {
  87. dev_err(&pdev->dev,
  88. "Found HC with no register addr. Check %s setup!\n",
  89. dev_name(&pdev->dev));
  90. retval = -ENODEV;
  91. goto err2;
  92. }
  93. hcd->rsrc_start = res->start;
  94. hcd->rsrc_len = resource_size(res);
  95. hcd->regs = devm_ioremap_resource(&pdev->dev, res);
  96. if (IS_ERR(hcd->regs)) {
  97. retval = PTR_ERR(hcd->regs);
  98. goto err2;
  99. }
  100. pdata->regs = hcd->regs;
  101. if (pdata->power_budget)
  102. hcd->power_budget = pdata->power_budget;
  103. /*
  104. * do platform specific init: check the clock, grab/config pins, etc.
  105. */
  106. if (pdata->init && pdata->init(pdev)) {
  107. retval = -ENODEV;
  108. goto err2;
  109. }
  110. /* Enable USB controller, 83xx or 8536 */
  111. if (pdata->have_sysif_regs && pdata->controller_ver < FSL_USB_VER_1_6)
  112. setbits32(hcd->regs + FSL_SOC_USB_CTRL, 0x4);
  113. /* Don't need to set host mode here. It will be done by tdi_reset() */
  114. retval = usb_add_hcd(hcd, irq, IRQF_SHARED);
  115. if (retval != 0)
  116. goto err2;
  117. device_wakeup_enable(hcd->self.controller);
  118. #ifdef CONFIG_USB_OTG
  119. if (pdata->operating_mode == FSL_USB2_DR_OTG) {
  120. struct ehci_hcd *ehci = hcd_to_ehci(hcd);
  121. hcd->phy = usb_get_phy(USB_PHY_TYPE_USB2);
  122. dev_dbg(&pdev->dev, "hcd=0x%p ehci=0x%p, phy=0x%p\n",
  123. hcd, ehci, hcd->phy);
  124. if (!IS_ERR_OR_NULL(hcd->phy)) {
  125. retval = otg_set_host(hcd->phy->otg,
  126. &ehci_to_hcd(ehci)->self);
  127. if (retval) {
  128. usb_put_phy(hcd->phy);
  129. goto err2;
  130. }
  131. } else {
  132. dev_err(&pdev->dev, "can't find phy\n");
  133. retval = -ENODEV;
  134. goto err2;
  135. }
  136. }
  137. #endif
  138. return retval;
  139. err2:
  140. usb_put_hcd(hcd);
  141. err1:
  142. dev_err(&pdev->dev, "init %s fail, %d\n", dev_name(&pdev->dev), retval);
  143. if (pdata->exit)
  144. pdata->exit(pdev);
  145. return retval;
  146. }
  147. /* may be called without controller electrically present */
  148. /* may be called with controller, bus, and devices active */
  149. /**
  150. * usb_hcd_fsl_remove - shutdown processing for FSL-based HCDs
  151. * @dev: USB Host Controller being removed
  152. * Context: !in_interrupt()
  153. *
  154. * Reverses the effect of usb_hcd_fsl_probe().
  155. *
  156. */
  157. static void usb_hcd_fsl_remove(struct usb_hcd *hcd,
  158. struct platform_device *pdev)
  159. {
  160. struct fsl_usb2_platform_data *pdata = dev_get_platdata(&pdev->dev);
  161. if (!IS_ERR_OR_NULL(hcd->phy)) {
  162. otg_set_host(hcd->phy->otg, NULL);
  163. usb_put_phy(hcd->phy);
  164. }
  165. usb_remove_hcd(hcd);
  166. /*
  167. * do platform specific un-initialization:
  168. * release iomux pins, disable clock, etc.
  169. */
  170. if (pdata->exit)
  171. pdata->exit(pdev);
  172. usb_put_hcd(hcd);
  173. }
  174. static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
  175. enum fsl_usb2_phy_modes phy_mode,
  176. unsigned int port_offset)
  177. {
  178. u32 portsc;
  179. struct ehci_hcd *ehci = hcd_to_ehci(hcd);
  180. void __iomem *non_ehci = hcd->regs;
  181. struct device *dev = hcd->self.controller;
  182. struct fsl_usb2_platform_data *pdata = dev_get_platdata(dev);
  183. if (pdata->controller_ver < 0) {
  184. dev_warn(hcd->self.controller, "Could not get controller version\n");
  185. return -ENODEV;
  186. }
  187. portsc = ehci_readl(ehci, &ehci->regs->port_status[port_offset]);
  188. portsc &= ~(PORT_PTS_MSK | PORT_PTS_PTW);
  189. switch (phy_mode) {
  190. case FSL_USB2_PHY_ULPI:
  191. if (pdata->have_sysif_regs && pdata->controller_ver) {
  192. /* controller version 1.6 or above */
  193. clrbits32(non_ehci + FSL_SOC_USB_CTRL, UTMI_PHY_EN);
  194. setbits32(non_ehci + FSL_SOC_USB_CTRL,
  195. ULPI_PHY_CLK_SEL | USB_CTRL_USB_EN);
  196. }
  197. portsc |= PORT_PTS_ULPI;
  198. break;
  199. case FSL_USB2_PHY_SERIAL:
  200. portsc |= PORT_PTS_SERIAL;
  201. break;
  202. case FSL_USB2_PHY_UTMI_WIDE:
  203. portsc |= PORT_PTS_PTW;
  204. /* fall through */
  205. case FSL_USB2_PHY_UTMI:
  206. if (pdata->have_sysif_regs && pdata->controller_ver) {
  207. /* controller version 1.6 or above */
  208. setbits32(non_ehci + FSL_SOC_USB_CTRL, UTMI_PHY_EN);
  209. mdelay(FSL_UTMI_PHY_DLY); /* Delay for UTMI PHY CLK to
  210. become stable - 10ms*/
  211. }
  212. /* enable UTMI PHY */
  213. if (pdata->have_sysif_regs)
  214. setbits32(non_ehci + FSL_SOC_USB_CTRL,
  215. CTRL_UTMI_PHY_EN);
  216. portsc |= PORT_PTS_UTMI;
  217. break;
  218. case FSL_USB2_PHY_NONE:
  219. break;
  220. }
  221. if (pdata->have_sysif_regs && pdata->controller_ver &&
  222. (phy_mode == FSL_USB2_PHY_ULPI)) {
  223. /* check PHY_CLK_VALID to get phy clk valid */
  224. if (!(spin_event_timeout(in_be32(non_ehci + FSL_SOC_USB_CTRL) &
  225. PHY_CLK_VALID, FSL_USB_PHY_CLK_TIMEOUT, 0) ||
  226. in_be32(non_ehci + FSL_SOC_USB_PRICTRL))) {
  227. dev_warn(hcd->self.controller, "USB PHY clock invalid\n");
  228. return -EINVAL;
  229. }
  230. }
  231. ehci_writel(ehci, portsc, &ehci->regs->port_status[port_offset]);
  232. if (phy_mode != FSL_USB2_PHY_ULPI && pdata->have_sysif_regs)
  233. setbits32(non_ehci + FSL_SOC_USB_CTRL, USB_CTRL_USB_EN);
  234. return 0;
  235. }
  236. static int ehci_fsl_usb_setup(struct ehci_hcd *ehci)
  237. {
  238. struct usb_hcd *hcd = ehci_to_hcd(ehci);
  239. struct fsl_usb2_platform_data *pdata;
  240. void __iomem *non_ehci = hcd->regs;
  241. pdata = dev_get_platdata(hcd->self.controller);
  242. if (pdata->have_sysif_regs) {
  243. /*
  244. * Turn on cache snooping hardware, since some PowerPC platforms
  245. * wholly rely on hardware to deal with cache coherent
  246. */
  247. /* Setup Snooping for all the 4GB space */
  248. /* SNOOP1 starts from 0x0, size 2G */
  249. out_be32(non_ehci + FSL_SOC_USB_SNOOP1, 0x0 | SNOOP_SIZE_2GB);
  250. /* SNOOP2 starts from 0x80000000, size 2G */
  251. out_be32(non_ehci + FSL_SOC_USB_SNOOP2, 0x80000000 | SNOOP_SIZE_2GB);
  252. }
  253. if ((pdata->operating_mode == FSL_USB2_DR_HOST) ||
  254. (pdata->operating_mode == FSL_USB2_DR_OTG))
  255. if (ehci_fsl_setup_phy(hcd, pdata->phy_mode, 0))
  256. return -EINVAL;
  257. if (pdata->operating_mode == FSL_USB2_MPH_HOST) {
  258. unsigned int chip, rev, svr;
  259. svr = mfspr(SPRN_SVR);
  260. chip = svr >> 16;
  261. rev = (svr >> 4) & 0xf;
  262. /* Deal with USB Erratum #14 on MPC834x Rev 1.0 & 1.1 chips */
  263. if ((rev == 1) && (chip >= 0x8050) && (chip <= 0x8055))
  264. ehci->has_fsl_port_bug = 1;
  265. if (pdata->port_enables & FSL_USB2_PORT0_ENABLED)
  266. if (ehci_fsl_setup_phy(hcd, pdata->phy_mode, 0))
  267. return -EINVAL;
  268. if (pdata->port_enables & FSL_USB2_PORT1_ENABLED)
  269. if (ehci_fsl_setup_phy(hcd, pdata->phy_mode, 1))
  270. return -EINVAL;
  271. }
  272. if (pdata->have_sysif_regs) {
  273. #ifdef CONFIG_FSL_SOC_BOOKE
  274. out_be32(non_ehci + FSL_SOC_USB_PRICTRL, 0x00000008);
  275. out_be32(non_ehci + FSL_SOC_USB_AGECNTTHRSH, 0x00000080);
  276. #else
  277. out_be32(non_ehci + FSL_SOC_USB_PRICTRL, 0x0000000c);
  278. out_be32(non_ehci + FSL_SOC_USB_AGECNTTHRSH, 0x00000040);
  279. #endif
  280. out_be32(non_ehci + FSL_SOC_USB_SICTRL, 0x00000001);
  281. }
  282. return 0;
  283. }
  284. /* called after powerup, by probe or system-pm "wakeup" */
  285. static int ehci_fsl_reinit(struct ehci_hcd *ehci)
  286. {
  287. if (ehci_fsl_usb_setup(ehci))
  288. return -EINVAL;
  289. return 0;
  290. }
  291. /* called during probe() after chip reset completes */
  292. static int ehci_fsl_setup(struct usb_hcd *hcd)
  293. {
  294. struct ehci_hcd *ehci = hcd_to_ehci(hcd);
  295. int retval;
  296. struct fsl_usb2_platform_data *pdata;
  297. struct device *dev;
  298. dev = hcd->self.controller;
  299. pdata = dev_get_platdata(hcd->self.controller);
  300. ehci->big_endian_desc = pdata->big_endian_desc;
  301. ehci->big_endian_mmio = pdata->big_endian_mmio;
  302. /* EHCI registers start at offset 0x100 */
  303. ehci->caps = hcd->regs + 0x100;
  304. #ifdef CONFIG_PPC_83xx
  305. /*
  306. * Deal with MPC834X that need port power to be cycled after the power
  307. * fault condition is removed. Otherwise the state machine does not
  308. * reflect PORTSC[CSC] correctly.
  309. */
  310. ehci->need_oc_pp_cycle = 1;
  311. #endif
  312. hcd->has_tt = 1;
  313. retval = ehci_setup(hcd);
  314. if (retval)
  315. return retval;
  316. if (of_device_is_compatible(dev->parent->of_node,
  317. "fsl,mpc5121-usb2-dr")) {
  318. /*
  319. * set SBUSCFG:AHBBRST so that control msgs don't
  320. * fail when doing heavy PATA writes.
  321. */
  322. ehci_writel(ehci, SBUSCFG_INCR8,
  323. hcd->regs + FSL_SOC_USB_SBUSCFG);
  324. }
  325. retval = ehci_fsl_reinit(ehci);
  326. return retval;
  327. }
  328. struct ehci_fsl {
  329. struct ehci_hcd ehci;
  330. #ifdef CONFIG_PM
  331. /* Saved USB PHY settings, need to restore after deep sleep. */
  332. u32 usb_ctrl;
  333. #endif
  334. };
  335. #ifdef CONFIG_PM
  336. #ifdef CONFIG_PPC_MPC512x
  337. static int ehci_fsl_mpc512x_drv_suspend(struct device *dev)
  338. {
  339. struct usb_hcd *hcd = dev_get_drvdata(dev);
  340. struct ehci_hcd *ehci = hcd_to_ehci(hcd);
  341. struct fsl_usb2_platform_data *pdata = dev_get_platdata(dev);
  342. u32 tmp;
  343. #ifdef CONFIG_DYNAMIC_DEBUG
  344. u32 mode = ehci_readl(ehci, hcd->regs + FSL_SOC_USB_USBMODE);
  345. mode &= USBMODE_CM_MASK;
  346. tmp = ehci_readl(ehci, hcd->regs + 0x140); /* usbcmd */
  347. dev_dbg(dev, "suspend=%d already_suspended=%d "
  348. "mode=%d usbcmd %08x\n", pdata->suspended,
  349. pdata->already_suspended, mode, tmp);
  350. #endif
  351. /*
  352. * If the controller is already suspended, then this must be a
  353. * PM suspend. Remember this fact, so that we will leave the
  354. * controller suspended at PM resume time.
  355. */
  356. if (pdata->suspended) {
  357. dev_dbg(dev, "already suspended, leaving early\n");
  358. pdata->already_suspended = 1;
  359. return 0;
  360. }
  361. dev_dbg(dev, "suspending...\n");
  362. ehci->rh_state = EHCI_RH_SUSPENDED;
  363. dev->power.power_state = PMSG_SUSPEND;
  364. /* ignore non-host interrupts */
  365. clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
  366. /* stop the controller */
  367. tmp = ehci_readl(ehci, &ehci->regs->command);
  368. tmp &= ~CMD_RUN;
  369. ehci_writel(ehci, tmp, &ehci->regs->command);
  370. /* save EHCI registers */
  371. pdata->pm_command = ehci_readl(ehci, &ehci->regs->command);
  372. pdata->pm_command &= ~CMD_RUN;
  373. pdata->pm_status = ehci_readl(ehci, &ehci->regs->status);
  374. pdata->pm_intr_enable = ehci_readl(ehci, &ehci->regs->intr_enable);
  375. pdata->pm_frame_index = ehci_readl(ehci, &ehci->regs->frame_index);
  376. pdata->pm_segment = ehci_readl(ehci, &ehci->regs->segment);
  377. pdata->pm_frame_list = ehci_readl(ehci, &ehci->regs->frame_list);
  378. pdata->pm_async_next = ehci_readl(ehci, &ehci->regs->async_next);
  379. pdata->pm_configured_flag =
  380. ehci_readl(ehci, &ehci->regs->configured_flag);
  381. pdata->pm_portsc = ehci_readl(ehci, &ehci->regs->port_status[0]);
  382. pdata->pm_usbgenctrl = ehci_readl(ehci,
  383. hcd->regs + FSL_SOC_USB_USBGENCTRL);
  384. /* clear the W1C bits */
  385. pdata->pm_portsc &= cpu_to_hc32(ehci, ~PORT_RWC_BITS);
  386. pdata->suspended = 1;
  387. /* clear PP to cut power to the port */
  388. tmp = ehci_readl(ehci, &ehci->regs->port_status[0]);
  389. tmp &= ~PORT_POWER;
  390. ehci_writel(ehci, tmp, &ehci->regs->port_status[0]);
  391. return 0;
  392. }
  393. static int ehci_fsl_mpc512x_drv_resume(struct device *dev)
  394. {
  395. struct usb_hcd *hcd = dev_get_drvdata(dev);
  396. struct ehci_hcd *ehci = hcd_to_ehci(hcd);
  397. struct fsl_usb2_platform_data *pdata = dev_get_platdata(dev);
  398. u32 tmp;
  399. dev_dbg(dev, "suspend=%d already_suspended=%d\n",
  400. pdata->suspended, pdata->already_suspended);
  401. /*
  402. * If the controller was already suspended at suspend time,
  403. * then don't resume it now.
  404. */
  405. if (pdata->already_suspended) {
  406. dev_dbg(dev, "already suspended, leaving early\n");
  407. pdata->already_suspended = 0;
  408. return 0;
  409. }
  410. if (!pdata->suspended) {
  411. dev_dbg(dev, "not suspended, leaving early\n");
  412. return 0;
  413. }
  414. pdata->suspended = 0;
  415. dev_dbg(dev, "resuming...\n");
  416. /* set host mode */
  417. tmp = USBMODE_CM_HOST | (pdata->es ? USBMODE_ES : 0);
  418. ehci_writel(ehci, tmp, hcd->regs + FSL_SOC_USB_USBMODE);
  419. ehci_writel(ehci, pdata->pm_usbgenctrl,
  420. hcd->regs + FSL_SOC_USB_USBGENCTRL);
  421. ehci_writel(ehci, ISIPHYCTRL_PXE | ISIPHYCTRL_PHYE,
  422. hcd->regs + FSL_SOC_USB_ISIPHYCTRL);
  423. ehci_writel(ehci, SBUSCFG_INCR8, hcd->regs + FSL_SOC_USB_SBUSCFG);
  424. /* restore EHCI registers */
  425. ehci_writel(ehci, pdata->pm_command, &ehci->regs->command);
  426. ehci_writel(ehci, pdata->pm_intr_enable, &ehci->regs->intr_enable);
  427. ehci_writel(ehci, pdata->pm_frame_index, &ehci->regs->frame_index);
  428. ehci_writel(ehci, pdata->pm_segment, &ehci->regs->segment);
  429. ehci_writel(ehci, pdata->pm_frame_list, &ehci->regs->frame_list);
  430. ehci_writel(ehci, pdata->pm_async_next, &ehci->regs->async_next);
  431. ehci_writel(ehci, pdata->pm_configured_flag,
  432. &ehci->regs->configured_flag);
  433. ehci_writel(ehci, pdata->pm_portsc, &ehci->regs->port_status[0]);
  434. set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
  435. ehci->rh_state = EHCI_RH_RUNNING;
  436. dev->power.power_state = PMSG_ON;
  437. tmp = ehci_readl(ehci, &ehci->regs->command);
  438. tmp |= CMD_RUN;
  439. ehci_writel(ehci, tmp, &ehci->regs->command);
  440. usb_hcd_resume_root_hub(hcd);
  441. return 0;
  442. }
  443. #else
  444. static inline int ehci_fsl_mpc512x_drv_suspend(struct device *dev)
  445. {
  446. return 0;
  447. }
  448. static inline int ehci_fsl_mpc512x_drv_resume(struct device *dev)
  449. {
  450. return 0;
  451. }
  452. #endif /* CONFIG_PPC_MPC512x */
  453. static struct ehci_fsl *hcd_to_ehci_fsl(struct usb_hcd *hcd)
  454. {
  455. struct ehci_hcd *ehci = hcd_to_ehci(hcd);
  456. return container_of(ehci, struct ehci_fsl, ehci);
  457. }
  458. static int ehci_fsl_drv_suspend(struct device *dev)
  459. {
  460. struct usb_hcd *hcd = dev_get_drvdata(dev);
  461. struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
  462. void __iomem *non_ehci = hcd->regs;
  463. if (of_device_is_compatible(dev->parent->of_node,
  464. "fsl,mpc5121-usb2-dr")) {
  465. return ehci_fsl_mpc512x_drv_suspend(dev);
  466. }
  467. ehci_prepare_ports_for_controller_suspend(hcd_to_ehci(hcd),
  468. device_may_wakeup(dev));
  469. if (!fsl_deep_sleep())
  470. return 0;
  471. ehci_fsl->usb_ctrl = in_be32(non_ehci + FSL_SOC_USB_CTRL);
  472. return 0;
  473. }
  474. static int ehci_fsl_drv_resume(struct device *dev)
  475. {
  476. struct usb_hcd *hcd = dev_get_drvdata(dev);
  477. struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
  478. struct ehci_hcd *ehci = hcd_to_ehci(hcd);
  479. void __iomem *non_ehci = hcd->regs;
  480. if (of_device_is_compatible(dev->parent->of_node,
  481. "fsl,mpc5121-usb2-dr")) {
  482. return ehci_fsl_mpc512x_drv_resume(dev);
  483. }
  484. ehci_prepare_ports_for_controller_resume(ehci);
  485. if (!fsl_deep_sleep())
  486. return 0;
  487. usb_root_hub_lost_power(hcd->self.root_hub);
  488. /* Restore USB PHY settings and enable the controller. */
  489. out_be32(non_ehci + FSL_SOC_USB_CTRL, ehci_fsl->usb_ctrl);
  490. ehci_reset(ehci);
  491. ehci_fsl_reinit(ehci);
  492. return 0;
  493. }
  494. static int ehci_fsl_drv_restore(struct device *dev)
  495. {
  496. struct usb_hcd *hcd = dev_get_drvdata(dev);
  497. usb_root_hub_lost_power(hcd->self.root_hub);
  498. return 0;
  499. }
  500. static struct dev_pm_ops ehci_fsl_pm_ops = {
  501. .suspend = ehci_fsl_drv_suspend,
  502. .resume = ehci_fsl_drv_resume,
  503. .restore = ehci_fsl_drv_restore,
  504. };
  505. #define EHCI_FSL_PM_OPS (&ehci_fsl_pm_ops)
  506. #else
  507. #define EHCI_FSL_PM_OPS NULL
  508. #endif /* CONFIG_PM */
  509. #ifdef CONFIG_USB_OTG
  510. static int ehci_start_port_reset(struct usb_hcd *hcd, unsigned port)
  511. {
  512. struct ehci_hcd *ehci = hcd_to_ehci(hcd);
  513. u32 status;
  514. if (!port)
  515. return -EINVAL;
  516. port--;
  517. /* start port reset before HNP protocol time out */
  518. status = readl(&ehci->regs->port_status[port]);
  519. if (!(status & PORT_CONNECT))
  520. return -ENODEV;
  521. /* khubd will finish the reset later */
  522. if (ehci_is_TDI(ehci)) {
  523. writel(PORT_RESET |
  524. (status & ~(PORT_CSC | PORT_PEC | PORT_OCC)),
  525. &ehci->regs->port_status[port]);
  526. } else {
  527. writel(PORT_RESET, &ehci->regs->port_status[port]);
  528. }
  529. return 0;
  530. }
  531. #else
  532. #define ehci_start_port_reset NULL
  533. #endif /* CONFIG_USB_OTG */
  534. static const struct hc_driver ehci_fsl_hc_driver = {
  535. .description = hcd_name,
  536. .product_desc = "Freescale On-Chip EHCI Host Controller",
  537. .hcd_priv_size = sizeof(struct ehci_fsl),
  538. /*
  539. * generic hardware linkage
  540. */
  541. .irq = ehci_irq,
  542. .flags = HCD_USB2 | HCD_MEMORY | HCD_BH,
  543. /*
  544. * basic lifecycle operations
  545. */
  546. .reset = ehci_fsl_setup,
  547. .start = ehci_run,
  548. .stop = ehci_stop,
  549. .shutdown = ehci_shutdown,
  550. /*
  551. * managing i/o requests and associated device resources
  552. */
  553. .urb_enqueue = ehci_urb_enqueue,
  554. .urb_dequeue = ehci_urb_dequeue,
  555. .endpoint_disable = ehci_endpoint_disable,
  556. .endpoint_reset = ehci_endpoint_reset,
  557. /*
  558. * scheduling support
  559. */
  560. .get_frame_number = ehci_get_frame,
  561. /*
  562. * root hub support
  563. */
  564. .hub_status_data = ehci_hub_status_data,
  565. .hub_control = ehci_hub_control,
  566. .bus_suspend = ehci_bus_suspend,
  567. .bus_resume = ehci_bus_resume,
  568. .start_port_reset = ehci_start_port_reset,
  569. .relinquish_port = ehci_relinquish_port,
  570. .port_handed_over = ehci_port_handed_over,
  571. .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete,
  572. };
  573. static int ehci_fsl_drv_probe(struct platform_device *pdev)
  574. {
  575. if (usb_disabled())
  576. return -ENODEV;
  577. /* FIXME we only want one one probe() not two */
  578. return usb_hcd_fsl_probe(&ehci_fsl_hc_driver, pdev);
  579. }
  580. static int ehci_fsl_drv_remove(struct platform_device *pdev)
  581. {
  582. struct usb_hcd *hcd = platform_get_drvdata(pdev);
  583. /* FIXME we only want one one remove() not two */
  584. usb_hcd_fsl_remove(hcd, pdev);
  585. return 0;
  586. }
  587. MODULE_ALIAS("platform:fsl-ehci");
  588. static struct platform_driver ehci_fsl_driver = {
  589. .probe = ehci_fsl_drv_probe,
  590. .remove = ehci_fsl_drv_remove,
  591. .shutdown = usb_hcd_platform_shutdown,
  592. .driver = {
  593. .name = "fsl-ehci",
  594. .owner = THIS_MODULE,
  595. .pm = EHCI_FSL_PM_OPS,
  596. },
  597. };