spi-nuc900.c 9.0 KB

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  1. /*
  2. * Copyright (c) 2009 Nuvoton technology.
  3. * Wan ZongShun <mcuos.com@gmail.com>
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License version 2 as
  7. * published by the Free Software Foundation.
  8. *
  9. */
  10. #include <linux/module.h>
  11. #include <linux/init.h>
  12. #include <linux/spinlock.h>
  13. #include <linux/workqueue.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/delay.h>
  16. #include <linux/errno.h>
  17. #include <linux/err.h>
  18. #include <linux/clk.h>
  19. #include <linux/device.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/gpio.h>
  22. #include <linux/io.h>
  23. #include <linux/slab.h>
  24. #include <linux/spi/spi.h>
  25. #include <linux/spi/spi_bitbang.h>
  26. #include <linux/platform_data/spi-nuc900.h>
  27. /* usi registers offset */
  28. #define USI_CNT 0x00
  29. #define USI_DIV 0x04
  30. #define USI_SSR 0x08
  31. #define USI_RX0 0x10
  32. #define USI_TX0 0x10
  33. /* usi register bit */
  34. #define ENINT (0x01 << 17)
  35. #define ENFLG (0x01 << 16)
  36. #define TXNUM (0x03 << 8)
  37. #define TXNEG (0x01 << 2)
  38. #define RXNEG (0x01 << 1)
  39. #define LSB (0x01 << 10)
  40. #define SELECTLEV (0x01 << 2)
  41. #define SELECTPOL (0x01 << 31)
  42. #define SELECTSLAVE 0x01
  43. #define GOBUSY 0x01
  44. struct nuc900_spi {
  45. struct spi_bitbang bitbang;
  46. struct completion done;
  47. void __iomem *regs;
  48. int irq;
  49. int len;
  50. int count;
  51. const unsigned char *tx;
  52. unsigned char *rx;
  53. struct clk *clk;
  54. struct spi_master *master;
  55. struct spi_device *curdev;
  56. struct device *dev;
  57. struct nuc900_spi_info *pdata;
  58. spinlock_t lock;
  59. struct resource *res;
  60. };
  61. static inline struct nuc900_spi *to_hw(struct spi_device *sdev)
  62. {
  63. return spi_master_get_devdata(sdev->master);
  64. }
  65. static void nuc900_slave_select(struct spi_device *spi, unsigned int ssr)
  66. {
  67. struct nuc900_spi *hw = to_hw(spi);
  68. unsigned int val;
  69. unsigned int cs = spi->mode & SPI_CS_HIGH ? 1 : 0;
  70. unsigned int cpol = spi->mode & SPI_CPOL ? 1 : 0;
  71. unsigned long flags;
  72. spin_lock_irqsave(&hw->lock, flags);
  73. val = __raw_readl(hw->regs + USI_SSR);
  74. if (!cs)
  75. val &= ~SELECTLEV;
  76. else
  77. val |= SELECTLEV;
  78. if (!ssr)
  79. val &= ~SELECTSLAVE;
  80. else
  81. val |= SELECTSLAVE;
  82. __raw_writel(val, hw->regs + USI_SSR);
  83. val = __raw_readl(hw->regs + USI_CNT);
  84. if (!cpol)
  85. val &= ~SELECTPOL;
  86. else
  87. val |= SELECTPOL;
  88. __raw_writel(val, hw->regs + USI_CNT);
  89. spin_unlock_irqrestore(&hw->lock, flags);
  90. }
  91. static void nuc900_spi_chipsel(struct spi_device *spi, int value)
  92. {
  93. switch (value) {
  94. case BITBANG_CS_INACTIVE:
  95. nuc900_slave_select(spi, 0);
  96. break;
  97. case BITBANG_CS_ACTIVE:
  98. nuc900_slave_select(spi, 1);
  99. break;
  100. }
  101. }
  102. static void nuc900_spi_setup_txnum(struct nuc900_spi *hw,
  103. unsigned int txnum)
  104. {
  105. unsigned int val;
  106. unsigned long flags;
  107. spin_lock_irqsave(&hw->lock, flags);
  108. val = __raw_readl(hw->regs + USI_CNT);
  109. if (!txnum)
  110. val &= ~TXNUM;
  111. else
  112. val |= txnum << 0x08;
  113. __raw_writel(val, hw->regs + USI_CNT);
  114. spin_unlock_irqrestore(&hw->lock, flags);
  115. }
  116. static void nuc900_spi_setup_txbitlen(struct nuc900_spi *hw,
  117. unsigned int txbitlen)
  118. {
  119. unsigned int val;
  120. unsigned long flags;
  121. spin_lock_irqsave(&hw->lock, flags);
  122. val = __raw_readl(hw->regs + USI_CNT);
  123. val |= (txbitlen << 0x03);
  124. __raw_writel(val, hw->regs + USI_CNT);
  125. spin_unlock_irqrestore(&hw->lock, flags);
  126. }
  127. static void nuc900_spi_gobusy(struct nuc900_spi *hw)
  128. {
  129. unsigned int val;
  130. unsigned long flags;
  131. spin_lock_irqsave(&hw->lock, flags);
  132. val = __raw_readl(hw->regs + USI_CNT);
  133. val |= GOBUSY;
  134. __raw_writel(val, hw->regs + USI_CNT);
  135. spin_unlock_irqrestore(&hw->lock, flags);
  136. }
  137. static inline unsigned int hw_txbyte(struct nuc900_spi *hw, int count)
  138. {
  139. return hw->tx ? hw->tx[count] : 0;
  140. }
  141. static int nuc900_spi_txrx(struct spi_device *spi, struct spi_transfer *t)
  142. {
  143. struct nuc900_spi *hw = to_hw(spi);
  144. hw->tx = t->tx_buf;
  145. hw->rx = t->rx_buf;
  146. hw->len = t->len;
  147. hw->count = 0;
  148. __raw_writel(hw_txbyte(hw, 0x0), hw->regs + USI_TX0);
  149. nuc900_spi_gobusy(hw);
  150. wait_for_completion(&hw->done);
  151. return hw->count;
  152. }
  153. static irqreturn_t nuc900_spi_irq(int irq, void *dev)
  154. {
  155. struct nuc900_spi *hw = dev;
  156. unsigned int status;
  157. unsigned int count = hw->count;
  158. status = __raw_readl(hw->regs + USI_CNT);
  159. __raw_writel(status, hw->regs + USI_CNT);
  160. if (status & ENFLG) {
  161. hw->count++;
  162. if (hw->rx)
  163. hw->rx[count] = __raw_readl(hw->regs + USI_RX0);
  164. count++;
  165. if (count < hw->len) {
  166. __raw_writel(hw_txbyte(hw, count), hw->regs + USI_TX0);
  167. nuc900_spi_gobusy(hw);
  168. } else {
  169. complete(&hw->done);
  170. }
  171. return IRQ_HANDLED;
  172. }
  173. complete(&hw->done);
  174. return IRQ_HANDLED;
  175. }
  176. static void nuc900_tx_edge(struct nuc900_spi *hw, unsigned int edge)
  177. {
  178. unsigned int val;
  179. unsigned long flags;
  180. spin_lock_irqsave(&hw->lock, flags);
  181. val = __raw_readl(hw->regs + USI_CNT);
  182. if (edge)
  183. val |= TXNEG;
  184. else
  185. val &= ~TXNEG;
  186. __raw_writel(val, hw->regs + USI_CNT);
  187. spin_unlock_irqrestore(&hw->lock, flags);
  188. }
  189. static void nuc900_rx_edge(struct nuc900_spi *hw, unsigned int edge)
  190. {
  191. unsigned int val;
  192. unsigned long flags;
  193. spin_lock_irqsave(&hw->lock, flags);
  194. val = __raw_readl(hw->regs + USI_CNT);
  195. if (edge)
  196. val |= RXNEG;
  197. else
  198. val &= ~RXNEG;
  199. __raw_writel(val, hw->regs + USI_CNT);
  200. spin_unlock_irqrestore(&hw->lock, flags);
  201. }
  202. static void nuc900_send_first(struct nuc900_spi *hw, unsigned int lsb)
  203. {
  204. unsigned int val;
  205. unsigned long flags;
  206. spin_lock_irqsave(&hw->lock, flags);
  207. val = __raw_readl(hw->regs + USI_CNT);
  208. if (lsb)
  209. val |= LSB;
  210. else
  211. val &= ~LSB;
  212. __raw_writel(val, hw->regs + USI_CNT);
  213. spin_unlock_irqrestore(&hw->lock, flags);
  214. }
  215. static void nuc900_set_sleep(struct nuc900_spi *hw, unsigned int sleep)
  216. {
  217. unsigned int val;
  218. unsigned long flags;
  219. spin_lock_irqsave(&hw->lock, flags);
  220. val = __raw_readl(hw->regs + USI_CNT);
  221. if (sleep)
  222. val |= (sleep << 12);
  223. else
  224. val &= ~(0x0f << 12);
  225. __raw_writel(val, hw->regs + USI_CNT);
  226. spin_unlock_irqrestore(&hw->lock, flags);
  227. }
  228. static void nuc900_enable_int(struct nuc900_spi *hw)
  229. {
  230. unsigned int val;
  231. unsigned long flags;
  232. spin_lock_irqsave(&hw->lock, flags);
  233. val = __raw_readl(hw->regs + USI_CNT);
  234. val |= ENINT;
  235. __raw_writel(val, hw->regs + USI_CNT);
  236. spin_unlock_irqrestore(&hw->lock, flags);
  237. }
  238. static void nuc900_set_divider(struct nuc900_spi *hw)
  239. {
  240. __raw_writel(hw->pdata->divider, hw->regs + USI_DIV);
  241. }
  242. static void nuc900_init_spi(struct nuc900_spi *hw)
  243. {
  244. clk_enable(hw->clk);
  245. spin_lock_init(&hw->lock);
  246. nuc900_tx_edge(hw, hw->pdata->txneg);
  247. nuc900_rx_edge(hw, hw->pdata->rxneg);
  248. nuc900_send_first(hw, hw->pdata->lsb);
  249. nuc900_set_sleep(hw, hw->pdata->sleep);
  250. nuc900_spi_setup_txbitlen(hw, hw->pdata->txbitlen);
  251. nuc900_spi_setup_txnum(hw, hw->pdata->txnum);
  252. nuc900_set_divider(hw);
  253. nuc900_enable_int(hw);
  254. }
  255. static int nuc900_spi_probe(struct platform_device *pdev)
  256. {
  257. struct nuc900_spi *hw;
  258. struct spi_master *master;
  259. int err = 0;
  260. master = spi_alloc_master(&pdev->dev, sizeof(struct nuc900_spi));
  261. if (master == NULL) {
  262. dev_err(&pdev->dev, "No memory for spi_master\n");
  263. return -ENOMEM;
  264. }
  265. hw = spi_master_get_devdata(master);
  266. hw->master = master;
  267. hw->pdata = dev_get_platdata(&pdev->dev);
  268. hw->dev = &pdev->dev;
  269. if (hw->pdata == NULL) {
  270. dev_err(&pdev->dev, "No platform data supplied\n");
  271. err = -ENOENT;
  272. goto err_pdata;
  273. }
  274. platform_set_drvdata(pdev, hw);
  275. init_completion(&hw->done);
  276. master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
  277. if (hw->pdata->lsb)
  278. master->mode_bits |= SPI_LSB_FIRST;
  279. master->num_chipselect = hw->pdata->num_cs;
  280. master->bus_num = hw->pdata->bus_num;
  281. hw->bitbang.master = hw->master;
  282. hw->bitbang.chipselect = nuc900_spi_chipsel;
  283. hw->bitbang.txrx_bufs = nuc900_spi_txrx;
  284. hw->res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  285. hw->regs = devm_ioremap_resource(&pdev->dev, hw->res);
  286. if (IS_ERR(hw->regs)) {
  287. err = PTR_ERR(hw->regs);
  288. goto err_pdata;
  289. }
  290. hw->irq = platform_get_irq(pdev, 0);
  291. if (hw->irq < 0) {
  292. dev_err(&pdev->dev, "No IRQ specified\n");
  293. err = -ENOENT;
  294. goto err_pdata;
  295. }
  296. err = devm_request_irq(&pdev->dev, hw->irq, nuc900_spi_irq, 0,
  297. pdev->name, hw);
  298. if (err) {
  299. dev_err(&pdev->dev, "Cannot claim IRQ\n");
  300. goto err_pdata;
  301. }
  302. hw->clk = devm_clk_get(&pdev->dev, "spi");
  303. if (IS_ERR(hw->clk)) {
  304. dev_err(&pdev->dev, "No clock for device\n");
  305. err = PTR_ERR(hw->clk);
  306. goto err_pdata;
  307. }
  308. mfp_set_groupg(&pdev->dev, NULL);
  309. nuc900_init_spi(hw);
  310. err = spi_bitbang_start(&hw->bitbang);
  311. if (err) {
  312. dev_err(&pdev->dev, "Failed to register SPI master\n");
  313. goto err_register;
  314. }
  315. return 0;
  316. err_register:
  317. clk_disable(hw->clk);
  318. err_pdata:
  319. spi_master_put(hw->master);
  320. return err;
  321. }
  322. static int nuc900_spi_remove(struct platform_device *dev)
  323. {
  324. struct nuc900_spi *hw = platform_get_drvdata(dev);
  325. spi_bitbang_stop(&hw->bitbang);
  326. clk_disable(hw->clk);
  327. spi_master_put(hw->master);
  328. return 0;
  329. }
  330. static struct platform_driver nuc900_spi_driver = {
  331. .probe = nuc900_spi_probe,
  332. .remove = nuc900_spi_remove,
  333. .driver = {
  334. .name = "nuc900-spi",
  335. .owner = THIS_MODULE,
  336. },
  337. };
  338. module_platform_driver(nuc900_spi_driver);
  339. MODULE_AUTHOR("Wan ZongShun <mcuos.com@gmail.com>");
  340. MODULE_DESCRIPTION("nuc900 spi driver!");
  341. MODULE_LICENSE("GPL");
  342. MODULE_ALIAS("platform:nuc900-spi");