intel_baytrail.h 2.5 KB

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  1. /*
  2. * intel_baytrail.h: MailBox access support for Intel BayTrail platforms
  3. */
  4. #ifndef INTEL_BAYTRAIL_MBI_SYMS_H
  5. #define INTEL_BAYTRAIL_MBI_SYMS_H
  6. #define BT_MBI_MCR_OFFSET 0xD0
  7. #define BT_MBI_MDR_OFFSET 0xD4
  8. #define BT_MBI_MCRX_OFFSET 0xD8
  9. #define BT_MBI_RD_MASK 0xFEFFFFFF
  10. #define BT_MBI_WR_MASK 0X01000000
  11. #define BT_MBI_MASK_HI 0xFFFFFF00
  12. #define BT_MBI_MASK_LO 0x000000FF
  13. #define BT_MBI_ENABLE 0xF0
  14. /* BT-SB unit access methods */
  15. #define BT_MBI_UNIT_AUNIT 0x00
  16. #define BT_MBI_UNIT_SMC 0x01
  17. #define BT_MBI_UNIT_CPU 0x02
  18. #define BT_MBI_UNIT_BUNIT 0x03
  19. #define BT_MBI_UNIT_PMC 0x04
  20. #define BT_MBI_UNIT_GFX 0x06
  21. #define BT_MBI_UNIT_SMI 0x0C
  22. #define BT_MBI_UNIT_USB 0x43
  23. #define BT_MBI_UNIT_SATA 0xA3
  24. #define BT_MBI_UNIT_PCIE 0xA6
  25. /* Read/write opcodes */
  26. #define BT_MBI_AUNIT_READ 0x10
  27. #define BT_MBI_AUNIT_WRITE 0x11
  28. #define BT_MBI_SMC_READ 0x10
  29. #define BT_MBI_SMC_WRITE 0x11
  30. #define BT_MBI_CPU_READ 0x10
  31. #define BT_MBI_CPU_WRITE 0x11
  32. #define BT_MBI_BUNIT_READ 0x10
  33. #define BT_MBI_BUNIT_WRITE 0x11
  34. #define BT_MBI_PMC_READ 0x06
  35. #define BT_MBI_PMC_WRITE 0x07
  36. #define BT_MBI_GFX_READ 0x00
  37. #define BT_MBI_GFX_WRITE 0x01
  38. #define BT_MBI_SMIO_READ 0x06
  39. #define BT_MBI_SMIO_WRITE 0x07
  40. #define BT_MBI_USB_READ 0x06
  41. #define BT_MBI_USB_WRITE 0x07
  42. #define BT_MBI_SATA_READ 0x00
  43. #define BT_MBI_SATA_WRITE 0x01
  44. #define BT_MBI_PCIE_READ 0x00
  45. #define BT_MBI_PCIE_WRITE 0x01
  46. /**
  47. * bt_mbi_read() - MailBox Interface read command
  48. * @port: port indicating subunit being accessed
  49. * @opcode: port specific read or write opcode
  50. * @offset: register address offset
  51. * @mdr: register data to be read
  52. *
  53. * Locking is handled by spinlock - cannot sleep.
  54. * Return: Nonzero on error
  55. */
  56. int bt_mbi_read(u8 port, u8 opcode, u32 offset, u32 *mdr);
  57. /**
  58. * bt_mbi_write() - MailBox unmasked write command
  59. * @port: port indicating subunit being accessed
  60. * @opcode: port specific read or write opcode
  61. * @offset: register address offset
  62. * @mdr: register data to be written
  63. *
  64. * Locking is handled by spinlock - cannot sleep.
  65. * Return: Nonzero on error
  66. */
  67. int bt_mbi_write(u8 port, u8 opcode, u32 offset, u32 mdr);
  68. /**
  69. * bt_mbi_modify() - MailBox masked write command
  70. * @port: port indicating subunit being accessed
  71. * @opcode: port specific read or write opcode
  72. * @offset: register address offset
  73. * @mdr: register data being modified
  74. * @mask: mask indicating bits in mdr to be modified
  75. *
  76. * Locking is handled by spinlock - cannot sleep.
  77. * Return: Nonzero on error
  78. */
  79. int bt_mbi_modify(u8 port, u8 opcode, u32 offset, u32 mdr, u32 mask);
  80. #endif /* INTEL_BAYTRAIL_MBI_SYMS_H */