pci-imx6.c 16 KB

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  1. /*
  2. * PCIe host controller driver for Freescale i.MX6 SoCs
  3. *
  4. * Copyright (C) 2013 Kosagi
  5. * http://www.kosagi.com
  6. *
  7. * Author: Sean Cross <xobs@kosagi.com>
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as
  11. * published by the Free Software Foundation.
  12. */
  13. #include <linux/clk.h>
  14. #include <linux/delay.h>
  15. #include <linux/gpio.h>
  16. #include <linux/kernel.h>
  17. #include <linux/mfd/syscon.h>
  18. #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
  19. #include <linux/module.h>
  20. #include <linux/of_gpio.h>
  21. #include <linux/pci.h>
  22. #include <linux/platform_device.h>
  23. #include <linux/regmap.h>
  24. #include <linux/resource.h>
  25. #include <linux/signal.h>
  26. #include <linux/types.h>
  27. #include "pcie-designware.h"
  28. #define to_imx6_pcie(x) container_of(x, struct imx6_pcie, pp)
  29. struct imx6_pcie {
  30. int reset_gpio;
  31. int power_on_gpio;
  32. int wake_up_gpio;
  33. int disable_gpio;
  34. struct clk *lvds_gate;
  35. struct clk *sata_ref_100m;
  36. struct clk *pcie_ref_125m;
  37. struct clk *pcie_axi;
  38. struct pcie_port pp;
  39. struct regmap *iomuxc_gpr;
  40. void __iomem *mem_base;
  41. };
  42. /* PCIe Root Complex registers (memory-mapped) */
  43. #define PCIE_RC_LCR 0x7c
  44. #define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1 0x1
  45. #define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2 0x2
  46. #define PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK 0xf
  47. /* PCIe Port Logic registers (memory-mapped) */
  48. #define PL_OFFSET 0x700
  49. #define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28)
  50. #define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c)
  51. #define PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING (1 << 29)
  52. #define PCIE_PHY_DEBUG_R1_XMLH_LINK_UP (1 << 4)
  53. #define PCIE_PHY_CTRL (PL_OFFSET + 0x114)
  54. #define PCIE_PHY_CTRL_DATA_LOC 0
  55. #define PCIE_PHY_CTRL_CAP_ADR_LOC 16
  56. #define PCIE_PHY_CTRL_CAP_DAT_LOC 17
  57. #define PCIE_PHY_CTRL_WR_LOC 18
  58. #define PCIE_PHY_CTRL_RD_LOC 19
  59. #define PCIE_PHY_STAT (PL_OFFSET + 0x110)
  60. #define PCIE_PHY_STAT_ACK_LOC 16
  61. #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
  62. #define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
  63. /* PHY registers (not memory-mapped) */
  64. #define PCIE_PHY_RX_ASIC_OUT 0x100D
  65. #define PHY_RX_OVRD_IN_LO 0x1005
  66. #define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5)
  67. #define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3)
  68. static int pcie_phy_poll_ack(void __iomem *dbi_base, int exp_val)
  69. {
  70. u32 val;
  71. u32 max_iterations = 10;
  72. u32 wait_counter = 0;
  73. do {
  74. val = readl(dbi_base + PCIE_PHY_STAT);
  75. val = (val >> PCIE_PHY_STAT_ACK_LOC) & 0x1;
  76. wait_counter++;
  77. if (val == exp_val)
  78. return 0;
  79. udelay(1);
  80. } while (wait_counter < max_iterations);
  81. return -ETIMEDOUT;
  82. }
  83. static int pcie_phy_wait_ack(void __iomem *dbi_base, int addr)
  84. {
  85. u32 val;
  86. int ret;
  87. val = addr << PCIE_PHY_CTRL_DATA_LOC;
  88. writel(val, dbi_base + PCIE_PHY_CTRL);
  89. val |= (0x1 << PCIE_PHY_CTRL_CAP_ADR_LOC);
  90. writel(val, dbi_base + PCIE_PHY_CTRL);
  91. ret = pcie_phy_poll_ack(dbi_base, 1);
  92. if (ret)
  93. return ret;
  94. val = addr << PCIE_PHY_CTRL_DATA_LOC;
  95. writel(val, dbi_base + PCIE_PHY_CTRL);
  96. ret = pcie_phy_poll_ack(dbi_base, 0);
  97. if (ret)
  98. return ret;
  99. return 0;
  100. }
  101. /* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */
  102. static int pcie_phy_read(void __iomem *dbi_base, int addr , int *data)
  103. {
  104. u32 val, phy_ctl;
  105. int ret;
  106. ret = pcie_phy_wait_ack(dbi_base, addr);
  107. if (ret)
  108. return ret;
  109. /* assert Read signal */
  110. phy_ctl = 0x1 << PCIE_PHY_CTRL_RD_LOC;
  111. writel(phy_ctl, dbi_base + PCIE_PHY_CTRL);
  112. ret = pcie_phy_poll_ack(dbi_base, 1);
  113. if (ret)
  114. return ret;
  115. val = readl(dbi_base + PCIE_PHY_STAT);
  116. *data = val & 0xffff;
  117. /* deassert Read signal */
  118. writel(0x00, dbi_base + PCIE_PHY_CTRL);
  119. ret = pcie_phy_poll_ack(dbi_base, 0);
  120. if (ret)
  121. return ret;
  122. return 0;
  123. }
  124. static int pcie_phy_write(void __iomem *dbi_base, int addr, int data)
  125. {
  126. u32 var;
  127. int ret;
  128. /* write addr */
  129. /* cap addr */
  130. ret = pcie_phy_wait_ack(dbi_base, addr);
  131. if (ret)
  132. return ret;
  133. var = data << PCIE_PHY_CTRL_DATA_LOC;
  134. writel(var, dbi_base + PCIE_PHY_CTRL);
  135. /* capture data */
  136. var |= (0x1 << PCIE_PHY_CTRL_CAP_DAT_LOC);
  137. writel(var, dbi_base + PCIE_PHY_CTRL);
  138. ret = pcie_phy_poll_ack(dbi_base, 1);
  139. if (ret)
  140. return ret;
  141. /* deassert cap data */
  142. var = data << PCIE_PHY_CTRL_DATA_LOC;
  143. writel(var, dbi_base + PCIE_PHY_CTRL);
  144. /* wait for ack de-assertion */
  145. ret = pcie_phy_poll_ack(dbi_base, 0);
  146. if (ret)
  147. return ret;
  148. /* assert wr signal */
  149. var = 0x1 << PCIE_PHY_CTRL_WR_LOC;
  150. writel(var, dbi_base + PCIE_PHY_CTRL);
  151. /* wait for ack */
  152. ret = pcie_phy_poll_ack(dbi_base, 1);
  153. if (ret)
  154. return ret;
  155. /* deassert wr signal */
  156. var = data << PCIE_PHY_CTRL_DATA_LOC;
  157. writel(var, dbi_base + PCIE_PHY_CTRL);
  158. /* wait for ack de-assertion */
  159. ret = pcie_phy_poll_ack(dbi_base, 0);
  160. if (ret)
  161. return ret;
  162. writel(0x0, dbi_base + PCIE_PHY_CTRL);
  163. return 0;
  164. }
  165. /* Added for PCI abort handling */
  166. static int imx6q_pcie_abort_handler(unsigned long addr,
  167. unsigned int fsr, struct pt_regs *regs)
  168. {
  169. return 0;
  170. }
  171. static int imx6_pcie_assert_core_reset(struct pcie_port *pp)
  172. {
  173. struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
  174. regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
  175. IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18);
  176. regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
  177. IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16);
  178. return 0;
  179. }
  180. static int imx6_pcie_deassert_core_reset(struct pcie_port *pp)
  181. {
  182. struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
  183. int ret;
  184. if (gpio_is_valid(imx6_pcie->power_on_gpio))
  185. gpio_set_value(imx6_pcie->power_on_gpio, 1);
  186. regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
  187. IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18);
  188. regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
  189. IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);
  190. ret = clk_prepare_enable(imx6_pcie->sata_ref_100m);
  191. if (ret) {
  192. dev_err(pp->dev, "unable to enable sata_ref_100m\n");
  193. goto err_sata_ref;
  194. }
  195. ret = clk_prepare_enable(imx6_pcie->pcie_ref_125m);
  196. if (ret) {
  197. dev_err(pp->dev, "unable to enable pcie_ref_125m\n");
  198. goto err_pcie_ref;
  199. }
  200. ret = clk_prepare_enable(imx6_pcie->lvds_gate);
  201. if (ret) {
  202. dev_err(pp->dev, "unable to enable lvds_gate\n");
  203. goto err_lvds_gate;
  204. }
  205. ret = clk_prepare_enable(imx6_pcie->pcie_axi);
  206. if (ret) {
  207. dev_err(pp->dev, "unable to enable pcie_axi\n");
  208. goto err_pcie_axi;
  209. }
  210. /* allow the clocks to stabilize */
  211. usleep_range(200, 500);
  212. /* Some boards don't have PCIe reset GPIO. */
  213. if (gpio_is_valid(imx6_pcie->reset_gpio)) {
  214. gpio_set_value(imx6_pcie->reset_gpio, 0);
  215. msleep(100);
  216. gpio_set_value(imx6_pcie->reset_gpio, 1);
  217. }
  218. return 0;
  219. err_pcie_axi:
  220. clk_disable_unprepare(imx6_pcie->lvds_gate);
  221. err_lvds_gate:
  222. clk_disable_unprepare(imx6_pcie->pcie_ref_125m);
  223. err_pcie_ref:
  224. clk_disable_unprepare(imx6_pcie->sata_ref_100m);
  225. err_sata_ref:
  226. return ret;
  227. }
  228. static void imx6_pcie_init_phy(struct pcie_port *pp)
  229. {
  230. struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
  231. regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
  232. IMX6Q_GPR12_PCIE_CTL_2, 0 << 10);
  233. /* configure constant input signal to the pcie ctrl and phy */
  234. regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
  235. IMX6Q_GPR12_DEVICE_TYPE, PCI_EXP_TYPE_ROOT_PORT << 12);
  236. regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
  237. IMX6Q_GPR12_LOS_LEVEL, 9 << 4);
  238. regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
  239. IMX6Q_GPR8_TX_DEEMPH_GEN1, 0 << 0);
  240. regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
  241. IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB, 0 << 6);
  242. regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
  243. IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB, 20 << 12);
  244. regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
  245. IMX6Q_GPR8_TX_SWING_FULL, 127 << 18);
  246. regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
  247. IMX6Q_GPR8_TX_SWING_LOW, 127 << 25);
  248. }
  249. static int imx6_pcie_wait_for_link(struct pcie_port *pp)
  250. {
  251. int count = 200;
  252. while (!dw_pcie_link_up(pp)) {
  253. usleep_range(100, 1000);
  254. if (--count)
  255. continue;
  256. dev_err(pp->dev, "phy link never came up\n");
  257. dev_dbg(pp->dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
  258. readl(pp->dbi_base + PCIE_PHY_DEBUG_R0),
  259. readl(pp->dbi_base + PCIE_PHY_DEBUG_R1));
  260. return -EINVAL;
  261. }
  262. return 0;
  263. }
  264. static int imx6_pcie_start_link(struct pcie_port *pp)
  265. {
  266. struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
  267. uint32_t tmp;
  268. int ret, count;
  269. /*
  270. * Force Gen1 operation when starting the link. In case the link is
  271. * started in Gen2 mode, there is a possibility the devices on the
  272. * bus will not be detected at all. This happens with PCIe switches.
  273. */
  274. tmp = readl(pp->dbi_base + PCIE_RC_LCR);
  275. tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK;
  276. tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1;
  277. writel(tmp, pp->dbi_base + PCIE_RC_LCR);
  278. /* Start LTSSM. */
  279. regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
  280. IMX6Q_GPR12_PCIE_CTL_2, 1 << 10);
  281. ret = imx6_pcie_wait_for_link(pp);
  282. if (ret)
  283. return ret;
  284. /* Allow Gen2 mode after the link is up. */
  285. tmp = readl(pp->dbi_base + PCIE_RC_LCR);
  286. tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK;
  287. tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2;
  288. writel(tmp, pp->dbi_base + PCIE_RC_LCR);
  289. /*
  290. * Start Directed Speed Change so the best possible speed both link
  291. * partners support can be negotiated.
  292. */
  293. tmp = readl(pp->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
  294. tmp |= PORT_LOGIC_SPEED_CHANGE;
  295. writel(tmp, pp->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
  296. count = 200;
  297. while (count--) {
  298. tmp = readl(pp->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
  299. /* Test if the speed change finished. */
  300. if (!(tmp & PORT_LOGIC_SPEED_CHANGE))
  301. break;
  302. usleep_range(100, 1000);
  303. }
  304. /* Make sure link training is finished as well! */
  305. if (count)
  306. ret = imx6_pcie_wait_for_link(pp);
  307. else
  308. ret = -EINVAL;
  309. if (ret) {
  310. dev_err(pp->dev, "Failed to bring link up!\n");
  311. } else {
  312. tmp = readl(pp->dbi_base + 0x80);
  313. dev_dbg(pp->dev, "Link up, Gen=%i\n", (tmp >> 16) & 0xf);
  314. }
  315. return ret;
  316. }
  317. static void imx6_pcie_host_init(struct pcie_port *pp)
  318. {
  319. imx6_pcie_assert_core_reset(pp);
  320. imx6_pcie_init_phy(pp);
  321. imx6_pcie_deassert_core_reset(pp);
  322. dw_pcie_setup_rc(pp);
  323. imx6_pcie_start_link(pp);
  324. }
  325. static void imx6_pcie_reset_phy(struct pcie_port *pp)
  326. {
  327. uint32_t temp;
  328. pcie_phy_read(pp->dbi_base, PHY_RX_OVRD_IN_LO, &temp);
  329. temp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN |
  330. PHY_RX_OVRD_IN_LO_RX_PLL_EN);
  331. pcie_phy_write(pp->dbi_base, PHY_RX_OVRD_IN_LO, temp);
  332. usleep_range(2000, 3000);
  333. pcie_phy_read(pp->dbi_base, PHY_RX_OVRD_IN_LO, &temp);
  334. temp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN |
  335. PHY_RX_OVRD_IN_LO_RX_PLL_EN);
  336. pcie_phy_write(pp->dbi_base, PHY_RX_OVRD_IN_LO, temp);
  337. }
  338. static int imx6_pcie_link_up(struct pcie_port *pp)
  339. {
  340. u32 rc, ltssm, rx_valid;
  341. /*
  342. * Test if the PHY reports that the link is up and also that
  343. * the link training finished. It might happen that the PHY
  344. * reports the link is already up, but the link training bit
  345. * is still set, so make sure to check the training is done
  346. * as well here.
  347. */
  348. rc = readl(pp->dbi_base + PCIE_PHY_DEBUG_R1);
  349. if ((rc & PCIE_PHY_DEBUG_R1_XMLH_LINK_UP) &&
  350. !(rc & PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING))
  351. return 1;
  352. /*
  353. * From L0, initiate MAC entry to gen2 if EP/RC supports gen2.
  354. * Wait 2ms (LTSSM timeout is 24ms, PHY lock is ~5us in gen2).
  355. * If (MAC/LTSSM.state == Recovery.RcvrLock)
  356. * && (PHY/rx_valid==0) then pulse PHY/rx_reset. Transition
  357. * to gen2 is stuck
  358. */
  359. pcie_phy_read(pp->dbi_base, PCIE_PHY_RX_ASIC_OUT, &rx_valid);
  360. ltssm = readl(pp->dbi_base + PCIE_PHY_DEBUG_R0) & 0x3F;
  361. if (rx_valid & 0x01)
  362. return 0;
  363. if (ltssm != 0x0d)
  364. return 0;
  365. dev_err(pp->dev, "transition to gen2 is stuck, reset PHY!\n");
  366. imx6_pcie_reset_phy(pp);
  367. return 0;
  368. }
  369. static struct pcie_host_ops imx6_pcie_host_ops = {
  370. .link_up = imx6_pcie_link_up,
  371. .host_init = imx6_pcie_host_init,
  372. };
  373. static int imx6_add_pcie_port(struct pcie_port *pp,
  374. struct platform_device *pdev)
  375. {
  376. int ret;
  377. pp->irq = platform_get_irq(pdev, 0);
  378. if (!pp->irq) {
  379. dev_err(&pdev->dev, "failed to get irq\n");
  380. return -ENODEV;
  381. }
  382. pp->root_bus_nr = -1;
  383. pp->ops = &imx6_pcie_host_ops;
  384. spin_lock_init(&pp->conf_lock);
  385. ret = dw_pcie_host_init(pp);
  386. if (ret) {
  387. dev_err(&pdev->dev, "failed to initialize host\n");
  388. return ret;
  389. }
  390. return 0;
  391. }
  392. static int __init imx6_pcie_probe(struct platform_device *pdev)
  393. {
  394. struct imx6_pcie *imx6_pcie;
  395. struct pcie_port *pp;
  396. struct device_node *np = pdev->dev.of_node;
  397. struct resource *dbi_base;
  398. int ret;
  399. imx6_pcie = devm_kzalloc(&pdev->dev, sizeof(*imx6_pcie), GFP_KERNEL);
  400. if (!imx6_pcie)
  401. return -ENOMEM;
  402. pp = &imx6_pcie->pp;
  403. pp->dev = &pdev->dev;
  404. /* Added for PCI abort handling */
  405. hook_fault_code(16 + 6, imx6q_pcie_abort_handler, SIGBUS, 0,
  406. "imprecise external abort");
  407. dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  408. pp->dbi_base = devm_ioremap_resource(&pdev->dev, dbi_base);
  409. if (IS_ERR(pp->dbi_base))
  410. return PTR_ERR(pp->dbi_base);
  411. /* Fetch GPIOs */
  412. imx6_pcie->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0);
  413. if (gpio_is_valid(imx6_pcie->reset_gpio)) {
  414. ret = devm_gpio_request_one(&pdev->dev, imx6_pcie->reset_gpio,
  415. GPIOF_OUT_INIT_LOW, "PCIe reset");
  416. if (ret) {
  417. dev_err(&pdev->dev, "unable to get reset gpio\n");
  418. return ret;
  419. }
  420. }
  421. imx6_pcie->power_on_gpio = of_get_named_gpio(np, "power-on-gpio", 0);
  422. if (gpio_is_valid(imx6_pcie->power_on_gpio)) {
  423. ret = devm_gpio_request_one(&pdev->dev,
  424. imx6_pcie->power_on_gpio,
  425. GPIOF_OUT_INIT_LOW,
  426. "PCIe power enable");
  427. if (ret) {
  428. dev_err(&pdev->dev, "unable to get power-on gpio\n");
  429. return ret;
  430. }
  431. }
  432. imx6_pcie->wake_up_gpio = of_get_named_gpio(np, "wake-up-gpio", 0);
  433. if (gpio_is_valid(imx6_pcie->wake_up_gpio)) {
  434. ret = devm_gpio_request_one(&pdev->dev,
  435. imx6_pcie->wake_up_gpio,
  436. GPIOF_IN,
  437. "PCIe wake up");
  438. if (ret) {
  439. dev_err(&pdev->dev, "unable to get wake-up gpio\n");
  440. return ret;
  441. }
  442. }
  443. imx6_pcie->disable_gpio = of_get_named_gpio(np, "disable-gpio", 0);
  444. if (gpio_is_valid(imx6_pcie->disable_gpio)) {
  445. ret = devm_gpio_request_one(&pdev->dev,
  446. imx6_pcie->disable_gpio,
  447. GPIOF_OUT_INIT_HIGH,
  448. "PCIe disable endpoint");
  449. if (ret) {
  450. dev_err(&pdev->dev, "unable to get disable-ep gpio\n");
  451. return ret;
  452. }
  453. }
  454. /* Fetch clocks */
  455. imx6_pcie->lvds_gate = devm_clk_get(&pdev->dev, "lvds_gate");
  456. if (IS_ERR(imx6_pcie->lvds_gate)) {
  457. dev_err(&pdev->dev,
  458. "lvds_gate clock select missing or invalid\n");
  459. return PTR_ERR(imx6_pcie->lvds_gate);
  460. }
  461. imx6_pcie->sata_ref_100m = devm_clk_get(&pdev->dev, "sata_ref_100m");
  462. if (IS_ERR(imx6_pcie->sata_ref_100m)) {
  463. dev_err(&pdev->dev,
  464. "sata_ref_100m clock source missing or invalid\n");
  465. return PTR_ERR(imx6_pcie->sata_ref_100m);
  466. }
  467. imx6_pcie->pcie_ref_125m = devm_clk_get(&pdev->dev, "pcie_ref_125m");
  468. if (IS_ERR(imx6_pcie->pcie_ref_125m)) {
  469. dev_err(&pdev->dev,
  470. "pcie_ref_125m clock source missing or invalid\n");
  471. return PTR_ERR(imx6_pcie->pcie_ref_125m);
  472. }
  473. imx6_pcie->pcie_axi = devm_clk_get(&pdev->dev, "pcie_axi");
  474. if (IS_ERR(imx6_pcie->pcie_axi)) {
  475. dev_err(&pdev->dev,
  476. "pcie_axi clock source missing or invalid\n");
  477. return PTR_ERR(imx6_pcie->pcie_axi);
  478. }
  479. /* Grab GPR config register range */
  480. imx6_pcie->iomuxc_gpr =
  481. syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
  482. if (IS_ERR(imx6_pcie->iomuxc_gpr)) {
  483. dev_err(&pdev->dev, "unable to find iomuxc registers\n");
  484. return PTR_ERR(imx6_pcie->iomuxc_gpr);
  485. }
  486. ret = imx6_add_pcie_port(pp, pdev);
  487. if (ret < 0)
  488. return ret;
  489. platform_set_drvdata(pdev, imx6_pcie);
  490. return 0;
  491. }
  492. static const struct of_device_id imx6_pcie_of_match[] = {
  493. { .compatible = "fsl,imx6q-pcie", },
  494. {},
  495. };
  496. MODULE_DEVICE_TABLE(of, imx6_pcie_of_match);
  497. static struct platform_driver imx6_pcie_driver = {
  498. .driver = {
  499. .name = "imx6q-pcie",
  500. .owner = THIS_MODULE,
  501. .of_match_table = imx6_pcie_of_match,
  502. },
  503. };
  504. /* Freescale PCIe driver does not allow module unload */
  505. static int __init imx6_pcie_init(void)
  506. {
  507. return platform_driver_probe(&imx6_pcie_driver, imx6_pcie_probe);
  508. }
  509. fs_initcall(imx6_pcie_init);
  510. MODULE_AUTHOR("Sean Cross <xobs@kosagi.com>");
  511. MODULE_DESCRIPTION("Freescale i.MX6 PCIe host controller driver");
  512. MODULE_LICENSE("GPL v2");