common.c 142 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628162916301631163216331634163516361637163816391640164116421643164416451646164716481649165016511652165316541655165616571658165916601661166216631664166516661667166816691670167116721673167416751676167716781679168016811682168316841685168616871688168916901691169216931694169516961697169816991700170117021703170417051706170717081709171017111712171317141715171617171718171917201721172217231724172517261727172817291730173117321733173417351736173717381739174017411742174317441745174617471748174917501751175217531754175517561757175817591760176117621763176417651766176717681769177017711772177317741775177617771778177917801781178217831784178517861787178817891790179117921793179417951796179717981799180018011802180318041805180618071808180918101811181218131814181518161817181818191820182118221823182418251826182718281829183018311832183318341835183618371838183918401841184218431844184518461847184818491850185118521853185418551856185718581859186018611862186318641865186618671868186918701871187218731874187518761877187818791880188118821883188418851886188718881889189018911892189318941895189618971898189919001901190219031904190519061907190819091910191119121913191419151916191719181919192019211922192319241925192619271928192919301931193219331934193519361937193819391940194119421943194419451946194719481949195019511952195319541955195619571958195919601961196219631964196519661967196819691970197119721973197419751976197719781979198019811982198319841985198619871988198919901991199219931994199519961997199819992000200120022003200420052006200720082009201020112012201320142015201620172018201920202021202220232024202520262027202820292030203120322033203420352036203720382039204020412042204320442045204620472048204920502051205220532054205520562057205820592060206120622063206420652066206720682069207020712072207320742075207620772078207920802081208220832084208520862087208820892090209120922093209420952096209720982099210021012102210321042105210621072108210921102111211221132114211521162117211821192120212121222123212421252126212721282129213021312132213321342135213621372138213921402141214221432144214521462147214821492150215121522153215421552156215721582159216021612162216321642165216621672168216921702171217221732174217521762177217821792180218121822183218421852186218721882189219021912192219321942195219621972198219922002201220222032204220522062207220822092210221122122213221422152216221722182219222022212222222322242225222622272228222922302231223222332234223522362237223822392240224122422243224422452246224722482249225022512252225322542255225622572258225922602261226222632264226522662267226822692270227122722273227422752276227722782279228022812282228322842285228622872288228922902291229222932294229522962297229822992300230123022303230423052306230723082309231023112312231323142315231623172318231923202321232223232324232523262327232823292330233123322333233423352336233723382339234023412342234323442345234623472348234923502351235223532354235523562357235823592360236123622363236423652366236723682369237023712372237323742375237623772378237923802381238223832384238523862387238823892390239123922393239423952396239723982399240024012402240324042405240624072408240924102411241224132414241524162417241824192420242124222423242424252426242724282429243024312432243324342435243624372438243924402441244224432444244524462447244824492450245124522453245424552456245724582459246024612462246324642465246624672468246924702471247224732474247524762477247824792480248124822483248424852486248724882489249024912492249324942495249624972498249925002501250225032504250525062507250825092510251125122513251425152516251725182519252025212522252325242525252625272528252925302531253225332534253525362537253825392540254125422543254425452546254725482549255025512552255325542555255625572558255925602561256225632564256525662567256825692570257125722573257425752576257725782579258025812582258325842585258625872588258925902591259225932594259525962597259825992600260126022603260426052606260726082609261026112612261326142615261626172618261926202621262226232624262526262627262826292630263126322633263426352636263726382639264026412642264326442645264626472648264926502651265226532654265526562657265826592660266126622663266426652666266726682669267026712672267326742675267626772678267926802681268226832684268526862687268826892690269126922693269426952696269726982699270027012702270327042705270627072708270927102711271227132714271527162717271827192720272127222723272427252726272727282729273027312732273327342735273627372738273927402741274227432744274527462747274827492750275127522753275427552756275727582759276027612762276327642765276627672768276927702771277227732774277527762777277827792780278127822783278427852786278727882789279027912792279327942795279627972798279928002801280228032804280528062807280828092810281128122813281428152816281728182819282028212822282328242825282628272828282928302831283228332834283528362837283828392840284128422843284428452846284728482849285028512852285328542855285628572858285928602861286228632864286528662867286828692870287128722873287428752876287728782879288028812882288328842885288628872888288928902891289228932894289528962897289828992900290129022903290429052906290729082909291029112912291329142915291629172918291929202921292229232924292529262927292829292930293129322933293429352936293729382939294029412942294329442945294629472948294929502951295229532954295529562957295829592960296129622963296429652966296729682969297029712972297329742975297629772978297929802981298229832984298529862987298829892990299129922993299429952996299729982999300030013002300330043005300630073008300930103011301230133014301530163017301830193020302130223023302430253026302730283029303030313032303330343035303630373038303930403041304230433044304530463047304830493050305130523053305430553056305730583059306030613062306330643065306630673068306930703071307230733074307530763077307830793080308130823083308430853086308730883089309030913092309330943095309630973098309931003101310231033104310531063107310831093110311131123113311431153116311731183119312031213122312331243125312631273128312931303131313231333134313531363137313831393140314131423143314431453146314731483149315031513152315331543155315631573158315931603161316231633164316531663167316831693170317131723173317431753176317731783179318031813182318331843185318631873188318931903191319231933194319531963197319831993200320132023203320432053206320732083209321032113212321332143215321632173218321932203221322232233224322532263227322832293230323132323233323432353236323732383239324032413242324332443245324632473248324932503251325232533254325532563257325832593260326132623263326432653266326732683269327032713272327332743275327632773278327932803281328232833284328532863287328832893290329132923293329432953296329732983299330033013302330333043305330633073308330933103311331233133314331533163317331833193320332133223323332433253326332733283329333033313332333333343335333633373338333933403341334233433344334533463347334833493350335133523353335433553356335733583359336033613362336333643365336633673368336933703371337233733374337533763377337833793380338133823383338433853386338733883389339033913392339333943395339633973398339934003401340234033404340534063407340834093410341134123413341434153416341734183419342034213422342334243425342634273428342934303431343234333434343534363437343834393440344134423443344434453446344734483449345034513452345334543455345634573458345934603461346234633464346534663467346834693470347134723473347434753476347734783479348034813482348334843485348634873488348934903491349234933494349534963497349834993500350135023503350435053506350735083509351035113512351335143515351635173518351935203521352235233524352535263527352835293530353135323533353435353536353735383539354035413542354335443545354635473548354935503551355235533554355535563557355835593560356135623563356435653566356735683569357035713572357335743575357635773578357935803581358235833584358535863587358835893590359135923593359435953596359735983599360036013602360336043605360636073608360936103611361236133614361536163617361836193620362136223623362436253626362736283629363036313632363336343635363636373638363936403641364236433644364536463647364836493650365136523653365436553656365736583659366036613662366336643665366636673668366936703671367236733674367536763677367836793680368136823683368436853686368736883689369036913692369336943695369636973698369937003701370237033704370537063707370837093710371137123713371437153716371737183719372037213722372337243725372637273728372937303731373237333734373537363737373837393740374137423743374437453746374737483749375037513752375337543755375637573758375937603761376237633764376537663767376837693770377137723773377437753776377737783779378037813782378337843785378637873788378937903791379237933794379537963797379837993800380138023803380438053806380738083809381038113812381338143815381638173818381938203821382238233824382538263827382838293830383138323833383438353836383738383839384038413842384338443845384638473848384938503851385238533854385538563857385838593860386138623863386438653866386738683869387038713872387338743875387638773878387938803881388238833884388538863887388838893890389138923893389438953896389738983899390039013902390339043905390639073908390939103911391239133914391539163917391839193920392139223923392439253926392739283929393039313932393339343935393639373938393939403941394239433944394539463947394839493950395139523953395439553956395739583959396039613962396339643965396639673968396939703971397239733974397539763977397839793980398139823983398439853986398739883989399039913992399339943995399639973998399940004001400240034004400540064007400840094010401140124013401440154016401740184019402040214022402340244025402640274028402940304031403240334034403540364037403840394040404140424043404440454046404740484049405040514052405340544055405640574058405940604061406240634064406540664067406840694070407140724073407440754076407740784079408040814082408340844085408640874088408940904091409240934094409540964097409840994100410141024103410441054106410741084109411041114112411341144115411641174118411941204121412241234124412541264127412841294130413141324133413441354136413741384139414041414142414341444145414641474148414941504151415241534154415541564157415841594160416141624163416441654166416741684169417041714172417341744175417641774178417941804181418241834184418541864187418841894190419141924193419441954196419741984199420042014202420342044205420642074208420942104211421242134214421542164217421842194220422142224223422442254226422742284229423042314232423342344235423642374238423942404241424242434244424542464247424842494250425142524253425442554256425742584259426042614262426342644265426642674268426942704271427242734274427542764277427842794280428142824283428442854286428742884289429042914292429342944295429642974298429943004301430243034304430543064307430843094310431143124313431443154316431743184319432043214322432343244325432643274328432943304331433243334334433543364337433843394340434143424343434443454346434743484349435043514352435343544355435643574358435943604361436243634364436543664367436843694370437143724373437443754376437743784379438043814382438343844385438643874388438943904391439243934394439543964397439843994400440144024403440444054406440744084409441044114412441344144415441644174418441944204421442244234424442544264427442844294430443144324433443444354436443744384439444044414442444344444445444644474448444944504451445244534454445544564457445844594460446144624463446444654466446744684469447044714472447344744475447644774478447944804481448244834484448544864487448844894490449144924493449444954496449744984499450045014502450345044505450645074508450945104511451245134514451545164517451845194520452145224523452445254526452745284529453045314532453345344535453645374538453945404541454245434544454545464547454845494550455145524553455445554556455745584559456045614562456345644565456645674568456945704571457245734574457545764577457845794580458145824583458445854586458745884589459045914592459345944595459645974598459946004601460246034604460546064607460846094610461146124613461446154616461746184619462046214622462346244625462646274628462946304631463246334634463546364637463846394640464146424643464446454646464746484649465046514652465346544655465646574658465946604661466246634664466546664667466846694670467146724673467446754676467746784679468046814682468346844685468646874688468946904691469246934694469546964697469846994700470147024703470447054706470747084709471047114712471347144715471647174718471947204721472247234724472547264727472847294730473147324733473447354736473747384739474047414742474347444745474647474748474947504751475247534754475547564757475847594760476147624763476447654766476747684769477047714772477347744775477647774778477947804781478247834784478547864787478847894790479147924793479447954796479747984799480048014802480348044805480648074808480948104811481248134814481548164817481848194820482148224823482448254826482748284829483048314832483348344835483648374838483948404841484248434844484548464847484848494850485148524853485448554856485748584859486048614862486348644865486648674868486948704871487248734874487548764877487848794880488148824883488448854886488748884889489048914892489348944895489648974898489949004901490249034904490549064907490849094910491149124913491449154916491749184919492049214922492349244925492649274928492949304931493249334934493549364937493849394940494149424943494449454946494749484949495049514952495349544955495649574958495949604961496249634964496549664967496849694970497149724973497449754976497749784979498049814982498349844985498649874988498949904991499249934994499549964997499849995000500150025003500450055006500750085009501050115012501350145015501650175018501950205021502250235024502550265027502850295030503150325033503450355036503750385039504050415042504350445045504650475048504950505051505250535054505550565057505850595060506150625063506450655066506750685069507050715072507350745075507650775078507950805081508250835084508550865087508850895090509150925093509450955096509750985099510051015102510351045105510651075108510951105111511251135114511551165117511851195120512151225123512451255126512751285129513051315132513351345135513651375138513951405141514251435144514551465147514851495150515151525153515451555156515751585159516051615162516351645165516651675168516951705171517251735174517551765177517851795180518151825183518451855186518751885189519051915192519351945195519651975198519952005201520252035204520552065207520852095210521152125213521452155216521752185219522052215222522352245225522652275228522952305231523252335234523552365237523852395240524152425243524452455246524752485249525052515252525352545255525652575258525952605261526252635264526552665267526852695270527152725273527452755276527752785279528052815282528352845285528652875288528952905291529252935294529552965297529852995300530153025303530453055306530753085309531053115312531353145315531653175318531953205321532253235324532553265327532853295330533153325333533453355336533753385339534053415342534353445345534653475348534953505351535253535354535553565357535853595360536153625363536453655366536753685369537053715372537353745375537653775378537953805381538253835384538553865387538853895390539153925393539453955396539753985399540054015402540354045405540654075408540954105411541254135414541554165417541854195420542154225423542454255426542754285429543054315432543354345435543654375438543954405441544254435444544554465447544854495450545154525453545454555456545754585459546054615462546354645465546654675468546954705471547254735474547554765477547854795480548154825483548454855486548754885489549054915492549354945495549654975498549955005501550255035504550555065507550855095510551155125513551455155516551755185519552055215522552355245525552655275528
  1. /******************************************************************************
  2. *
  3. * GPL LICENSE SUMMARY
  4. *
  5. * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of version 2 of the GNU General Public License as
  9. * published by the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful, but
  12. * WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  14. * General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
  19. * USA
  20. *
  21. * The full GNU General Public License is included in this distribution
  22. * in the file called LICENSE.GPL.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *****************************************************************************/
  28. #include <linux/kernel.h>
  29. #include <linux/module.h>
  30. #include <linux/etherdevice.h>
  31. #include <linux/sched.h>
  32. #include <linux/slab.h>
  33. #include <linux/types.h>
  34. #include <linux/lockdep.h>
  35. #include <linux/pci.h>
  36. #include <linux/dma-mapping.h>
  37. #include <linux/delay.h>
  38. #include <linux/skbuff.h>
  39. #include <net/mac80211.h>
  40. #include "common.h"
  41. int
  42. _il_poll_bit(struct il_priv *il, u32 addr, u32 bits, u32 mask, int timeout)
  43. {
  44. const int interval = 10; /* microseconds */
  45. int t = 0;
  46. do {
  47. if ((_il_rd(il, addr) & mask) == (bits & mask))
  48. return t;
  49. udelay(interval);
  50. t += interval;
  51. } while (t < timeout);
  52. return -ETIMEDOUT;
  53. }
  54. EXPORT_SYMBOL(_il_poll_bit);
  55. void
  56. il_set_bit(struct il_priv *p, u32 r, u32 m)
  57. {
  58. unsigned long reg_flags;
  59. spin_lock_irqsave(&p->reg_lock, reg_flags);
  60. _il_set_bit(p, r, m);
  61. spin_unlock_irqrestore(&p->reg_lock, reg_flags);
  62. }
  63. EXPORT_SYMBOL(il_set_bit);
  64. void
  65. il_clear_bit(struct il_priv *p, u32 r, u32 m)
  66. {
  67. unsigned long reg_flags;
  68. spin_lock_irqsave(&p->reg_lock, reg_flags);
  69. _il_clear_bit(p, r, m);
  70. spin_unlock_irqrestore(&p->reg_lock, reg_flags);
  71. }
  72. EXPORT_SYMBOL(il_clear_bit);
  73. bool
  74. _il_grab_nic_access(struct il_priv *il)
  75. {
  76. int ret;
  77. u32 val;
  78. /* this bit wakes up the NIC */
  79. _il_set_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  80. /*
  81. * These bits say the device is running, and should keep running for
  82. * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
  83. * but they do not indicate that embedded SRAM is restored yet;
  84. * 3945 and 4965 have volatile SRAM, and must save/restore contents
  85. * to/from host DRAM when sleeping/waking for power-saving.
  86. * Each direction takes approximately 1/4 millisecond; with this
  87. * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
  88. * series of register accesses are expected (e.g. reading Event Log),
  89. * to keep device from sleeping.
  90. *
  91. * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
  92. * SRAM is okay/restored. We don't check that here because this call
  93. * is just for hardware register access; but GP1 MAC_SLEEP check is a
  94. * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
  95. *
  96. */
  97. ret =
  98. _il_poll_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
  99. (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
  100. CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
  101. if (unlikely(ret < 0)) {
  102. val = _il_rd(il, CSR_GP_CNTRL);
  103. WARN_ONCE(1, "Timeout waiting for ucode processor access "
  104. "(CSR_GP_CNTRL 0x%08x)\n", val);
  105. _il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
  106. return false;
  107. }
  108. return true;
  109. }
  110. EXPORT_SYMBOL_GPL(_il_grab_nic_access);
  111. int
  112. il_poll_bit(struct il_priv *il, u32 addr, u32 mask, int timeout)
  113. {
  114. const int interval = 10; /* microseconds */
  115. int t = 0;
  116. do {
  117. if ((il_rd(il, addr) & mask) == mask)
  118. return t;
  119. udelay(interval);
  120. t += interval;
  121. } while (t < timeout);
  122. return -ETIMEDOUT;
  123. }
  124. EXPORT_SYMBOL(il_poll_bit);
  125. u32
  126. il_rd_prph(struct il_priv *il, u32 reg)
  127. {
  128. unsigned long reg_flags;
  129. u32 val;
  130. spin_lock_irqsave(&il->reg_lock, reg_flags);
  131. _il_grab_nic_access(il);
  132. val = _il_rd_prph(il, reg);
  133. _il_release_nic_access(il);
  134. spin_unlock_irqrestore(&il->reg_lock, reg_flags);
  135. return val;
  136. }
  137. EXPORT_SYMBOL(il_rd_prph);
  138. void
  139. il_wr_prph(struct il_priv *il, u32 addr, u32 val)
  140. {
  141. unsigned long reg_flags;
  142. spin_lock_irqsave(&il->reg_lock, reg_flags);
  143. if (likely(_il_grab_nic_access(il))) {
  144. _il_wr_prph(il, addr, val);
  145. _il_release_nic_access(il);
  146. }
  147. spin_unlock_irqrestore(&il->reg_lock, reg_flags);
  148. }
  149. EXPORT_SYMBOL(il_wr_prph);
  150. u32
  151. il_read_targ_mem(struct il_priv *il, u32 addr)
  152. {
  153. unsigned long reg_flags;
  154. u32 value;
  155. spin_lock_irqsave(&il->reg_lock, reg_flags);
  156. _il_grab_nic_access(il);
  157. _il_wr(il, HBUS_TARG_MEM_RADDR, addr);
  158. value = _il_rd(il, HBUS_TARG_MEM_RDAT);
  159. _il_release_nic_access(il);
  160. spin_unlock_irqrestore(&il->reg_lock, reg_flags);
  161. return value;
  162. }
  163. EXPORT_SYMBOL(il_read_targ_mem);
  164. void
  165. il_write_targ_mem(struct il_priv *il, u32 addr, u32 val)
  166. {
  167. unsigned long reg_flags;
  168. spin_lock_irqsave(&il->reg_lock, reg_flags);
  169. if (likely(_il_grab_nic_access(il))) {
  170. _il_wr(il, HBUS_TARG_MEM_WADDR, addr);
  171. _il_wr(il, HBUS_TARG_MEM_WDAT, val);
  172. _il_release_nic_access(il);
  173. }
  174. spin_unlock_irqrestore(&il->reg_lock, reg_flags);
  175. }
  176. EXPORT_SYMBOL(il_write_targ_mem);
  177. const char *
  178. il_get_cmd_string(u8 cmd)
  179. {
  180. switch (cmd) {
  181. IL_CMD(N_ALIVE);
  182. IL_CMD(N_ERROR);
  183. IL_CMD(C_RXON);
  184. IL_CMD(C_RXON_ASSOC);
  185. IL_CMD(C_QOS_PARAM);
  186. IL_CMD(C_RXON_TIMING);
  187. IL_CMD(C_ADD_STA);
  188. IL_CMD(C_REM_STA);
  189. IL_CMD(C_WEPKEY);
  190. IL_CMD(N_3945_RX);
  191. IL_CMD(C_TX);
  192. IL_CMD(C_RATE_SCALE);
  193. IL_CMD(C_LEDS);
  194. IL_CMD(C_TX_LINK_QUALITY_CMD);
  195. IL_CMD(C_CHANNEL_SWITCH);
  196. IL_CMD(N_CHANNEL_SWITCH);
  197. IL_CMD(C_SPECTRUM_MEASUREMENT);
  198. IL_CMD(N_SPECTRUM_MEASUREMENT);
  199. IL_CMD(C_POWER_TBL);
  200. IL_CMD(N_PM_SLEEP);
  201. IL_CMD(N_PM_DEBUG_STATS);
  202. IL_CMD(C_SCAN);
  203. IL_CMD(C_SCAN_ABORT);
  204. IL_CMD(N_SCAN_START);
  205. IL_CMD(N_SCAN_RESULTS);
  206. IL_CMD(N_SCAN_COMPLETE);
  207. IL_CMD(N_BEACON);
  208. IL_CMD(C_TX_BEACON);
  209. IL_CMD(C_TX_PWR_TBL);
  210. IL_CMD(C_BT_CONFIG);
  211. IL_CMD(C_STATS);
  212. IL_CMD(N_STATS);
  213. IL_CMD(N_CARD_STATE);
  214. IL_CMD(N_MISSED_BEACONS);
  215. IL_CMD(C_CT_KILL_CONFIG);
  216. IL_CMD(C_SENSITIVITY);
  217. IL_CMD(C_PHY_CALIBRATION);
  218. IL_CMD(N_RX_PHY);
  219. IL_CMD(N_RX_MPDU);
  220. IL_CMD(N_RX);
  221. IL_CMD(N_COMPRESSED_BA);
  222. default:
  223. return "UNKNOWN";
  224. }
  225. }
  226. EXPORT_SYMBOL(il_get_cmd_string);
  227. #define HOST_COMPLETE_TIMEOUT (HZ / 2)
  228. static void
  229. il_generic_cmd_callback(struct il_priv *il, struct il_device_cmd *cmd,
  230. struct il_rx_pkt *pkt)
  231. {
  232. if (pkt->hdr.flags & IL_CMD_FAILED_MSK) {
  233. IL_ERR("Bad return from %s (0x%08X)\n",
  234. il_get_cmd_string(cmd->hdr.cmd), pkt->hdr.flags);
  235. return;
  236. }
  237. #ifdef CONFIG_IWLEGACY_DEBUG
  238. switch (cmd->hdr.cmd) {
  239. case C_TX_LINK_QUALITY_CMD:
  240. case C_SENSITIVITY:
  241. D_HC_DUMP("back from %s (0x%08X)\n",
  242. il_get_cmd_string(cmd->hdr.cmd), pkt->hdr.flags);
  243. break;
  244. default:
  245. D_HC("back from %s (0x%08X)\n", il_get_cmd_string(cmd->hdr.cmd),
  246. pkt->hdr.flags);
  247. }
  248. #endif
  249. }
  250. static int
  251. il_send_cmd_async(struct il_priv *il, struct il_host_cmd *cmd)
  252. {
  253. int ret;
  254. BUG_ON(!(cmd->flags & CMD_ASYNC));
  255. /* An asynchronous command can not expect an SKB to be set. */
  256. BUG_ON(cmd->flags & CMD_WANT_SKB);
  257. /* Assign a generic callback if one is not provided */
  258. if (!cmd->callback)
  259. cmd->callback = il_generic_cmd_callback;
  260. if (test_bit(S_EXIT_PENDING, &il->status))
  261. return -EBUSY;
  262. ret = il_enqueue_hcmd(il, cmd);
  263. if (ret < 0) {
  264. IL_ERR("Error sending %s: enqueue_hcmd failed: %d\n",
  265. il_get_cmd_string(cmd->id), ret);
  266. return ret;
  267. }
  268. return 0;
  269. }
  270. int
  271. il_send_cmd_sync(struct il_priv *il, struct il_host_cmd *cmd)
  272. {
  273. int cmd_idx;
  274. int ret;
  275. lockdep_assert_held(&il->mutex);
  276. BUG_ON(cmd->flags & CMD_ASYNC);
  277. /* A synchronous command can not have a callback set. */
  278. BUG_ON(cmd->callback);
  279. D_INFO("Attempting to send sync command %s\n",
  280. il_get_cmd_string(cmd->id));
  281. set_bit(S_HCMD_ACTIVE, &il->status);
  282. D_INFO("Setting HCMD_ACTIVE for command %s\n",
  283. il_get_cmd_string(cmd->id));
  284. cmd_idx = il_enqueue_hcmd(il, cmd);
  285. if (cmd_idx < 0) {
  286. ret = cmd_idx;
  287. IL_ERR("Error sending %s: enqueue_hcmd failed: %d\n",
  288. il_get_cmd_string(cmd->id), ret);
  289. goto out;
  290. }
  291. ret = wait_event_timeout(il->wait_command_queue,
  292. !test_bit(S_HCMD_ACTIVE, &il->status),
  293. HOST_COMPLETE_TIMEOUT);
  294. if (!ret) {
  295. if (test_bit(S_HCMD_ACTIVE, &il->status)) {
  296. IL_ERR("Error sending %s: time out after %dms.\n",
  297. il_get_cmd_string(cmd->id),
  298. jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
  299. clear_bit(S_HCMD_ACTIVE, &il->status);
  300. D_INFO("Clearing HCMD_ACTIVE for command %s\n",
  301. il_get_cmd_string(cmd->id));
  302. ret = -ETIMEDOUT;
  303. goto cancel;
  304. }
  305. }
  306. if (test_bit(S_RFKILL, &il->status)) {
  307. IL_ERR("Command %s aborted: RF KILL Switch\n",
  308. il_get_cmd_string(cmd->id));
  309. ret = -ECANCELED;
  310. goto fail;
  311. }
  312. if (test_bit(S_FW_ERROR, &il->status)) {
  313. IL_ERR("Command %s failed: FW Error\n",
  314. il_get_cmd_string(cmd->id));
  315. ret = -EIO;
  316. goto fail;
  317. }
  318. if ((cmd->flags & CMD_WANT_SKB) && !cmd->reply_page) {
  319. IL_ERR("Error: Response NULL in '%s'\n",
  320. il_get_cmd_string(cmd->id));
  321. ret = -EIO;
  322. goto cancel;
  323. }
  324. ret = 0;
  325. goto out;
  326. cancel:
  327. if (cmd->flags & CMD_WANT_SKB) {
  328. /*
  329. * Cancel the CMD_WANT_SKB flag for the cmd in the
  330. * TX cmd queue. Otherwise in case the cmd comes
  331. * in later, it will possibly set an invalid
  332. * address (cmd->meta.source).
  333. */
  334. il->txq[il->cmd_queue].meta[cmd_idx].flags &= ~CMD_WANT_SKB;
  335. }
  336. fail:
  337. if (cmd->reply_page) {
  338. il_free_pages(il, cmd->reply_page);
  339. cmd->reply_page = 0;
  340. }
  341. out:
  342. return ret;
  343. }
  344. EXPORT_SYMBOL(il_send_cmd_sync);
  345. int
  346. il_send_cmd(struct il_priv *il, struct il_host_cmd *cmd)
  347. {
  348. if (cmd->flags & CMD_ASYNC)
  349. return il_send_cmd_async(il, cmd);
  350. return il_send_cmd_sync(il, cmd);
  351. }
  352. EXPORT_SYMBOL(il_send_cmd);
  353. int
  354. il_send_cmd_pdu(struct il_priv *il, u8 id, u16 len, const void *data)
  355. {
  356. struct il_host_cmd cmd = {
  357. .id = id,
  358. .len = len,
  359. .data = data,
  360. };
  361. return il_send_cmd_sync(il, &cmd);
  362. }
  363. EXPORT_SYMBOL(il_send_cmd_pdu);
  364. int
  365. il_send_cmd_pdu_async(struct il_priv *il, u8 id, u16 len, const void *data,
  366. void (*callback) (struct il_priv *il,
  367. struct il_device_cmd *cmd,
  368. struct il_rx_pkt *pkt))
  369. {
  370. struct il_host_cmd cmd = {
  371. .id = id,
  372. .len = len,
  373. .data = data,
  374. };
  375. cmd.flags |= CMD_ASYNC;
  376. cmd.callback = callback;
  377. return il_send_cmd_async(il, &cmd);
  378. }
  379. EXPORT_SYMBOL(il_send_cmd_pdu_async);
  380. /* default: IL_LED_BLINK(0) using blinking idx table */
  381. static int led_mode;
  382. module_param(led_mode, int, S_IRUGO);
  383. MODULE_PARM_DESC(led_mode,
  384. "0=system default, " "1=On(RF On)/Off(RF Off), 2=blinking");
  385. /* Throughput OFF time(ms) ON time (ms)
  386. * >300 25 25
  387. * >200 to 300 40 40
  388. * >100 to 200 55 55
  389. * >70 to 100 65 65
  390. * >50 to 70 75 75
  391. * >20 to 50 85 85
  392. * >10 to 20 95 95
  393. * >5 to 10 110 110
  394. * >1 to 5 130 130
  395. * >0 to 1 167 167
  396. * <=0 SOLID ON
  397. */
  398. static const struct ieee80211_tpt_blink il_blink[] = {
  399. {.throughput = 0, .blink_time = 334},
  400. {.throughput = 1 * 1024 - 1, .blink_time = 260},
  401. {.throughput = 5 * 1024 - 1, .blink_time = 220},
  402. {.throughput = 10 * 1024 - 1, .blink_time = 190},
  403. {.throughput = 20 * 1024 - 1, .blink_time = 170},
  404. {.throughput = 50 * 1024 - 1, .blink_time = 150},
  405. {.throughput = 70 * 1024 - 1, .blink_time = 130},
  406. {.throughput = 100 * 1024 - 1, .blink_time = 110},
  407. {.throughput = 200 * 1024 - 1, .blink_time = 80},
  408. {.throughput = 300 * 1024 - 1, .blink_time = 50},
  409. };
  410. /*
  411. * Adjust led blink rate to compensate on a MAC Clock difference on every HW
  412. * Led blink rate analysis showed an average deviation of 0% on 3945,
  413. * 5% on 4965 HW.
  414. * Need to compensate on the led on/off time per HW according to the deviation
  415. * to achieve the desired led frequency
  416. * The calculation is: (100-averageDeviation)/100 * blinkTime
  417. * For code efficiency the calculation will be:
  418. * compensation = (100 - averageDeviation) * 64 / 100
  419. * NewBlinkTime = (compensation * BlinkTime) / 64
  420. */
  421. static inline u8
  422. il_blink_compensation(struct il_priv *il, u8 time, u16 compensation)
  423. {
  424. if (!compensation) {
  425. IL_ERR("undefined blink compensation: "
  426. "use pre-defined blinking time\n");
  427. return time;
  428. }
  429. return (u8) ((time * compensation) >> 6);
  430. }
  431. /* Set led pattern command */
  432. static int
  433. il_led_cmd(struct il_priv *il, unsigned long on, unsigned long off)
  434. {
  435. struct il_led_cmd led_cmd = {
  436. .id = IL_LED_LINK,
  437. .interval = IL_DEF_LED_INTRVL
  438. };
  439. int ret;
  440. if (!test_bit(S_READY, &il->status))
  441. return -EBUSY;
  442. if (il->blink_on == on && il->blink_off == off)
  443. return 0;
  444. if (off == 0) {
  445. /* led is SOLID_ON */
  446. on = IL_LED_SOLID;
  447. }
  448. D_LED("Led blink time compensation=%u\n",
  449. il->cfg->led_compensation);
  450. led_cmd.on =
  451. il_blink_compensation(il, on,
  452. il->cfg->led_compensation);
  453. led_cmd.off =
  454. il_blink_compensation(il, off,
  455. il->cfg->led_compensation);
  456. ret = il->ops->send_led_cmd(il, &led_cmd);
  457. if (!ret) {
  458. il->blink_on = on;
  459. il->blink_off = off;
  460. }
  461. return ret;
  462. }
  463. static void
  464. il_led_brightness_set(struct led_classdev *led_cdev,
  465. enum led_brightness brightness)
  466. {
  467. struct il_priv *il = container_of(led_cdev, struct il_priv, led);
  468. unsigned long on = 0;
  469. if (brightness > 0)
  470. on = IL_LED_SOLID;
  471. il_led_cmd(il, on, 0);
  472. }
  473. static int
  474. il_led_blink_set(struct led_classdev *led_cdev, unsigned long *delay_on,
  475. unsigned long *delay_off)
  476. {
  477. struct il_priv *il = container_of(led_cdev, struct il_priv, led);
  478. return il_led_cmd(il, *delay_on, *delay_off);
  479. }
  480. void
  481. il_leds_init(struct il_priv *il)
  482. {
  483. int mode = led_mode;
  484. int ret;
  485. if (mode == IL_LED_DEFAULT)
  486. mode = il->cfg->led_mode;
  487. il->led.name =
  488. kasprintf(GFP_KERNEL, "%s-led", wiphy_name(il->hw->wiphy));
  489. il->led.brightness_set = il_led_brightness_set;
  490. il->led.blink_set = il_led_blink_set;
  491. il->led.max_brightness = 1;
  492. switch (mode) {
  493. case IL_LED_DEFAULT:
  494. WARN_ON(1);
  495. break;
  496. case IL_LED_BLINK:
  497. il->led.default_trigger =
  498. ieee80211_create_tpt_led_trigger(il->hw,
  499. IEEE80211_TPT_LEDTRIG_FL_CONNECTED,
  500. il_blink,
  501. ARRAY_SIZE(il_blink));
  502. break;
  503. case IL_LED_RF_STATE:
  504. il->led.default_trigger = ieee80211_get_radio_led_name(il->hw);
  505. break;
  506. }
  507. ret = led_classdev_register(&il->pci_dev->dev, &il->led);
  508. if (ret) {
  509. kfree(il->led.name);
  510. return;
  511. }
  512. il->led_registered = true;
  513. }
  514. EXPORT_SYMBOL(il_leds_init);
  515. void
  516. il_leds_exit(struct il_priv *il)
  517. {
  518. if (!il->led_registered)
  519. return;
  520. led_classdev_unregister(&il->led);
  521. kfree(il->led.name);
  522. }
  523. EXPORT_SYMBOL(il_leds_exit);
  524. /************************** EEPROM BANDS ****************************
  525. *
  526. * The il_eeprom_band definitions below provide the mapping from the
  527. * EEPROM contents to the specific channel number supported for each
  528. * band.
  529. *
  530. * For example, il_priv->eeprom.band_3_channels[4] from the band_3
  531. * definition below maps to physical channel 42 in the 5.2GHz spectrum.
  532. * The specific geography and calibration information for that channel
  533. * is contained in the eeprom map itself.
  534. *
  535. * During init, we copy the eeprom information and channel map
  536. * information into il->channel_info_24/52 and il->channel_map_24/52
  537. *
  538. * channel_map_24/52 provides the idx in the channel_info array for a
  539. * given channel. We have to have two separate maps as there is channel
  540. * overlap with the 2.4GHz and 5.2GHz spectrum as seen in band_1 and
  541. * band_2
  542. *
  543. * A value of 0xff stored in the channel_map indicates that the channel
  544. * is not supported by the hardware at all.
  545. *
  546. * A value of 0xfe in the channel_map indicates that the channel is not
  547. * valid for Tx with the current hardware. This means that
  548. * while the system can tune and receive on a given channel, it may not
  549. * be able to associate or transmit any frames on that
  550. * channel. There is no corresponding channel information for that
  551. * entry.
  552. *
  553. *********************************************************************/
  554. /* 2.4 GHz */
  555. const u8 il_eeprom_band_1[14] = {
  556. 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
  557. };
  558. /* 5.2 GHz bands */
  559. static const u8 il_eeprom_band_2[] = { /* 4915-5080MHz */
  560. 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16
  561. };
  562. static const u8 il_eeprom_band_3[] = { /* 5170-5320MHz */
  563. 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
  564. };
  565. static const u8 il_eeprom_band_4[] = { /* 5500-5700MHz */
  566. 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
  567. };
  568. static const u8 il_eeprom_band_5[] = { /* 5725-5825MHz */
  569. 145, 149, 153, 157, 161, 165
  570. };
  571. static const u8 il_eeprom_band_6[] = { /* 2.4 ht40 channel */
  572. 1, 2, 3, 4, 5, 6, 7
  573. };
  574. static const u8 il_eeprom_band_7[] = { /* 5.2 ht40 channel */
  575. 36, 44, 52, 60, 100, 108, 116, 124, 132, 149, 157
  576. };
  577. /******************************************************************************
  578. *
  579. * EEPROM related functions
  580. *
  581. ******************************************************************************/
  582. static int
  583. il_eeprom_verify_signature(struct il_priv *il)
  584. {
  585. u32 gp = _il_rd(il, CSR_EEPROM_GP) & CSR_EEPROM_GP_VALID_MSK;
  586. int ret = 0;
  587. D_EEPROM("EEPROM signature=0x%08x\n", gp);
  588. switch (gp) {
  589. case CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K:
  590. case CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K:
  591. break;
  592. default:
  593. IL_ERR("bad EEPROM signature," "EEPROM_GP=0x%08x\n", gp);
  594. ret = -ENOENT;
  595. break;
  596. }
  597. return ret;
  598. }
  599. const u8 *
  600. il_eeprom_query_addr(const struct il_priv *il, size_t offset)
  601. {
  602. BUG_ON(offset >= il->cfg->eeprom_size);
  603. return &il->eeprom[offset];
  604. }
  605. EXPORT_SYMBOL(il_eeprom_query_addr);
  606. u16
  607. il_eeprom_query16(const struct il_priv *il, size_t offset)
  608. {
  609. if (!il->eeprom)
  610. return 0;
  611. return (u16) il->eeprom[offset] | ((u16) il->eeprom[offset + 1] << 8);
  612. }
  613. EXPORT_SYMBOL(il_eeprom_query16);
  614. /**
  615. * il_eeprom_init - read EEPROM contents
  616. *
  617. * Load the EEPROM contents from adapter into il->eeprom
  618. *
  619. * NOTE: This routine uses the non-debug IO access functions.
  620. */
  621. int
  622. il_eeprom_init(struct il_priv *il)
  623. {
  624. __le16 *e;
  625. u32 gp = _il_rd(il, CSR_EEPROM_GP);
  626. int sz;
  627. int ret;
  628. u16 addr;
  629. /* allocate eeprom */
  630. sz = il->cfg->eeprom_size;
  631. D_EEPROM("NVM size = %d\n", sz);
  632. il->eeprom = kzalloc(sz, GFP_KERNEL);
  633. if (!il->eeprom) {
  634. ret = -ENOMEM;
  635. goto alloc_err;
  636. }
  637. e = (__le16 *) il->eeprom;
  638. il->ops->apm_init(il);
  639. ret = il_eeprom_verify_signature(il);
  640. if (ret < 0) {
  641. IL_ERR("EEPROM not found, EEPROM_GP=0x%08x\n", gp);
  642. ret = -ENOENT;
  643. goto err;
  644. }
  645. /* Make sure driver (instead of uCode) is allowed to read EEPROM */
  646. ret = il->ops->eeprom_acquire_semaphore(il);
  647. if (ret < 0) {
  648. IL_ERR("Failed to acquire EEPROM semaphore.\n");
  649. ret = -ENOENT;
  650. goto err;
  651. }
  652. /* eeprom is an array of 16bit values */
  653. for (addr = 0; addr < sz; addr += sizeof(u16)) {
  654. u32 r;
  655. _il_wr(il, CSR_EEPROM_REG,
  656. CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
  657. ret =
  658. _il_poll_bit(il, CSR_EEPROM_REG,
  659. CSR_EEPROM_REG_READ_VALID_MSK,
  660. CSR_EEPROM_REG_READ_VALID_MSK,
  661. IL_EEPROM_ACCESS_TIMEOUT);
  662. if (ret < 0) {
  663. IL_ERR("Time out reading EEPROM[%d]\n", addr);
  664. goto done;
  665. }
  666. r = _il_rd(il, CSR_EEPROM_REG);
  667. e[addr / 2] = cpu_to_le16(r >> 16);
  668. }
  669. D_EEPROM("NVM Type: %s, version: 0x%x\n", "EEPROM",
  670. il_eeprom_query16(il, EEPROM_VERSION));
  671. ret = 0;
  672. done:
  673. il->ops->eeprom_release_semaphore(il);
  674. err:
  675. if (ret)
  676. il_eeprom_free(il);
  677. /* Reset chip to save power until we load uCode during "up". */
  678. il_apm_stop(il);
  679. alloc_err:
  680. return ret;
  681. }
  682. EXPORT_SYMBOL(il_eeprom_init);
  683. void
  684. il_eeprom_free(struct il_priv *il)
  685. {
  686. kfree(il->eeprom);
  687. il->eeprom = NULL;
  688. }
  689. EXPORT_SYMBOL(il_eeprom_free);
  690. static void
  691. il_init_band_reference(const struct il_priv *il, int eep_band,
  692. int *eeprom_ch_count,
  693. const struct il_eeprom_channel **eeprom_ch_info,
  694. const u8 **eeprom_ch_idx)
  695. {
  696. u32 offset = il->cfg->regulatory_bands[eep_band - 1];
  697. switch (eep_band) {
  698. case 1: /* 2.4GHz band */
  699. *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_1);
  700. *eeprom_ch_info =
  701. (struct il_eeprom_channel *)il_eeprom_query_addr(il,
  702. offset);
  703. *eeprom_ch_idx = il_eeprom_band_1;
  704. break;
  705. case 2: /* 4.9GHz band */
  706. *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_2);
  707. *eeprom_ch_info =
  708. (struct il_eeprom_channel *)il_eeprom_query_addr(il,
  709. offset);
  710. *eeprom_ch_idx = il_eeprom_band_2;
  711. break;
  712. case 3: /* 5.2GHz band */
  713. *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_3);
  714. *eeprom_ch_info =
  715. (struct il_eeprom_channel *)il_eeprom_query_addr(il,
  716. offset);
  717. *eeprom_ch_idx = il_eeprom_band_3;
  718. break;
  719. case 4: /* 5.5GHz band */
  720. *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_4);
  721. *eeprom_ch_info =
  722. (struct il_eeprom_channel *)il_eeprom_query_addr(il,
  723. offset);
  724. *eeprom_ch_idx = il_eeprom_band_4;
  725. break;
  726. case 5: /* 5.7GHz band */
  727. *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_5);
  728. *eeprom_ch_info =
  729. (struct il_eeprom_channel *)il_eeprom_query_addr(il,
  730. offset);
  731. *eeprom_ch_idx = il_eeprom_band_5;
  732. break;
  733. case 6: /* 2.4GHz ht40 channels */
  734. *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_6);
  735. *eeprom_ch_info =
  736. (struct il_eeprom_channel *)il_eeprom_query_addr(il,
  737. offset);
  738. *eeprom_ch_idx = il_eeprom_band_6;
  739. break;
  740. case 7: /* 5 GHz ht40 channels */
  741. *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_7);
  742. *eeprom_ch_info =
  743. (struct il_eeprom_channel *)il_eeprom_query_addr(il,
  744. offset);
  745. *eeprom_ch_idx = il_eeprom_band_7;
  746. break;
  747. default:
  748. BUG();
  749. }
  750. }
  751. #define CHECK_AND_PRINT(x) ((eeprom_ch->flags & EEPROM_CHANNEL_##x) \
  752. ? # x " " : "")
  753. /**
  754. * il_mod_ht40_chan_info - Copy ht40 channel info into driver's il.
  755. *
  756. * Does not set up a command, or touch hardware.
  757. */
  758. static int
  759. il_mod_ht40_chan_info(struct il_priv *il, enum ieee80211_band band, u16 channel,
  760. const struct il_eeprom_channel *eeprom_ch,
  761. u8 clear_ht40_extension_channel)
  762. {
  763. struct il_channel_info *ch_info;
  764. ch_info =
  765. (struct il_channel_info *)il_get_channel_info(il, band, channel);
  766. if (!il_is_channel_valid(ch_info))
  767. return -1;
  768. D_EEPROM("HT40 Ch. %d [%sGHz] %s%s%s%s%s(0x%02x %ddBm):"
  769. " Ad-Hoc %ssupported\n", ch_info->channel,
  770. il_is_channel_a_band(ch_info) ? "5.2" : "2.4",
  771. CHECK_AND_PRINT(IBSS), CHECK_AND_PRINT(ACTIVE),
  772. CHECK_AND_PRINT(RADAR), CHECK_AND_PRINT(WIDE),
  773. CHECK_AND_PRINT(DFS), eeprom_ch->flags,
  774. eeprom_ch->max_power_avg,
  775. ((eeprom_ch->flags & EEPROM_CHANNEL_IBSS) &&
  776. !(eeprom_ch->flags & EEPROM_CHANNEL_RADAR)) ? "" : "not ");
  777. ch_info->ht40_eeprom = *eeprom_ch;
  778. ch_info->ht40_max_power_avg = eeprom_ch->max_power_avg;
  779. ch_info->ht40_flags = eeprom_ch->flags;
  780. if (eeprom_ch->flags & EEPROM_CHANNEL_VALID)
  781. ch_info->ht40_extension_channel &=
  782. ~clear_ht40_extension_channel;
  783. return 0;
  784. }
  785. #define CHECK_AND_PRINT_I(x) ((eeprom_ch_info[ch].flags & EEPROM_CHANNEL_##x) \
  786. ? # x " " : "")
  787. /**
  788. * il_init_channel_map - Set up driver's info for all possible channels
  789. */
  790. int
  791. il_init_channel_map(struct il_priv *il)
  792. {
  793. int eeprom_ch_count = 0;
  794. const u8 *eeprom_ch_idx = NULL;
  795. const struct il_eeprom_channel *eeprom_ch_info = NULL;
  796. int band, ch;
  797. struct il_channel_info *ch_info;
  798. if (il->channel_count) {
  799. D_EEPROM("Channel map already initialized.\n");
  800. return 0;
  801. }
  802. D_EEPROM("Initializing regulatory info from EEPROM\n");
  803. il->channel_count =
  804. ARRAY_SIZE(il_eeprom_band_1) + ARRAY_SIZE(il_eeprom_band_2) +
  805. ARRAY_SIZE(il_eeprom_band_3) + ARRAY_SIZE(il_eeprom_band_4) +
  806. ARRAY_SIZE(il_eeprom_band_5);
  807. D_EEPROM("Parsing data for %d channels.\n", il->channel_count);
  808. il->channel_info =
  809. kzalloc(sizeof(struct il_channel_info) * il->channel_count,
  810. GFP_KERNEL);
  811. if (!il->channel_info) {
  812. IL_ERR("Could not allocate channel_info\n");
  813. il->channel_count = 0;
  814. return -ENOMEM;
  815. }
  816. ch_info = il->channel_info;
  817. /* Loop through the 5 EEPROM bands adding them in order to the
  818. * channel map we maintain (that contains additional information than
  819. * what just in the EEPROM) */
  820. for (band = 1; band <= 5; band++) {
  821. il_init_band_reference(il, band, &eeprom_ch_count,
  822. &eeprom_ch_info, &eeprom_ch_idx);
  823. /* Loop through each band adding each of the channels */
  824. for (ch = 0; ch < eeprom_ch_count; ch++) {
  825. ch_info->channel = eeprom_ch_idx[ch];
  826. ch_info->band =
  827. (band ==
  828. 1) ? IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
  829. /* permanently store EEPROM's channel regulatory flags
  830. * and max power in channel info database. */
  831. ch_info->eeprom = eeprom_ch_info[ch];
  832. /* Copy the run-time flags so they are there even on
  833. * invalid channels */
  834. ch_info->flags = eeprom_ch_info[ch].flags;
  835. /* First write that ht40 is not enabled, and then enable
  836. * one by one */
  837. ch_info->ht40_extension_channel =
  838. IEEE80211_CHAN_NO_HT40;
  839. if (!(il_is_channel_valid(ch_info))) {
  840. D_EEPROM("Ch. %d Flags %x [%sGHz] - "
  841. "No traffic\n", ch_info->channel,
  842. ch_info->flags,
  843. il_is_channel_a_band(ch_info) ? "5.2" :
  844. "2.4");
  845. ch_info++;
  846. continue;
  847. }
  848. /* Initialize regulatory-based run-time data */
  849. ch_info->max_power_avg = ch_info->curr_txpow =
  850. eeprom_ch_info[ch].max_power_avg;
  851. ch_info->scan_power = eeprom_ch_info[ch].max_power_avg;
  852. ch_info->min_power = 0;
  853. D_EEPROM("Ch. %d [%sGHz] " "%s%s%s%s%s%s(0x%02x %ddBm):"
  854. " Ad-Hoc %ssupported\n", ch_info->channel,
  855. il_is_channel_a_band(ch_info) ? "5.2" : "2.4",
  856. CHECK_AND_PRINT_I(VALID),
  857. CHECK_AND_PRINT_I(IBSS),
  858. CHECK_AND_PRINT_I(ACTIVE),
  859. CHECK_AND_PRINT_I(RADAR),
  860. CHECK_AND_PRINT_I(WIDE),
  861. CHECK_AND_PRINT_I(DFS),
  862. eeprom_ch_info[ch].flags,
  863. eeprom_ch_info[ch].max_power_avg,
  864. ((eeprom_ch_info[ch].
  865. flags & EEPROM_CHANNEL_IBSS) &&
  866. !(eeprom_ch_info[ch].
  867. flags & EEPROM_CHANNEL_RADAR)) ? "" :
  868. "not ");
  869. ch_info++;
  870. }
  871. }
  872. /* Check if we do have HT40 channels */
  873. if (il->cfg->regulatory_bands[5] == EEPROM_REGULATORY_BAND_NO_HT40 &&
  874. il->cfg->regulatory_bands[6] == EEPROM_REGULATORY_BAND_NO_HT40)
  875. return 0;
  876. /* Two additional EEPROM bands for 2.4 and 5 GHz HT40 channels */
  877. for (band = 6; band <= 7; band++) {
  878. enum ieee80211_band ieeeband;
  879. il_init_band_reference(il, band, &eeprom_ch_count,
  880. &eeprom_ch_info, &eeprom_ch_idx);
  881. /* EEPROM band 6 is 2.4, band 7 is 5 GHz */
  882. ieeeband =
  883. (band == 6) ? IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
  884. /* Loop through each band adding each of the channels */
  885. for (ch = 0; ch < eeprom_ch_count; ch++) {
  886. /* Set up driver's info for lower half */
  887. il_mod_ht40_chan_info(il, ieeeband, eeprom_ch_idx[ch],
  888. &eeprom_ch_info[ch],
  889. IEEE80211_CHAN_NO_HT40PLUS);
  890. /* Set up driver's info for upper half */
  891. il_mod_ht40_chan_info(il, ieeeband,
  892. eeprom_ch_idx[ch] + 4,
  893. &eeprom_ch_info[ch],
  894. IEEE80211_CHAN_NO_HT40MINUS);
  895. }
  896. }
  897. return 0;
  898. }
  899. EXPORT_SYMBOL(il_init_channel_map);
  900. /*
  901. * il_free_channel_map - undo allocations in il_init_channel_map
  902. */
  903. void
  904. il_free_channel_map(struct il_priv *il)
  905. {
  906. kfree(il->channel_info);
  907. il->channel_count = 0;
  908. }
  909. EXPORT_SYMBOL(il_free_channel_map);
  910. /**
  911. * il_get_channel_info - Find driver's ilate channel info
  912. *
  913. * Based on band and channel number.
  914. */
  915. const struct il_channel_info *
  916. il_get_channel_info(const struct il_priv *il, enum ieee80211_band band,
  917. u16 channel)
  918. {
  919. int i;
  920. switch (band) {
  921. case IEEE80211_BAND_5GHZ:
  922. for (i = 14; i < il->channel_count; i++) {
  923. if (il->channel_info[i].channel == channel)
  924. return &il->channel_info[i];
  925. }
  926. break;
  927. case IEEE80211_BAND_2GHZ:
  928. if (channel >= 1 && channel <= 14)
  929. return &il->channel_info[channel - 1];
  930. break;
  931. default:
  932. BUG();
  933. }
  934. return NULL;
  935. }
  936. EXPORT_SYMBOL(il_get_channel_info);
  937. /*
  938. * Setting power level allows the card to go to sleep when not busy.
  939. *
  940. * We calculate a sleep command based on the required latency, which
  941. * we get from mac80211. In order to handle thermal throttling, we can
  942. * also use pre-defined power levels.
  943. */
  944. /*
  945. * This defines the old power levels. They are still used by default
  946. * (level 1) and for thermal throttle (levels 3 through 5)
  947. */
  948. struct il_power_vec_entry {
  949. struct il_powertable_cmd cmd;
  950. u8 no_dtim; /* number of skip dtim */
  951. };
  952. static void
  953. il_power_sleep_cam_cmd(struct il_priv *il, struct il_powertable_cmd *cmd)
  954. {
  955. memset(cmd, 0, sizeof(*cmd));
  956. if (il->power_data.pci_pm)
  957. cmd->flags |= IL_POWER_PCI_PM_MSK;
  958. D_POWER("Sleep command for CAM\n");
  959. }
  960. static int
  961. il_set_power(struct il_priv *il, struct il_powertable_cmd *cmd)
  962. {
  963. D_POWER("Sending power/sleep command\n");
  964. D_POWER("Flags value = 0x%08X\n", cmd->flags);
  965. D_POWER("Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout));
  966. D_POWER("Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout));
  967. D_POWER("Sleep interval vector = { %d , %d , %d , %d , %d }\n",
  968. le32_to_cpu(cmd->sleep_interval[0]),
  969. le32_to_cpu(cmd->sleep_interval[1]),
  970. le32_to_cpu(cmd->sleep_interval[2]),
  971. le32_to_cpu(cmd->sleep_interval[3]),
  972. le32_to_cpu(cmd->sleep_interval[4]));
  973. return il_send_cmd_pdu(il, C_POWER_TBL,
  974. sizeof(struct il_powertable_cmd), cmd);
  975. }
  976. static int
  977. il_power_set_mode(struct il_priv *il, struct il_powertable_cmd *cmd, bool force)
  978. {
  979. int ret;
  980. bool update_chains;
  981. lockdep_assert_held(&il->mutex);
  982. /* Don't update the RX chain when chain noise calibration is running */
  983. update_chains = il->chain_noise_data.state == IL_CHAIN_NOISE_DONE ||
  984. il->chain_noise_data.state == IL_CHAIN_NOISE_ALIVE;
  985. if (!memcmp(&il->power_data.sleep_cmd, cmd, sizeof(*cmd)) && !force)
  986. return 0;
  987. if (!il_is_ready_rf(il))
  988. return -EIO;
  989. /* scan complete use sleep_power_next, need to be updated */
  990. memcpy(&il->power_data.sleep_cmd_next, cmd, sizeof(*cmd));
  991. if (test_bit(S_SCANNING, &il->status) && !force) {
  992. D_INFO("Defer power set mode while scanning\n");
  993. return 0;
  994. }
  995. if (cmd->flags & IL_POWER_DRIVER_ALLOW_SLEEP_MSK)
  996. set_bit(S_POWER_PMI, &il->status);
  997. ret = il_set_power(il, cmd);
  998. if (!ret) {
  999. if (!(cmd->flags & IL_POWER_DRIVER_ALLOW_SLEEP_MSK))
  1000. clear_bit(S_POWER_PMI, &il->status);
  1001. if (il->ops->update_chain_flags && update_chains)
  1002. il->ops->update_chain_flags(il);
  1003. else if (il->ops->update_chain_flags)
  1004. D_POWER("Cannot update the power, chain noise "
  1005. "calibration running: %d\n",
  1006. il->chain_noise_data.state);
  1007. memcpy(&il->power_data.sleep_cmd, cmd, sizeof(*cmd));
  1008. } else
  1009. IL_ERR("set power fail, ret = %d", ret);
  1010. return ret;
  1011. }
  1012. int
  1013. il_power_update_mode(struct il_priv *il, bool force)
  1014. {
  1015. struct il_powertable_cmd cmd;
  1016. il_power_sleep_cam_cmd(il, &cmd);
  1017. return il_power_set_mode(il, &cmd, force);
  1018. }
  1019. EXPORT_SYMBOL(il_power_update_mode);
  1020. /* initialize to default */
  1021. void
  1022. il_power_initialize(struct il_priv *il)
  1023. {
  1024. u16 lctl;
  1025. pcie_capability_read_word(il->pci_dev, PCI_EXP_LNKCTL, &lctl);
  1026. il->power_data.pci_pm = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
  1027. il->power_data.debug_sleep_level_override = -1;
  1028. memset(&il->power_data.sleep_cmd, 0, sizeof(il->power_data.sleep_cmd));
  1029. }
  1030. EXPORT_SYMBOL(il_power_initialize);
  1031. /* For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after
  1032. * sending probe req. This should be set long enough to hear probe responses
  1033. * from more than one AP. */
  1034. #define IL_ACTIVE_DWELL_TIME_24 (30) /* all times in msec */
  1035. #define IL_ACTIVE_DWELL_TIME_52 (20)
  1036. #define IL_ACTIVE_DWELL_FACTOR_24GHZ (3)
  1037. #define IL_ACTIVE_DWELL_FACTOR_52GHZ (2)
  1038. /* For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel.
  1039. * Must be set longer than active dwell time.
  1040. * For the most reliable scan, set > AP beacon interval (typically 100msec). */
  1041. #define IL_PASSIVE_DWELL_TIME_24 (20) /* all times in msec */
  1042. #define IL_PASSIVE_DWELL_TIME_52 (10)
  1043. #define IL_PASSIVE_DWELL_BASE (100)
  1044. #define IL_CHANNEL_TUNE_TIME 5
  1045. static int
  1046. il_send_scan_abort(struct il_priv *il)
  1047. {
  1048. int ret;
  1049. struct il_rx_pkt *pkt;
  1050. struct il_host_cmd cmd = {
  1051. .id = C_SCAN_ABORT,
  1052. .flags = CMD_WANT_SKB,
  1053. };
  1054. /* Exit instantly with error when device is not ready
  1055. * to receive scan abort command or it does not perform
  1056. * hardware scan currently */
  1057. if (!test_bit(S_READY, &il->status) ||
  1058. !test_bit(S_GEO_CONFIGURED, &il->status) ||
  1059. !test_bit(S_SCAN_HW, &il->status) ||
  1060. test_bit(S_FW_ERROR, &il->status) ||
  1061. test_bit(S_EXIT_PENDING, &il->status))
  1062. return -EIO;
  1063. ret = il_send_cmd_sync(il, &cmd);
  1064. if (ret)
  1065. return ret;
  1066. pkt = (struct il_rx_pkt *)cmd.reply_page;
  1067. if (pkt->u.status != CAN_ABORT_STATUS) {
  1068. /* The scan abort will return 1 for success or
  1069. * 2 for "failure". A failure condition can be
  1070. * due to simply not being in an active scan which
  1071. * can occur if we send the scan abort before we
  1072. * the microcode has notified us that a scan is
  1073. * completed. */
  1074. D_SCAN("SCAN_ABORT ret %d.\n", pkt->u.status);
  1075. ret = -EIO;
  1076. }
  1077. il_free_pages(il, cmd.reply_page);
  1078. return ret;
  1079. }
  1080. static void
  1081. il_complete_scan(struct il_priv *il, bool aborted)
  1082. {
  1083. /* check if scan was requested from mac80211 */
  1084. if (il->scan_request) {
  1085. D_SCAN("Complete scan in mac80211\n");
  1086. ieee80211_scan_completed(il->hw, aborted);
  1087. }
  1088. il->scan_vif = NULL;
  1089. il->scan_request = NULL;
  1090. }
  1091. void
  1092. il_force_scan_end(struct il_priv *il)
  1093. {
  1094. lockdep_assert_held(&il->mutex);
  1095. if (!test_bit(S_SCANNING, &il->status)) {
  1096. D_SCAN("Forcing scan end while not scanning\n");
  1097. return;
  1098. }
  1099. D_SCAN("Forcing scan end\n");
  1100. clear_bit(S_SCANNING, &il->status);
  1101. clear_bit(S_SCAN_HW, &il->status);
  1102. clear_bit(S_SCAN_ABORTING, &il->status);
  1103. il_complete_scan(il, true);
  1104. }
  1105. static void
  1106. il_do_scan_abort(struct il_priv *il)
  1107. {
  1108. int ret;
  1109. lockdep_assert_held(&il->mutex);
  1110. if (!test_bit(S_SCANNING, &il->status)) {
  1111. D_SCAN("Not performing scan to abort\n");
  1112. return;
  1113. }
  1114. if (test_and_set_bit(S_SCAN_ABORTING, &il->status)) {
  1115. D_SCAN("Scan abort in progress\n");
  1116. return;
  1117. }
  1118. ret = il_send_scan_abort(il);
  1119. if (ret) {
  1120. D_SCAN("Send scan abort failed %d\n", ret);
  1121. il_force_scan_end(il);
  1122. } else
  1123. D_SCAN("Successfully send scan abort\n");
  1124. }
  1125. /**
  1126. * il_scan_cancel - Cancel any currently executing HW scan
  1127. */
  1128. int
  1129. il_scan_cancel(struct il_priv *il)
  1130. {
  1131. D_SCAN("Queuing abort scan\n");
  1132. queue_work(il->workqueue, &il->abort_scan);
  1133. return 0;
  1134. }
  1135. EXPORT_SYMBOL(il_scan_cancel);
  1136. /**
  1137. * il_scan_cancel_timeout - Cancel any currently executing HW scan
  1138. * @ms: amount of time to wait (in milliseconds) for scan to abort
  1139. *
  1140. */
  1141. int
  1142. il_scan_cancel_timeout(struct il_priv *il, unsigned long ms)
  1143. {
  1144. unsigned long timeout = jiffies + msecs_to_jiffies(ms);
  1145. lockdep_assert_held(&il->mutex);
  1146. D_SCAN("Scan cancel timeout\n");
  1147. il_do_scan_abort(il);
  1148. while (time_before_eq(jiffies, timeout)) {
  1149. if (!test_bit(S_SCAN_HW, &il->status))
  1150. break;
  1151. msleep(20);
  1152. }
  1153. return test_bit(S_SCAN_HW, &il->status);
  1154. }
  1155. EXPORT_SYMBOL(il_scan_cancel_timeout);
  1156. /* Service response to C_SCAN (0x80) */
  1157. static void
  1158. il_hdl_scan(struct il_priv *il, struct il_rx_buf *rxb)
  1159. {
  1160. #ifdef CONFIG_IWLEGACY_DEBUG
  1161. struct il_rx_pkt *pkt = rxb_addr(rxb);
  1162. struct il_scanreq_notification *notif =
  1163. (struct il_scanreq_notification *)pkt->u.raw;
  1164. D_SCAN("Scan request status = 0x%x\n", notif->status);
  1165. #endif
  1166. }
  1167. /* Service N_SCAN_START (0x82) */
  1168. static void
  1169. il_hdl_scan_start(struct il_priv *il, struct il_rx_buf *rxb)
  1170. {
  1171. struct il_rx_pkt *pkt = rxb_addr(rxb);
  1172. struct il_scanstart_notification *notif =
  1173. (struct il_scanstart_notification *)pkt->u.raw;
  1174. il->scan_start_tsf = le32_to_cpu(notif->tsf_low);
  1175. D_SCAN("Scan start: " "%d [802.11%s] "
  1176. "(TSF: 0x%08X:%08X) - %d (beacon timer %u)\n", notif->channel,
  1177. notif->band ? "bg" : "a", le32_to_cpu(notif->tsf_high),
  1178. le32_to_cpu(notif->tsf_low), notif->status, notif->beacon_timer);
  1179. }
  1180. /* Service N_SCAN_RESULTS (0x83) */
  1181. static void
  1182. il_hdl_scan_results(struct il_priv *il, struct il_rx_buf *rxb)
  1183. {
  1184. #ifdef CONFIG_IWLEGACY_DEBUG
  1185. struct il_rx_pkt *pkt = rxb_addr(rxb);
  1186. struct il_scanresults_notification *notif =
  1187. (struct il_scanresults_notification *)pkt->u.raw;
  1188. D_SCAN("Scan ch.res: " "%d [802.11%s] " "(TSF: 0x%08X:%08X) - %d "
  1189. "elapsed=%lu usec\n", notif->channel, notif->band ? "bg" : "a",
  1190. le32_to_cpu(notif->tsf_high), le32_to_cpu(notif->tsf_low),
  1191. le32_to_cpu(notif->stats[0]),
  1192. le32_to_cpu(notif->tsf_low) - il->scan_start_tsf);
  1193. #endif
  1194. }
  1195. /* Service N_SCAN_COMPLETE (0x84) */
  1196. static void
  1197. il_hdl_scan_complete(struct il_priv *il, struct il_rx_buf *rxb)
  1198. {
  1199. #ifdef CONFIG_IWLEGACY_DEBUG
  1200. struct il_rx_pkt *pkt = rxb_addr(rxb);
  1201. struct il_scancomplete_notification *scan_notif = (void *)pkt->u.raw;
  1202. #endif
  1203. D_SCAN("Scan complete: %d channels (TSF 0x%08X:%08X) - %d\n",
  1204. scan_notif->scanned_channels, scan_notif->tsf_low,
  1205. scan_notif->tsf_high, scan_notif->status);
  1206. /* The HW is no longer scanning */
  1207. clear_bit(S_SCAN_HW, &il->status);
  1208. D_SCAN("Scan on %sGHz took %dms\n",
  1209. (il->scan_band == IEEE80211_BAND_2GHZ) ? "2.4" : "5.2",
  1210. jiffies_to_msecs(jiffies - il->scan_start));
  1211. queue_work(il->workqueue, &il->scan_completed);
  1212. }
  1213. void
  1214. il_setup_rx_scan_handlers(struct il_priv *il)
  1215. {
  1216. /* scan handlers */
  1217. il->handlers[C_SCAN] = il_hdl_scan;
  1218. il->handlers[N_SCAN_START] = il_hdl_scan_start;
  1219. il->handlers[N_SCAN_RESULTS] = il_hdl_scan_results;
  1220. il->handlers[N_SCAN_COMPLETE] = il_hdl_scan_complete;
  1221. }
  1222. EXPORT_SYMBOL(il_setup_rx_scan_handlers);
  1223. u16
  1224. il_get_active_dwell_time(struct il_priv *il, enum ieee80211_band band,
  1225. u8 n_probes)
  1226. {
  1227. if (band == IEEE80211_BAND_5GHZ)
  1228. return IL_ACTIVE_DWELL_TIME_52 +
  1229. IL_ACTIVE_DWELL_FACTOR_52GHZ * (n_probes + 1);
  1230. else
  1231. return IL_ACTIVE_DWELL_TIME_24 +
  1232. IL_ACTIVE_DWELL_FACTOR_24GHZ * (n_probes + 1);
  1233. }
  1234. EXPORT_SYMBOL(il_get_active_dwell_time);
  1235. u16
  1236. il_get_passive_dwell_time(struct il_priv *il, enum ieee80211_band band,
  1237. struct ieee80211_vif *vif)
  1238. {
  1239. u16 value;
  1240. u16 passive =
  1241. (band ==
  1242. IEEE80211_BAND_2GHZ) ? IL_PASSIVE_DWELL_BASE +
  1243. IL_PASSIVE_DWELL_TIME_24 : IL_PASSIVE_DWELL_BASE +
  1244. IL_PASSIVE_DWELL_TIME_52;
  1245. if (il_is_any_associated(il)) {
  1246. /*
  1247. * If we're associated, we clamp the maximum passive
  1248. * dwell time to be 98% of the smallest beacon interval
  1249. * (minus 2 * channel tune time)
  1250. */
  1251. value = il->vif ? il->vif->bss_conf.beacon_int : 0;
  1252. if (value > IL_PASSIVE_DWELL_BASE || !value)
  1253. value = IL_PASSIVE_DWELL_BASE;
  1254. value = (value * 98) / 100 - IL_CHANNEL_TUNE_TIME * 2;
  1255. passive = min(value, passive);
  1256. }
  1257. return passive;
  1258. }
  1259. EXPORT_SYMBOL(il_get_passive_dwell_time);
  1260. void
  1261. il_init_scan_params(struct il_priv *il)
  1262. {
  1263. u8 ant_idx = fls(il->hw_params.valid_tx_ant) - 1;
  1264. if (!il->scan_tx_ant[IEEE80211_BAND_5GHZ])
  1265. il->scan_tx_ant[IEEE80211_BAND_5GHZ] = ant_idx;
  1266. if (!il->scan_tx_ant[IEEE80211_BAND_2GHZ])
  1267. il->scan_tx_ant[IEEE80211_BAND_2GHZ] = ant_idx;
  1268. }
  1269. EXPORT_SYMBOL(il_init_scan_params);
  1270. static int
  1271. il_scan_initiate(struct il_priv *il, struct ieee80211_vif *vif)
  1272. {
  1273. int ret;
  1274. lockdep_assert_held(&il->mutex);
  1275. cancel_delayed_work(&il->scan_check);
  1276. if (!il_is_ready_rf(il)) {
  1277. IL_WARN("Request scan called when driver not ready.\n");
  1278. return -EIO;
  1279. }
  1280. if (test_bit(S_SCAN_HW, &il->status)) {
  1281. D_SCAN("Multiple concurrent scan requests in parallel.\n");
  1282. return -EBUSY;
  1283. }
  1284. if (test_bit(S_SCAN_ABORTING, &il->status)) {
  1285. D_SCAN("Scan request while abort pending.\n");
  1286. return -EBUSY;
  1287. }
  1288. D_SCAN("Starting scan...\n");
  1289. set_bit(S_SCANNING, &il->status);
  1290. il->scan_start = jiffies;
  1291. ret = il->ops->request_scan(il, vif);
  1292. if (ret) {
  1293. clear_bit(S_SCANNING, &il->status);
  1294. return ret;
  1295. }
  1296. queue_delayed_work(il->workqueue, &il->scan_check,
  1297. IL_SCAN_CHECK_WATCHDOG);
  1298. return 0;
  1299. }
  1300. int
  1301. il_mac_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
  1302. struct cfg80211_scan_request *req)
  1303. {
  1304. struct il_priv *il = hw->priv;
  1305. int ret;
  1306. if (req->n_channels == 0) {
  1307. IL_ERR("Can not scan on no channels.\n");
  1308. return -EINVAL;
  1309. }
  1310. mutex_lock(&il->mutex);
  1311. D_MAC80211("enter\n");
  1312. if (test_bit(S_SCANNING, &il->status)) {
  1313. D_SCAN("Scan already in progress.\n");
  1314. ret = -EAGAIN;
  1315. goto out_unlock;
  1316. }
  1317. /* mac80211 will only ask for one band at a time */
  1318. il->scan_request = req;
  1319. il->scan_vif = vif;
  1320. il->scan_band = req->channels[0]->band;
  1321. ret = il_scan_initiate(il, vif);
  1322. out_unlock:
  1323. D_MAC80211("leave ret %d\n", ret);
  1324. mutex_unlock(&il->mutex);
  1325. return ret;
  1326. }
  1327. EXPORT_SYMBOL(il_mac_hw_scan);
  1328. static void
  1329. il_bg_scan_check(struct work_struct *data)
  1330. {
  1331. struct il_priv *il =
  1332. container_of(data, struct il_priv, scan_check.work);
  1333. D_SCAN("Scan check work\n");
  1334. /* Since we are here firmware does not finish scan and
  1335. * most likely is in bad shape, so we don't bother to
  1336. * send abort command, just force scan complete to mac80211 */
  1337. mutex_lock(&il->mutex);
  1338. il_force_scan_end(il);
  1339. mutex_unlock(&il->mutex);
  1340. }
  1341. /**
  1342. * il_fill_probe_req - fill in all required fields and IE for probe request
  1343. */
  1344. u16
  1345. il_fill_probe_req(struct il_priv *il, struct ieee80211_mgmt *frame,
  1346. const u8 *ta, const u8 *ies, int ie_len, int left)
  1347. {
  1348. int len = 0;
  1349. u8 *pos = NULL;
  1350. /* Make sure there is enough space for the probe request,
  1351. * two mandatory IEs and the data */
  1352. left -= 24;
  1353. if (left < 0)
  1354. return 0;
  1355. frame->frame_control = cpu_to_le16(IEEE80211_STYPE_PROBE_REQ);
  1356. eth_broadcast_addr(frame->da);
  1357. memcpy(frame->sa, ta, ETH_ALEN);
  1358. eth_broadcast_addr(frame->bssid);
  1359. frame->seq_ctrl = 0;
  1360. len += 24;
  1361. /* ...next IE... */
  1362. pos = &frame->u.probe_req.variable[0];
  1363. /* fill in our indirect SSID IE */
  1364. left -= 2;
  1365. if (left < 0)
  1366. return 0;
  1367. *pos++ = WLAN_EID_SSID;
  1368. *pos++ = 0;
  1369. len += 2;
  1370. if (WARN_ON(left < ie_len))
  1371. return len;
  1372. if (ies && ie_len) {
  1373. memcpy(pos, ies, ie_len);
  1374. len += ie_len;
  1375. }
  1376. return (u16) len;
  1377. }
  1378. EXPORT_SYMBOL(il_fill_probe_req);
  1379. static void
  1380. il_bg_abort_scan(struct work_struct *work)
  1381. {
  1382. struct il_priv *il = container_of(work, struct il_priv, abort_scan);
  1383. D_SCAN("Abort scan work\n");
  1384. /* We keep scan_check work queued in case when firmware will not
  1385. * report back scan completed notification */
  1386. mutex_lock(&il->mutex);
  1387. il_scan_cancel_timeout(il, 200);
  1388. mutex_unlock(&il->mutex);
  1389. }
  1390. static void
  1391. il_bg_scan_completed(struct work_struct *work)
  1392. {
  1393. struct il_priv *il = container_of(work, struct il_priv, scan_completed);
  1394. bool aborted;
  1395. D_SCAN("Completed scan.\n");
  1396. cancel_delayed_work(&il->scan_check);
  1397. mutex_lock(&il->mutex);
  1398. aborted = test_and_clear_bit(S_SCAN_ABORTING, &il->status);
  1399. if (aborted)
  1400. D_SCAN("Aborted scan completed.\n");
  1401. if (!test_and_clear_bit(S_SCANNING, &il->status)) {
  1402. D_SCAN("Scan already completed.\n");
  1403. goto out_settings;
  1404. }
  1405. il_complete_scan(il, aborted);
  1406. out_settings:
  1407. /* Can we still talk to firmware ? */
  1408. if (!il_is_ready_rf(il))
  1409. goto out;
  1410. /*
  1411. * We do not commit power settings while scan is pending,
  1412. * do it now if the settings changed.
  1413. */
  1414. il_power_set_mode(il, &il->power_data.sleep_cmd_next, false);
  1415. il_set_tx_power(il, il->tx_power_next, false);
  1416. il->ops->post_scan(il);
  1417. out:
  1418. mutex_unlock(&il->mutex);
  1419. }
  1420. void
  1421. il_setup_scan_deferred_work(struct il_priv *il)
  1422. {
  1423. INIT_WORK(&il->scan_completed, il_bg_scan_completed);
  1424. INIT_WORK(&il->abort_scan, il_bg_abort_scan);
  1425. INIT_DELAYED_WORK(&il->scan_check, il_bg_scan_check);
  1426. }
  1427. EXPORT_SYMBOL(il_setup_scan_deferred_work);
  1428. void
  1429. il_cancel_scan_deferred_work(struct il_priv *il)
  1430. {
  1431. cancel_work_sync(&il->abort_scan);
  1432. cancel_work_sync(&il->scan_completed);
  1433. if (cancel_delayed_work_sync(&il->scan_check)) {
  1434. mutex_lock(&il->mutex);
  1435. il_force_scan_end(il);
  1436. mutex_unlock(&il->mutex);
  1437. }
  1438. }
  1439. EXPORT_SYMBOL(il_cancel_scan_deferred_work);
  1440. /* il->sta_lock must be held */
  1441. static void
  1442. il_sta_ucode_activate(struct il_priv *il, u8 sta_id)
  1443. {
  1444. if (!(il->stations[sta_id].used & IL_STA_DRIVER_ACTIVE))
  1445. IL_ERR("ACTIVATE a non DRIVER active station id %u addr %pM\n",
  1446. sta_id, il->stations[sta_id].sta.sta.addr);
  1447. if (il->stations[sta_id].used & IL_STA_UCODE_ACTIVE) {
  1448. D_ASSOC("STA id %u addr %pM already present"
  1449. " in uCode (according to driver)\n", sta_id,
  1450. il->stations[sta_id].sta.sta.addr);
  1451. } else {
  1452. il->stations[sta_id].used |= IL_STA_UCODE_ACTIVE;
  1453. D_ASSOC("Added STA id %u addr %pM to uCode\n", sta_id,
  1454. il->stations[sta_id].sta.sta.addr);
  1455. }
  1456. }
  1457. static int
  1458. il_process_add_sta_resp(struct il_priv *il, struct il_addsta_cmd *addsta,
  1459. struct il_rx_pkt *pkt, bool sync)
  1460. {
  1461. u8 sta_id = addsta->sta.sta_id;
  1462. unsigned long flags;
  1463. int ret = -EIO;
  1464. if (pkt->hdr.flags & IL_CMD_FAILED_MSK) {
  1465. IL_ERR("Bad return from C_ADD_STA (0x%08X)\n", pkt->hdr.flags);
  1466. return ret;
  1467. }
  1468. D_INFO("Processing response for adding station %u\n", sta_id);
  1469. spin_lock_irqsave(&il->sta_lock, flags);
  1470. switch (pkt->u.add_sta.status) {
  1471. case ADD_STA_SUCCESS_MSK:
  1472. D_INFO("C_ADD_STA PASSED\n");
  1473. il_sta_ucode_activate(il, sta_id);
  1474. ret = 0;
  1475. break;
  1476. case ADD_STA_NO_ROOM_IN_TBL:
  1477. IL_ERR("Adding station %d failed, no room in table.\n", sta_id);
  1478. break;
  1479. case ADD_STA_NO_BLOCK_ACK_RESOURCE:
  1480. IL_ERR("Adding station %d failed, no block ack resource.\n",
  1481. sta_id);
  1482. break;
  1483. case ADD_STA_MODIFY_NON_EXIST_STA:
  1484. IL_ERR("Attempting to modify non-existing station %d\n",
  1485. sta_id);
  1486. break;
  1487. default:
  1488. D_ASSOC("Received C_ADD_STA:(0x%08X)\n", pkt->u.add_sta.status);
  1489. break;
  1490. }
  1491. D_INFO("%s station id %u addr %pM\n",
  1492. il->stations[sta_id].sta.mode ==
  1493. STA_CONTROL_MODIFY_MSK ? "Modified" : "Added", sta_id,
  1494. il->stations[sta_id].sta.sta.addr);
  1495. /*
  1496. * XXX: The MAC address in the command buffer is often changed from
  1497. * the original sent to the device. That is, the MAC address
  1498. * written to the command buffer often is not the same MAC address
  1499. * read from the command buffer when the command returns. This
  1500. * issue has not yet been resolved and this debugging is left to
  1501. * observe the problem.
  1502. */
  1503. D_INFO("%s station according to cmd buffer %pM\n",
  1504. il->stations[sta_id].sta.mode ==
  1505. STA_CONTROL_MODIFY_MSK ? "Modified" : "Added", addsta->sta.addr);
  1506. spin_unlock_irqrestore(&il->sta_lock, flags);
  1507. return ret;
  1508. }
  1509. static void
  1510. il_add_sta_callback(struct il_priv *il, struct il_device_cmd *cmd,
  1511. struct il_rx_pkt *pkt)
  1512. {
  1513. struct il_addsta_cmd *addsta = (struct il_addsta_cmd *)cmd->cmd.payload;
  1514. il_process_add_sta_resp(il, addsta, pkt, false);
  1515. }
  1516. int
  1517. il_send_add_sta(struct il_priv *il, struct il_addsta_cmd *sta, u8 flags)
  1518. {
  1519. struct il_rx_pkt *pkt = NULL;
  1520. int ret = 0;
  1521. u8 data[sizeof(*sta)];
  1522. struct il_host_cmd cmd = {
  1523. .id = C_ADD_STA,
  1524. .flags = flags,
  1525. .data = data,
  1526. };
  1527. u8 sta_id __maybe_unused = sta->sta.sta_id;
  1528. D_INFO("Adding sta %u (%pM) %ssynchronously\n", sta_id, sta->sta.addr,
  1529. flags & CMD_ASYNC ? "a" : "");
  1530. if (flags & CMD_ASYNC)
  1531. cmd.callback = il_add_sta_callback;
  1532. else {
  1533. cmd.flags |= CMD_WANT_SKB;
  1534. might_sleep();
  1535. }
  1536. cmd.len = il->ops->build_addsta_hcmd(sta, data);
  1537. ret = il_send_cmd(il, &cmd);
  1538. if (ret || (flags & CMD_ASYNC))
  1539. return ret;
  1540. if (ret == 0) {
  1541. pkt = (struct il_rx_pkt *)cmd.reply_page;
  1542. ret = il_process_add_sta_resp(il, sta, pkt, true);
  1543. }
  1544. il_free_pages(il, cmd.reply_page);
  1545. return ret;
  1546. }
  1547. EXPORT_SYMBOL(il_send_add_sta);
  1548. static void
  1549. il_set_ht_add_station(struct il_priv *il, u8 idx, struct ieee80211_sta *sta)
  1550. {
  1551. struct ieee80211_sta_ht_cap *sta_ht_inf = &sta->ht_cap;
  1552. __le32 sta_flags;
  1553. if (!sta || !sta_ht_inf->ht_supported)
  1554. goto done;
  1555. D_ASSOC("spatial multiplexing power save mode: %s\n",
  1556. (sta->smps_mode == IEEE80211_SMPS_STATIC) ? "static" :
  1557. (sta->smps_mode == IEEE80211_SMPS_DYNAMIC) ? "dynamic" :
  1558. "disabled");
  1559. sta_flags = il->stations[idx].sta.station_flags;
  1560. sta_flags &= ~(STA_FLG_RTS_MIMO_PROT_MSK | STA_FLG_MIMO_DIS_MSK);
  1561. switch (sta->smps_mode) {
  1562. case IEEE80211_SMPS_STATIC:
  1563. sta_flags |= STA_FLG_MIMO_DIS_MSK;
  1564. break;
  1565. case IEEE80211_SMPS_DYNAMIC:
  1566. sta_flags |= STA_FLG_RTS_MIMO_PROT_MSK;
  1567. break;
  1568. case IEEE80211_SMPS_OFF:
  1569. break;
  1570. default:
  1571. IL_WARN("Invalid MIMO PS mode %d\n", sta->smps_mode);
  1572. break;
  1573. }
  1574. sta_flags |=
  1575. cpu_to_le32((u32) sta_ht_inf->
  1576. ampdu_factor << STA_FLG_MAX_AGG_SIZE_POS);
  1577. sta_flags |=
  1578. cpu_to_le32((u32) sta_ht_inf->
  1579. ampdu_density << STA_FLG_AGG_MPDU_DENSITY_POS);
  1580. if (il_is_ht40_tx_allowed(il, &sta->ht_cap))
  1581. sta_flags |= STA_FLG_HT40_EN_MSK;
  1582. else
  1583. sta_flags &= ~STA_FLG_HT40_EN_MSK;
  1584. il->stations[idx].sta.station_flags = sta_flags;
  1585. done:
  1586. return;
  1587. }
  1588. /**
  1589. * il_prep_station - Prepare station information for addition
  1590. *
  1591. * should be called with sta_lock held
  1592. */
  1593. u8
  1594. il_prep_station(struct il_priv *il, const u8 *addr, bool is_ap,
  1595. struct ieee80211_sta *sta)
  1596. {
  1597. struct il_station_entry *station;
  1598. int i;
  1599. u8 sta_id = IL_INVALID_STATION;
  1600. u16 rate;
  1601. if (is_ap)
  1602. sta_id = IL_AP_ID;
  1603. else if (is_broadcast_ether_addr(addr))
  1604. sta_id = il->hw_params.bcast_id;
  1605. else
  1606. for (i = IL_STA_ID; i < il->hw_params.max_stations; i++) {
  1607. if (ether_addr_equal(il->stations[i].sta.sta.addr,
  1608. addr)) {
  1609. sta_id = i;
  1610. break;
  1611. }
  1612. if (!il->stations[i].used &&
  1613. sta_id == IL_INVALID_STATION)
  1614. sta_id = i;
  1615. }
  1616. /*
  1617. * These two conditions have the same outcome, but keep them
  1618. * separate
  1619. */
  1620. if (unlikely(sta_id == IL_INVALID_STATION))
  1621. return sta_id;
  1622. /*
  1623. * uCode is not able to deal with multiple requests to add a
  1624. * station. Keep track if one is in progress so that we do not send
  1625. * another.
  1626. */
  1627. if (il->stations[sta_id].used & IL_STA_UCODE_INPROGRESS) {
  1628. D_INFO("STA %d already in process of being added.\n", sta_id);
  1629. return sta_id;
  1630. }
  1631. if ((il->stations[sta_id].used & IL_STA_DRIVER_ACTIVE) &&
  1632. (il->stations[sta_id].used & IL_STA_UCODE_ACTIVE) &&
  1633. ether_addr_equal(il->stations[sta_id].sta.sta.addr, addr)) {
  1634. D_ASSOC("STA %d (%pM) already added, not adding again.\n",
  1635. sta_id, addr);
  1636. return sta_id;
  1637. }
  1638. station = &il->stations[sta_id];
  1639. station->used = IL_STA_DRIVER_ACTIVE;
  1640. D_ASSOC("Add STA to driver ID %d: %pM\n", sta_id, addr);
  1641. il->num_stations++;
  1642. /* Set up the C_ADD_STA command to send to device */
  1643. memset(&station->sta, 0, sizeof(struct il_addsta_cmd));
  1644. memcpy(station->sta.sta.addr, addr, ETH_ALEN);
  1645. station->sta.mode = 0;
  1646. station->sta.sta.sta_id = sta_id;
  1647. station->sta.station_flags = 0;
  1648. /*
  1649. * OK to call unconditionally, since local stations (IBSS BSSID
  1650. * STA and broadcast STA) pass in a NULL sta, and mac80211
  1651. * doesn't allow HT IBSS.
  1652. */
  1653. il_set_ht_add_station(il, sta_id, sta);
  1654. /* 3945 only */
  1655. rate = (il->band == IEEE80211_BAND_5GHZ) ? RATE_6M_PLCP : RATE_1M_PLCP;
  1656. /* Turn on both antennas for the station... */
  1657. station->sta.rate_n_flags = cpu_to_le16(rate | RATE_MCS_ANT_AB_MSK);
  1658. return sta_id;
  1659. }
  1660. EXPORT_SYMBOL_GPL(il_prep_station);
  1661. #define STA_WAIT_TIMEOUT (HZ/2)
  1662. /**
  1663. * il_add_station_common -
  1664. */
  1665. int
  1666. il_add_station_common(struct il_priv *il, const u8 *addr, bool is_ap,
  1667. struct ieee80211_sta *sta, u8 *sta_id_r)
  1668. {
  1669. unsigned long flags_spin;
  1670. int ret = 0;
  1671. u8 sta_id;
  1672. struct il_addsta_cmd sta_cmd;
  1673. *sta_id_r = 0;
  1674. spin_lock_irqsave(&il->sta_lock, flags_spin);
  1675. sta_id = il_prep_station(il, addr, is_ap, sta);
  1676. if (sta_id == IL_INVALID_STATION) {
  1677. IL_ERR("Unable to prepare station %pM for addition\n", addr);
  1678. spin_unlock_irqrestore(&il->sta_lock, flags_spin);
  1679. return -EINVAL;
  1680. }
  1681. /*
  1682. * uCode is not able to deal with multiple requests to add a
  1683. * station. Keep track if one is in progress so that we do not send
  1684. * another.
  1685. */
  1686. if (il->stations[sta_id].used & IL_STA_UCODE_INPROGRESS) {
  1687. D_INFO("STA %d already in process of being added.\n", sta_id);
  1688. spin_unlock_irqrestore(&il->sta_lock, flags_spin);
  1689. return -EEXIST;
  1690. }
  1691. if ((il->stations[sta_id].used & IL_STA_DRIVER_ACTIVE) &&
  1692. (il->stations[sta_id].used & IL_STA_UCODE_ACTIVE)) {
  1693. D_ASSOC("STA %d (%pM) already added, not adding again.\n",
  1694. sta_id, addr);
  1695. spin_unlock_irqrestore(&il->sta_lock, flags_spin);
  1696. return -EEXIST;
  1697. }
  1698. il->stations[sta_id].used |= IL_STA_UCODE_INPROGRESS;
  1699. memcpy(&sta_cmd, &il->stations[sta_id].sta,
  1700. sizeof(struct il_addsta_cmd));
  1701. spin_unlock_irqrestore(&il->sta_lock, flags_spin);
  1702. /* Add station to device's station table */
  1703. ret = il_send_add_sta(il, &sta_cmd, CMD_SYNC);
  1704. if (ret) {
  1705. spin_lock_irqsave(&il->sta_lock, flags_spin);
  1706. IL_ERR("Adding station %pM failed.\n",
  1707. il->stations[sta_id].sta.sta.addr);
  1708. il->stations[sta_id].used &= ~IL_STA_DRIVER_ACTIVE;
  1709. il->stations[sta_id].used &= ~IL_STA_UCODE_INPROGRESS;
  1710. spin_unlock_irqrestore(&il->sta_lock, flags_spin);
  1711. }
  1712. *sta_id_r = sta_id;
  1713. return ret;
  1714. }
  1715. EXPORT_SYMBOL(il_add_station_common);
  1716. /**
  1717. * il_sta_ucode_deactivate - deactivate ucode status for a station
  1718. *
  1719. * il->sta_lock must be held
  1720. */
  1721. static void
  1722. il_sta_ucode_deactivate(struct il_priv *il, u8 sta_id)
  1723. {
  1724. /* Ucode must be active and driver must be non active */
  1725. if ((il->stations[sta_id].
  1726. used & (IL_STA_UCODE_ACTIVE | IL_STA_DRIVER_ACTIVE)) !=
  1727. IL_STA_UCODE_ACTIVE)
  1728. IL_ERR("removed non active STA %u\n", sta_id);
  1729. il->stations[sta_id].used &= ~IL_STA_UCODE_ACTIVE;
  1730. memset(&il->stations[sta_id], 0, sizeof(struct il_station_entry));
  1731. D_ASSOC("Removed STA %u\n", sta_id);
  1732. }
  1733. static int
  1734. il_send_remove_station(struct il_priv *il, const u8 * addr, int sta_id,
  1735. bool temporary)
  1736. {
  1737. struct il_rx_pkt *pkt;
  1738. int ret;
  1739. unsigned long flags_spin;
  1740. struct il_rem_sta_cmd rm_sta_cmd;
  1741. struct il_host_cmd cmd = {
  1742. .id = C_REM_STA,
  1743. .len = sizeof(struct il_rem_sta_cmd),
  1744. .flags = CMD_SYNC,
  1745. .data = &rm_sta_cmd,
  1746. };
  1747. memset(&rm_sta_cmd, 0, sizeof(rm_sta_cmd));
  1748. rm_sta_cmd.num_sta = 1;
  1749. memcpy(&rm_sta_cmd.addr, addr, ETH_ALEN);
  1750. cmd.flags |= CMD_WANT_SKB;
  1751. ret = il_send_cmd(il, &cmd);
  1752. if (ret)
  1753. return ret;
  1754. pkt = (struct il_rx_pkt *)cmd.reply_page;
  1755. if (pkt->hdr.flags & IL_CMD_FAILED_MSK) {
  1756. IL_ERR("Bad return from C_REM_STA (0x%08X)\n", pkt->hdr.flags);
  1757. ret = -EIO;
  1758. }
  1759. if (!ret) {
  1760. switch (pkt->u.rem_sta.status) {
  1761. case REM_STA_SUCCESS_MSK:
  1762. if (!temporary) {
  1763. spin_lock_irqsave(&il->sta_lock, flags_spin);
  1764. il_sta_ucode_deactivate(il, sta_id);
  1765. spin_unlock_irqrestore(&il->sta_lock,
  1766. flags_spin);
  1767. }
  1768. D_ASSOC("C_REM_STA PASSED\n");
  1769. break;
  1770. default:
  1771. ret = -EIO;
  1772. IL_ERR("C_REM_STA failed\n");
  1773. break;
  1774. }
  1775. }
  1776. il_free_pages(il, cmd.reply_page);
  1777. return ret;
  1778. }
  1779. /**
  1780. * il_remove_station - Remove driver's knowledge of station.
  1781. */
  1782. int
  1783. il_remove_station(struct il_priv *il, const u8 sta_id, const u8 * addr)
  1784. {
  1785. unsigned long flags;
  1786. if (!il_is_ready(il)) {
  1787. D_INFO("Unable to remove station %pM, device not ready.\n",
  1788. addr);
  1789. /*
  1790. * It is typical for stations to be removed when we are
  1791. * going down. Return success since device will be down
  1792. * soon anyway
  1793. */
  1794. return 0;
  1795. }
  1796. D_ASSOC("Removing STA from driver:%d %pM\n", sta_id, addr);
  1797. if (WARN_ON(sta_id == IL_INVALID_STATION))
  1798. return -EINVAL;
  1799. spin_lock_irqsave(&il->sta_lock, flags);
  1800. if (!(il->stations[sta_id].used & IL_STA_DRIVER_ACTIVE)) {
  1801. D_INFO("Removing %pM but non DRIVER active\n", addr);
  1802. goto out_err;
  1803. }
  1804. if (!(il->stations[sta_id].used & IL_STA_UCODE_ACTIVE)) {
  1805. D_INFO("Removing %pM but non UCODE active\n", addr);
  1806. goto out_err;
  1807. }
  1808. if (il->stations[sta_id].used & IL_STA_LOCAL) {
  1809. kfree(il->stations[sta_id].lq);
  1810. il->stations[sta_id].lq = NULL;
  1811. }
  1812. il->stations[sta_id].used &= ~IL_STA_DRIVER_ACTIVE;
  1813. il->num_stations--;
  1814. BUG_ON(il->num_stations < 0);
  1815. spin_unlock_irqrestore(&il->sta_lock, flags);
  1816. return il_send_remove_station(il, addr, sta_id, false);
  1817. out_err:
  1818. spin_unlock_irqrestore(&il->sta_lock, flags);
  1819. return -EINVAL;
  1820. }
  1821. EXPORT_SYMBOL_GPL(il_remove_station);
  1822. /**
  1823. * il_clear_ucode_stations - clear ucode station table bits
  1824. *
  1825. * This function clears all the bits in the driver indicating
  1826. * which stations are active in the ucode. Call when something
  1827. * other than explicit station management would cause this in
  1828. * the ucode, e.g. unassociated RXON.
  1829. */
  1830. void
  1831. il_clear_ucode_stations(struct il_priv *il)
  1832. {
  1833. int i;
  1834. unsigned long flags_spin;
  1835. bool cleared = false;
  1836. D_INFO("Clearing ucode stations in driver\n");
  1837. spin_lock_irqsave(&il->sta_lock, flags_spin);
  1838. for (i = 0; i < il->hw_params.max_stations; i++) {
  1839. if (il->stations[i].used & IL_STA_UCODE_ACTIVE) {
  1840. D_INFO("Clearing ucode active for station %d\n", i);
  1841. il->stations[i].used &= ~IL_STA_UCODE_ACTIVE;
  1842. cleared = true;
  1843. }
  1844. }
  1845. spin_unlock_irqrestore(&il->sta_lock, flags_spin);
  1846. if (!cleared)
  1847. D_INFO("No active stations found to be cleared\n");
  1848. }
  1849. EXPORT_SYMBOL(il_clear_ucode_stations);
  1850. /**
  1851. * il_restore_stations() - Restore driver known stations to device
  1852. *
  1853. * All stations considered active by driver, but not present in ucode, is
  1854. * restored.
  1855. *
  1856. * Function sleeps.
  1857. */
  1858. void
  1859. il_restore_stations(struct il_priv *il)
  1860. {
  1861. struct il_addsta_cmd sta_cmd;
  1862. struct il_link_quality_cmd lq;
  1863. unsigned long flags_spin;
  1864. int i;
  1865. bool found = false;
  1866. int ret;
  1867. bool send_lq;
  1868. if (!il_is_ready(il)) {
  1869. D_INFO("Not ready yet, not restoring any stations.\n");
  1870. return;
  1871. }
  1872. D_ASSOC("Restoring all known stations ... start.\n");
  1873. spin_lock_irqsave(&il->sta_lock, flags_spin);
  1874. for (i = 0; i < il->hw_params.max_stations; i++) {
  1875. if ((il->stations[i].used & IL_STA_DRIVER_ACTIVE) &&
  1876. !(il->stations[i].used & IL_STA_UCODE_ACTIVE)) {
  1877. D_ASSOC("Restoring sta %pM\n",
  1878. il->stations[i].sta.sta.addr);
  1879. il->stations[i].sta.mode = 0;
  1880. il->stations[i].used |= IL_STA_UCODE_INPROGRESS;
  1881. found = true;
  1882. }
  1883. }
  1884. for (i = 0; i < il->hw_params.max_stations; i++) {
  1885. if ((il->stations[i].used & IL_STA_UCODE_INPROGRESS)) {
  1886. memcpy(&sta_cmd, &il->stations[i].sta,
  1887. sizeof(struct il_addsta_cmd));
  1888. send_lq = false;
  1889. if (il->stations[i].lq) {
  1890. memcpy(&lq, il->stations[i].lq,
  1891. sizeof(struct il_link_quality_cmd));
  1892. send_lq = true;
  1893. }
  1894. spin_unlock_irqrestore(&il->sta_lock, flags_spin);
  1895. ret = il_send_add_sta(il, &sta_cmd, CMD_SYNC);
  1896. if (ret) {
  1897. spin_lock_irqsave(&il->sta_lock, flags_spin);
  1898. IL_ERR("Adding station %pM failed.\n",
  1899. il->stations[i].sta.sta.addr);
  1900. il->stations[i].used &= ~IL_STA_DRIVER_ACTIVE;
  1901. il->stations[i].used &=
  1902. ~IL_STA_UCODE_INPROGRESS;
  1903. spin_unlock_irqrestore(&il->sta_lock,
  1904. flags_spin);
  1905. }
  1906. /*
  1907. * Rate scaling has already been initialized, send
  1908. * current LQ command
  1909. */
  1910. if (send_lq)
  1911. il_send_lq_cmd(il, &lq, CMD_SYNC, true);
  1912. spin_lock_irqsave(&il->sta_lock, flags_spin);
  1913. il->stations[i].used &= ~IL_STA_UCODE_INPROGRESS;
  1914. }
  1915. }
  1916. spin_unlock_irqrestore(&il->sta_lock, flags_spin);
  1917. if (!found)
  1918. D_INFO("Restoring all known stations"
  1919. " .... no stations to be restored.\n");
  1920. else
  1921. D_INFO("Restoring all known stations" " .... complete.\n");
  1922. }
  1923. EXPORT_SYMBOL(il_restore_stations);
  1924. int
  1925. il_get_free_ucode_key_idx(struct il_priv *il)
  1926. {
  1927. int i;
  1928. for (i = 0; i < il->sta_key_max_num; i++)
  1929. if (!test_and_set_bit(i, &il->ucode_key_table))
  1930. return i;
  1931. return WEP_INVALID_OFFSET;
  1932. }
  1933. EXPORT_SYMBOL(il_get_free_ucode_key_idx);
  1934. void
  1935. il_dealloc_bcast_stations(struct il_priv *il)
  1936. {
  1937. unsigned long flags;
  1938. int i;
  1939. spin_lock_irqsave(&il->sta_lock, flags);
  1940. for (i = 0; i < il->hw_params.max_stations; i++) {
  1941. if (!(il->stations[i].used & IL_STA_BCAST))
  1942. continue;
  1943. il->stations[i].used &= ~IL_STA_UCODE_ACTIVE;
  1944. il->num_stations--;
  1945. BUG_ON(il->num_stations < 0);
  1946. kfree(il->stations[i].lq);
  1947. il->stations[i].lq = NULL;
  1948. }
  1949. spin_unlock_irqrestore(&il->sta_lock, flags);
  1950. }
  1951. EXPORT_SYMBOL_GPL(il_dealloc_bcast_stations);
  1952. #ifdef CONFIG_IWLEGACY_DEBUG
  1953. static void
  1954. il_dump_lq_cmd(struct il_priv *il, struct il_link_quality_cmd *lq)
  1955. {
  1956. int i;
  1957. D_RATE("lq station id 0x%x\n", lq->sta_id);
  1958. D_RATE("lq ant 0x%X 0x%X\n", lq->general_params.single_stream_ant_msk,
  1959. lq->general_params.dual_stream_ant_msk);
  1960. for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++)
  1961. D_RATE("lq idx %d 0x%X\n", i, lq->rs_table[i].rate_n_flags);
  1962. }
  1963. #else
  1964. static inline void
  1965. il_dump_lq_cmd(struct il_priv *il, struct il_link_quality_cmd *lq)
  1966. {
  1967. }
  1968. #endif
  1969. /**
  1970. * il_is_lq_table_valid() - Test one aspect of LQ cmd for validity
  1971. *
  1972. * It sometimes happens when a HT rate has been in use and we
  1973. * loose connectivity with AP then mac80211 will first tell us that the
  1974. * current channel is not HT anymore before removing the station. In such a
  1975. * scenario the RXON flags will be updated to indicate we are not
  1976. * communicating HT anymore, but the LQ command may still contain HT rates.
  1977. * Test for this to prevent driver from sending LQ command between the time
  1978. * RXON flags are updated and when LQ command is updated.
  1979. */
  1980. static bool
  1981. il_is_lq_table_valid(struct il_priv *il, struct il_link_quality_cmd *lq)
  1982. {
  1983. int i;
  1984. if (il->ht.enabled)
  1985. return true;
  1986. D_INFO("Channel %u is not an HT channel\n", il->active.channel);
  1987. for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++) {
  1988. if (le32_to_cpu(lq->rs_table[i].rate_n_flags) & RATE_MCS_HT_MSK) {
  1989. D_INFO("idx %d of LQ expects HT channel\n", i);
  1990. return false;
  1991. }
  1992. }
  1993. return true;
  1994. }
  1995. /**
  1996. * il_send_lq_cmd() - Send link quality command
  1997. * @init: This command is sent as part of station initialization right
  1998. * after station has been added.
  1999. *
  2000. * The link quality command is sent as the last step of station creation.
  2001. * This is the special case in which init is set and we call a callback in
  2002. * this case to clear the state indicating that station creation is in
  2003. * progress.
  2004. */
  2005. int
  2006. il_send_lq_cmd(struct il_priv *il, struct il_link_quality_cmd *lq,
  2007. u8 flags, bool init)
  2008. {
  2009. int ret = 0;
  2010. unsigned long flags_spin;
  2011. struct il_host_cmd cmd = {
  2012. .id = C_TX_LINK_QUALITY_CMD,
  2013. .len = sizeof(struct il_link_quality_cmd),
  2014. .flags = flags,
  2015. .data = lq,
  2016. };
  2017. if (WARN_ON(lq->sta_id == IL_INVALID_STATION))
  2018. return -EINVAL;
  2019. spin_lock_irqsave(&il->sta_lock, flags_spin);
  2020. if (!(il->stations[lq->sta_id].used & IL_STA_DRIVER_ACTIVE)) {
  2021. spin_unlock_irqrestore(&il->sta_lock, flags_spin);
  2022. return -EINVAL;
  2023. }
  2024. spin_unlock_irqrestore(&il->sta_lock, flags_spin);
  2025. il_dump_lq_cmd(il, lq);
  2026. BUG_ON(init && (cmd.flags & CMD_ASYNC));
  2027. if (il_is_lq_table_valid(il, lq))
  2028. ret = il_send_cmd(il, &cmd);
  2029. else
  2030. ret = -EINVAL;
  2031. if (cmd.flags & CMD_ASYNC)
  2032. return ret;
  2033. if (init) {
  2034. D_INFO("init LQ command complete,"
  2035. " clearing sta addition status for sta %d\n",
  2036. lq->sta_id);
  2037. spin_lock_irqsave(&il->sta_lock, flags_spin);
  2038. il->stations[lq->sta_id].used &= ~IL_STA_UCODE_INPROGRESS;
  2039. spin_unlock_irqrestore(&il->sta_lock, flags_spin);
  2040. }
  2041. return ret;
  2042. }
  2043. EXPORT_SYMBOL(il_send_lq_cmd);
  2044. int
  2045. il_mac_sta_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
  2046. struct ieee80211_sta *sta)
  2047. {
  2048. struct il_priv *il = hw->priv;
  2049. struct il_station_priv_common *sta_common = (void *)sta->drv_priv;
  2050. int ret;
  2051. mutex_lock(&il->mutex);
  2052. D_MAC80211("enter station %pM\n", sta->addr);
  2053. ret = il_remove_station(il, sta_common->sta_id, sta->addr);
  2054. if (ret)
  2055. IL_ERR("Error removing station %pM\n", sta->addr);
  2056. D_MAC80211("leave ret %d\n", ret);
  2057. mutex_unlock(&il->mutex);
  2058. return ret;
  2059. }
  2060. EXPORT_SYMBOL(il_mac_sta_remove);
  2061. /************************** RX-FUNCTIONS ****************************/
  2062. /*
  2063. * Rx theory of operation
  2064. *
  2065. * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs),
  2066. * each of which point to Receive Buffers to be filled by the NIC. These get
  2067. * used not only for Rx frames, but for any command response or notification
  2068. * from the NIC. The driver and NIC manage the Rx buffers by means
  2069. * of idxes into the circular buffer.
  2070. *
  2071. * Rx Queue Indexes
  2072. * The host/firmware share two idx registers for managing the Rx buffers.
  2073. *
  2074. * The READ idx maps to the first position that the firmware may be writing
  2075. * to -- the driver can read up to (but not including) this position and get
  2076. * good data.
  2077. * The READ idx is managed by the firmware once the card is enabled.
  2078. *
  2079. * The WRITE idx maps to the last position the driver has read from -- the
  2080. * position preceding WRITE is the last slot the firmware can place a packet.
  2081. *
  2082. * The queue is empty (no good data) if WRITE = READ - 1, and is full if
  2083. * WRITE = READ.
  2084. *
  2085. * During initialization, the host sets up the READ queue position to the first
  2086. * IDX position, and WRITE to the last (READ - 1 wrapped)
  2087. *
  2088. * When the firmware places a packet in a buffer, it will advance the READ idx
  2089. * and fire the RX interrupt. The driver can then query the READ idx and
  2090. * process as many packets as possible, moving the WRITE idx forward as it
  2091. * resets the Rx queue buffers with new memory.
  2092. *
  2093. * The management in the driver is as follows:
  2094. * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
  2095. * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
  2096. * to replenish the iwl->rxq->rx_free.
  2097. * + In il_rx_replenish (scheduled) if 'processed' != 'read' then the
  2098. * iwl->rxq is replenished and the READ IDX is updated (updating the
  2099. * 'processed' and 'read' driver idxes as well)
  2100. * + A received packet is processed and handed to the kernel network stack,
  2101. * detached from the iwl->rxq. The driver 'processed' idx is updated.
  2102. * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
  2103. * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
  2104. * IDX is not incremented and iwl->status(RX_STALLED) is set. If there
  2105. * were enough free buffers and RX_STALLED is set it is cleared.
  2106. *
  2107. *
  2108. * Driver sequence:
  2109. *
  2110. * il_rx_queue_alloc() Allocates rx_free
  2111. * il_rx_replenish() Replenishes rx_free list from rx_used, and calls
  2112. * il_rx_queue_restock
  2113. * il_rx_queue_restock() Moves available buffers from rx_free into Rx
  2114. * queue, updates firmware pointers, and updates
  2115. * the WRITE idx. If insufficient rx_free buffers
  2116. * are available, schedules il_rx_replenish
  2117. *
  2118. * -- enable interrupts --
  2119. * ISR - il_rx() Detach il_rx_bufs from pool up to the
  2120. * READ IDX, detaching the SKB from the pool.
  2121. * Moves the packet buffer from queue to rx_used.
  2122. * Calls il_rx_queue_restock to refill any empty
  2123. * slots.
  2124. * ...
  2125. *
  2126. */
  2127. /**
  2128. * il_rx_queue_space - Return number of free slots available in queue.
  2129. */
  2130. int
  2131. il_rx_queue_space(const struct il_rx_queue *q)
  2132. {
  2133. int s = q->read - q->write;
  2134. if (s <= 0)
  2135. s += RX_QUEUE_SIZE;
  2136. /* keep some buffer to not confuse full and empty queue */
  2137. s -= 2;
  2138. if (s < 0)
  2139. s = 0;
  2140. return s;
  2141. }
  2142. EXPORT_SYMBOL(il_rx_queue_space);
  2143. /**
  2144. * il_rx_queue_update_write_ptr - Update the write pointer for the RX queue
  2145. */
  2146. void
  2147. il_rx_queue_update_write_ptr(struct il_priv *il, struct il_rx_queue *q)
  2148. {
  2149. unsigned long flags;
  2150. u32 rx_wrt_ptr_reg = il->hw_params.rx_wrt_ptr_reg;
  2151. u32 reg;
  2152. spin_lock_irqsave(&q->lock, flags);
  2153. if (q->need_update == 0)
  2154. goto exit_unlock;
  2155. /* If power-saving is in use, make sure device is awake */
  2156. if (test_bit(S_POWER_PMI, &il->status)) {
  2157. reg = _il_rd(il, CSR_UCODE_DRV_GP1);
  2158. if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
  2159. D_INFO("Rx queue requesting wakeup," " GP1 = 0x%x\n",
  2160. reg);
  2161. il_set_bit(il, CSR_GP_CNTRL,
  2162. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  2163. goto exit_unlock;
  2164. }
  2165. q->write_actual = (q->write & ~0x7);
  2166. il_wr(il, rx_wrt_ptr_reg, q->write_actual);
  2167. /* Else device is assumed to be awake */
  2168. } else {
  2169. /* Device expects a multiple of 8 */
  2170. q->write_actual = (q->write & ~0x7);
  2171. il_wr(il, rx_wrt_ptr_reg, q->write_actual);
  2172. }
  2173. q->need_update = 0;
  2174. exit_unlock:
  2175. spin_unlock_irqrestore(&q->lock, flags);
  2176. }
  2177. EXPORT_SYMBOL(il_rx_queue_update_write_ptr);
  2178. int
  2179. il_rx_queue_alloc(struct il_priv *il)
  2180. {
  2181. struct il_rx_queue *rxq = &il->rxq;
  2182. struct device *dev = &il->pci_dev->dev;
  2183. int i;
  2184. spin_lock_init(&rxq->lock);
  2185. INIT_LIST_HEAD(&rxq->rx_free);
  2186. INIT_LIST_HEAD(&rxq->rx_used);
  2187. /* Alloc the circular buffer of Read Buffer Descriptors (RBDs) */
  2188. rxq->bd = dma_alloc_coherent(dev, 4 * RX_QUEUE_SIZE, &rxq->bd_dma,
  2189. GFP_KERNEL);
  2190. if (!rxq->bd)
  2191. goto err_bd;
  2192. rxq->rb_stts = dma_alloc_coherent(dev, sizeof(struct il_rb_status),
  2193. &rxq->rb_stts_dma, GFP_KERNEL);
  2194. if (!rxq->rb_stts)
  2195. goto err_rb;
  2196. /* Fill the rx_used queue with _all_ of the Rx buffers */
  2197. for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++)
  2198. list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
  2199. /* Set us so that we have processed and used all buffers, but have
  2200. * not restocked the Rx queue with fresh buffers */
  2201. rxq->read = rxq->write = 0;
  2202. rxq->write_actual = 0;
  2203. rxq->free_count = 0;
  2204. rxq->need_update = 0;
  2205. return 0;
  2206. err_rb:
  2207. dma_free_coherent(&il->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd,
  2208. rxq->bd_dma);
  2209. err_bd:
  2210. return -ENOMEM;
  2211. }
  2212. EXPORT_SYMBOL(il_rx_queue_alloc);
  2213. void
  2214. il_hdl_spectrum_measurement(struct il_priv *il, struct il_rx_buf *rxb)
  2215. {
  2216. struct il_rx_pkt *pkt = rxb_addr(rxb);
  2217. struct il_spectrum_notification *report = &(pkt->u.spectrum_notif);
  2218. if (!report->state) {
  2219. D_11H("Spectrum Measure Notification: Start\n");
  2220. return;
  2221. }
  2222. memcpy(&il->measure_report, report, sizeof(*report));
  2223. il->measurement_status |= MEASUREMENT_READY;
  2224. }
  2225. EXPORT_SYMBOL(il_hdl_spectrum_measurement);
  2226. /*
  2227. * returns non-zero if packet should be dropped
  2228. */
  2229. int
  2230. il_set_decrypted_flag(struct il_priv *il, struct ieee80211_hdr *hdr,
  2231. u32 decrypt_res, struct ieee80211_rx_status *stats)
  2232. {
  2233. u16 fc = le16_to_cpu(hdr->frame_control);
  2234. /*
  2235. * All contexts have the same setting here due to it being
  2236. * a module parameter, so OK to check any context.
  2237. */
  2238. if (il->active.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
  2239. return 0;
  2240. if (!(fc & IEEE80211_FCTL_PROTECTED))
  2241. return 0;
  2242. D_RX("decrypt_res:0x%x\n", decrypt_res);
  2243. switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
  2244. case RX_RES_STATUS_SEC_TYPE_TKIP:
  2245. /* The uCode has got a bad phase 1 Key, pushes the packet.
  2246. * Decryption will be done in SW. */
  2247. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  2248. RX_RES_STATUS_BAD_KEY_TTAK)
  2249. break;
  2250. case RX_RES_STATUS_SEC_TYPE_WEP:
  2251. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  2252. RX_RES_STATUS_BAD_ICV_MIC) {
  2253. /* bad ICV, the packet is destroyed since the
  2254. * decryption is inplace, drop it */
  2255. D_RX("Packet destroyed\n");
  2256. return -1;
  2257. }
  2258. case RX_RES_STATUS_SEC_TYPE_CCMP:
  2259. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  2260. RX_RES_STATUS_DECRYPT_OK) {
  2261. D_RX("hw decrypt successfully!!!\n");
  2262. stats->flag |= RX_FLAG_DECRYPTED;
  2263. }
  2264. break;
  2265. default:
  2266. break;
  2267. }
  2268. return 0;
  2269. }
  2270. EXPORT_SYMBOL(il_set_decrypted_flag);
  2271. /**
  2272. * il_txq_update_write_ptr - Send new write idx to hardware
  2273. */
  2274. void
  2275. il_txq_update_write_ptr(struct il_priv *il, struct il_tx_queue *txq)
  2276. {
  2277. u32 reg = 0;
  2278. int txq_id = txq->q.id;
  2279. if (txq->need_update == 0)
  2280. return;
  2281. /* if we're trying to save power */
  2282. if (test_bit(S_POWER_PMI, &il->status)) {
  2283. /* wake up nic if it's powered down ...
  2284. * uCode will wake up, and interrupt us again, so next
  2285. * time we'll skip this part. */
  2286. reg = _il_rd(il, CSR_UCODE_DRV_GP1);
  2287. if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
  2288. D_INFO("Tx queue %d requesting wakeup," " GP1 = 0x%x\n",
  2289. txq_id, reg);
  2290. il_set_bit(il, CSR_GP_CNTRL,
  2291. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  2292. return;
  2293. }
  2294. il_wr(il, HBUS_TARG_WRPTR, txq->q.write_ptr | (txq_id << 8));
  2295. /*
  2296. * else not in power-save mode,
  2297. * uCode will never sleep when we're
  2298. * trying to tx (during RFKILL, we're not trying to tx).
  2299. */
  2300. } else
  2301. _il_wr(il, HBUS_TARG_WRPTR, txq->q.write_ptr | (txq_id << 8));
  2302. txq->need_update = 0;
  2303. }
  2304. EXPORT_SYMBOL(il_txq_update_write_ptr);
  2305. /**
  2306. * il_tx_queue_unmap - Unmap any remaining DMA mappings and free skb's
  2307. */
  2308. void
  2309. il_tx_queue_unmap(struct il_priv *il, int txq_id)
  2310. {
  2311. struct il_tx_queue *txq = &il->txq[txq_id];
  2312. struct il_queue *q = &txq->q;
  2313. if (q->n_bd == 0)
  2314. return;
  2315. while (q->write_ptr != q->read_ptr) {
  2316. il->ops->txq_free_tfd(il, txq);
  2317. q->read_ptr = il_queue_inc_wrap(q->read_ptr, q->n_bd);
  2318. }
  2319. }
  2320. EXPORT_SYMBOL(il_tx_queue_unmap);
  2321. /**
  2322. * il_tx_queue_free - Deallocate DMA queue.
  2323. * @txq: Transmit queue to deallocate.
  2324. *
  2325. * Empty queue by removing and destroying all BD's.
  2326. * Free all buffers.
  2327. * 0-fill, but do not free "txq" descriptor structure.
  2328. */
  2329. void
  2330. il_tx_queue_free(struct il_priv *il, int txq_id)
  2331. {
  2332. struct il_tx_queue *txq = &il->txq[txq_id];
  2333. struct device *dev = &il->pci_dev->dev;
  2334. int i;
  2335. il_tx_queue_unmap(il, txq_id);
  2336. /* De-alloc array of command/tx buffers */
  2337. for (i = 0; i < TFD_TX_CMD_SLOTS; i++)
  2338. kfree(txq->cmd[i]);
  2339. /* De-alloc circular buffer of TFDs */
  2340. if (txq->q.n_bd)
  2341. dma_free_coherent(dev, il->hw_params.tfd_size * txq->q.n_bd,
  2342. txq->tfds, txq->q.dma_addr);
  2343. /* De-alloc array of per-TFD driver data */
  2344. kfree(txq->skbs);
  2345. txq->skbs = NULL;
  2346. /* deallocate arrays */
  2347. kfree(txq->cmd);
  2348. kfree(txq->meta);
  2349. txq->cmd = NULL;
  2350. txq->meta = NULL;
  2351. /* 0-fill queue descriptor structure */
  2352. memset(txq, 0, sizeof(*txq));
  2353. }
  2354. EXPORT_SYMBOL(il_tx_queue_free);
  2355. /**
  2356. * il_cmd_queue_unmap - Unmap any remaining DMA mappings from command queue
  2357. */
  2358. void
  2359. il_cmd_queue_unmap(struct il_priv *il)
  2360. {
  2361. struct il_tx_queue *txq = &il->txq[il->cmd_queue];
  2362. struct il_queue *q = &txq->q;
  2363. int i;
  2364. if (q->n_bd == 0)
  2365. return;
  2366. while (q->read_ptr != q->write_ptr) {
  2367. i = il_get_cmd_idx(q, q->read_ptr, 0);
  2368. if (txq->meta[i].flags & CMD_MAPPED) {
  2369. pci_unmap_single(il->pci_dev,
  2370. dma_unmap_addr(&txq->meta[i], mapping),
  2371. dma_unmap_len(&txq->meta[i], len),
  2372. PCI_DMA_BIDIRECTIONAL);
  2373. txq->meta[i].flags = 0;
  2374. }
  2375. q->read_ptr = il_queue_inc_wrap(q->read_ptr, q->n_bd);
  2376. }
  2377. i = q->n_win;
  2378. if (txq->meta[i].flags & CMD_MAPPED) {
  2379. pci_unmap_single(il->pci_dev,
  2380. dma_unmap_addr(&txq->meta[i], mapping),
  2381. dma_unmap_len(&txq->meta[i], len),
  2382. PCI_DMA_BIDIRECTIONAL);
  2383. txq->meta[i].flags = 0;
  2384. }
  2385. }
  2386. EXPORT_SYMBOL(il_cmd_queue_unmap);
  2387. /**
  2388. * il_cmd_queue_free - Deallocate DMA queue.
  2389. * @txq: Transmit queue to deallocate.
  2390. *
  2391. * Empty queue by removing and destroying all BD's.
  2392. * Free all buffers.
  2393. * 0-fill, but do not free "txq" descriptor structure.
  2394. */
  2395. void
  2396. il_cmd_queue_free(struct il_priv *il)
  2397. {
  2398. struct il_tx_queue *txq = &il->txq[il->cmd_queue];
  2399. struct device *dev = &il->pci_dev->dev;
  2400. int i;
  2401. il_cmd_queue_unmap(il);
  2402. /* De-alloc array of command/tx buffers */
  2403. for (i = 0; i <= TFD_CMD_SLOTS; i++)
  2404. kfree(txq->cmd[i]);
  2405. /* De-alloc circular buffer of TFDs */
  2406. if (txq->q.n_bd)
  2407. dma_free_coherent(dev, il->hw_params.tfd_size * txq->q.n_bd,
  2408. txq->tfds, txq->q.dma_addr);
  2409. /* deallocate arrays */
  2410. kfree(txq->cmd);
  2411. kfree(txq->meta);
  2412. txq->cmd = NULL;
  2413. txq->meta = NULL;
  2414. /* 0-fill queue descriptor structure */
  2415. memset(txq, 0, sizeof(*txq));
  2416. }
  2417. EXPORT_SYMBOL(il_cmd_queue_free);
  2418. /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
  2419. * DMA services
  2420. *
  2421. * Theory of operation
  2422. *
  2423. * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
  2424. * of buffer descriptors, each of which points to one or more data buffers for
  2425. * the device to read from or fill. Driver and device exchange status of each
  2426. * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
  2427. * entries in each circular buffer, to protect against confusing empty and full
  2428. * queue states.
  2429. *
  2430. * The device reads or writes the data in the queues via the device's several
  2431. * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
  2432. *
  2433. * For Tx queue, there are low mark and high mark limits. If, after queuing
  2434. * the packet for Tx, free space become < low mark, Tx queue stopped. When
  2435. * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
  2436. * Tx queue resumed.
  2437. *
  2438. * See more detailed info in 4965.h.
  2439. ***************************************************/
  2440. int
  2441. il_queue_space(const struct il_queue *q)
  2442. {
  2443. int s = q->read_ptr - q->write_ptr;
  2444. if (q->read_ptr > q->write_ptr)
  2445. s -= q->n_bd;
  2446. if (s <= 0)
  2447. s += q->n_win;
  2448. /* keep some reserve to not confuse empty and full situations */
  2449. s -= 2;
  2450. if (s < 0)
  2451. s = 0;
  2452. return s;
  2453. }
  2454. EXPORT_SYMBOL(il_queue_space);
  2455. /**
  2456. * il_queue_init - Initialize queue's high/low-water and read/write idxes
  2457. */
  2458. static int
  2459. il_queue_init(struct il_priv *il, struct il_queue *q, int slots, u32 id)
  2460. {
  2461. /*
  2462. * TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
  2463. * il_queue_inc_wrap and il_queue_dec_wrap are broken.
  2464. */
  2465. BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
  2466. /* FIXME: remove q->n_bd */
  2467. q->n_bd = TFD_QUEUE_SIZE_MAX;
  2468. q->n_win = slots;
  2469. q->id = id;
  2470. /* slots_must be power-of-two size, otherwise
  2471. * il_get_cmd_idx is broken. */
  2472. BUG_ON(!is_power_of_2(slots));
  2473. q->low_mark = q->n_win / 4;
  2474. if (q->low_mark < 4)
  2475. q->low_mark = 4;
  2476. q->high_mark = q->n_win / 8;
  2477. if (q->high_mark < 2)
  2478. q->high_mark = 2;
  2479. q->write_ptr = q->read_ptr = 0;
  2480. return 0;
  2481. }
  2482. /**
  2483. * il_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
  2484. */
  2485. static int
  2486. il_tx_queue_alloc(struct il_priv *il, struct il_tx_queue *txq, u32 id)
  2487. {
  2488. struct device *dev = &il->pci_dev->dev;
  2489. size_t tfd_sz = il->hw_params.tfd_size * TFD_QUEUE_SIZE_MAX;
  2490. /* Driver ilate data, only for Tx (not command) queues,
  2491. * not shared with device. */
  2492. if (id != il->cmd_queue) {
  2493. txq->skbs = kcalloc(TFD_QUEUE_SIZE_MAX, sizeof(struct skb *),
  2494. GFP_KERNEL);
  2495. if (!txq->skbs) {
  2496. IL_ERR("Fail to alloc skbs\n");
  2497. goto error;
  2498. }
  2499. } else
  2500. txq->skbs = NULL;
  2501. /* Circular buffer of transmit frame descriptors (TFDs),
  2502. * shared with device */
  2503. txq->tfds =
  2504. dma_alloc_coherent(dev, tfd_sz, &txq->q.dma_addr, GFP_KERNEL);
  2505. if (!txq->tfds)
  2506. goto error;
  2507. txq->q.id = id;
  2508. return 0;
  2509. error:
  2510. kfree(txq->skbs);
  2511. txq->skbs = NULL;
  2512. return -ENOMEM;
  2513. }
  2514. /**
  2515. * il_tx_queue_init - Allocate and initialize one tx/cmd queue
  2516. */
  2517. int
  2518. il_tx_queue_init(struct il_priv *il, u32 txq_id)
  2519. {
  2520. int i, len, ret;
  2521. int slots, actual_slots;
  2522. struct il_tx_queue *txq = &il->txq[txq_id];
  2523. /*
  2524. * Alloc buffer array for commands (Tx or other types of commands).
  2525. * For the command queue (#4/#9), allocate command space + one big
  2526. * command for scan, since scan command is very huge; the system will
  2527. * not have two scans at the same time, so only one is needed.
  2528. * For normal Tx queues (all other queues), no super-size command
  2529. * space is needed.
  2530. */
  2531. if (txq_id == il->cmd_queue) {
  2532. slots = TFD_CMD_SLOTS;
  2533. actual_slots = slots + 1;
  2534. } else {
  2535. slots = TFD_TX_CMD_SLOTS;
  2536. actual_slots = slots;
  2537. }
  2538. txq->meta =
  2539. kzalloc(sizeof(struct il_cmd_meta) * actual_slots, GFP_KERNEL);
  2540. txq->cmd =
  2541. kzalloc(sizeof(struct il_device_cmd *) * actual_slots, GFP_KERNEL);
  2542. if (!txq->meta || !txq->cmd)
  2543. goto out_free_arrays;
  2544. len = sizeof(struct il_device_cmd);
  2545. for (i = 0; i < actual_slots; i++) {
  2546. /* only happens for cmd queue */
  2547. if (i == slots)
  2548. len = IL_MAX_CMD_SIZE;
  2549. txq->cmd[i] = kmalloc(len, GFP_KERNEL);
  2550. if (!txq->cmd[i])
  2551. goto err;
  2552. }
  2553. /* Alloc driver data array and TFD circular buffer */
  2554. ret = il_tx_queue_alloc(il, txq, txq_id);
  2555. if (ret)
  2556. goto err;
  2557. txq->need_update = 0;
  2558. /*
  2559. * For the default queues 0-3, set up the swq_id
  2560. * already -- all others need to get one later
  2561. * (if they need one at all).
  2562. */
  2563. if (txq_id < 4)
  2564. il_set_swq_id(txq, txq_id, txq_id);
  2565. /* Initialize queue's high/low-water marks, and head/tail idxes */
  2566. il_queue_init(il, &txq->q, slots, txq_id);
  2567. /* Tell device where to find queue */
  2568. il->ops->txq_init(il, txq);
  2569. return 0;
  2570. err:
  2571. for (i = 0; i < actual_slots; i++)
  2572. kfree(txq->cmd[i]);
  2573. out_free_arrays:
  2574. kfree(txq->meta);
  2575. kfree(txq->cmd);
  2576. return -ENOMEM;
  2577. }
  2578. EXPORT_SYMBOL(il_tx_queue_init);
  2579. void
  2580. il_tx_queue_reset(struct il_priv *il, u32 txq_id)
  2581. {
  2582. int slots, actual_slots;
  2583. struct il_tx_queue *txq = &il->txq[txq_id];
  2584. if (txq_id == il->cmd_queue) {
  2585. slots = TFD_CMD_SLOTS;
  2586. actual_slots = TFD_CMD_SLOTS + 1;
  2587. } else {
  2588. slots = TFD_TX_CMD_SLOTS;
  2589. actual_slots = TFD_TX_CMD_SLOTS;
  2590. }
  2591. memset(txq->meta, 0, sizeof(struct il_cmd_meta) * actual_slots);
  2592. txq->need_update = 0;
  2593. /* Initialize queue's high/low-water marks, and head/tail idxes */
  2594. il_queue_init(il, &txq->q, slots, txq_id);
  2595. /* Tell device where to find queue */
  2596. il->ops->txq_init(il, txq);
  2597. }
  2598. EXPORT_SYMBOL(il_tx_queue_reset);
  2599. /*************** HOST COMMAND QUEUE FUNCTIONS *****/
  2600. /**
  2601. * il_enqueue_hcmd - enqueue a uCode command
  2602. * @il: device ilate data point
  2603. * @cmd: a point to the ucode command structure
  2604. *
  2605. * The function returns < 0 values to indicate the operation is
  2606. * failed. On success, it turns the idx (> 0) of command in the
  2607. * command queue.
  2608. */
  2609. int
  2610. il_enqueue_hcmd(struct il_priv *il, struct il_host_cmd *cmd)
  2611. {
  2612. struct il_tx_queue *txq = &il->txq[il->cmd_queue];
  2613. struct il_queue *q = &txq->q;
  2614. struct il_device_cmd *out_cmd;
  2615. struct il_cmd_meta *out_meta;
  2616. dma_addr_t phys_addr;
  2617. unsigned long flags;
  2618. int len;
  2619. u32 idx;
  2620. u16 fix_size;
  2621. cmd->len = il->ops->get_hcmd_size(cmd->id, cmd->len);
  2622. fix_size = (u16) (cmd->len + sizeof(out_cmd->hdr));
  2623. /* If any of the command structures end up being larger than
  2624. * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
  2625. * we will need to increase the size of the TFD entries
  2626. * Also, check to see if command buffer should not exceed the size
  2627. * of device_cmd and max_cmd_size. */
  2628. BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
  2629. !(cmd->flags & CMD_SIZE_HUGE));
  2630. BUG_ON(fix_size > IL_MAX_CMD_SIZE);
  2631. if (il_is_rfkill(il) || il_is_ctkill(il)) {
  2632. IL_WARN("Not sending command - %s KILL\n",
  2633. il_is_rfkill(il) ? "RF" : "CT");
  2634. return -EIO;
  2635. }
  2636. spin_lock_irqsave(&il->hcmd_lock, flags);
  2637. if (il_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
  2638. spin_unlock_irqrestore(&il->hcmd_lock, flags);
  2639. IL_ERR("Restarting adapter due to command queue full\n");
  2640. queue_work(il->workqueue, &il->restart);
  2641. return -ENOSPC;
  2642. }
  2643. idx = il_get_cmd_idx(q, q->write_ptr, cmd->flags & CMD_SIZE_HUGE);
  2644. out_cmd = txq->cmd[idx];
  2645. out_meta = &txq->meta[idx];
  2646. if (WARN_ON(out_meta->flags & CMD_MAPPED)) {
  2647. spin_unlock_irqrestore(&il->hcmd_lock, flags);
  2648. return -ENOSPC;
  2649. }
  2650. memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */
  2651. out_meta->flags = cmd->flags | CMD_MAPPED;
  2652. if (cmd->flags & CMD_WANT_SKB)
  2653. out_meta->source = cmd;
  2654. if (cmd->flags & CMD_ASYNC)
  2655. out_meta->callback = cmd->callback;
  2656. out_cmd->hdr.cmd = cmd->id;
  2657. memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
  2658. /* At this point, the out_cmd now has all of the incoming cmd
  2659. * information */
  2660. out_cmd->hdr.flags = 0;
  2661. out_cmd->hdr.sequence =
  2662. cpu_to_le16(QUEUE_TO_SEQ(il->cmd_queue) | IDX_TO_SEQ(q->write_ptr));
  2663. if (cmd->flags & CMD_SIZE_HUGE)
  2664. out_cmd->hdr.sequence |= SEQ_HUGE_FRAME;
  2665. len = sizeof(struct il_device_cmd);
  2666. if (idx == TFD_CMD_SLOTS)
  2667. len = IL_MAX_CMD_SIZE;
  2668. #ifdef CONFIG_IWLEGACY_DEBUG
  2669. switch (out_cmd->hdr.cmd) {
  2670. case C_TX_LINK_QUALITY_CMD:
  2671. case C_SENSITIVITY:
  2672. D_HC_DUMP("Sending command %s (#%x), seq: 0x%04X, "
  2673. "%d bytes at %d[%d]:%d\n",
  2674. il_get_cmd_string(out_cmd->hdr.cmd), out_cmd->hdr.cmd,
  2675. le16_to_cpu(out_cmd->hdr.sequence), fix_size,
  2676. q->write_ptr, idx, il->cmd_queue);
  2677. break;
  2678. default:
  2679. D_HC("Sending command %s (#%x), seq: 0x%04X, "
  2680. "%d bytes at %d[%d]:%d\n",
  2681. il_get_cmd_string(out_cmd->hdr.cmd), out_cmd->hdr.cmd,
  2682. le16_to_cpu(out_cmd->hdr.sequence), fix_size, q->write_ptr,
  2683. idx, il->cmd_queue);
  2684. }
  2685. #endif
  2686. phys_addr =
  2687. pci_map_single(il->pci_dev, &out_cmd->hdr, fix_size,
  2688. PCI_DMA_BIDIRECTIONAL);
  2689. if (unlikely(pci_dma_mapping_error(il->pci_dev, phys_addr))) {
  2690. idx = -ENOMEM;
  2691. goto out;
  2692. }
  2693. dma_unmap_addr_set(out_meta, mapping, phys_addr);
  2694. dma_unmap_len_set(out_meta, len, fix_size);
  2695. txq->need_update = 1;
  2696. if (il->ops->txq_update_byte_cnt_tbl)
  2697. /* Set up entry in queue's byte count circular buffer */
  2698. il->ops->txq_update_byte_cnt_tbl(il, txq, 0);
  2699. il->ops->txq_attach_buf_to_tfd(il, txq, phys_addr, fix_size, 1,
  2700. U32_PAD(cmd->len));
  2701. /* Increment and update queue's write idx */
  2702. q->write_ptr = il_queue_inc_wrap(q->write_ptr, q->n_bd);
  2703. il_txq_update_write_ptr(il, txq);
  2704. out:
  2705. spin_unlock_irqrestore(&il->hcmd_lock, flags);
  2706. return idx;
  2707. }
  2708. /**
  2709. * il_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd
  2710. *
  2711. * When FW advances 'R' idx, all entries between old and new 'R' idx
  2712. * need to be reclaimed. As result, some free space forms. If there is
  2713. * enough free space (> low mark), wake the stack that feeds us.
  2714. */
  2715. static void
  2716. il_hcmd_queue_reclaim(struct il_priv *il, int txq_id, int idx, int cmd_idx)
  2717. {
  2718. struct il_tx_queue *txq = &il->txq[txq_id];
  2719. struct il_queue *q = &txq->q;
  2720. int nfreed = 0;
  2721. if (idx >= q->n_bd || il_queue_used(q, idx) == 0) {
  2722. IL_ERR("Read idx for DMA queue txq id (%d), idx %d, "
  2723. "is out of range [0-%d] %d %d.\n", txq_id, idx, q->n_bd,
  2724. q->write_ptr, q->read_ptr);
  2725. return;
  2726. }
  2727. for (idx = il_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx;
  2728. q->read_ptr = il_queue_inc_wrap(q->read_ptr, q->n_bd)) {
  2729. if (nfreed++ > 0) {
  2730. IL_ERR("HCMD skipped: idx (%d) %d %d\n", idx,
  2731. q->write_ptr, q->read_ptr);
  2732. queue_work(il->workqueue, &il->restart);
  2733. }
  2734. }
  2735. }
  2736. /**
  2737. * il_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
  2738. * @rxb: Rx buffer to reclaim
  2739. *
  2740. * If an Rx buffer has an async callback associated with it the callback
  2741. * will be executed. The attached skb (if present) will only be freed
  2742. * if the callback returns 1
  2743. */
  2744. void
  2745. il_tx_cmd_complete(struct il_priv *il, struct il_rx_buf *rxb)
  2746. {
  2747. struct il_rx_pkt *pkt = rxb_addr(rxb);
  2748. u16 sequence = le16_to_cpu(pkt->hdr.sequence);
  2749. int txq_id = SEQ_TO_QUEUE(sequence);
  2750. int idx = SEQ_TO_IDX(sequence);
  2751. int cmd_idx;
  2752. bool huge = !!(pkt->hdr.sequence & SEQ_HUGE_FRAME);
  2753. struct il_device_cmd *cmd;
  2754. struct il_cmd_meta *meta;
  2755. struct il_tx_queue *txq = &il->txq[il->cmd_queue];
  2756. unsigned long flags;
  2757. /* If a Tx command is being handled and it isn't in the actual
  2758. * command queue then there a command routing bug has been introduced
  2759. * in the queue management code. */
  2760. if (WARN
  2761. (txq_id != il->cmd_queue,
  2762. "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n",
  2763. txq_id, il->cmd_queue, sequence, il->txq[il->cmd_queue].q.read_ptr,
  2764. il->txq[il->cmd_queue].q.write_ptr)) {
  2765. il_print_hex_error(il, pkt, 32);
  2766. return;
  2767. }
  2768. cmd_idx = il_get_cmd_idx(&txq->q, idx, huge);
  2769. cmd = txq->cmd[cmd_idx];
  2770. meta = &txq->meta[cmd_idx];
  2771. txq->time_stamp = jiffies;
  2772. pci_unmap_single(il->pci_dev, dma_unmap_addr(meta, mapping),
  2773. dma_unmap_len(meta, len), PCI_DMA_BIDIRECTIONAL);
  2774. /* Input error checking is done when commands are added to queue. */
  2775. if (meta->flags & CMD_WANT_SKB) {
  2776. meta->source->reply_page = (unsigned long)rxb_addr(rxb);
  2777. rxb->page = NULL;
  2778. } else if (meta->callback)
  2779. meta->callback(il, cmd, pkt);
  2780. spin_lock_irqsave(&il->hcmd_lock, flags);
  2781. il_hcmd_queue_reclaim(il, txq_id, idx, cmd_idx);
  2782. if (!(meta->flags & CMD_ASYNC)) {
  2783. clear_bit(S_HCMD_ACTIVE, &il->status);
  2784. D_INFO("Clearing HCMD_ACTIVE for command %s\n",
  2785. il_get_cmd_string(cmd->hdr.cmd));
  2786. wake_up(&il->wait_command_queue);
  2787. }
  2788. /* Mark as unmapped */
  2789. meta->flags = 0;
  2790. spin_unlock_irqrestore(&il->hcmd_lock, flags);
  2791. }
  2792. EXPORT_SYMBOL(il_tx_cmd_complete);
  2793. MODULE_DESCRIPTION("iwl-legacy: common functions for 3945 and 4965");
  2794. MODULE_VERSION(IWLWIFI_VERSION);
  2795. MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
  2796. MODULE_LICENSE("GPL");
  2797. /*
  2798. * set bt_coex_active to true, uCode will do kill/defer
  2799. * every time the priority line is asserted (BT is sending signals on the
  2800. * priority line in the PCIx).
  2801. * set bt_coex_active to false, uCode will ignore the BT activity and
  2802. * perform the normal operation
  2803. *
  2804. * User might experience transmit issue on some platform due to WiFi/BT
  2805. * co-exist problem. The possible behaviors are:
  2806. * Able to scan and finding all the available AP
  2807. * Not able to associate with any AP
  2808. * On those platforms, WiFi communication can be restored by set
  2809. * "bt_coex_active" module parameter to "false"
  2810. *
  2811. * default: bt_coex_active = true (BT_COEX_ENABLE)
  2812. */
  2813. static bool bt_coex_active = true;
  2814. module_param(bt_coex_active, bool, S_IRUGO);
  2815. MODULE_PARM_DESC(bt_coex_active, "enable wifi/bluetooth co-exist");
  2816. u32 il_debug_level;
  2817. EXPORT_SYMBOL(il_debug_level);
  2818. const u8 il_bcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
  2819. EXPORT_SYMBOL(il_bcast_addr);
  2820. #define MAX_BIT_RATE_40_MHZ 150 /* Mbps */
  2821. #define MAX_BIT_RATE_20_MHZ 72 /* Mbps */
  2822. static void
  2823. il_init_ht_hw_capab(const struct il_priv *il,
  2824. struct ieee80211_sta_ht_cap *ht_info,
  2825. enum ieee80211_band band)
  2826. {
  2827. u16 max_bit_rate = 0;
  2828. u8 rx_chains_num = il->hw_params.rx_chains_num;
  2829. u8 tx_chains_num = il->hw_params.tx_chains_num;
  2830. ht_info->cap = 0;
  2831. memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
  2832. ht_info->ht_supported = true;
  2833. ht_info->cap |= IEEE80211_HT_CAP_SGI_20;
  2834. max_bit_rate = MAX_BIT_RATE_20_MHZ;
  2835. if (il->hw_params.ht40_channel & BIT(band)) {
  2836. ht_info->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
  2837. ht_info->cap |= IEEE80211_HT_CAP_SGI_40;
  2838. ht_info->mcs.rx_mask[4] = 0x01;
  2839. max_bit_rate = MAX_BIT_RATE_40_MHZ;
  2840. }
  2841. if (il->cfg->mod_params->amsdu_size_8K)
  2842. ht_info->cap |= IEEE80211_HT_CAP_MAX_AMSDU;
  2843. ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF;
  2844. ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF;
  2845. ht_info->mcs.rx_mask[0] = 0xFF;
  2846. if (rx_chains_num >= 2)
  2847. ht_info->mcs.rx_mask[1] = 0xFF;
  2848. if (rx_chains_num >= 3)
  2849. ht_info->mcs.rx_mask[2] = 0xFF;
  2850. /* Highest supported Rx data rate */
  2851. max_bit_rate *= rx_chains_num;
  2852. WARN_ON(max_bit_rate & ~IEEE80211_HT_MCS_RX_HIGHEST_MASK);
  2853. ht_info->mcs.rx_highest = cpu_to_le16(max_bit_rate);
  2854. /* Tx MCS capabilities */
  2855. ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
  2856. if (tx_chains_num != rx_chains_num) {
  2857. ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
  2858. ht_info->mcs.tx_params |=
  2859. ((tx_chains_num -
  2860. 1) << IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
  2861. }
  2862. }
  2863. /**
  2864. * il_init_geos - Initialize mac80211's geo/channel info based from eeprom
  2865. */
  2866. int
  2867. il_init_geos(struct il_priv *il)
  2868. {
  2869. struct il_channel_info *ch;
  2870. struct ieee80211_supported_band *sband;
  2871. struct ieee80211_channel *channels;
  2872. struct ieee80211_channel *geo_ch;
  2873. struct ieee80211_rate *rates;
  2874. int i = 0;
  2875. s8 max_tx_power = 0;
  2876. if (il->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
  2877. il->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
  2878. D_INFO("Geography modes already initialized.\n");
  2879. set_bit(S_GEO_CONFIGURED, &il->status);
  2880. return 0;
  2881. }
  2882. channels =
  2883. kzalloc(sizeof(struct ieee80211_channel) * il->channel_count,
  2884. GFP_KERNEL);
  2885. if (!channels)
  2886. return -ENOMEM;
  2887. rates =
  2888. kzalloc((sizeof(struct ieee80211_rate) * RATE_COUNT_LEGACY),
  2889. GFP_KERNEL);
  2890. if (!rates) {
  2891. kfree(channels);
  2892. return -ENOMEM;
  2893. }
  2894. /* 5.2GHz channels start after the 2.4GHz channels */
  2895. sband = &il->bands[IEEE80211_BAND_5GHZ];
  2896. sband->channels = &channels[ARRAY_SIZE(il_eeprom_band_1)];
  2897. /* just OFDM */
  2898. sband->bitrates = &rates[IL_FIRST_OFDM_RATE];
  2899. sband->n_bitrates = RATE_COUNT_LEGACY - IL_FIRST_OFDM_RATE;
  2900. if (il->cfg->sku & IL_SKU_N)
  2901. il_init_ht_hw_capab(il, &sband->ht_cap, IEEE80211_BAND_5GHZ);
  2902. sband = &il->bands[IEEE80211_BAND_2GHZ];
  2903. sband->channels = channels;
  2904. /* OFDM & CCK */
  2905. sband->bitrates = rates;
  2906. sband->n_bitrates = RATE_COUNT_LEGACY;
  2907. if (il->cfg->sku & IL_SKU_N)
  2908. il_init_ht_hw_capab(il, &sband->ht_cap, IEEE80211_BAND_2GHZ);
  2909. il->ieee_channels = channels;
  2910. il->ieee_rates = rates;
  2911. for (i = 0; i < il->channel_count; i++) {
  2912. ch = &il->channel_info[i];
  2913. if (!il_is_channel_valid(ch))
  2914. continue;
  2915. sband = &il->bands[ch->band];
  2916. geo_ch = &sband->channels[sband->n_channels++];
  2917. geo_ch->center_freq =
  2918. ieee80211_channel_to_frequency(ch->channel, ch->band);
  2919. geo_ch->max_power = ch->max_power_avg;
  2920. geo_ch->max_antenna_gain = 0xff;
  2921. geo_ch->hw_value = ch->channel;
  2922. if (il_is_channel_valid(ch)) {
  2923. if (!(ch->flags & EEPROM_CHANNEL_IBSS))
  2924. geo_ch->flags |= IEEE80211_CHAN_NO_IR;
  2925. if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
  2926. geo_ch->flags |= IEEE80211_CHAN_NO_IR;
  2927. if (ch->flags & EEPROM_CHANNEL_RADAR)
  2928. geo_ch->flags |= IEEE80211_CHAN_RADAR;
  2929. geo_ch->flags |= ch->ht40_extension_channel;
  2930. if (ch->max_power_avg > max_tx_power)
  2931. max_tx_power = ch->max_power_avg;
  2932. } else {
  2933. geo_ch->flags |= IEEE80211_CHAN_DISABLED;
  2934. }
  2935. D_INFO("Channel %d Freq=%d[%sGHz] %s flag=0x%X\n", ch->channel,
  2936. geo_ch->center_freq,
  2937. il_is_channel_a_band(ch) ? "5.2" : "2.4",
  2938. geo_ch->
  2939. flags & IEEE80211_CHAN_DISABLED ? "restricted" : "valid",
  2940. geo_ch->flags);
  2941. }
  2942. il->tx_power_device_lmt = max_tx_power;
  2943. il->tx_power_user_lmt = max_tx_power;
  2944. il->tx_power_next = max_tx_power;
  2945. if (il->bands[IEEE80211_BAND_5GHZ].n_channels == 0 &&
  2946. (il->cfg->sku & IL_SKU_A)) {
  2947. IL_INFO("Incorrectly detected BG card as ABG. "
  2948. "Please send your PCI ID 0x%04X:0x%04X to maintainer.\n",
  2949. il->pci_dev->device, il->pci_dev->subsystem_device);
  2950. il->cfg->sku &= ~IL_SKU_A;
  2951. }
  2952. IL_INFO("Tunable channels: %d 802.11bg, %d 802.11a channels\n",
  2953. il->bands[IEEE80211_BAND_2GHZ].n_channels,
  2954. il->bands[IEEE80211_BAND_5GHZ].n_channels);
  2955. set_bit(S_GEO_CONFIGURED, &il->status);
  2956. return 0;
  2957. }
  2958. EXPORT_SYMBOL(il_init_geos);
  2959. /*
  2960. * il_free_geos - undo allocations in il_init_geos
  2961. */
  2962. void
  2963. il_free_geos(struct il_priv *il)
  2964. {
  2965. kfree(il->ieee_channels);
  2966. kfree(il->ieee_rates);
  2967. clear_bit(S_GEO_CONFIGURED, &il->status);
  2968. }
  2969. EXPORT_SYMBOL(il_free_geos);
  2970. static bool
  2971. il_is_channel_extension(struct il_priv *il, enum ieee80211_band band,
  2972. u16 channel, u8 extension_chan_offset)
  2973. {
  2974. const struct il_channel_info *ch_info;
  2975. ch_info = il_get_channel_info(il, band, channel);
  2976. if (!il_is_channel_valid(ch_info))
  2977. return false;
  2978. if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_ABOVE)
  2979. return !(ch_info->
  2980. ht40_extension_channel & IEEE80211_CHAN_NO_HT40PLUS);
  2981. else if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_BELOW)
  2982. return !(ch_info->
  2983. ht40_extension_channel & IEEE80211_CHAN_NO_HT40MINUS);
  2984. return false;
  2985. }
  2986. bool
  2987. il_is_ht40_tx_allowed(struct il_priv *il, struct ieee80211_sta_ht_cap *ht_cap)
  2988. {
  2989. if (!il->ht.enabled || !il->ht.is_40mhz)
  2990. return false;
  2991. /*
  2992. * We do not check for IEEE80211_HT_CAP_SUP_WIDTH_20_40
  2993. * the bit will not set if it is pure 40MHz case
  2994. */
  2995. if (ht_cap && !ht_cap->ht_supported)
  2996. return false;
  2997. #ifdef CONFIG_IWLEGACY_DEBUGFS
  2998. if (il->disable_ht40)
  2999. return false;
  3000. #endif
  3001. return il_is_channel_extension(il, il->band,
  3002. le16_to_cpu(il->staging.channel),
  3003. il->ht.extension_chan_offset);
  3004. }
  3005. EXPORT_SYMBOL(il_is_ht40_tx_allowed);
  3006. static u16
  3007. il_adjust_beacon_interval(u16 beacon_val, u16 max_beacon_val)
  3008. {
  3009. u16 new_val;
  3010. u16 beacon_factor;
  3011. /*
  3012. * If mac80211 hasn't given us a beacon interval, program
  3013. * the default into the device.
  3014. */
  3015. if (!beacon_val)
  3016. return DEFAULT_BEACON_INTERVAL;
  3017. /*
  3018. * If the beacon interval we obtained from the peer
  3019. * is too large, we'll have to wake up more often
  3020. * (and in IBSS case, we'll beacon too much)
  3021. *
  3022. * For example, if max_beacon_val is 4096, and the
  3023. * requested beacon interval is 7000, we'll have to
  3024. * use 3500 to be able to wake up on the beacons.
  3025. *
  3026. * This could badly influence beacon detection stats.
  3027. */
  3028. beacon_factor = (beacon_val + max_beacon_val) / max_beacon_val;
  3029. new_val = beacon_val / beacon_factor;
  3030. if (!new_val)
  3031. new_val = max_beacon_val;
  3032. return new_val;
  3033. }
  3034. int
  3035. il_send_rxon_timing(struct il_priv *il)
  3036. {
  3037. u64 tsf;
  3038. s32 interval_tm, rem;
  3039. struct ieee80211_conf *conf = NULL;
  3040. u16 beacon_int;
  3041. struct ieee80211_vif *vif = il->vif;
  3042. conf = &il->hw->conf;
  3043. lockdep_assert_held(&il->mutex);
  3044. memset(&il->timing, 0, sizeof(struct il_rxon_time_cmd));
  3045. il->timing.timestamp = cpu_to_le64(il->timestamp);
  3046. il->timing.listen_interval = cpu_to_le16(conf->listen_interval);
  3047. beacon_int = vif ? vif->bss_conf.beacon_int : 0;
  3048. /*
  3049. * TODO: For IBSS we need to get atim_win from mac80211,
  3050. * for now just always use 0
  3051. */
  3052. il->timing.atim_win = 0;
  3053. beacon_int =
  3054. il_adjust_beacon_interval(beacon_int,
  3055. il->hw_params.max_beacon_itrvl *
  3056. TIME_UNIT);
  3057. il->timing.beacon_interval = cpu_to_le16(beacon_int);
  3058. tsf = il->timestamp; /* tsf is modifed by do_div: copy it */
  3059. interval_tm = beacon_int * TIME_UNIT;
  3060. rem = do_div(tsf, interval_tm);
  3061. il->timing.beacon_init_val = cpu_to_le32(interval_tm - rem);
  3062. il->timing.dtim_period = vif ? (vif->bss_conf.dtim_period ? : 1) : 1;
  3063. D_ASSOC("beacon interval %d beacon timer %d beacon tim %d\n",
  3064. le16_to_cpu(il->timing.beacon_interval),
  3065. le32_to_cpu(il->timing.beacon_init_val),
  3066. le16_to_cpu(il->timing.atim_win));
  3067. return il_send_cmd_pdu(il, C_RXON_TIMING, sizeof(il->timing),
  3068. &il->timing);
  3069. }
  3070. EXPORT_SYMBOL(il_send_rxon_timing);
  3071. void
  3072. il_set_rxon_hwcrypto(struct il_priv *il, int hw_decrypt)
  3073. {
  3074. struct il_rxon_cmd *rxon = &il->staging;
  3075. if (hw_decrypt)
  3076. rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
  3077. else
  3078. rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK;
  3079. }
  3080. EXPORT_SYMBOL(il_set_rxon_hwcrypto);
  3081. /* validate RXON structure is valid */
  3082. int
  3083. il_check_rxon_cmd(struct il_priv *il)
  3084. {
  3085. struct il_rxon_cmd *rxon = &il->staging;
  3086. bool error = false;
  3087. if (rxon->flags & RXON_FLG_BAND_24G_MSK) {
  3088. if (rxon->flags & RXON_FLG_TGJ_NARROW_BAND_MSK) {
  3089. IL_WARN("check 2.4G: wrong narrow\n");
  3090. error = true;
  3091. }
  3092. if (rxon->flags & RXON_FLG_RADAR_DETECT_MSK) {
  3093. IL_WARN("check 2.4G: wrong radar\n");
  3094. error = true;
  3095. }
  3096. } else {
  3097. if (!(rxon->flags & RXON_FLG_SHORT_SLOT_MSK)) {
  3098. IL_WARN("check 5.2G: not short slot!\n");
  3099. error = true;
  3100. }
  3101. if (rxon->flags & RXON_FLG_CCK_MSK) {
  3102. IL_WARN("check 5.2G: CCK!\n");
  3103. error = true;
  3104. }
  3105. }
  3106. if ((rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1) {
  3107. IL_WARN("mac/bssid mcast!\n");
  3108. error = true;
  3109. }
  3110. /* make sure basic rates 6Mbps and 1Mbps are supported */
  3111. if ((rxon->ofdm_basic_rates & RATE_6M_MASK) == 0 &&
  3112. (rxon->cck_basic_rates & RATE_1M_MASK) == 0) {
  3113. IL_WARN("neither 1 nor 6 are basic\n");
  3114. error = true;
  3115. }
  3116. if (le16_to_cpu(rxon->assoc_id) > 2007) {
  3117. IL_WARN("aid > 2007\n");
  3118. error = true;
  3119. }
  3120. if ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK)) ==
  3121. (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK)) {
  3122. IL_WARN("CCK and short slot\n");
  3123. error = true;
  3124. }
  3125. if ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK)) ==
  3126. (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK)) {
  3127. IL_WARN("CCK and auto detect");
  3128. error = true;
  3129. }
  3130. if ((rxon->
  3131. flags & (RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK)) ==
  3132. RXON_FLG_TGG_PROTECT_MSK) {
  3133. IL_WARN("TGg but no auto-detect\n");
  3134. error = true;
  3135. }
  3136. if (error)
  3137. IL_WARN("Tuning to channel %d\n", le16_to_cpu(rxon->channel));
  3138. if (error) {
  3139. IL_ERR("Invalid RXON\n");
  3140. return -EINVAL;
  3141. }
  3142. return 0;
  3143. }
  3144. EXPORT_SYMBOL(il_check_rxon_cmd);
  3145. /**
  3146. * il_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed
  3147. * @il: staging_rxon is compared to active_rxon
  3148. *
  3149. * If the RXON structure is changing enough to require a new tune,
  3150. * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that
  3151. * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required.
  3152. */
  3153. int
  3154. il_full_rxon_required(struct il_priv *il)
  3155. {
  3156. const struct il_rxon_cmd *staging = &il->staging;
  3157. const struct il_rxon_cmd *active = &il->active;
  3158. #define CHK(cond) \
  3159. if ((cond)) { \
  3160. D_INFO("need full RXON - " #cond "\n"); \
  3161. return 1; \
  3162. }
  3163. #define CHK_NEQ(c1, c2) \
  3164. if ((c1) != (c2)) { \
  3165. D_INFO("need full RXON - " \
  3166. #c1 " != " #c2 " - %d != %d\n", \
  3167. (c1), (c2)); \
  3168. return 1; \
  3169. }
  3170. /* These items are only settable from the full RXON command */
  3171. CHK(!il_is_associated(il));
  3172. CHK(!ether_addr_equal_64bits(staging->bssid_addr, active->bssid_addr));
  3173. CHK(!ether_addr_equal_64bits(staging->node_addr, active->node_addr));
  3174. CHK(!ether_addr_equal_64bits(staging->wlap_bssid_addr,
  3175. active->wlap_bssid_addr));
  3176. CHK_NEQ(staging->dev_type, active->dev_type);
  3177. CHK_NEQ(staging->channel, active->channel);
  3178. CHK_NEQ(staging->air_propagation, active->air_propagation);
  3179. CHK_NEQ(staging->ofdm_ht_single_stream_basic_rates,
  3180. active->ofdm_ht_single_stream_basic_rates);
  3181. CHK_NEQ(staging->ofdm_ht_dual_stream_basic_rates,
  3182. active->ofdm_ht_dual_stream_basic_rates);
  3183. CHK_NEQ(staging->assoc_id, active->assoc_id);
  3184. /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can
  3185. * be updated with the RXON_ASSOC command -- however only some
  3186. * flag transitions are allowed using RXON_ASSOC */
  3187. /* Check if we are not switching bands */
  3188. CHK_NEQ(staging->flags & RXON_FLG_BAND_24G_MSK,
  3189. active->flags & RXON_FLG_BAND_24G_MSK);
  3190. /* Check if we are switching association toggle */
  3191. CHK_NEQ(staging->filter_flags & RXON_FILTER_ASSOC_MSK,
  3192. active->filter_flags & RXON_FILTER_ASSOC_MSK);
  3193. #undef CHK
  3194. #undef CHK_NEQ
  3195. return 0;
  3196. }
  3197. EXPORT_SYMBOL(il_full_rxon_required);
  3198. u8
  3199. il_get_lowest_plcp(struct il_priv *il)
  3200. {
  3201. /*
  3202. * Assign the lowest rate -- should really get this from
  3203. * the beacon skb from mac80211.
  3204. */
  3205. if (il->staging.flags & RXON_FLG_BAND_24G_MSK)
  3206. return RATE_1M_PLCP;
  3207. else
  3208. return RATE_6M_PLCP;
  3209. }
  3210. EXPORT_SYMBOL(il_get_lowest_plcp);
  3211. static void
  3212. _il_set_rxon_ht(struct il_priv *il, struct il_ht_config *ht_conf)
  3213. {
  3214. struct il_rxon_cmd *rxon = &il->staging;
  3215. if (!il->ht.enabled) {
  3216. rxon->flags &=
  3217. ~(RXON_FLG_CHANNEL_MODE_MSK |
  3218. RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK | RXON_FLG_HT40_PROT_MSK
  3219. | RXON_FLG_HT_PROT_MSK);
  3220. return;
  3221. }
  3222. rxon->flags |=
  3223. cpu_to_le32(il->ht.protection << RXON_FLG_HT_OPERATING_MODE_POS);
  3224. /* Set up channel bandwidth:
  3225. * 20 MHz only, 20/40 mixed or pure 40 if ht40 ok */
  3226. /* clear the HT channel mode before set the mode */
  3227. rxon->flags &=
  3228. ~(RXON_FLG_CHANNEL_MODE_MSK | RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
  3229. if (il_is_ht40_tx_allowed(il, NULL)) {
  3230. /* pure ht40 */
  3231. if (il->ht.protection == IEEE80211_HT_OP_MODE_PROTECTION_20MHZ) {
  3232. rxon->flags |= RXON_FLG_CHANNEL_MODE_PURE_40;
  3233. /* Note: control channel is opposite of extension channel */
  3234. switch (il->ht.extension_chan_offset) {
  3235. case IEEE80211_HT_PARAM_CHA_SEC_ABOVE:
  3236. rxon->flags &=
  3237. ~RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
  3238. break;
  3239. case IEEE80211_HT_PARAM_CHA_SEC_BELOW:
  3240. rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
  3241. break;
  3242. }
  3243. } else {
  3244. /* Note: control channel is opposite of extension channel */
  3245. switch (il->ht.extension_chan_offset) {
  3246. case IEEE80211_HT_PARAM_CHA_SEC_ABOVE:
  3247. rxon->flags &=
  3248. ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
  3249. rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED;
  3250. break;
  3251. case IEEE80211_HT_PARAM_CHA_SEC_BELOW:
  3252. rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
  3253. rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED;
  3254. break;
  3255. case IEEE80211_HT_PARAM_CHA_SEC_NONE:
  3256. default:
  3257. /* channel location only valid if in Mixed mode */
  3258. IL_ERR("invalid extension channel offset\n");
  3259. break;
  3260. }
  3261. }
  3262. } else {
  3263. rxon->flags |= RXON_FLG_CHANNEL_MODE_LEGACY;
  3264. }
  3265. if (il->ops->set_rxon_chain)
  3266. il->ops->set_rxon_chain(il);
  3267. D_ASSOC("rxon flags 0x%X operation mode :0x%X "
  3268. "extension channel offset 0x%x\n", le32_to_cpu(rxon->flags),
  3269. il->ht.protection, il->ht.extension_chan_offset);
  3270. }
  3271. void
  3272. il_set_rxon_ht(struct il_priv *il, struct il_ht_config *ht_conf)
  3273. {
  3274. _il_set_rxon_ht(il, ht_conf);
  3275. }
  3276. EXPORT_SYMBOL(il_set_rxon_ht);
  3277. /* Return valid, unused, channel for a passive scan to reset the RF */
  3278. u8
  3279. il_get_single_channel_number(struct il_priv *il, enum ieee80211_band band)
  3280. {
  3281. const struct il_channel_info *ch_info;
  3282. int i;
  3283. u8 channel = 0;
  3284. u8 min, max;
  3285. if (band == IEEE80211_BAND_5GHZ) {
  3286. min = 14;
  3287. max = il->channel_count;
  3288. } else {
  3289. min = 0;
  3290. max = 14;
  3291. }
  3292. for (i = min; i < max; i++) {
  3293. channel = il->channel_info[i].channel;
  3294. if (channel == le16_to_cpu(il->staging.channel))
  3295. continue;
  3296. ch_info = il_get_channel_info(il, band, channel);
  3297. if (il_is_channel_valid(ch_info))
  3298. break;
  3299. }
  3300. return channel;
  3301. }
  3302. EXPORT_SYMBOL(il_get_single_channel_number);
  3303. /**
  3304. * il_set_rxon_channel - Set the band and channel values in staging RXON
  3305. * @ch: requested channel as a pointer to struct ieee80211_channel
  3306. * NOTE: Does not commit to the hardware; it sets appropriate bit fields
  3307. * in the staging RXON flag structure based on the ch->band
  3308. */
  3309. int
  3310. il_set_rxon_channel(struct il_priv *il, struct ieee80211_channel *ch)
  3311. {
  3312. enum ieee80211_band band = ch->band;
  3313. u16 channel = ch->hw_value;
  3314. if (le16_to_cpu(il->staging.channel) == channel && il->band == band)
  3315. return 0;
  3316. il->staging.channel = cpu_to_le16(channel);
  3317. if (band == IEEE80211_BAND_5GHZ)
  3318. il->staging.flags &= ~RXON_FLG_BAND_24G_MSK;
  3319. else
  3320. il->staging.flags |= RXON_FLG_BAND_24G_MSK;
  3321. il->band = band;
  3322. D_INFO("Staging channel set to %d [%d]\n", channel, band);
  3323. return 0;
  3324. }
  3325. EXPORT_SYMBOL(il_set_rxon_channel);
  3326. void
  3327. il_set_flags_for_band(struct il_priv *il, enum ieee80211_band band,
  3328. struct ieee80211_vif *vif)
  3329. {
  3330. if (band == IEEE80211_BAND_5GHZ) {
  3331. il->staging.flags &=
  3332. ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK |
  3333. RXON_FLG_CCK_MSK);
  3334. il->staging.flags |= RXON_FLG_SHORT_SLOT_MSK;
  3335. } else {
  3336. /* Copied from il_post_associate() */
  3337. if (vif && vif->bss_conf.use_short_slot)
  3338. il->staging.flags |= RXON_FLG_SHORT_SLOT_MSK;
  3339. else
  3340. il->staging.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  3341. il->staging.flags |= RXON_FLG_BAND_24G_MSK;
  3342. il->staging.flags |= RXON_FLG_AUTO_DETECT_MSK;
  3343. il->staging.flags &= ~RXON_FLG_CCK_MSK;
  3344. }
  3345. }
  3346. EXPORT_SYMBOL(il_set_flags_for_band);
  3347. /*
  3348. * initialize rxon structure with default values from eeprom
  3349. */
  3350. void
  3351. il_connection_init_rx_config(struct il_priv *il)
  3352. {
  3353. const struct il_channel_info *ch_info;
  3354. memset(&il->staging, 0, sizeof(il->staging));
  3355. switch (il->iw_mode) {
  3356. case NL80211_IFTYPE_UNSPECIFIED:
  3357. il->staging.dev_type = RXON_DEV_TYPE_ESS;
  3358. break;
  3359. case NL80211_IFTYPE_STATION:
  3360. il->staging.dev_type = RXON_DEV_TYPE_ESS;
  3361. il->staging.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK;
  3362. break;
  3363. case NL80211_IFTYPE_ADHOC:
  3364. il->staging.dev_type = RXON_DEV_TYPE_IBSS;
  3365. il->staging.flags = RXON_FLG_SHORT_PREAMBLE_MSK;
  3366. il->staging.filter_flags =
  3367. RXON_FILTER_BCON_AWARE_MSK | RXON_FILTER_ACCEPT_GRP_MSK;
  3368. break;
  3369. default:
  3370. IL_ERR("Unsupported interface type %d\n", il->vif->type);
  3371. return;
  3372. }
  3373. #if 0
  3374. /* TODO: Figure out when short_preamble would be set and cache from
  3375. * that */
  3376. if (!hw_to_local(il->hw)->short_preamble)
  3377. il->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  3378. else
  3379. il->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  3380. #endif
  3381. ch_info =
  3382. il_get_channel_info(il, il->band, le16_to_cpu(il->active.channel));
  3383. if (!ch_info)
  3384. ch_info = &il->channel_info[0];
  3385. il->staging.channel = cpu_to_le16(ch_info->channel);
  3386. il->band = ch_info->band;
  3387. il_set_flags_for_band(il, il->band, il->vif);
  3388. il->staging.ofdm_basic_rates =
  3389. (IL_OFDM_RATES_MASK >> IL_FIRST_OFDM_RATE) & 0xFF;
  3390. il->staging.cck_basic_rates =
  3391. (IL_CCK_RATES_MASK >> IL_FIRST_CCK_RATE) & 0xF;
  3392. /* clear both MIX and PURE40 mode flag */
  3393. il->staging.flags &=
  3394. ~(RXON_FLG_CHANNEL_MODE_MIXED | RXON_FLG_CHANNEL_MODE_PURE_40);
  3395. if (il->vif)
  3396. memcpy(il->staging.node_addr, il->vif->addr, ETH_ALEN);
  3397. il->staging.ofdm_ht_single_stream_basic_rates = 0xff;
  3398. il->staging.ofdm_ht_dual_stream_basic_rates = 0xff;
  3399. }
  3400. EXPORT_SYMBOL(il_connection_init_rx_config);
  3401. void
  3402. il_set_rate(struct il_priv *il)
  3403. {
  3404. const struct ieee80211_supported_band *hw = NULL;
  3405. struct ieee80211_rate *rate;
  3406. int i;
  3407. hw = il_get_hw_mode(il, il->band);
  3408. if (!hw) {
  3409. IL_ERR("Failed to set rate: unable to get hw mode\n");
  3410. return;
  3411. }
  3412. il->active_rate = 0;
  3413. for (i = 0; i < hw->n_bitrates; i++) {
  3414. rate = &(hw->bitrates[i]);
  3415. if (rate->hw_value < RATE_COUNT_LEGACY)
  3416. il->active_rate |= (1 << rate->hw_value);
  3417. }
  3418. D_RATE("Set active_rate = %0x\n", il->active_rate);
  3419. il->staging.cck_basic_rates =
  3420. (IL_CCK_BASIC_RATES_MASK >> IL_FIRST_CCK_RATE) & 0xF;
  3421. il->staging.ofdm_basic_rates =
  3422. (IL_OFDM_BASIC_RATES_MASK >> IL_FIRST_OFDM_RATE) & 0xFF;
  3423. }
  3424. EXPORT_SYMBOL(il_set_rate);
  3425. void
  3426. il_chswitch_done(struct il_priv *il, bool is_success)
  3427. {
  3428. if (test_bit(S_EXIT_PENDING, &il->status))
  3429. return;
  3430. if (test_and_clear_bit(S_CHANNEL_SWITCH_PENDING, &il->status))
  3431. ieee80211_chswitch_done(il->vif, is_success);
  3432. }
  3433. EXPORT_SYMBOL(il_chswitch_done);
  3434. void
  3435. il_hdl_csa(struct il_priv *il, struct il_rx_buf *rxb)
  3436. {
  3437. struct il_rx_pkt *pkt = rxb_addr(rxb);
  3438. struct il_csa_notification *csa = &(pkt->u.csa_notif);
  3439. struct il_rxon_cmd *rxon = (void *)&il->active;
  3440. if (!test_bit(S_CHANNEL_SWITCH_PENDING, &il->status))
  3441. return;
  3442. if (!le32_to_cpu(csa->status) && csa->channel == il->switch_channel) {
  3443. rxon->channel = csa->channel;
  3444. il->staging.channel = csa->channel;
  3445. D_11H("CSA notif: channel %d\n", le16_to_cpu(csa->channel));
  3446. il_chswitch_done(il, true);
  3447. } else {
  3448. IL_ERR("CSA notif (fail) : channel %d\n",
  3449. le16_to_cpu(csa->channel));
  3450. il_chswitch_done(il, false);
  3451. }
  3452. }
  3453. EXPORT_SYMBOL(il_hdl_csa);
  3454. #ifdef CONFIG_IWLEGACY_DEBUG
  3455. void
  3456. il_print_rx_config_cmd(struct il_priv *il)
  3457. {
  3458. struct il_rxon_cmd *rxon = &il->staging;
  3459. D_RADIO("RX CONFIG:\n");
  3460. il_print_hex_dump(il, IL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
  3461. D_RADIO("u16 channel: 0x%x\n", le16_to_cpu(rxon->channel));
  3462. D_RADIO("u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
  3463. D_RADIO("u32 filter_flags: 0x%08x\n", le32_to_cpu(rxon->filter_flags));
  3464. D_RADIO("u8 dev_type: 0x%x\n", rxon->dev_type);
  3465. D_RADIO("u8 ofdm_basic_rates: 0x%02x\n", rxon->ofdm_basic_rates);
  3466. D_RADIO("u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates);
  3467. D_RADIO("u8[6] node_addr: %pM\n", rxon->node_addr);
  3468. D_RADIO("u8[6] bssid_addr: %pM\n", rxon->bssid_addr);
  3469. D_RADIO("u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
  3470. }
  3471. EXPORT_SYMBOL(il_print_rx_config_cmd);
  3472. #endif
  3473. /**
  3474. * il_irq_handle_error - called for HW or SW error interrupt from card
  3475. */
  3476. void
  3477. il_irq_handle_error(struct il_priv *il)
  3478. {
  3479. /* Set the FW error flag -- cleared on il_down */
  3480. set_bit(S_FW_ERROR, &il->status);
  3481. /* Cancel currently queued command. */
  3482. clear_bit(S_HCMD_ACTIVE, &il->status);
  3483. IL_ERR("Loaded firmware version: %s\n", il->hw->wiphy->fw_version);
  3484. il->ops->dump_nic_error_log(il);
  3485. if (il->ops->dump_fh)
  3486. il->ops->dump_fh(il, NULL, false);
  3487. #ifdef CONFIG_IWLEGACY_DEBUG
  3488. if (il_get_debug_level(il) & IL_DL_FW_ERRORS)
  3489. il_print_rx_config_cmd(il);
  3490. #endif
  3491. wake_up(&il->wait_command_queue);
  3492. /* Keep the restart process from trying to send host
  3493. * commands by clearing the INIT status bit */
  3494. clear_bit(S_READY, &il->status);
  3495. if (!test_bit(S_EXIT_PENDING, &il->status)) {
  3496. IL_DBG(IL_DL_FW_ERRORS,
  3497. "Restarting adapter due to uCode error.\n");
  3498. if (il->cfg->mod_params->restart_fw)
  3499. queue_work(il->workqueue, &il->restart);
  3500. }
  3501. }
  3502. EXPORT_SYMBOL(il_irq_handle_error);
  3503. static int
  3504. _il_apm_stop_master(struct il_priv *il)
  3505. {
  3506. int ret = 0;
  3507. /* stop device's busmaster DMA activity */
  3508. _il_set_bit(il, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
  3509. ret =
  3510. _il_poll_bit(il, CSR_RESET, CSR_RESET_REG_FLAG_MASTER_DISABLED,
  3511. CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
  3512. if (ret < 0)
  3513. IL_WARN("Master Disable Timed Out, 100 usec\n");
  3514. D_INFO("stop master\n");
  3515. return ret;
  3516. }
  3517. void
  3518. _il_apm_stop(struct il_priv *il)
  3519. {
  3520. lockdep_assert_held(&il->reg_lock);
  3521. D_INFO("Stop card, put in low power state\n");
  3522. /* Stop device's DMA activity */
  3523. _il_apm_stop_master(il);
  3524. /* Reset the entire device */
  3525. _il_set_bit(il, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
  3526. udelay(10);
  3527. /*
  3528. * Clear "initialization complete" bit to move adapter from
  3529. * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
  3530. */
  3531. _il_clear_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
  3532. }
  3533. EXPORT_SYMBOL(_il_apm_stop);
  3534. void
  3535. il_apm_stop(struct il_priv *il)
  3536. {
  3537. unsigned long flags;
  3538. spin_lock_irqsave(&il->reg_lock, flags);
  3539. _il_apm_stop(il);
  3540. spin_unlock_irqrestore(&il->reg_lock, flags);
  3541. }
  3542. EXPORT_SYMBOL(il_apm_stop);
  3543. /*
  3544. * Start up NIC's basic functionality after it has been reset
  3545. * (e.g. after platform boot, or shutdown via il_apm_stop())
  3546. * NOTE: This does not load uCode nor start the embedded processor
  3547. */
  3548. int
  3549. il_apm_init(struct il_priv *il)
  3550. {
  3551. int ret = 0;
  3552. u16 lctl;
  3553. D_INFO("Init card's basic functions\n");
  3554. /*
  3555. * Use "set_bit" below rather than "write", to preserve any hardware
  3556. * bits already set by default after reset.
  3557. */
  3558. /* Disable L0S exit timer (platform NMI Work/Around) */
  3559. il_set_bit(il, CSR_GIO_CHICKEN_BITS,
  3560. CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
  3561. /*
  3562. * Disable L0s without affecting L1;
  3563. * don't wait for ICH L0s (ICH bug W/A)
  3564. */
  3565. il_set_bit(il, CSR_GIO_CHICKEN_BITS,
  3566. CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
  3567. /* Set FH wait threshold to maximum (HW error during stress W/A) */
  3568. il_set_bit(il, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
  3569. /*
  3570. * Enable HAP INTA (interrupt from management bus) to
  3571. * wake device's PCI Express link L1a -> L0s
  3572. * NOTE: This is no-op for 3945 (non-existent bit)
  3573. */
  3574. il_set_bit(il, CSR_HW_IF_CONFIG_REG,
  3575. CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
  3576. /*
  3577. * HW bug W/A for instability in PCIe bus L0->L0S->L1 transition.
  3578. * Check if BIOS (or OS) enabled L1-ASPM on this device.
  3579. * If so (likely), disable L0S, so device moves directly L0->L1;
  3580. * costs negligible amount of power savings.
  3581. * If not (unlikely), enable L0S, so there is at least some
  3582. * power savings, even without L1.
  3583. */
  3584. if (il->cfg->set_l0s) {
  3585. pcie_capability_read_word(il->pci_dev, PCI_EXP_LNKCTL, &lctl);
  3586. if (lctl & PCI_EXP_LNKCTL_ASPM_L1) {
  3587. /* L1-ASPM enabled; disable(!) L0S */
  3588. il_set_bit(il, CSR_GIO_REG,
  3589. CSR_GIO_REG_VAL_L0S_ENABLED);
  3590. D_POWER("L1 Enabled; Disabling L0S\n");
  3591. } else {
  3592. /* L1-ASPM disabled; enable(!) L0S */
  3593. il_clear_bit(il, CSR_GIO_REG,
  3594. CSR_GIO_REG_VAL_L0S_ENABLED);
  3595. D_POWER("L1 Disabled; Enabling L0S\n");
  3596. }
  3597. }
  3598. /* Configure analog phase-lock-loop before activating to D0A */
  3599. if (il->cfg->pll_cfg_val)
  3600. il_set_bit(il, CSR_ANA_PLL_CFG,
  3601. il->cfg->pll_cfg_val);
  3602. /*
  3603. * Set "initialization complete" bit to move adapter from
  3604. * D0U* --> D0A* (powered-up active) state.
  3605. */
  3606. il_set_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
  3607. /*
  3608. * Wait for clock stabilization; once stabilized, access to
  3609. * device-internal resources is supported, e.g. il_wr_prph()
  3610. * and accesses to uCode SRAM.
  3611. */
  3612. ret =
  3613. _il_poll_bit(il, CSR_GP_CNTRL,
  3614. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
  3615. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
  3616. if (ret < 0) {
  3617. D_INFO("Failed to init the card\n");
  3618. goto out;
  3619. }
  3620. /*
  3621. * Enable DMA and BSM (if used) clocks, wait for them to stabilize.
  3622. * BSM (Boostrap State Machine) is only in 3945 and 4965.
  3623. *
  3624. * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits
  3625. * do not disable clocks. This preserves any hardware bits already
  3626. * set by default in "CLK_CTRL_REG" after reset.
  3627. */
  3628. if (il->cfg->use_bsm)
  3629. il_wr_prph(il, APMG_CLK_EN_REG,
  3630. APMG_CLK_VAL_DMA_CLK_RQT | APMG_CLK_VAL_BSM_CLK_RQT);
  3631. else
  3632. il_wr_prph(il, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
  3633. udelay(20);
  3634. /* Disable L1-Active */
  3635. il_set_bits_prph(il, APMG_PCIDEV_STT_REG,
  3636. APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
  3637. out:
  3638. return ret;
  3639. }
  3640. EXPORT_SYMBOL(il_apm_init);
  3641. int
  3642. il_set_tx_power(struct il_priv *il, s8 tx_power, bool force)
  3643. {
  3644. int ret;
  3645. s8 prev_tx_power;
  3646. bool defer;
  3647. lockdep_assert_held(&il->mutex);
  3648. if (il->tx_power_user_lmt == tx_power && !force)
  3649. return 0;
  3650. if (!il->ops->send_tx_power)
  3651. return -EOPNOTSUPP;
  3652. /* 0 dBm mean 1 milliwatt */
  3653. if (tx_power < 0) {
  3654. IL_WARN("Requested user TXPOWER %d below 1 mW.\n", tx_power);
  3655. return -EINVAL;
  3656. }
  3657. if (tx_power > il->tx_power_device_lmt) {
  3658. IL_WARN("Requested user TXPOWER %d above upper limit %d.\n",
  3659. tx_power, il->tx_power_device_lmt);
  3660. return -EINVAL;
  3661. }
  3662. if (!il_is_ready_rf(il))
  3663. return -EIO;
  3664. /* scan complete and commit_rxon use tx_power_next value,
  3665. * it always need to be updated for newest request */
  3666. il->tx_power_next = tx_power;
  3667. /* do not set tx power when scanning or channel changing */
  3668. defer = test_bit(S_SCANNING, &il->status) ||
  3669. memcmp(&il->active, &il->staging, sizeof(il->staging));
  3670. if (defer && !force) {
  3671. D_INFO("Deferring tx power set\n");
  3672. return 0;
  3673. }
  3674. prev_tx_power = il->tx_power_user_lmt;
  3675. il->tx_power_user_lmt = tx_power;
  3676. ret = il->ops->send_tx_power(il);
  3677. /* if fail to set tx_power, restore the orig. tx power */
  3678. if (ret) {
  3679. il->tx_power_user_lmt = prev_tx_power;
  3680. il->tx_power_next = prev_tx_power;
  3681. }
  3682. return ret;
  3683. }
  3684. EXPORT_SYMBOL(il_set_tx_power);
  3685. void
  3686. il_send_bt_config(struct il_priv *il)
  3687. {
  3688. struct il_bt_cmd bt_cmd = {
  3689. .lead_time = BT_LEAD_TIME_DEF,
  3690. .max_kill = BT_MAX_KILL_DEF,
  3691. .kill_ack_mask = 0,
  3692. .kill_cts_mask = 0,
  3693. };
  3694. if (!bt_coex_active)
  3695. bt_cmd.flags = BT_COEX_DISABLE;
  3696. else
  3697. bt_cmd.flags = BT_COEX_ENABLE;
  3698. D_INFO("BT coex %s\n",
  3699. (bt_cmd.flags == BT_COEX_DISABLE) ? "disable" : "active");
  3700. if (il_send_cmd_pdu(il, C_BT_CONFIG, sizeof(struct il_bt_cmd), &bt_cmd))
  3701. IL_ERR("failed to send BT Coex Config\n");
  3702. }
  3703. EXPORT_SYMBOL(il_send_bt_config);
  3704. int
  3705. il_send_stats_request(struct il_priv *il, u8 flags, bool clear)
  3706. {
  3707. struct il_stats_cmd stats_cmd = {
  3708. .configuration_flags = clear ? IL_STATS_CONF_CLEAR_STATS : 0,
  3709. };
  3710. if (flags & CMD_ASYNC)
  3711. return il_send_cmd_pdu_async(il, C_STATS, sizeof(struct il_stats_cmd),
  3712. &stats_cmd, NULL);
  3713. else
  3714. return il_send_cmd_pdu(il, C_STATS, sizeof(struct il_stats_cmd),
  3715. &stats_cmd);
  3716. }
  3717. EXPORT_SYMBOL(il_send_stats_request);
  3718. void
  3719. il_hdl_pm_sleep(struct il_priv *il, struct il_rx_buf *rxb)
  3720. {
  3721. #ifdef CONFIG_IWLEGACY_DEBUG
  3722. struct il_rx_pkt *pkt = rxb_addr(rxb);
  3723. struct il_sleep_notification *sleep = &(pkt->u.sleep_notif);
  3724. D_RX("sleep mode: %d, src: %d\n",
  3725. sleep->pm_sleep_mode, sleep->pm_wakeup_src);
  3726. #endif
  3727. }
  3728. EXPORT_SYMBOL(il_hdl_pm_sleep);
  3729. void
  3730. il_hdl_pm_debug_stats(struct il_priv *il, struct il_rx_buf *rxb)
  3731. {
  3732. struct il_rx_pkt *pkt = rxb_addr(rxb);
  3733. u32 len = le32_to_cpu(pkt->len_n_flags) & IL_RX_FRAME_SIZE_MSK;
  3734. D_RADIO("Dumping %d bytes of unhandled notification for %s:\n", len,
  3735. il_get_cmd_string(pkt->hdr.cmd));
  3736. il_print_hex_dump(il, IL_DL_RADIO, pkt->u.raw, len);
  3737. }
  3738. EXPORT_SYMBOL(il_hdl_pm_debug_stats);
  3739. void
  3740. il_hdl_error(struct il_priv *il, struct il_rx_buf *rxb)
  3741. {
  3742. struct il_rx_pkt *pkt = rxb_addr(rxb);
  3743. IL_ERR("Error Reply type 0x%08X cmd %s (0x%02X) "
  3744. "seq 0x%04X ser 0x%08X\n",
  3745. le32_to_cpu(pkt->u.err_resp.error_type),
  3746. il_get_cmd_string(pkt->u.err_resp.cmd_id),
  3747. pkt->u.err_resp.cmd_id,
  3748. le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num),
  3749. le32_to_cpu(pkt->u.err_resp.error_info));
  3750. }
  3751. EXPORT_SYMBOL(il_hdl_error);
  3752. void
  3753. il_clear_isr_stats(struct il_priv *il)
  3754. {
  3755. memset(&il->isr_stats, 0, sizeof(il->isr_stats));
  3756. }
  3757. int
  3758. il_mac_conf_tx(struct ieee80211_hw *hw, struct ieee80211_vif *vif, u16 queue,
  3759. const struct ieee80211_tx_queue_params *params)
  3760. {
  3761. struct il_priv *il = hw->priv;
  3762. unsigned long flags;
  3763. int q;
  3764. D_MAC80211("enter\n");
  3765. if (!il_is_ready_rf(il)) {
  3766. D_MAC80211("leave - RF not ready\n");
  3767. return -EIO;
  3768. }
  3769. if (queue >= AC_NUM) {
  3770. D_MAC80211("leave - queue >= AC_NUM %d\n", queue);
  3771. return 0;
  3772. }
  3773. q = AC_NUM - 1 - queue;
  3774. spin_lock_irqsave(&il->lock, flags);
  3775. il->qos_data.def_qos_parm.ac[q].cw_min =
  3776. cpu_to_le16(params->cw_min);
  3777. il->qos_data.def_qos_parm.ac[q].cw_max =
  3778. cpu_to_le16(params->cw_max);
  3779. il->qos_data.def_qos_parm.ac[q].aifsn = params->aifs;
  3780. il->qos_data.def_qos_parm.ac[q].edca_txop =
  3781. cpu_to_le16((params->txop * 32));
  3782. il->qos_data.def_qos_parm.ac[q].reserved1 = 0;
  3783. spin_unlock_irqrestore(&il->lock, flags);
  3784. D_MAC80211("leave\n");
  3785. return 0;
  3786. }
  3787. EXPORT_SYMBOL(il_mac_conf_tx);
  3788. int
  3789. il_mac_tx_last_beacon(struct ieee80211_hw *hw)
  3790. {
  3791. struct il_priv *il = hw->priv;
  3792. int ret;
  3793. D_MAC80211("enter\n");
  3794. ret = (il->ibss_manager == IL_IBSS_MANAGER);
  3795. D_MAC80211("leave ret %d\n", ret);
  3796. return ret;
  3797. }
  3798. EXPORT_SYMBOL_GPL(il_mac_tx_last_beacon);
  3799. static int
  3800. il_set_mode(struct il_priv *il)
  3801. {
  3802. il_connection_init_rx_config(il);
  3803. if (il->ops->set_rxon_chain)
  3804. il->ops->set_rxon_chain(il);
  3805. return il_commit_rxon(il);
  3806. }
  3807. int
  3808. il_mac_add_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
  3809. {
  3810. struct il_priv *il = hw->priv;
  3811. int err;
  3812. bool reset;
  3813. mutex_lock(&il->mutex);
  3814. D_MAC80211("enter: type %d, addr %pM\n", vif->type, vif->addr);
  3815. if (!il_is_ready_rf(il)) {
  3816. IL_WARN("Try to add interface when device not ready\n");
  3817. err = -EINVAL;
  3818. goto out;
  3819. }
  3820. /*
  3821. * We do not support multiple virtual interfaces, but on hardware reset
  3822. * we have to add the same interface again.
  3823. */
  3824. reset = (il->vif == vif);
  3825. if (il->vif && !reset) {
  3826. err = -EOPNOTSUPP;
  3827. goto out;
  3828. }
  3829. il->vif = vif;
  3830. il->iw_mode = vif->type;
  3831. err = il_set_mode(il);
  3832. if (err) {
  3833. IL_WARN("Fail to set mode %d\n", vif->type);
  3834. if (!reset) {
  3835. il->vif = NULL;
  3836. il->iw_mode = NL80211_IFTYPE_STATION;
  3837. }
  3838. }
  3839. out:
  3840. D_MAC80211("leave err %d\n", err);
  3841. mutex_unlock(&il->mutex);
  3842. return err;
  3843. }
  3844. EXPORT_SYMBOL(il_mac_add_interface);
  3845. static void
  3846. il_teardown_interface(struct il_priv *il, struct ieee80211_vif *vif)
  3847. {
  3848. lockdep_assert_held(&il->mutex);
  3849. if (il->scan_vif == vif) {
  3850. il_scan_cancel_timeout(il, 200);
  3851. il_force_scan_end(il);
  3852. }
  3853. il_set_mode(il);
  3854. }
  3855. void
  3856. il_mac_remove_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
  3857. {
  3858. struct il_priv *il = hw->priv;
  3859. mutex_lock(&il->mutex);
  3860. D_MAC80211("enter: type %d, addr %pM\n", vif->type, vif->addr);
  3861. WARN_ON(il->vif != vif);
  3862. il->vif = NULL;
  3863. il->iw_mode = NL80211_IFTYPE_UNSPECIFIED;
  3864. il_teardown_interface(il, vif);
  3865. memset(il->bssid, 0, ETH_ALEN);
  3866. D_MAC80211("leave\n");
  3867. mutex_unlock(&il->mutex);
  3868. }
  3869. EXPORT_SYMBOL(il_mac_remove_interface);
  3870. int
  3871. il_alloc_txq_mem(struct il_priv *il)
  3872. {
  3873. if (!il->txq)
  3874. il->txq =
  3875. kzalloc(sizeof(struct il_tx_queue) *
  3876. il->cfg->num_of_queues, GFP_KERNEL);
  3877. if (!il->txq) {
  3878. IL_ERR("Not enough memory for txq\n");
  3879. return -ENOMEM;
  3880. }
  3881. return 0;
  3882. }
  3883. EXPORT_SYMBOL(il_alloc_txq_mem);
  3884. void
  3885. il_free_txq_mem(struct il_priv *il)
  3886. {
  3887. kfree(il->txq);
  3888. il->txq = NULL;
  3889. }
  3890. EXPORT_SYMBOL(il_free_txq_mem);
  3891. int
  3892. il_force_reset(struct il_priv *il, bool external)
  3893. {
  3894. struct il_force_reset *force_reset;
  3895. if (test_bit(S_EXIT_PENDING, &il->status))
  3896. return -EINVAL;
  3897. force_reset = &il->force_reset;
  3898. force_reset->reset_request_count++;
  3899. if (!external) {
  3900. if (force_reset->last_force_reset_jiffies &&
  3901. time_after(force_reset->last_force_reset_jiffies +
  3902. force_reset->reset_duration, jiffies)) {
  3903. D_INFO("force reset rejected\n");
  3904. force_reset->reset_reject_count++;
  3905. return -EAGAIN;
  3906. }
  3907. }
  3908. force_reset->reset_success_count++;
  3909. force_reset->last_force_reset_jiffies = jiffies;
  3910. /*
  3911. * if the request is from external(ex: debugfs),
  3912. * then always perform the request in regardless the module
  3913. * parameter setting
  3914. * if the request is from internal (uCode error or driver
  3915. * detect failure), then fw_restart module parameter
  3916. * need to be check before performing firmware reload
  3917. */
  3918. if (!external && !il->cfg->mod_params->restart_fw) {
  3919. D_INFO("Cancel firmware reload based on "
  3920. "module parameter setting\n");
  3921. return 0;
  3922. }
  3923. IL_ERR("On demand firmware reload\n");
  3924. /* Set the FW error flag -- cleared on il_down */
  3925. set_bit(S_FW_ERROR, &il->status);
  3926. wake_up(&il->wait_command_queue);
  3927. /*
  3928. * Keep the restart process from trying to send host
  3929. * commands by clearing the INIT status bit
  3930. */
  3931. clear_bit(S_READY, &il->status);
  3932. queue_work(il->workqueue, &il->restart);
  3933. return 0;
  3934. }
  3935. EXPORT_SYMBOL(il_force_reset);
  3936. int
  3937. il_mac_change_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
  3938. enum nl80211_iftype newtype, bool newp2p)
  3939. {
  3940. struct il_priv *il = hw->priv;
  3941. int err;
  3942. mutex_lock(&il->mutex);
  3943. D_MAC80211("enter: type %d, addr %pM newtype %d newp2p %d\n",
  3944. vif->type, vif->addr, newtype, newp2p);
  3945. if (newp2p) {
  3946. err = -EOPNOTSUPP;
  3947. goto out;
  3948. }
  3949. if (!il->vif || !il_is_ready_rf(il)) {
  3950. /*
  3951. * Huh? But wait ... this can maybe happen when
  3952. * we're in the middle of a firmware restart!
  3953. */
  3954. err = -EBUSY;
  3955. goto out;
  3956. }
  3957. /* success */
  3958. vif->type = newtype;
  3959. vif->p2p = false;
  3960. il->iw_mode = newtype;
  3961. il_teardown_interface(il, vif);
  3962. err = 0;
  3963. out:
  3964. D_MAC80211("leave err %d\n", err);
  3965. mutex_unlock(&il->mutex);
  3966. return err;
  3967. }
  3968. EXPORT_SYMBOL(il_mac_change_interface);
  3969. void il_mac_flush(struct ieee80211_hw *hw, u32 queues, bool drop)
  3970. {
  3971. struct il_priv *il = hw->priv;
  3972. unsigned long timeout = jiffies + msecs_to_jiffies(500);
  3973. int i;
  3974. mutex_lock(&il->mutex);
  3975. D_MAC80211("enter\n");
  3976. if (il->txq == NULL)
  3977. goto out;
  3978. for (i = 0; i < il->hw_params.max_txq_num; i++) {
  3979. struct il_queue *q;
  3980. if (i == il->cmd_queue)
  3981. continue;
  3982. q = &il->txq[i].q;
  3983. if (q->read_ptr == q->write_ptr)
  3984. continue;
  3985. if (time_after(jiffies, timeout)) {
  3986. IL_ERR("Failed to flush queue %d\n", q->id);
  3987. break;
  3988. }
  3989. msleep(20);
  3990. }
  3991. out:
  3992. D_MAC80211("leave\n");
  3993. mutex_unlock(&il->mutex);
  3994. }
  3995. EXPORT_SYMBOL(il_mac_flush);
  3996. /*
  3997. * On every watchdog tick we check (latest) time stamp. If it does not
  3998. * change during timeout period and queue is not empty we reset firmware.
  3999. */
  4000. static int
  4001. il_check_stuck_queue(struct il_priv *il, int cnt)
  4002. {
  4003. struct il_tx_queue *txq = &il->txq[cnt];
  4004. struct il_queue *q = &txq->q;
  4005. unsigned long timeout;
  4006. unsigned long now = jiffies;
  4007. int ret;
  4008. if (q->read_ptr == q->write_ptr) {
  4009. txq->time_stamp = now;
  4010. return 0;
  4011. }
  4012. timeout =
  4013. txq->time_stamp +
  4014. msecs_to_jiffies(il->cfg->wd_timeout);
  4015. if (time_after(now, timeout)) {
  4016. IL_ERR("Queue %d stuck for %u ms.\n", q->id,
  4017. jiffies_to_msecs(now - txq->time_stamp));
  4018. ret = il_force_reset(il, false);
  4019. return (ret == -EAGAIN) ? 0 : 1;
  4020. }
  4021. return 0;
  4022. }
  4023. /*
  4024. * Making watchdog tick be a quarter of timeout assure we will
  4025. * discover the queue hung between timeout and 1.25*timeout
  4026. */
  4027. #define IL_WD_TICK(timeout) ((timeout) / 4)
  4028. /*
  4029. * Watchdog timer callback, we check each tx queue for stuck, if if hung
  4030. * we reset the firmware. If everything is fine just rearm the timer.
  4031. */
  4032. void
  4033. il_bg_watchdog(unsigned long data)
  4034. {
  4035. struct il_priv *il = (struct il_priv *)data;
  4036. int cnt;
  4037. unsigned long timeout;
  4038. if (test_bit(S_EXIT_PENDING, &il->status))
  4039. return;
  4040. timeout = il->cfg->wd_timeout;
  4041. if (timeout == 0)
  4042. return;
  4043. /* monitor and check for stuck cmd queue */
  4044. if (il_check_stuck_queue(il, il->cmd_queue))
  4045. return;
  4046. /* monitor and check for other stuck queues */
  4047. for (cnt = 0; cnt < il->hw_params.max_txq_num; cnt++) {
  4048. /* skip as we already checked the command queue */
  4049. if (cnt == il->cmd_queue)
  4050. continue;
  4051. if (il_check_stuck_queue(il, cnt))
  4052. return;
  4053. }
  4054. mod_timer(&il->watchdog,
  4055. jiffies + msecs_to_jiffies(IL_WD_TICK(timeout)));
  4056. }
  4057. EXPORT_SYMBOL(il_bg_watchdog);
  4058. void
  4059. il_setup_watchdog(struct il_priv *il)
  4060. {
  4061. unsigned int timeout = il->cfg->wd_timeout;
  4062. if (timeout)
  4063. mod_timer(&il->watchdog,
  4064. jiffies + msecs_to_jiffies(IL_WD_TICK(timeout)));
  4065. else
  4066. del_timer(&il->watchdog);
  4067. }
  4068. EXPORT_SYMBOL(il_setup_watchdog);
  4069. /*
  4070. * extended beacon time format
  4071. * time in usec will be changed into a 32-bit value in extended:internal format
  4072. * the extended part is the beacon counts
  4073. * the internal part is the time in usec within one beacon interval
  4074. */
  4075. u32
  4076. il_usecs_to_beacons(struct il_priv *il, u32 usec, u32 beacon_interval)
  4077. {
  4078. u32 quot;
  4079. u32 rem;
  4080. u32 interval = beacon_interval * TIME_UNIT;
  4081. if (!interval || !usec)
  4082. return 0;
  4083. quot =
  4084. (usec /
  4085. interval) & (il_beacon_time_mask_high(il,
  4086. il->hw_params.
  4087. beacon_time_tsf_bits) >> il->
  4088. hw_params.beacon_time_tsf_bits);
  4089. rem =
  4090. (usec % interval) & il_beacon_time_mask_low(il,
  4091. il->hw_params.
  4092. beacon_time_tsf_bits);
  4093. return (quot << il->hw_params.beacon_time_tsf_bits) + rem;
  4094. }
  4095. EXPORT_SYMBOL(il_usecs_to_beacons);
  4096. /* base is usually what we get from ucode with each received frame,
  4097. * the same as HW timer counter counting down
  4098. */
  4099. __le32
  4100. il_add_beacon_time(struct il_priv *il, u32 base, u32 addon,
  4101. u32 beacon_interval)
  4102. {
  4103. u32 base_low = base & il_beacon_time_mask_low(il,
  4104. il->hw_params.
  4105. beacon_time_tsf_bits);
  4106. u32 addon_low = addon & il_beacon_time_mask_low(il,
  4107. il->hw_params.
  4108. beacon_time_tsf_bits);
  4109. u32 interval = beacon_interval * TIME_UNIT;
  4110. u32 res = (base & il_beacon_time_mask_high(il,
  4111. il->hw_params.
  4112. beacon_time_tsf_bits)) +
  4113. (addon & il_beacon_time_mask_high(il,
  4114. il->hw_params.
  4115. beacon_time_tsf_bits));
  4116. if (base_low > addon_low)
  4117. res += base_low - addon_low;
  4118. else if (base_low < addon_low) {
  4119. res += interval + base_low - addon_low;
  4120. res += (1 << il->hw_params.beacon_time_tsf_bits);
  4121. } else
  4122. res += (1 << il->hw_params.beacon_time_tsf_bits);
  4123. return cpu_to_le32(res);
  4124. }
  4125. EXPORT_SYMBOL(il_add_beacon_time);
  4126. #ifdef CONFIG_PM_SLEEP
  4127. static int
  4128. il_pci_suspend(struct device *device)
  4129. {
  4130. struct pci_dev *pdev = to_pci_dev(device);
  4131. struct il_priv *il = pci_get_drvdata(pdev);
  4132. /*
  4133. * This function is called when system goes into suspend state
  4134. * mac80211 will call il_mac_stop() from the mac80211 suspend function
  4135. * first but since il_mac_stop() has no knowledge of who the caller is,
  4136. * it will not call apm_ops.stop() to stop the DMA operation.
  4137. * Calling apm_ops.stop here to make sure we stop the DMA.
  4138. */
  4139. il_apm_stop(il);
  4140. return 0;
  4141. }
  4142. static int
  4143. il_pci_resume(struct device *device)
  4144. {
  4145. struct pci_dev *pdev = to_pci_dev(device);
  4146. struct il_priv *il = pci_get_drvdata(pdev);
  4147. bool hw_rfkill = false;
  4148. /*
  4149. * We disable the RETRY_TIMEOUT register (0x41) to keep
  4150. * PCI Tx retries from interfering with C3 CPU state.
  4151. */
  4152. pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
  4153. il_enable_interrupts(il);
  4154. if (!(_il_rd(il, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  4155. hw_rfkill = true;
  4156. if (hw_rfkill)
  4157. set_bit(S_RFKILL, &il->status);
  4158. else
  4159. clear_bit(S_RFKILL, &il->status);
  4160. wiphy_rfkill_set_hw_state(il->hw->wiphy, hw_rfkill);
  4161. return 0;
  4162. }
  4163. SIMPLE_DEV_PM_OPS(il_pm_ops, il_pci_suspend, il_pci_resume);
  4164. EXPORT_SYMBOL(il_pm_ops);
  4165. #endif /* CONFIG_PM_SLEEP */
  4166. static void
  4167. il_update_qos(struct il_priv *il)
  4168. {
  4169. if (test_bit(S_EXIT_PENDING, &il->status))
  4170. return;
  4171. il->qos_data.def_qos_parm.qos_flags = 0;
  4172. if (il->qos_data.qos_active)
  4173. il->qos_data.def_qos_parm.qos_flags |=
  4174. QOS_PARAM_FLG_UPDATE_EDCA_MSK;
  4175. if (il->ht.enabled)
  4176. il->qos_data.def_qos_parm.qos_flags |= QOS_PARAM_FLG_TGN_MSK;
  4177. D_QOS("send QoS cmd with Qos active=%d FLAGS=0x%X\n",
  4178. il->qos_data.qos_active, il->qos_data.def_qos_parm.qos_flags);
  4179. il_send_cmd_pdu_async(il, C_QOS_PARAM, sizeof(struct il_qosparam_cmd),
  4180. &il->qos_data.def_qos_parm, NULL);
  4181. }
  4182. /**
  4183. * il_mac_config - mac80211 config callback
  4184. */
  4185. int
  4186. il_mac_config(struct ieee80211_hw *hw, u32 changed)
  4187. {
  4188. struct il_priv *il = hw->priv;
  4189. const struct il_channel_info *ch_info;
  4190. struct ieee80211_conf *conf = &hw->conf;
  4191. struct ieee80211_channel *channel = conf->chandef.chan;
  4192. struct il_ht_config *ht_conf = &il->current_ht_config;
  4193. unsigned long flags = 0;
  4194. int ret = 0;
  4195. u16 ch;
  4196. int scan_active = 0;
  4197. bool ht_changed = false;
  4198. mutex_lock(&il->mutex);
  4199. D_MAC80211("enter: channel %d changed 0x%X\n", channel->hw_value,
  4200. changed);
  4201. if (unlikely(test_bit(S_SCANNING, &il->status))) {
  4202. scan_active = 1;
  4203. D_MAC80211("scan active\n");
  4204. }
  4205. if (changed &
  4206. (IEEE80211_CONF_CHANGE_SMPS | IEEE80211_CONF_CHANGE_CHANNEL)) {
  4207. /* mac80211 uses static for non-HT which is what we want */
  4208. il->current_ht_config.smps = conf->smps_mode;
  4209. /*
  4210. * Recalculate chain counts.
  4211. *
  4212. * If monitor mode is enabled then mac80211 will
  4213. * set up the SM PS mode to OFF if an HT channel is
  4214. * configured.
  4215. */
  4216. if (il->ops->set_rxon_chain)
  4217. il->ops->set_rxon_chain(il);
  4218. }
  4219. /* during scanning mac80211 will delay channel setting until
  4220. * scan finish with changed = 0
  4221. */
  4222. if (!changed || (changed & IEEE80211_CONF_CHANGE_CHANNEL)) {
  4223. if (scan_active)
  4224. goto set_ch_out;
  4225. ch = channel->hw_value;
  4226. ch_info = il_get_channel_info(il, channel->band, ch);
  4227. if (!il_is_channel_valid(ch_info)) {
  4228. D_MAC80211("leave - invalid channel\n");
  4229. ret = -EINVAL;
  4230. goto set_ch_out;
  4231. }
  4232. if (il->iw_mode == NL80211_IFTYPE_ADHOC &&
  4233. !il_is_channel_ibss(ch_info)) {
  4234. D_MAC80211("leave - not IBSS channel\n");
  4235. ret = -EINVAL;
  4236. goto set_ch_out;
  4237. }
  4238. spin_lock_irqsave(&il->lock, flags);
  4239. /* Configure HT40 channels */
  4240. if (il->ht.enabled != conf_is_ht(conf)) {
  4241. il->ht.enabled = conf_is_ht(conf);
  4242. ht_changed = true;
  4243. }
  4244. if (il->ht.enabled) {
  4245. if (conf_is_ht40_minus(conf)) {
  4246. il->ht.extension_chan_offset =
  4247. IEEE80211_HT_PARAM_CHA_SEC_BELOW;
  4248. il->ht.is_40mhz = true;
  4249. } else if (conf_is_ht40_plus(conf)) {
  4250. il->ht.extension_chan_offset =
  4251. IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
  4252. il->ht.is_40mhz = true;
  4253. } else {
  4254. il->ht.extension_chan_offset =
  4255. IEEE80211_HT_PARAM_CHA_SEC_NONE;
  4256. il->ht.is_40mhz = false;
  4257. }
  4258. } else
  4259. il->ht.is_40mhz = false;
  4260. /*
  4261. * Default to no protection. Protection mode will
  4262. * later be set from BSS config in il_ht_conf
  4263. */
  4264. il->ht.protection = IEEE80211_HT_OP_MODE_PROTECTION_NONE;
  4265. /* if we are switching from ht to 2.4 clear flags
  4266. * from any ht related info since 2.4 does not
  4267. * support ht */
  4268. if ((le16_to_cpu(il->staging.channel) != ch))
  4269. il->staging.flags = 0;
  4270. il_set_rxon_channel(il, channel);
  4271. il_set_rxon_ht(il, ht_conf);
  4272. il_set_flags_for_band(il, channel->band, il->vif);
  4273. spin_unlock_irqrestore(&il->lock, flags);
  4274. if (il->ops->update_bcast_stations)
  4275. ret = il->ops->update_bcast_stations(il);
  4276. set_ch_out:
  4277. /* The list of supported rates and rate mask can be different
  4278. * for each band; since the band may have changed, reset
  4279. * the rate mask to what mac80211 lists */
  4280. il_set_rate(il);
  4281. }
  4282. if (changed & (IEEE80211_CONF_CHANGE_PS | IEEE80211_CONF_CHANGE_IDLE)) {
  4283. ret = il_power_update_mode(il, false);
  4284. if (ret)
  4285. D_MAC80211("Error setting sleep level\n");
  4286. }
  4287. if (changed & IEEE80211_CONF_CHANGE_POWER) {
  4288. D_MAC80211("TX Power old=%d new=%d\n", il->tx_power_user_lmt,
  4289. conf->power_level);
  4290. il_set_tx_power(il, conf->power_level, false);
  4291. }
  4292. if (!il_is_ready(il)) {
  4293. D_MAC80211("leave - not ready\n");
  4294. goto out;
  4295. }
  4296. if (scan_active)
  4297. goto out;
  4298. if (memcmp(&il->active, &il->staging, sizeof(il->staging)))
  4299. il_commit_rxon(il);
  4300. else
  4301. D_INFO("Not re-sending same RXON configuration.\n");
  4302. if (ht_changed)
  4303. il_update_qos(il);
  4304. out:
  4305. D_MAC80211("leave ret %d\n", ret);
  4306. mutex_unlock(&il->mutex);
  4307. return ret;
  4308. }
  4309. EXPORT_SYMBOL(il_mac_config);
  4310. void
  4311. il_mac_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
  4312. {
  4313. struct il_priv *il = hw->priv;
  4314. unsigned long flags;
  4315. mutex_lock(&il->mutex);
  4316. D_MAC80211("enter: type %d, addr %pM\n", vif->type, vif->addr);
  4317. spin_lock_irqsave(&il->lock, flags);
  4318. memset(&il->current_ht_config, 0, sizeof(struct il_ht_config));
  4319. /* new association get rid of ibss beacon skb */
  4320. if (il->beacon_skb)
  4321. dev_kfree_skb(il->beacon_skb);
  4322. il->beacon_skb = NULL;
  4323. il->timestamp = 0;
  4324. spin_unlock_irqrestore(&il->lock, flags);
  4325. il_scan_cancel_timeout(il, 100);
  4326. if (!il_is_ready_rf(il)) {
  4327. D_MAC80211("leave - not ready\n");
  4328. mutex_unlock(&il->mutex);
  4329. return;
  4330. }
  4331. /* we are restarting association process */
  4332. il->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  4333. il_commit_rxon(il);
  4334. il_set_rate(il);
  4335. D_MAC80211("leave\n");
  4336. mutex_unlock(&il->mutex);
  4337. }
  4338. EXPORT_SYMBOL(il_mac_reset_tsf);
  4339. static void
  4340. il_ht_conf(struct il_priv *il, struct ieee80211_vif *vif)
  4341. {
  4342. struct il_ht_config *ht_conf = &il->current_ht_config;
  4343. struct ieee80211_sta *sta;
  4344. struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
  4345. D_ASSOC("enter:\n");
  4346. if (!il->ht.enabled)
  4347. return;
  4348. il->ht.protection =
  4349. bss_conf->ht_operation_mode & IEEE80211_HT_OP_MODE_PROTECTION;
  4350. il->ht.non_gf_sta_present =
  4351. !!(bss_conf->
  4352. ht_operation_mode & IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
  4353. ht_conf->single_chain_sufficient = false;
  4354. switch (vif->type) {
  4355. case NL80211_IFTYPE_STATION:
  4356. rcu_read_lock();
  4357. sta = ieee80211_find_sta(vif, bss_conf->bssid);
  4358. if (sta) {
  4359. struct ieee80211_sta_ht_cap *ht_cap = &sta->ht_cap;
  4360. int maxstreams;
  4361. maxstreams =
  4362. (ht_cap->mcs.
  4363. tx_params & IEEE80211_HT_MCS_TX_MAX_STREAMS_MASK)
  4364. >> IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT;
  4365. maxstreams += 1;
  4366. if (ht_cap->mcs.rx_mask[1] == 0 &&
  4367. ht_cap->mcs.rx_mask[2] == 0)
  4368. ht_conf->single_chain_sufficient = true;
  4369. if (maxstreams <= 1)
  4370. ht_conf->single_chain_sufficient = true;
  4371. } else {
  4372. /*
  4373. * If at all, this can only happen through a race
  4374. * when the AP disconnects us while we're still
  4375. * setting up the connection, in that case mac80211
  4376. * will soon tell us about that.
  4377. */
  4378. ht_conf->single_chain_sufficient = true;
  4379. }
  4380. rcu_read_unlock();
  4381. break;
  4382. case NL80211_IFTYPE_ADHOC:
  4383. ht_conf->single_chain_sufficient = true;
  4384. break;
  4385. default:
  4386. break;
  4387. }
  4388. D_ASSOC("leave\n");
  4389. }
  4390. static inline void
  4391. il_set_no_assoc(struct il_priv *il, struct ieee80211_vif *vif)
  4392. {
  4393. /*
  4394. * inform the ucode that there is no longer an
  4395. * association and that no more packets should be
  4396. * sent
  4397. */
  4398. il->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  4399. il->staging.assoc_id = 0;
  4400. il_commit_rxon(il);
  4401. }
  4402. static void
  4403. il_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
  4404. {
  4405. struct il_priv *il = hw->priv;
  4406. unsigned long flags;
  4407. __le64 timestamp;
  4408. struct sk_buff *skb = ieee80211_beacon_get(hw, vif);
  4409. if (!skb)
  4410. return;
  4411. D_MAC80211("enter\n");
  4412. lockdep_assert_held(&il->mutex);
  4413. if (!il->beacon_enabled) {
  4414. IL_ERR("update beacon with no beaconing enabled\n");
  4415. dev_kfree_skb(skb);
  4416. return;
  4417. }
  4418. spin_lock_irqsave(&il->lock, flags);
  4419. if (il->beacon_skb)
  4420. dev_kfree_skb(il->beacon_skb);
  4421. il->beacon_skb = skb;
  4422. timestamp = ((struct ieee80211_mgmt *)skb->data)->u.beacon.timestamp;
  4423. il->timestamp = le64_to_cpu(timestamp);
  4424. D_MAC80211("leave\n");
  4425. spin_unlock_irqrestore(&il->lock, flags);
  4426. if (!il_is_ready_rf(il)) {
  4427. D_MAC80211("leave - RF not ready\n");
  4428. return;
  4429. }
  4430. il->ops->post_associate(il);
  4431. }
  4432. void
  4433. il_mac_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
  4434. struct ieee80211_bss_conf *bss_conf, u32 changes)
  4435. {
  4436. struct il_priv *il = hw->priv;
  4437. int ret;
  4438. mutex_lock(&il->mutex);
  4439. D_MAC80211("enter: changes 0x%x\n", changes);
  4440. if (!il_is_alive(il)) {
  4441. D_MAC80211("leave - not alive\n");
  4442. mutex_unlock(&il->mutex);
  4443. return;
  4444. }
  4445. if (changes & BSS_CHANGED_QOS) {
  4446. unsigned long flags;
  4447. spin_lock_irqsave(&il->lock, flags);
  4448. il->qos_data.qos_active = bss_conf->qos;
  4449. il_update_qos(il);
  4450. spin_unlock_irqrestore(&il->lock, flags);
  4451. }
  4452. if (changes & BSS_CHANGED_BEACON_ENABLED) {
  4453. /* FIXME: can we remove beacon_enabled ? */
  4454. if (vif->bss_conf.enable_beacon)
  4455. il->beacon_enabled = true;
  4456. else
  4457. il->beacon_enabled = false;
  4458. }
  4459. if (changes & BSS_CHANGED_BSSID) {
  4460. D_MAC80211("BSSID %pM\n", bss_conf->bssid);
  4461. /*
  4462. * On passive channel we wait with blocked queues to see if
  4463. * there is traffic on that channel. If no frame will be
  4464. * received (what is very unlikely since scan detects AP on
  4465. * that channel, but theoretically possible), mac80211 associate
  4466. * procedure will time out and mac80211 will call us with NULL
  4467. * bssid. We have to unblock queues on such condition.
  4468. */
  4469. if (is_zero_ether_addr(bss_conf->bssid))
  4470. il_wake_queues_by_reason(il, IL_STOP_REASON_PASSIVE);
  4471. /*
  4472. * If there is currently a HW scan going on in the background,
  4473. * then we need to cancel it, otherwise sometimes we are not
  4474. * able to authenticate (FIXME: why ?)
  4475. */
  4476. if (il_scan_cancel_timeout(il, 100)) {
  4477. D_MAC80211("leave - scan abort failed\n");
  4478. mutex_unlock(&il->mutex);
  4479. return;
  4480. }
  4481. /* mac80211 only sets assoc when in STATION mode */
  4482. memcpy(il->staging.bssid_addr, bss_conf->bssid, ETH_ALEN);
  4483. /* FIXME: currently needed in a few places */
  4484. memcpy(il->bssid, bss_conf->bssid, ETH_ALEN);
  4485. }
  4486. /*
  4487. * This needs to be after setting the BSSID in case
  4488. * mac80211 decides to do both changes at once because
  4489. * it will invoke post_associate.
  4490. */
  4491. if (vif->type == NL80211_IFTYPE_ADHOC && (changes & BSS_CHANGED_BEACON))
  4492. il_beacon_update(hw, vif);
  4493. if (changes & BSS_CHANGED_ERP_PREAMBLE) {
  4494. D_MAC80211("ERP_PREAMBLE %d\n", bss_conf->use_short_preamble);
  4495. if (bss_conf->use_short_preamble)
  4496. il->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  4497. else
  4498. il->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  4499. }
  4500. if (changes & BSS_CHANGED_ERP_CTS_PROT) {
  4501. D_MAC80211("ERP_CTS %d\n", bss_conf->use_cts_prot);
  4502. if (bss_conf->use_cts_prot && il->band != IEEE80211_BAND_5GHZ)
  4503. il->staging.flags |= RXON_FLG_TGG_PROTECT_MSK;
  4504. else
  4505. il->staging.flags &= ~RXON_FLG_TGG_PROTECT_MSK;
  4506. if (bss_conf->use_cts_prot)
  4507. il->staging.flags |= RXON_FLG_SELF_CTS_EN;
  4508. else
  4509. il->staging.flags &= ~RXON_FLG_SELF_CTS_EN;
  4510. }
  4511. if (changes & BSS_CHANGED_BASIC_RATES) {
  4512. /* XXX use this information
  4513. *
  4514. * To do that, remove code from il_set_rate() and put something
  4515. * like this here:
  4516. *
  4517. if (A-band)
  4518. il->staging.ofdm_basic_rates =
  4519. bss_conf->basic_rates;
  4520. else
  4521. il->staging.ofdm_basic_rates =
  4522. bss_conf->basic_rates >> 4;
  4523. il->staging.cck_basic_rates =
  4524. bss_conf->basic_rates & 0xF;
  4525. */
  4526. }
  4527. if (changes & BSS_CHANGED_HT) {
  4528. il_ht_conf(il, vif);
  4529. if (il->ops->set_rxon_chain)
  4530. il->ops->set_rxon_chain(il);
  4531. }
  4532. if (changes & BSS_CHANGED_ASSOC) {
  4533. D_MAC80211("ASSOC %d\n", bss_conf->assoc);
  4534. if (bss_conf->assoc) {
  4535. il->timestamp = bss_conf->sync_tsf;
  4536. if (!il_is_rfkill(il))
  4537. il->ops->post_associate(il);
  4538. } else
  4539. il_set_no_assoc(il, vif);
  4540. }
  4541. if (changes && il_is_associated(il) && bss_conf->aid) {
  4542. D_MAC80211("Changes (%#x) while associated\n", changes);
  4543. ret = il_send_rxon_assoc(il);
  4544. if (!ret) {
  4545. /* Sync active_rxon with latest change. */
  4546. memcpy((void *)&il->active, &il->staging,
  4547. sizeof(struct il_rxon_cmd));
  4548. }
  4549. }
  4550. if (changes & BSS_CHANGED_BEACON_ENABLED) {
  4551. if (vif->bss_conf.enable_beacon) {
  4552. memcpy(il->staging.bssid_addr, bss_conf->bssid,
  4553. ETH_ALEN);
  4554. memcpy(il->bssid, bss_conf->bssid, ETH_ALEN);
  4555. il->ops->config_ap(il);
  4556. } else
  4557. il_set_no_assoc(il, vif);
  4558. }
  4559. if (changes & BSS_CHANGED_IBSS) {
  4560. ret = il->ops->manage_ibss_station(il, vif,
  4561. bss_conf->ibss_joined);
  4562. if (ret)
  4563. IL_ERR("failed to %s IBSS station %pM\n",
  4564. bss_conf->ibss_joined ? "add" : "remove",
  4565. bss_conf->bssid);
  4566. }
  4567. D_MAC80211("leave\n");
  4568. mutex_unlock(&il->mutex);
  4569. }
  4570. EXPORT_SYMBOL(il_mac_bss_info_changed);
  4571. irqreturn_t
  4572. il_isr(int irq, void *data)
  4573. {
  4574. struct il_priv *il = data;
  4575. u32 inta, inta_mask;
  4576. u32 inta_fh;
  4577. unsigned long flags;
  4578. if (!il)
  4579. return IRQ_NONE;
  4580. spin_lock_irqsave(&il->lock, flags);
  4581. /* Disable (but don't clear!) interrupts here to avoid
  4582. * back-to-back ISRs and sporadic interrupts from our NIC.
  4583. * If we have something to service, the tasklet will re-enable ints.
  4584. * If we *don't* have something, we'll re-enable before leaving here. */
  4585. inta_mask = _il_rd(il, CSR_INT_MASK); /* just for debug */
  4586. _il_wr(il, CSR_INT_MASK, 0x00000000);
  4587. /* Discover which interrupts are active/pending */
  4588. inta = _il_rd(il, CSR_INT);
  4589. inta_fh = _il_rd(il, CSR_FH_INT_STATUS);
  4590. /* Ignore interrupt if there's nothing in NIC to service.
  4591. * This may be due to IRQ shared with another device,
  4592. * or due to sporadic interrupts thrown from our NIC. */
  4593. if (!inta && !inta_fh) {
  4594. D_ISR("Ignore interrupt, inta == 0, inta_fh == 0\n");
  4595. goto none;
  4596. }
  4597. if (inta == 0xFFFFFFFF || (inta & 0xFFFFFFF0) == 0xa5a5a5a0) {
  4598. /* Hardware disappeared. It might have already raised
  4599. * an interrupt */
  4600. IL_WARN("HARDWARE GONE?? INTA == 0x%08x\n", inta);
  4601. goto unplugged;
  4602. }
  4603. D_ISR("ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n", inta, inta_mask,
  4604. inta_fh);
  4605. inta &= ~CSR_INT_BIT_SCD;
  4606. /* il_irq_tasklet() will service interrupts and re-enable them */
  4607. if (likely(inta || inta_fh))
  4608. tasklet_schedule(&il->irq_tasklet);
  4609. unplugged:
  4610. spin_unlock_irqrestore(&il->lock, flags);
  4611. return IRQ_HANDLED;
  4612. none:
  4613. /* re-enable interrupts here since we don't have anything to service. */
  4614. /* only Re-enable if disabled by irq */
  4615. if (test_bit(S_INT_ENABLED, &il->status))
  4616. il_enable_interrupts(il);
  4617. spin_unlock_irqrestore(&il->lock, flags);
  4618. return IRQ_NONE;
  4619. }
  4620. EXPORT_SYMBOL(il_isr);
  4621. /*
  4622. * il_tx_cmd_protection: Set rts/cts. 3945 and 4965 only share this
  4623. * function.
  4624. */
  4625. void
  4626. il_tx_cmd_protection(struct il_priv *il, struct ieee80211_tx_info *info,
  4627. __le16 fc, __le32 *tx_flags)
  4628. {
  4629. if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
  4630. *tx_flags |= TX_CMD_FLG_RTS_MSK;
  4631. *tx_flags &= ~TX_CMD_FLG_CTS_MSK;
  4632. *tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
  4633. if (!ieee80211_is_mgmt(fc))
  4634. return;
  4635. switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
  4636. case cpu_to_le16(IEEE80211_STYPE_AUTH):
  4637. case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
  4638. case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
  4639. case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
  4640. *tx_flags &= ~TX_CMD_FLG_RTS_MSK;
  4641. *tx_flags |= TX_CMD_FLG_CTS_MSK;
  4642. break;
  4643. }
  4644. } else if (info->control.rates[0].
  4645. flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
  4646. *tx_flags &= ~TX_CMD_FLG_RTS_MSK;
  4647. *tx_flags |= TX_CMD_FLG_CTS_MSK;
  4648. *tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
  4649. }
  4650. }
  4651. EXPORT_SYMBOL(il_tx_cmd_protection);