xmit.c 70 KB

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  1. /*
  2. * Copyright (c) 2008-2011 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include <linux/dma-mapping.h>
  17. #include "ath9k.h"
  18. #include "ar9003_mac.h"
  19. #define BITS_PER_BYTE 8
  20. #define OFDM_PLCP_BITS 22
  21. #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
  22. #define L_STF 8
  23. #define L_LTF 8
  24. #define L_SIG 4
  25. #define HT_SIG 8
  26. #define HT_STF 4
  27. #define HT_LTF(_ns) (4 * (_ns))
  28. #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
  29. #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
  30. #define TIME_SYMBOLS(t) ((t) >> 2)
  31. #define TIME_SYMBOLS_HALFGI(t) (((t) * 5 - 4) / 18)
  32. #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
  33. #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
  34. static u16 bits_per_symbol[][2] = {
  35. /* 20MHz 40MHz */
  36. { 26, 54 }, /* 0: BPSK */
  37. { 52, 108 }, /* 1: QPSK 1/2 */
  38. { 78, 162 }, /* 2: QPSK 3/4 */
  39. { 104, 216 }, /* 3: 16-QAM 1/2 */
  40. { 156, 324 }, /* 4: 16-QAM 3/4 */
  41. { 208, 432 }, /* 5: 64-QAM 2/3 */
  42. { 234, 486 }, /* 6: 64-QAM 3/4 */
  43. { 260, 540 }, /* 7: 64-QAM 5/6 */
  44. };
  45. static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
  46. struct ath_atx_tid *tid, struct sk_buff *skb);
  47. static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
  48. int tx_flags, struct ath_txq *txq);
  49. static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
  50. struct ath_txq *txq, struct list_head *bf_q,
  51. struct ath_tx_status *ts, int txok);
  52. static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
  53. struct list_head *head, bool internal);
  54. static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
  55. struct ath_tx_status *ts, int nframes, int nbad,
  56. int txok);
  57. static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
  58. int seqno);
  59. static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
  60. struct ath_txq *txq,
  61. struct ath_atx_tid *tid,
  62. struct sk_buff *skb);
  63. enum {
  64. MCS_HT20,
  65. MCS_HT20_SGI,
  66. MCS_HT40,
  67. MCS_HT40_SGI,
  68. };
  69. /*********************/
  70. /* Aggregation logic */
  71. /*********************/
  72. void ath_txq_lock(struct ath_softc *sc, struct ath_txq *txq)
  73. __acquires(&txq->axq_lock)
  74. {
  75. spin_lock_bh(&txq->axq_lock);
  76. }
  77. void ath_txq_unlock(struct ath_softc *sc, struct ath_txq *txq)
  78. __releases(&txq->axq_lock)
  79. {
  80. spin_unlock_bh(&txq->axq_lock);
  81. }
  82. void ath_txq_unlock_complete(struct ath_softc *sc, struct ath_txq *txq)
  83. __releases(&txq->axq_lock)
  84. {
  85. struct sk_buff_head q;
  86. struct sk_buff *skb;
  87. __skb_queue_head_init(&q);
  88. skb_queue_splice_init(&txq->complete_q, &q);
  89. spin_unlock_bh(&txq->axq_lock);
  90. while ((skb = __skb_dequeue(&q)))
  91. ieee80211_tx_status(sc->hw, skb);
  92. }
  93. static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid)
  94. {
  95. struct ath_atx_ac *ac = tid->ac;
  96. if (tid->paused)
  97. return;
  98. if (tid->sched)
  99. return;
  100. tid->sched = true;
  101. list_add_tail(&tid->list, &ac->tid_q);
  102. if (ac->sched)
  103. return;
  104. ac->sched = true;
  105. list_add_tail(&ac->list, &txq->axq_acq);
  106. }
  107. static struct ath_frame_info *get_frame_info(struct sk_buff *skb)
  108. {
  109. struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
  110. BUILD_BUG_ON(sizeof(struct ath_frame_info) >
  111. sizeof(tx_info->rate_driver_data));
  112. return (struct ath_frame_info *) &tx_info->rate_driver_data[0];
  113. }
  114. static void ath_send_bar(struct ath_atx_tid *tid, u16 seqno)
  115. {
  116. if (!tid->an->sta)
  117. return;
  118. ieee80211_send_bar(tid->an->vif, tid->an->sta->addr, tid->tidno,
  119. seqno << IEEE80211_SEQ_SEQ_SHIFT);
  120. }
  121. static void ath_set_rates(struct ieee80211_vif *vif, struct ieee80211_sta *sta,
  122. struct ath_buf *bf)
  123. {
  124. ieee80211_get_tx_rates(vif, sta, bf->bf_mpdu, bf->rates,
  125. ARRAY_SIZE(bf->rates));
  126. }
  127. static void ath_txq_skb_done(struct ath_softc *sc, struct ath_txq *txq,
  128. struct sk_buff *skb)
  129. {
  130. int q;
  131. q = skb_get_queue_mapping(skb);
  132. if (txq == sc->tx.uapsdq)
  133. txq = sc->tx.txq_map[q];
  134. if (txq != sc->tx.txq_map[q])
  135. return;
  136. if (WARN_ON(--txq->pending_frames < 0))
  137. txq->pending_frames = 0;
  138. if (txq->stopped &&
  139. txq->pending_frames < sc->tx.txq_max_pending[q]) {
  140. ieee80211_wake_queue(sc->hw, q);
  141. txq->stopped = false;
  142. }
  143. }
  144. static struct ath_atx_tid *
  145. ath_get_skb_tid(struct ath_softc *sc, struct ath_node *an, struct sk_buff *skb)
  146. {
  147. u8 tidno = skb->priority & IEEE80211_QOS_CTL_TID_MASK;
  148. return ATH_AN_2_TID(an, tidno);
  149. }
  150. static bool ath_tid_has_buffered(struct ath_atx_tid *tid)
  151. {
  152. return !skb_queue_empty(&tid->buf_q) || !skb_queue_empty(&tid->retry_q);
  153. }
  154. static struct sk_buff *ath_tid_dequeue(struct ath_atx_tid *tid)
  155. {
  156. struct sk_buff *skb;
  157. skb = __skb_dequeue(&tid->retry_q);
  158. if (!skb)
  159. skb = __skb_dequeue(&tid->buf_q);
  160. return skb;
  161. }
  162. /*
  163. * ath_tx_tid_change_state:
  164. * - clears a-mpdu flag of previous session
  165. * - force sequence number allocation to fix next BlockAck Window
  166. */
  167. static void
  168. ath_tx_tid_change_state(struct ath_softc *sc, struct ath_atx_tid *tid)
  169. {
  170. struct ath_txq *txq = tid->ac->txq;
  171. struct ieee80211_tx_info *tx_info;
  172. struct sk_buff *skb, *tskb;
  173. struct ath_buf *bf;
  174. struct ath_frame_info *fi;
  175. skb_queue_walk_safe(&tid->buf_q, skb, tskb) {
  176. fi = get_frame_info(skb);
  177. bf = fi->bf;
  178. tx_info = IEEE80211_SKB_CB(skb);
  179. tx_info->flags &= ~IEEE80211_TX_CTL_AMPDU;
  180. if (bf)
  181. continue;
  182. bf = ath_tx_setup_buffer(sc, txq, tid, skb);
  183. if (!bf) {
  184. __skb_unlink(skb, &tid->buf_q);
  185. ath_txq_skb_done(sc, txq, skb);
  186. ieee80211_free_txskb(sc->hw, skb);
  187. continue;
  188. }
  189. }
  190. }
  191. static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
  192. {
  193. struct ath_txq *txq = tid->ac->txq;
  194. struct sk_buff *skb;
  195. struct ath_buf *bf;
  196. struct list_head bf_head;
  197. struct ath_tx_status ts;
  198. struct ath_frame_info *fi;
  199. bool sendbar = false;
  200. INIT_LIST_HEAD(&bf_head);
  201. memset(&ts, 0, sizeof(ts));
  202. while ((skb = __skb_dequeue(&tid->retry_q))) {
  203. fi = get_frame_info(skb);
  204. bf = fi->bf;
  205. if (!bf) {
  206. ath_txq_skb_done(sc, txq, skb);
  207. ieee80211_free_txskb(sc->hw, skb);
  208. continue;
  209. }
  210. if (fi->baw_tracked) {
  211. ath_tx_update_baw(sc, tid, bf->bf_state.seqno);
  212. sendbar = true;
  213. }
  214. list_add_tail(&bf->list, &bf_head);
  215. ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
  216. }
  217. if (sendbar) {
  218. ath_txq_unlock(sc, txq);
  219. ath_send_bar(tid, tid->seq_start);
  220. ath_txq_lock(sc, txq);
  221. }
  222. }
  223. static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
  224. int seqno)
  225. {
  226. int index, cindex;
  227. index = ATH_BA_INDEX(tid->seq_start, seqno);
  228. cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
  229. __clear_bit(cindex, tid->tx_buf);
  230. while (tid->baw_head != tid->baw_tail && !test_bit(tid->baw_head, tid->tx_buf)) {
  231. INCR(tid->seq_start, IEEE80211_SEQ_MAX);
  232. INCR(tid->baw_head, ATH_TID_MAX_BUFS);
  233. if (tid->bar_index >= 0)
  234. tid->bar_index--;
  235. }
  236. }
  237. static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
  238. struct ath_buf *bf)
  239. {
  240. struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
  241. u16 seqno = bf->bf_state.seqno;
  242. int index, cindex;
  243. index = ATH_BA_INDEX(tid->seq_start, seqno);
  244. cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
  245. __set_bit(cindex, tid->tx_buf);
  246. fi->baw_tracked = 1;
  247. if (index >= ((tid->baw_tail - tid->baw_head) &
  248. (ATH_TID_MAX_BUFS - 1))) {
  249. tid->baw_tail = cindex;
  250. INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
  251. }
  252. }
  253. static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
  254. struct ath_atx_tid *tid)
  255. {
  256. struct sk_buff *skb;
  257. struct ath_buf *bf;
  258. struct list_head bf_head;
  259. struct ath_tx_status ts;
  260. struct ath_frame_info *fi;
  261. memset(&ts, 0, sizeof(ts));
  262. INIT_LIST_HEAD(&bf_head);
  263. while ((skb = ath_tid_dequeue(tid))) {
  264. fi = get_frame_info(skb);
  265. bf = fi->bf;
  266. if (!bf) {
  267. ath_tx_complete(sc, skb, ATH_TX_ERROR, txq);
  268. continue;
  269. }
  270. list_add_tail(&bf->list, &bf_head);
  271. ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
  272. }
  273. }
  274. static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq,
  275. struct sk_buff *skb, int count)
  276. {
  277. struct ath_frame_info *fi = get_frame_info(skb);
  278. struct ath_buf *bf = fi->bf;
  279. struct ieee80211_hdr *hdr;
  280. int prev = fi->retries;
  281. TX_STAT_INC(txq->axq_qnum, a_retries);
  282. fi->retries += count;
  283. if (prev > 0)
  284. return;
  285. hdr = (struct ieee80211_hdr *)skb->data;
  286. hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
  287. dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
  288. sizeof(*hdr), DMA_TO_DEVICE);
  289. }
  290. static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
  291. {
  292. struct ath_buf *bf = NULL;
  293. spin_lock_bh(&sc->tx.txbuflock);
  294. if (unlikely(list_empty(&sc->tx.txbuf))) {
  295. spin_unlock_bh(&sc->tx.txbuflock);
  296. return NULL;
  297. }
  298. bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
  299. list_del(&bf->list);
  300. spin_unlock_bh(&sc->tx.txbuflock);
  301. return bf;
  302. }
  303. static void ath_tx_return_buffer(struct ath_softc *sc, struct ath_buf *bf)
  304. {
  305. spin_lock_bh(&sc->tx.txbuflock);
  306. list_add_tail(&bf->list, &sc->tx.txbuf);
  307. spin_unlock_bh(&sc->tx.txbuflock);
  308. }
  309. static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
  310. {
  311. struct ath_buf *tbf;
  312. tbf = ath_tx_get_buffer(sc);
  313. if (WARN_ON(!tbf))
  314. return NULL;
  315. ATH_TXBUF_RESET(tbf);
  316. tbf->bf_mpdu = bf->bf_mpdu;
  317. tbf->bf_buf_addr = bf->bf_buf_addr;
  318. memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len);
  319. tbf->bf_state = bf->bf_state;
  320. tbf->bf_state.stale = false;
  321. return tbf;
  322. }
  323. static void ath_tx_count_frames(struct ath_softc *sc, struct ath_buf *bf,
  324. struct ath_tx_status *ts, int txok,
  325. int *nframes, int *nbad)
  326. {
  327. struct ath_frame_info *fi;
  328. u16 seq_st = 0;
  329. u32 ba[WME_BA_BMP_SIZE >> 5];
  330. int ba_index;
  331. int isaggr = 0;
  332. *nbad = 0;
  333. *nframes = 0;
  334. isaggr = bf_isaggr(bf);
  335. if (isaggr) {
  336. seq_st = ts->ts_seqnum;
  337. memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
  338. }
  339. while (bf) {
  340. fi = get_frame_info(bf->bf_mpdu);
  341. ba_index = ATH_BA_INDEX(seq_st, bf->bf_state.seqno);
  342. (*nframes)++;
  343. if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
  344. (*nbad)++;
  345. bf = bf->bf_next;
  346. }
  347. }
  348. static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
  349. struct ath_buf *bf, struct list_head *bf_q,
  350. struct ath_tx_status *ts, int txok)
  351. {
  352. struct ath_node *an = NULL;
  353. struct sk_buff *skb;
  354. struct ieee80211_sta *sta;
  355. struct ieee80211_hw *hw = sc->hw;
  356. struct ieee80211_hdr *hdr;
  357. struct ieee80211_tx_info *tx_info;
  358. struct ath_atx_tid *tid = NULL;
  359. struct ath_buf *bf_next, *bf_last = bf->bf_lastbf;
  360. struct list_head bf_head;
  361. struct sk_buff_head bf_pending;
  362. u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0, seq_first;
  363. u32 ba[WME_BA_BMP_SIZE >> 5];
  364. int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0;
  365. bool rc_update = true, isba;
  366. struct ieee80211_tx_rate rates[4];
  367. struct ath_frame_info *fi;
  368. int nframes;
  369. bool flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
  370. int i, retries;
  371. int bar_index = -1;
  372. skb = bf->bf_mpdu;
  373. hdr = (struct ieee80211_hdr *)skb->data;
  374. tx_info = IEEE80211_SKB_CB(skb);
  375. memcpy(rates, bf->rates, sizeof(rates));
  376. retries = ts->ts_longretry + 1;
  377. for (i = 0; i < ts->ts_rateindex; i++)
  378. retries += rates[i].count;
  379. rcu_read_lock();
  380. sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr1, hdr->addr2);
  381. if (!sta) {
  382. rcu_read_unlock();
  383. INIT_LIST_HEAD(&bf_head);
  384. while (bf) {
  385. bf_next = bf->bf_next;
  386. if (!bf->bf_state.stale || bf_next != NULL)
  387. list_move_tail(&bf->list, &bf_head);
  388. ath_tx_complete_buf(sc, bf, txq, &bf_head, ts, 0);
  389. bf = bf_next;
  390. }
  391. return;
  392. }
  393. an = (struct ath_node *)sta->drv_priv;
  394. tid = ath_get_skb_tid(sc, an, skb);
  395. seq_first = tid->seq_start;
  396. isba = ts->ts_flags & ATH9K_TX_BA;
  397. /*
  398. * The hardware occasionally sends a tx status for the wrong TID.
  399. * In this case, the BA status cannot be considered valid and all
  400. * subframes need to be retransmitted
  401. *
  402. * Only BlockAcks have a TID and therefore normal Acks cannot be
  403. * checked
  404. */
  405. if (isba && tid->tidno != ts->tid)
  406. txok = false;
  407. isaggr = bf_isaggr(bf);
  408. memset(ba, 0, WME_BA_BMP_SIZE >> 3);
  409. if (isaggr && txok) {
  410. if (ts->ts_flags & ATH9K_TX_BA) {
  411. seq_st = ts->ts_seqnum;
  412. memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
  413. } else {
  414. /*
  415. * AR5416 can become deaf/mute when BA
  416. * issue happens. Chip needs to be reset.
  417. * But AP code may have sychronization issues
  418. * when perform internal reset in this routine.
  419. * Only enable reset in STA mode for now.
  420. */
  421. if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION)
  422. needreset = 1;
  423. }
  424. }
  425. __skb_queue_head_init(&bf_pending);
  426. ath_tx_count_frames(sc, bf, ts, txok, &nframes, &nbad);
  427. while (bf) {
  428. u16 seqno = bf->bf_state.seqno;
  429. txfail = txpending = sendbar = 0;
  430. bf_next = bf->bf_next;
  431. skb = bf->bf_mpdu;
  432. tx_info = IEEE80211_SKB_CB(skb);
  433. fi = get_frame_info(skb);
  434. if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno) ||
  435. !tid->active) {
  436. /*
  437. * Outside of the current BlockAck window,
  438. * maybe part of a previous session
  439. */
  440. txfail = 1;
  441. } else if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, seqno))) {
  442. /* transmit completion, subframe is
  443. * acked by block ack */
  444. acked_cnt++;
  445. } else if (!isaggr && txok) {
  446. /* transmit completion */
  447. acked_cnt++;
  448. } else if (flush) {
  449. txpending = 1;
  450. } else if (fi->retries < ATH_MAX_SW_RETRIES) {
  451. if (txok || !an->sleeping)
  452. ath_tx_set_retry(sc, txq, bf->bf_mpdu,
  453. retries);
  454. txpending = 1;
  455. } else {
  456. txfail = 1;
  457. txfail_cnt++;
  458. bar_index = max_t(int, bar_index,
  459. ATH_BA_INDEX(seq_first, seqno));
  460. }
  461. /*
  462. * Make sure the last desc is reclaimed if it
  463. * not a holding desc.
  464. */
  465. INIT_LIST_HEAD(&bf_head);
  466. if (bf_next != NULL || !bf_last->bf_state.stale)
  467. list_move_tail(&bf->list, &bf_head);
  468. if (!txpending) {
  469. /*
  470. * complete the acked-ones/xretried ones; update
  471. * block-ack window
  472. */
  473. ath_tx_update_baw(sc, tid, seqno);
  474. if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) {
  475. memcpy(tx_info->control.rates, rates, sizeof(rates));
  476. ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok);
  477. rc_update = false;
  478. }
  479. ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
  480. !txfail);
  481. } else {
  482. if (tx_info->flags & IEEE80211_TX_STATUS_EOSP) {
  483. tx_info->flags &= ~IEEE80211_TX_STATUS_EOSP;
  484. ieee80211_sta_eosp(sta);
  485. }
  486. /* retry the un-acked ones */
  487. if (bf->bf_next == NULL && bf_last->bf_state.stale) {
  488. struct ath_buf *tbf;
  489. tbf = ath_clone_txbuf(sc, bf_last);
  490. /*
  491. * Update tx baw and complete the
  492. * frame with failed status if we
  493. * run out of tx buf.
  494. */
  495. if (!tbf) {
  496. ath_tx_update_baw(sc, tid, seqno);
  497. ath_tx_complete_buf(sc, bf, txq,
  498. &bf_head, ts, 0);
  499. bar_index = max_t(int, bar_index,
  500. ATH_BA_INDEX(seq_first, seqno));
  501. break;
  502. }
  503. fi->bf = tbf;
  504. }
  505. /*
  506. * Put this buffer to the temporary pending
  507. * queue to retain ordering
  508. */
  509. __skb_queue_tail(&bf_pending, skb);
  510. }
  511. bf = bf_next;
  512. }
  513. /* prepend un-acked frames to the beginning of the pending frame queue */
  514. if (!skb_queue_empty(&bf_pending)) {
  515. if (an->sleeping)
  516. ieee80211_sta_set_buffered(sta, tid->tidno, true);
  517. skb_queue_splice_tail(&bf_pending, &tid->retry_q);
  518. if (!an->sleeping) {
  519. ath_tx_queue_tid(txq, tid);
  520. if (ts->ts_status & (ATH9K_TXERR_FILT | ATH9K_TXERR_XRETRY))
  521. tid->ac->clear_ps_filter = true;
  522. }
  523. }
  524. if (bar_index >= 0) {
  525. u16 bar_seq = ATH_BA_INDEX2SEQ(seq_first, bar_index);
  526. if (BAW_WITHIN(tid->seq_start, tid->baw_size, bar_seq))
  527. tid->bar_index = ATH_BA_INDEX(tid->seq_start, bar_seq);
  528. ath_txq_unlock(sc, txq);
  529. ath_send_bar(tid, ATH_BA_INDEX2SEQ(seq_first, bar_index + 1));
  530. ath_txq_lock(sc, txq);
  531. }
  532. rcu_read_unlock();
  533. if (needreset)
  534. ath9k_queue_reset(sc, RESET_TYPE_TX_ERROR);
  535. }
  536. static bool bf_is_ampdu_not_probing(struct ath_buf *bf)
  537. {
  538. struct ieee80211_tx_info *info = IEEE80211_SKB_CB(bf->bf_mpdu);
  539. return bf_isampdu(bf) && !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE);
  540. }
  541. static void ath_tx_process_buffer(struct ath_softc *sc, struct ath_txq *txq,
  542. struct ath_tx_status *ts, struct ath_buf *bf,
  543. struct list_head *bf_head)
  544. {
  545. struct ieee80211_tx_info *info;
  546. bool txok, flush;
  547. txok = !(ts->ts_status & ATH9K_TXERR_MASK);
  548. flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
  549. txq->axq_tx_inprogress = false;
  550. txq->axq_depth--;
  551. if (bf_is_ampdu_not_probing(bf))
  552. txq->axq_ampdu_depth--;
  553. if (!bf_isampdu(bf)) {
  554. if (!flush) {
  555. info = IEEE80211_SKB_CB(bf->bf_mpdu);
  556. memcpy(info->control.rates, bf->rates,
  557. sizeof(info->control.rates));
  558. ath_tx_rc_status(sc, bf, ts, 1, txok ? 0 : 1, txok);
  559. }
  560. ath_tx_complete_buf(sc, bf, txq, bf_head, ts, txok);
  561. } else
  562. ath_tx_complete_aggr(sc, txq, bf, bf_head, ts, txok);
  563. if (!flush)
  564. ath_txq_schedule(sc, txq);
  565. }
  566. static bool ath_lookup_legacy(struct ath_buf *bf)
  567. {
  568. struct sk_buff *skb;
  569. struct ieee80211_tx_info *tx_info;
  570. struct ieee80211_tx_rate *rates;
  571. int i;
  572. skb = bf->bf_mpdu;
  573. tx_info = IEEE80211_SKB_CB(skb);
  574. rates = tx_info->control.rates;
  575. for (i = 0; i < 4; i++) {
  576. if (!rates[i].count || rates[i].idx < 0)
  577. break;
  578. if (!(rates[i].flags & IEEE80211_TX_RC_MCS))
  579. return true;
  580. }
  581. return false;
  582. }
  583. static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
  584. struct ath_atx_tid *tid)
  585. {
  586. struct sk_buff *skb;
  587. struct ieee80211_tx_info *tx_info;
  588. struct ieee80211_tx_rate *rates;
  589. u32 max_4ms_framelen, frmlen;
  590. u16 aggr_limit, bt_aggr_limit, legacy = 0;
  591. int q = tid->ac->txq->mac80211_qnum;
  592. int i;
  593. skb = bf->bf_mpdu;
  594. tx_info = IEEE80211_SKB_CB(skb);
  595. rates = bf->rates;
  596. /*
  597. * Find the lowest frame length among the rate series that will have a
  598. * 4ms (or TXOP limited) transmit duration.
  599. */
  600. max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
  601. for (i = 0; i < 4; i++) {
  602. int modeidx;
  603. if (!rates[i].count)
  604. continue;
  605. if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) {
  606. legacy = 1;
  607. break;
  608. }
  609. if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
  610. modeidx = MCS_HT40;
  611. else
  612. modeidx = MCS_HT20;
  613. if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
  614. modeidx++;
  615. frmlen = sc->tx.max_aggr_framelen[q][modeidx][rates[i].idx];
  616. max_4ms_framelen = min(max_4ms_framelen, frmlen);
  617. }
  618. /*
  619. * limit aggregate size by the minimum rate if rate selected is
  620. * not a probe rate, if rate selected is a probe rate then
  621. * avoid aggregation of this packet.
  622. */
  623. if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
  624. return 0;
  625. aggr_limit = min(max_4ms_framelen, (u32)ATH_AMPDU_LIMIT_MAX);
  626. /*
  627. * Override the default aggregation limit for BTCOEX.
  628. */
  629. bt_aggr_limit = ath9k_btcoex_aggr_limit(sc, max_4ms_framelen);
  630. if (bt_aggr_limit)
  631. aggr_limit = bt_aggr_limit;
  632. if (tid->an->maxampdu)
  633. aggr_limit = min(aggr_limit, tid->an->maxampdu);
  634. return aggr_limit;
  635. }
  636. /*
  637. * Returns the number of delimiters to be added to
  638. * meet the minimum required mpdudensity.
  639. */
  640. static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
  641. struct ath_buf *bf, u16 frmlen,
  642. bool first_subfrm)
  643. {
  644. #define FIRST_DESC_NDELIMS 60
  645. u32 nsymbits, nsymbols;
  646. u16 minlen;
  647. u8 flags, rix;
  648. int width, streams, half_gi, ndelim, mindelim;
  649. struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
  650. /* Select standard number of delimiters based on frame length alone */
  651. ndelim = ATH_AGGR_GET_NDELIM(frmlen);
  652. /*
  653. * If encryption enabled, hardware requires some more padding between
  654. * subframes.
  655. * TODO - this could be improved to be dependent on the rate.
  656. * The hardware can keep up at lower rates, but not higher rates
  657. */
  658. if ((fi->keyix != ATH9K_TXKEYIX_INVALID) &&
  659. !(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))
  660. ndelim += ATH_AGGR_ENCRYPTDELIM;
  661. /*
  662. * Add delimiter when using RTS/CTS with aggregation
  663. * and non enterprise AR9003 card
  664. */
  665. if (first_subfrm && !AR_SREV_9580_10_OR_LATER(sc->sc_ah) &&
  666. (sc->sc_ah->ent_mode & AR_ENT_OTP_MIN_PKT_SIZE_DISABLE))
  667. ndelim = max(ndelim, FIRST_DESC_NDELIMS);
  668. /*
  669. * Convert desired mpdu density from microeconds to bytes based
  670. * on highest rate in rate series (i.e. first rate) to determine
  671. * required minimum length for subframe. Take into account
  672. * whether high rate is 20 or 40Mhz and half or full GI.
  673. *
  674. * If there is no mpdu density restriction, no further calculation
  675. * is needed.
  676. */
  677. if (tid->an->mpdudensity == 0)
  678. return ndelim;
  679. rix = bf->rates[0].idx;
  680. flags = bf->rates[0].flags;
  681. width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0;
  682. half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0;
  683. if (half_gi)
  684. nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity);
  685. else
  686. nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity);
  687. if (nsymbols == 0)
  688. nsymbols = 1;
  689. streams = HT_RC_2_STREAMS(rix);
  690. nsymbits = bits_per_symbol[rix % 8][width] * streams;
  691. minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
  692. if (frmlen < minlen) {
  693. mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
  694. ndelim = max(mindelim, ndelim);
  695. }
  696. return ndelim;
  697. }
  698. static struct ath_buf *
  699. ath_tx_get_tid_subframe(struct ath_softc *sc, struct ath_txq *txq,
  700. struct ath_atx_tid *tid, struct sk_buff_head **q)
  701. {
  702. struct ieee80211_tx_info *tx_info;
  703. struct ath_frame_info *fi;
  704. struct sk_buff *skb;
  705. struct ath_buf *bf;
  706. u16 seqno;
  707. while (1) {
  708. *q = &tid->retry_q;
  709. if (skb_queue_empty(*q))
  710. *q = &tid->buf_q;
  711. skb = skb_peek(*q);
  712. if (!skb)
  713. break;
  714. fi = get_frame_info(skb);
  715. bf = fi->bf;
  716. if (!fi->bf)
  717. bf = ath_tx_setup_buffer(sc, txq, tid, skb);
  718. else
  719. bf->bf_state.stale = false;
  720. if (!bf) {
  721. __skb_unlink(skb, *q);
  722. ath_txq_skb_done(sc, txq, skb);
  723. ieee80211_free_txskb(sc->hw, skb);
  724. continue;
  725. }
  726. bf->bf_next = NULL;
  727. bf->bf_lastbf = bf;
  728. tx_info = IEEE80211_SKB_CB(skb);
  729. tx_info->flags &= ~IEEE80211_TX_CTL_CLEAR_PS_FILT;
  730. if (!(tx_info->flags & IEEE80211_TX_CTL_AMPDU)) {
  731. bf->bf_state.bf_type = 0;
  732. return bf;
  733. }
  734. bf->bf_state.bf_type = BUF_AMPDU | BUF_AGGR;
  735. seqno = bf->bf_state.seqno;
  736. /* do not step over block-ack window */
  737. if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno))
  738. break;
  739. if (tid->bar_index > ATH_BA_INDEX(tid->seq_start, seqno)) {
  740. struct ath_tx_status ts = {};
  741. struct list_head bf_head;
  742. INIT_LIST_HEAD(&bf_head);
  743. list_add(&bf->list, &bf_head);
  744. __skb_unlink(skb, *q);
  745. ath_tx_update_baw(sc, tid, seqno);
  746. ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
  747. continue;
  748. }
  749. return bf;
  750. }
  751. return NULL;
  752. }
  753. static bool
  754. ath_tx_form_aggr(struct ath_softc *sc, struct ath_txq *txq,
  755. struct ath_atx_tid *tid, struct list_head *bf_q,
  756. struct ath_buf *bf_first, struct sk_buff_head *tid_q,
  757. int *aggr_len)
  758. {
  759. #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
  760. struct ath_buf *bf = bf_first, *bf_prev = NULL;
  761. int nframes = 0, ndelim;
  762. u16 aggr_limit = 0, al = 0, bpad = 0,
  763. al_delta, h_baw = tid->baw_size / 2;
  764. struct ieee80211_tx_info *tx_info;
  765. struct ath_frame_info *fi;
  766. struct sk_buff *skb;
  767. bool closed = false;
  768. bf = bf_first;
  769. aggr_limit = ath_lookup_rate(sc, bf, tid);
  770. do {
  771. skb = bf->bf_mpdu;
  772. fi = get_frame_info(skb);
  773. /* do not exceed aggregation limit */
  774. al_delta = ATH_AGGR_DELIM_SZ + fi->framelen;
  775. if (nframes) {
  776. if (aggr_limit < al + bpad + al_delta ||
  777. ath_lookup_legacy(bf) || nframes >= h_baw)
  778. break;
  779. tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
  780. if ((tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) ||
  781. !(tx_info->flags & IEEE80211_TX_CTL_AMPDU))
  782. break;
  783. }
  784. /* add padding for previous frame to aggregation length */
  785. al += bpad + al_delta;
  786. /*
  787. * Get the delimiters needed to meet the MPDU
  788. * density for this node.
  789. */
  790. ndelim = ath_compute_num_delims(sc, tid, bf_first, fi->framelen,
  791. !nframes);
  792. bpad = PADBYTES(al_delta) + (ndelim << 2);
  793. nframes++;
  794. bf->bf_next = NULL;
  795. /* link buffers of this frame to the aggregate */
  796. if (!fi->baw_tracked)
  797. ath_tx_addto_baw(sc, tid, bf);
  798. bf->bf_state.ndelim = ndelim;
  799. __skb_unlink(skb, tid_q);
  800. list_add_tail(&bf->list, bf_q);
  801. if (bf_prev)
  802. bf_prev->bf_next = bf;
  803. bf_prev = bf;
  804. bf = ath_tx_get_tid_subframe(sc, txq, tid, &tid_q);
  805. if (!bf) {
  806. closed = true;
  807. break;
  808. }
  809. } while (ath_tid_has_buffered(tid));
  810. bf = bf_first;
  811. bf->bf_lastbf = bf_prev;
  812. if (bf == bf_prev) {
  813. al = get_frame_info(bf->bf_mpdu)->framelen;
  814. bf->bf_state.bf_type = BUF_AMPDU;
  815. } else {
  816. TX_STAT_INC(txq->axq_qnum, a_aggr);
  817. }
  818. *aggr_len = al;
  819. return closed;
  820. #undef PADBYTES
  821. }
  822. /*
  823. * rix - rate index
  824. * pktlen - total bytes (delims + data + fcs + pads + pad delims)
  825. * width - 0 for 20 MHz, 1 for 40 MHz
  826. * half_gi - to use 4us v/s 3.6 us for symbol time
  827. */
  828. static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, int pktlen,
  829. int width, int half_gi, bool shortPreamble)
  830. {
  831. u32 nbits, nsymbits, duration, nsymbols;
  832. int streams;
  833. /* find number of symbols: PLCP + data */
  834. streams = HT_RC_2_STREAMS(rix);
  835. nbits = (pktlen << 3) + OFDM_PLCP_BITS;
  836. nsymbits = bits_per_symbol[rix % 8][width] * streams;
  837. nsymbols = (nbits + nsymbits - 1) / nsymbits;
  838. if (!half_gi)
  839. duration = SYMBOL_TIME(nsymbols);
  840. else
  841. duration = SYMBOL_TIME_HALFGI(nsymbols);
  842. /* addup duration for legacy/ht training and signal fields */
  843. duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
  844. return duration;
  845. }
  846. static int ath_max_framelen(int usec, int mcs, bool ht40, bool sgi)
  847. {
  848. int streams = HT_RC_2_STREAMS(mcs);
  849. int symbols, bits;
  850. int bytes = 0;
  851. symbols = sgi ? TIME_SYMBOLS_HALFGI(usec) : TIME_SYMBOLS(usec);
  852. bits = symbols * bits_per_symbol[mcs % 8][ht40] * streams;
  853. bits -= OFDM_PLCP_BITS;
  854. bytes = bits / 8;
  855. bytes -= L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
  856. if (bytes > 65532)
  857. bytes = 65532;
  858. return bytes;
  859. }
  860. void ath_update_max_aggr_framelen(struct ath_softc *sc, int queue, int txop)
  861. {
  862. u16 *cur_ht20, *cur_ht20_sgi, *cur_ht40, *cur_ht40_sgi;
  863. int mcs;
  864. /* 4ms is the default (and maximum) duration */
  865. if (!txop || txop > 4096)
  866. txop = 4096;
  867. cur_ht20 = sc->tx.max_aggr_framelen[queue][MCS_HT20];
  868. cur_ht20_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT20_SGI];
  869. cur_ht40 = sc->tx.max_aggr_framelen[queue][MCS_HT40];
  870. cur_ht40_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT40_SGI];
  871. for (mcs = 0; mcs < 32; mcs++) {
  872. cur_ht20[mcs] = ath_max_framelen(txop, mcs, false, false);
  873. cur_ht20_sgi[mcs] = ath_max_framelen(txop, mcs, false, true);
  874. cur_ht40[mcs] = ath_max_framelen(txop, mcs, true, false);
  875. cur_ht40_sgi[mcs] = ath_max_framelen(txop, mcs, true, true);
  876. }
  877. }
  878. static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf,
  879. struct ath_tx_info *info, int len, bool rts)
  880. {
  881. struct ath_hw *ah = sc->sc_ah;
  882. struct sk_buff *skb;
  883. struct ieee80211_tx_info *tx_info;
  884. struct ieee80211_tx_rate *rates;
  885. const struct ieee80211_rate *rate;
  886. struct ieee80211_hdr *hdr;
  887. struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
  888. u32 rts_thresh = sc->hw->wiphy->rts_threshold;
  889. int i;
  890. u8 rix = 0;
  891. skb = bf->bf_mpdu;
  892. tx_info = IEEE80211_SKB_CB(skb);
  893. rates = bf->rates;
  894. hdr = (struct ieee80211_hdr *)skb->data;
  895. /* set dur_update_en for l-sig computation except for PS-Poll frames */
  896. info->dur_update = !ieee80211_is_pspoll(hdr->frame_control);
  897. info->rtscts_rate = fi->rtscts_rate;
  898. for (i = 0; i < ARRAY_SIZE(bf->rates); i++) {
  899. bool is_40, is_sgi, is_sp;
  900. int phy;
  901. if (!rates[i].count || (rates[i].idx < 0))
  902. continue;
  903. rix = rates[i].idx;
  904. info->rates[i].Tries = rates[i].count;
  905. /*
  906. * Handle RTS threshold for unaggregated HT frames.
  907. */
  908. if (bf_isampdu(bf) && !bf_isaggr(bf) &&
  909. (rates[i].flags & IEEE80211_TX_RC_MCS) &&
  910. unlikely(rts_thresh != (u32) -1)) {
  911. if (!rts_thresh || (len > rts_thresh))
  912. rts = true;
  913. }
  914. if (rts || rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
  915. info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
  916. info->flags |= ATH9K_TXDESC_RTSENA;
  917. } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
  918. info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
  919. info->flags |= ATH9K_TXDESC_CTSENA;
  920. }
  921. if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
  922. info->rates[i].RateFlags |= ATH9K_RATESERIES_2040;
  923. if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
  924. info->rates[i].RateFlags |= ATH9K_RATESERIES_HALFGI;
  925. is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI);
  926. is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH);
  927. is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE);
  928. if (rates[i].flags & IEEE80211_TX_RC_MCS) {
  929. /* MCS rates */
  930. info->rates[i].Rate = rix | 0x80;
  931. info->rates[i].ChSel = ath_txchainmask_reduction(sc,
  932. ah->txchainmask, info->rates[i].Rate);
  933. info->rates[i].PktDuration = ath_pkt_duration(sc, rix, len,
  934. is_40, is_sgi, is_sp);
  935. if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC))
  936. info->rates[i].RateFlags |= ATH9K_RATESERIES_STBC;
  937. continue;
  938. }
  939. /* legacy rates */
  940. rate = &sc->sbands[tx_info->band].bitrates[rates[i].idx];
  941. if ((tx_info->band == IEEE80211_BAND_2GHZ) &&
  942. !(rate->flags & IEEE80211_RATE_ERP_G))
  943. phy = WLAN_RC_PHY_CCK;
  944. else
  945. phy = WLAN_RC_PHY_OFDM;
  946. info->rates[i].Rate = rate->hw_value;
  947. if (rate->hw_value_short) {
  948. if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
  949. info->rates[i].Rate |= rate->hw_value_short;
  950. } else {
  951. is_sp = false;
  952. }
  953. if (bf->bf_state.bfs_paprd)
  954. info->rates[i].ChSel = ah->txchainmask;
  955. else
  956. info->rates[i].ChSel = ath_txchainmask_reduction(sc,
  957. ah->txchainmask, info->rates[i].Rate);
  958. info->rates[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah,
  959. phy, rate->bitrate * 100, len, rix, is_sp);
  960. }
  961. /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
  962. if (bf_isaggr(bf) && (len > sc->sc_ah->caps.rts_aggr_limit))
  963. info->flags &= ~ATH9K_TXDESC_RTSENA;
  964. /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */
  965. if (info->flags & ATH9K_TXDESC_RTSENA)
  966. info->flags &= ~ATH9K_TXDESC_CTSENA;
  967. }
  968. static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
  969. {
  970. struct ieee80211_hdr *hdr;
  971. enum ath9k_pkt_type htype;
  972. __le16 fc;
  973. hdr = (struct ieee80211_hdr *)skb->data;
  974. fc = hdr->frame_control;
  975. if (ieee80211_is_beacon(fc))
  976. htype = ATH9K_PKT_TYPE_BEACON;
  977. else if (ieee80211_is_probe_resp(fc))
  978. htype = ATH9K_PKT_TYPE_PROBE_RESP;
  979. else if (ieee80211_is_atim(fc))
  980. htype = ATH9K_PKT_TYPE_ATIM;
  981. else if (ieee80211_is_pspoll(fc))
  982. htype = ATH9K_PKT_TYPE_PSPOLL;
  983. else
  984. htype = ATH9K_PKT_TYPE_NORMAL;
  985. return htype;
  986. }
  987. static void ath_tx_fill_desc(struct ath_softc *sc, struct ath_buf *bf,
  988. struct ath_txq *txq, int len)
  989. {
  990. struct ath_hw *ah = sc->sc_ah;
  991. struct ath_buf *bf_first = NULL;
  992. struct ath_tx_info info;
  993. u32 rts_thresh = sc->hw->wiphy->rts_threshold;
  994. bool rts = false;
  995. memset(&info, 0, sizeof(info));
  996. info.is_first = true;
  997. info.is_last = true;
  998. info.txpower = MAX_RATE_POWER;
  999. info.qcu = txq->axq_qnum;
  1000. while (bf) {
  1001. struct sk_buff *skb = bf->bf_mpdu;
  1002. struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
  1003. struct ath_frame_info *fi = get_frame_info(skb);
  1004. bool aggr = !!(bf->bf_state.bf_type & BUF_AGGR);
  1005. info.type = get_hw_packet_type(skb);
  1006. if (bf->bf_next)
  1007. info.link = bf->bf_next->bf_daddr;
  1008. else
  1009. info.link = (sc->tx99_state) ? bf->bf_daddr : 0;
  1010. if (!bf_first) {
  1011. bf_first = bf;
  1012. if (!sc->tx99_state)
  1013. info.flags = ATH9K_TXDESC_INTREQ;
  1014. if ((tx_info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT) ||
  1015. txq == sc->tx.uapsdq)
  1016. info.flags |= ATH9K_TXDESC_CLRDMASK;
  1017. if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
  1018. info.flags |= ATH9K_TXDESC_NOACK;
  1019. if (tx_info->flags & IEEE80211_TX_CTL_LDPC)
  1020. info.flags |= ATH9K_TXDESC_LDPC;
  1021. if (bf->bf_state.bfs_paprd)
  1022. info.flags |= (u32) bf->bf_state.bfs_paprd <<
  1023. ATH9K_TXDESC_PAPRD_S;
  1024. /*
  1025. * mac80211 doesn't handle RTS threshold for HT because
  1026. * the decision has to be taken based on AMPDU length
  1027. * and aggregation is done entirely inside ath9k.
  1028. * Set the RTS/CTS flag for the first subframe based
  1029. * on the threshold.
  1030. */
  1031. if (aggr && (bf == bf_first) &&
  1032. unlikely(rts_thresh != (u32) -1)) {
  1033. /*
  1034. * "len" is the size of the entire AMPDU.
  1035. */
  1036. if (!rts_thresh || (len > rts_thresh))
  1037. rts = true;
  1038. }
  1039. if (!aggr)
  1040. len = fi->framelen;
  1041. ath_buf_set_rate(sc, bf, &info, len, rts);
  1042. }
  1043. info.buf_addr[0] = bf->bf_buf_addr;
  1044. info.buf_len[0] = skb->len;
  1045. info.pkt_len = fi->framelen;
  1046. info.keyix = fi->keyix;
  1047. info.keytype = fi->keytype;
  1048. if (aggr) {
  1049. if (bf == bf_first)
  1050. info.aggr = AGGR_BUF_FIRST;
  1051. else if (bf == bf_first->bf_lastbf)
  1052. info.aggr = AGGR_BUF_LAST;
  1053. else
  1054. info.aggr = AGGR_BUF_MIDDLE;
  1055. info.ndelim = bf->bf_state.ndelim;
  1056. info.aggr_len = len;
  1057. }
  1058. if (bf == bf_first->bf_lastbf)
  1059. bf_first = NULL;
  1060. ath9k_hw_set_txdesc(ah, bf->bf_desc, &info);
  1061. bf = bf->bf_next;
  1062. }
  1063. }
  1064. static void
  1065. ath_tx_form_burst(struct ath_softc *sc, struct ath_txq *txq,
  1066. struct ath_atx_tid *tid, struct list_head *bf_q,
  1067. struct ath_buf *bf_first, struct sk_buff_head *tid_q)
  1068. {
  1069. struct ath_buf *bf = bf_first, *bf_prev = NULL;
  1070. struct sk_buff *skb;
  1071. int nframes = 0;
  1072. do {
  1073. struct ieee80211_tx_info *tx_info;
  1074. skb = bf->bf_mpdu;
  1075. nframes++;
  1076. __skb_unlink(skb, tid_q);
  1077. list_add_tail(&bf->list, bf_q);
  1078. if (bf_prev)
  1079. bf_prev->bf_next = bf;
  1080. bf_prev = bf;
  1081. if (nframes >= 2)
  1082. break;
  1083. bf = ath_tx_get_tid_subframe(sc, txq, tid, &tid_q);
  1084. if (!bf)
  1085. break;
  1086. tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
  1087. if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
  1088. break;
  1089. ath_set_rates(tid->an->vif, tid->an->sta, bf);
  1090. } while (1);
  1091. }
  1092. static bool ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
  1093. struct ath_atx_tid *tid, bool *stop)
  1094. {
  1095. struct ath_buf *bf;
  1096. struct ieee80211_tx_info *tx_info;
  1097. struct sk_buff_head *tid_q;
  1098. struct list_head bf_q;
  1099. int aggr_len = 0;
  1100. bool aggr, last = true;
  1101. if (!ath_tid_has_buffered(tid))
  1102. return false;
  1103. INIT_LIST_HEAD(&bf_q);
  1104. bf = ath_tx_get_tid_subframe(sc, txq, tid, &tid_q);
  1105. if (!bf)
  1106. return false;
  1107. tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
  1108. aggr = !!(tx_info->flags & IEEE80211_TX_CTL_AMPDU);
  1109. if ((aggr && txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) ||
  1110. (!aggr && txq->axq_depth >= ATH_NON_AGGR_MIN_QDEPTH)) {
  1111. *stop = true;
  1112. return false;
  1113. }
  1114. ath_set_rates(tid->an->vif, tid->an->sta, bf);
  1115. if (aggr)
  1116. last = ath_tx_form_aggr(sc, txq, tid, &bf_q, bf,
  1117. tid_q, &aggr_len);
  1118. else
  1119. ath_tx_form_burst(sc, txq, tid, &bf_q, bf, tid_q);
  1120. if (list_empty(&bf_q))
  1121. return false;
  1122. if (tid->ac->clear_ps_filter || tid->an->no_ps_filter) {
  1123. tid->ac->clear_ps_filter = false;
  1124. tx_info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
  1125. }
  1126. ath_tx_fill_desc(sc, bf, txq, aggr_len);
  1127. ath_tx_txqaddbuf(sc, txq, &bf_q, false);
  1128. return true;
  1129. }
  1130. int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
  1131. u16 tid, u16 *ssn)
  1132. {
  1133. struct ath_atx_tid *txtid;
  1134. struct ath_txq *txq;
  1135. struct ath_node *an;
  1136. u8 density;
  1137. an = (struct ath_node *)sta->drv_priv;
  1138. txtid = ATH_AN_2_TID(an, tid);
  1139. txq = txtid->ac->txq;
  1140. ath_txq_lock(sc, txq);
  1141. /* update ampdu factor/density, they may have changed. This may happen
  1142. * in HT IBSS when a beacon with HT-info is received after the station
  1143. * has already been added.
  1144. */
  1145. if (sta->ht_cap.ht_supported) {
  1146. an->maxampdu = (1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
  1147. sta->ht_cap.ampdu_factor)) - 1;
  1148. density = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density);
  1149. an->mpdudensity = density;
  1150. }
  1151. /* force sequence number allocation for pending frames */
  1152. ath_tx_tid_change_state(sc, txtid);
  1153. txtid->active = true;
  1154. txtid->paused = true;
  1155. *ssn = txtid->seq_start = txtid->seq_next;
  1156. txtid->bar_index = -1;
  1157. memset(txtid->tx_buf, 0, sizeof(txtid->tx_buf));
  1158. txtid->baw_head = txtid->baw_tail = 0;
  1159. ath_txq_unlock_complete(sc, txq);
  1160. return 0;
  1161. }
  1162. void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
  1163. {
  1164. struct ath_node *an = (struct ath_node *)sta->drv_priv;
  1165. struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
  1166. struct ath_txq *txq = txtid->ac->txq;
  1167. ath_txq_lock(sc, txq);
  1168. txtid->active = false;
  1169. txtid->paused = false;
  1170. ath_tx_flush_tid(sc, txtid);
  1171. ath_tx_tid_change_state(sc, txtid);
  1172. ath_txq_unlock_complete(sc, txq);
  1173. }
  1174. void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc,
  1175. struct ath_node *an)
  1176. {
  1177. struct ath_atx_tid *tid;
  1178. struct ath_atx_ac *ac;
  1179. struct ath_txq *txq;
  1180. bool buffered;
  1181. int tidno;
  1182. for (tidno = 0, tid = &an->tid[tidno];
  1183. tidno < IEEE80211_NUM_TIDS; tidno++, tid++) {
  1184. ac = tid->ac;
  1185. txq = ac->txq;
  1186. ath_txq_lock(sc, txq);
  1187. if (!tid->sched) {
  1188. ath_txq_unlock(sc, txq);
  1189. continue;
  1190. }
  1191. buffered = ath_tid_has_buffered(tid);
  1192. tid->sched = false;
  1193. list_del(&tid->list);
  1194. if (ac->sched) {
  1195. ac->sched = false;
  1196. list_del(&ac->list);
  1197. }
  1198. ath_txq_unlock(sc, txq);
  1199. ieee80211_sta_set_buffered(sta, tidno, buffered);
  1200. }
  1201. }
  1202. void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an)
  1203. {
  1204. struct ath_atx_tid *tid;
  1205. struct ath_atx_ac *ac;
  1206. struct ath_txq *txq;
  1207. int tidno;
  1208. for (tidno = 0, tid = &an->tid[tidno];
  1209. tidno < IEEE80211_NUM_TIDS; tidno++, tid++) {
  1210. ac = tid->ac;
  1211. txq = ac->txq;
  1212. ath_txq_lock(sc, txq);
  1213. ac->clear_ps_filter = true;
  1214. if (!tid->paused && ath_tid_has_buffered(tid)) {
  1215. ath_tx_queue_tid(txq, tid);
  1216. ath_txq_schedule(sc, txq);
  1217. }
  1218. ath_txq_unlock_complete(sc, txq);
  1219. }
  1220. }
  1221. void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta,
  1222. u16 tidno)
  1223. {
  1224. struct ath_atx_tid *tid;
  1225. struct ath_node *an;
  1226. struct ath_txq *txq;
  1227. an = (struct ath_node *)sta->drv_priv;
  1228. tid = ATH_AN_2_TID(an, tidno);
  1229. txq = tid->ac->txq;
  1230. ath_txq_lock(sc, txq);
  1231. tid->baw_size = IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor;
  1232. tid->paused = false;
  1233. if (ath_tid_has_buffered(tid)) {
  1234. ath_tx_queue_tid(txq, tid);
  1235. ath_txq_schedule(sc, txq);
  1236. }
  1237. ath_txq_unlock_complete(sc, txq);
  1238. }
  1239. void ath9k_release_buffered_frames(struct ieee80211_hw *hw,
  1240. struct ieee80211_sta *sta,
  1241. u16 tids, int nframes,
  1242. enum ieee80211_frame_release_type reason,
  1243. bool more_data)
  1244. {
  1245. struct ath_softc *sc = hw->priv;
  1246. struct ath_node *an = (struct ath_node *)sta->drv_priv;
  1247. struct ath_txq *txq = sc->tx.uapsdq;
  1248. struct ieee80211_tx_info *info;
  1249. struct list_head bf_q;
  1250. struct ath_buf *bf_tail = NULL, *bf;
  1251. struct sk_buff_head *tid_q;
  1252. int sent = 0;
  1253. int i;
  1254. INIT_LIST_HEAD(&bf_q);
  1255. for (i = 0; tids && nframes; i++, tids >>= 1) {
  1256. struct ath_atx_tid *tid;
  1257. if (!(tids & 1))
  1258. continue;
  1259. tid = ATH_AN_2_TID(an, i);
  1260. if (tid->paused)
  1261. continue;
  1262. ath_txq_lock(sc, tid->ac->txq);
  1263. while (nframes > 0) {
  1264. bf = ath_tx_get_tid_subframe(sc, sc->tx.uapsdq, tid, &tid_q);
  1265. if (!bf)
  1266. break;
  1267. __skb_unlink(bf->bf_mpdu, tid_q);
  1268. list_add_tail(&bf->list, &bf_q);
  1269. ath_set_rates(tid->an->vif, tid->an->sta, bf);
  1270. if (bf_isampdu(bf)) {
  1271. ath_tx_addto_baw(sc, tid, bf);
  1272. bf->bf_state.bf_type &= ~BUF_AGGR;
  1273. }
  1274. if (bf_tail)
  1275. bf_tail->bf_next = bf;
  1276. bf_tail = bf;
  1277. nframes--;
  1278. sent++;
  1279. TX_STAT_INC(txq->axq_qnum, a_queued_hw);
  1280. if (an->sta && !ath_tid_has_buffered(tid))
  1281. ieee80211_sta_set_buffered(an->sta, i, false);
  1282. }
  1283. ath_txq_unlock_complete(sc, tid->ac->txq);
  1284. }
  1285. if (list_empty(&bf_q))
  1286. return;
  1287. info = IEEE80211_SKB_CB(bf_tail->bf_mpdu);
  1288. info->flags |= IEEE80211_TX_STATUS_EOSP;
  1289. bf = list_first_entry(&bf_q, struct ath_buf, list);
  1290. ath_txq_lock(sc, txq);
  1291. ath_tx_fill_desc(sc, bf, txq, 0);
  1292. ath_tx_txqaddbuf(sc, txq, &bf_q, false);
  1293. ath_txq_unlock(sc, txq);
  1294. }
  1295. /********************/
  1296. /* Queue Management */
  1297. /********************/
  1298. struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
  1299. {
  1300. struct ath_hw *ah = sc->sc_ah;
  1301. struct ath9k_tx_queue_info qi;
  1302. static const int subtype_txq_to_hwq[] = {
  1303. [IEEE80211_AC_BE] = ATH_TXQ_AC_BE,
  1304. [IEEE80211_AC_BK] = ATH_TXQ_AC_BK,
  1305. [IEEE80211_AC_VI] = ATH_TXQ_AC_VI,
  1306. [IEEE80211_AC_VO] = ATH_TXQ_AC_VO,
  1307. };
  1308. int axq_qnum, i;
  1309. memset(&qi, 0, sizeof(qi));
  1310. qi.tqi_subtype = subtype_txq_to_hwq[subtype];
  1311. qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
  1312. qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
  1313. qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
  1314. qi.tqi_physCompBuf = 0;
  1315. /*
  1316. * Enable interrupts only for EOL and DESC conditions.
  1317. * We mark tx descriptors to receive a DESC interrupt
  1318. * when a tx queue gets deep; otherwise waiting for the
  1319. * EOL to reap descriptors. Note that this is done to
  1320. * reduce interrupt load and this only defers reaping
  1321. * descriptors, never transmitting frames. Aside from
  1322. * reducing interrupts this also permits more concurrency.
  1323. * The only potential downside is if the tx queue backs
  1324. * up in which case the top half of the kernel may backup
  1325. * due to a lack of tx descriptors.
  1326. *
  1327. * The UAPSD queue is an exception, since we take a desc-
  1328. * based intr on the EOSP frames.
  1329. */
  1330. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
  1331. qi.tqi_qflags = TXQ_FLAG_TXINT_ENABLE;
  1332. } else {
  1333. if (qtype == ATH9K_TX_QUEUE_UAPSD)
  1334. qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
  1335. else
  1336. qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
  1337. TXQ_FLAG_TXDESCINT_ENABLE;
  1338. }
  1339. axq_qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
  1340. if (axq_qnum == -1) {
  1341. /*
  1342. * NB: don't print a message, this happens
  1343. * normally on parts with too few tx queues
  1344. */
  1345. return NULL;
  1346. }
  1347. if (!ATH_TXQ_SETUP(sc, axq_qnum)) {
  1348. struct ath_txq *txq = &sc->tx.txq[axq_qnum];
  1349. txq->axq_qnum = axq_qnum;
  1350. txq->mac80211_qnum = -1;
  1351. txq->axq_link = NULL;
  1352. __skb_queue_head_init(&txq->complete_q);
  1353. INIT_LIST_HEAD(&txq->axq_q);
  1354. INIT_LIST_HEAD(&txq->axq_acq);
  1355. spin_lock_init(&txq->axq_lock);
  1356. txq->axq_depth = 0;
  1357. txq->axq_ampdu_depth = 0;
  1358. txq->axq_tx_inprogress = false;
  1359. sc->tx.txqsetup |= 1<<axq_qnum;
  1360. txq->txq_headidx = txq->txq_tailidx = 0;
  1361. for (i = 0; i < ATH_TXFIFO_DEPTH; i++)
  1362. INIT_LIST_HEAD(&txq->txq_fifo[i]);
  1363. }
  1364. return &sc->tx.txq[axq_qnum];
  1365. }
  1366. int ath_txq_update(struct ath_softc *sc, int qnum,
  1367. struct ath9k_tx_queue_info *qinfo)
  1368. {
  1369. struct ath_hw *ah = sc->sc_ah;
  1370. int error = 0;
  1371. struct ath9k_tx_queue_info qi;
  1372. BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum);
  1373. ath9k_hw_get_txq_props(ah, qnum, &qi);
  1374. qi.tqi_aifs = qinfo->tqi_aifs;
  1375. qi.tqi_cwmin = qinfo->tqi_cwmin;
  1376. qi.tqi_cwmax = qinfo->tqi_cwmax;
  1377. qi.tqi_burstTime = qinfo->tqi_burstTime;
  1378. qi.tqi_readyTime = qinfo->tqi_readyTime;
  1379. if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
  1380. ath_err(ath9k_hw_common(sc->sc_ah),
  1381. "Unable to update hardware queue %u!\n", qnum);
  1382. error = -EIO;
  1383. } else {
  1384. ath9k_hw_resettxqueue(ah, qnum);
  1385. }
  1386. return error;
  1387. }
  1388. int ath_cabq_update(struct ath_softc *sc)
  1389. {
  1390. struct ath9k_tx_queue_info qi;
  1391. struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
  1392. int qnum = sc->beacon.cabq->axq_qnum;
  1393. ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
  1394. qi.tqi_readyTime = (cur_conf->beacon_interval *
  1395. ATH_CABQ_READY_TIME) / 100;
  1396. ath_txq_update(sc, qnum, &qi);
  1397. return 0;
  1398. }
  1399. static void ath_drain_txq_list(struct ath_softc *sc, struct ath_txq *txq,
  1400. struct list_head *list)
  1401. {
  1402. struct ath_buf *bf, *lastbf;
  1403. struct list_head bf_head;
  1404. struct ath_tx_status ts;
  1405. memset(&ts, 0, sizeof(ts));
  1406. ts.ts_status = ATH9K_TX_FLUSH;
  1407. INIT_LIST_HEAD(&bf_head);
  1408. while (!list_empty(list)) {
  1409. bf = list_first_entry(list, struct ath_buf, list);
  1410. if (bf->bf_state.stale) {
  1411. list_del(&bf->list);
  1412. ath_tx_return_buffer(sc, bf);
  1413. continue;
  1414. }
  1415. lastbf = bf->bf_lastbf;
  1416. list_cut_position(&bf_head, list, &lastbf->list);
  1417. ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
  1418. }
  1419. }
  1420. /*
  1421. * Drain a given TX queue (could be Beacon or Data)
  1422. *
  1423. * This assumes output has been stopped and
  1424. * we do not need to block ath_tx_tasklet.
  1425. */
  1426. void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq)
  1427. {
  1428. ath_txq_lock(sc, txq);
  1429. if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
  1430. int idx = txq->txq_tailidx;
  1431. while (!list_empty(&txq->txq_fifo[idx])) {
  1432. ath_drain_txq_list(sc, txq, &txq->txq_fifo[idx]);
  1433. INCR(idx, ATH_TXFIFO_DEPTH);
  1434. }
  1435. txq->txq_tailidx = idx;
  1436. }
  1437. txq->axq_link = NULL;
  1438. txq->axq_tx_inprogress = false;
  1439. ath_drain_txq_list(sc, txq, &txq->axq_q);
  1440. ath_txq_unlock_complete(sc, txq);
  1441. }
  1442. bool ath_drain_all_txq(struct ath_softc *sc)
  1443. {
  1444. struct ath_hw *ah = sc->sc_ah;
  1445. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1446. struct ath_txq *txq;
  1447. int i;
  1448. u32 npend = 0;
  1449. if (test_bit(SC_OP_INVALID, &sc->sc_flags))
  1450. return true;
  1451. ath9k_hw_abort_tx_dma(ah);
  1452. /* Check if any queue remains active */
  1453. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  1454. if (!ATH_TXQ_SETUP(sc, i))
  1455. continue;
  1456. if (!sc->tx.txq[i].axq_depth)
  1457. continue;
  1458. if (ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum))
  1459. npend |= BIT(i);
  1460. }
  1461. if (npend)
  1462. ath_err(common, "Failed to stop TX DMA, queues=0x%03x!\n", npend);
  1463. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  1464. if (!ATH_TXQ_SETUP(sc, i))
  1465. continue;
  1466. /*
  1467. * The caller will resume queues with ieee80211_wake_queues.
  1468. * Mark the queue as not stopped to prevent ath_tx_complete
  1469. * from waking the queue too early.
  1470. */
  1471. txq = &sc->tx.txq[i];
  1472. txq->stopped = false;
  1473. ath_draintxq(sc, txq);
  1474. }
  1475. return !npend;
  1476. }
  1477. void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
  1478. {
  1479. ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
  1480. sc->tx.txqsetup &= ~(1<<txq->axq_qnum);
  1481. }
  1482. /* For each axq_acq entry, for each tid, try to schedule packets
  1483. * for transmit until ampdu_depth has reached min Q depth.
  1484. */
  1485. void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
  1486. {
  1487. struct ath_atx_ac *ac, *last_ac;
  1488. struct ath_atx_tid *tid, *last_tid;
  1489. bool sent = false;
  1490. if (test_bit(SC_OP_HW_RESET, &sc->sc_flags) ||
  1491. list_empty(&txq->axq_acq))
  1492. return;
  1493. rcu_read_lock();
  1494. last_ac = list_entry(txq->axq_acq.prev, struct ath_atx_ac, list);
  1495. while (!list_empty(&txq->axq_acq)) {
  1496. bool stop = false;
  1497. ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list);
  1498. last_tid = list_entry(ac->tid_q.prev, struct ath_atx_tid, list);
  1499. list_del(&ac->list);
  1500. ac->sched = false;
  1501. while (!list_empty(&ac->tid_q)) {
  1502. tid = list_first_entry(&ac->tid_q, struct ath_atx_tid,
  1503. list);
  1504. list_del(&tid->list);
  1505. tid->sched = false;
  1506. if (tid->paused)
  1507. continue;
  1508. if (ath_tx_sched_aggr(sc, txq, tid, &stop))
  1509. sent = true;
  1510. /*
  1511. * add tid to round-robin queue if more frames
  1512. * are pending for the tid
  1513. */
  1514. if (ath_tid_has_buffered(tid))
  1515. ath_tx_queue_tid(txq, tid);
  1516. if (stop || tid == last_tid)
  1517. break;
  1518. }
  1519. if (!list_empty(&ac->tid_q) && !ac->sched) {
  1520. ac->sched = true;
  1521. list_add_tail(&ac->list, &txq->axq_acq);
  1522. }
  1523. if (stop)
  1524. break;
  1525. if (ac == last_ac) {
  1526. if (!sent)
  1527. break;
  1528. sent = false;
  1529. last_ac = list_entry(txq->axq_acq.prev,
  1530. struct ath_atx_ac, list);
  1531. }
  1532. }
  1533. rcu_read_unlock();
  1534. }
  1535. /***********/
  1536. /* TX, DMA */
  1537. /***********/
  1538. /*
  1539. * Insert a chain of ath_buf (descriptors) on a txq and
  1540. * assume the descriptors are already chained together by caller.
  1541. */
  1542. static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
  1543. struct list_head *head, bool internal)
  1544. {
  1545. struct ath_hw *ah = sc->sc_ah;
  1546. struct ath_common *common = ath9k_hw_common(ah);
  1547. struct ath_buf *bf, *bf_last;
  1548. bool puttxbuf = false;
  1549. bool edma;
  1550. /*
  1551. * Insert the frame on the outbound list and
  1552. * pass it on to the hardware.
  1553. */
  1554. if (list_empty(head))
  1555. return;
  1556. edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
  1557. bf = list_first_entry(head, struct ath_buf, list);
  1558. bf_last = list_entry(head->prev, struct ath_buf, list);
  1559. ath_dbg(common, QUEUE, "qnum: %d, txq depth: %d\n",
  1560. txq->axq_qnum, txq->axq_depth);
  1561. if (edma && list_empty(&txq->txq_fifo[txq->txq_headidx])) {
  1562. list_splice_tail_init(head, &txq->txq_fifo[txq->txq_headidx]);
  1563. INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH);
  1564. puttxbuf = true;
  1565. } else {
  1566. list_splice_tail_init(head, &txq->axq_q);
  1567. if (txq->axq_link) {
  1568. ath9k_hw_set_desc_link(ah, txq->axq_link, bf->bf_daddr);
  1569. ath_dbg(common, XMIT, "link[%u] (%p)=%llx (%p)\n",
  1570. txq->axq_qnum, txq->axq_link,
  1571. ito64(bf->bf_daddr), bf->bf_desc);
  1572. } else if (!edma)
  1573. puttxbuf = true;
  1574. txq->axq_link = bf_last->bf_desc;
  1575. }
  1576. if (puttxbuf) {
  1577. TX_STAT_INC(txq->axq_qnum, puttxbuf);
  1578. ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
  1579. ath_dbg(common, XMIT, "TXDP[%u] = %llx (%p)\n",
  1580. txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
  1581. }
  1582. if (!edma || sc->tx99_state) {
  1583. TX_STAT_INC(txq->axq_qnum, txstart);
  1584. ath9k_hw_txstart(ah, txq->axq_qnum);
  1585. }
  1586. if (!internal) {
  1587. while (bf) {
  1588. txq->axq_depth++;
  1589. if (bf_is_ampdu_not_probing(bf))
  1590. txq->axq_ampdu_depth++;
  1591. bf_last = bf->bf_lastbf;
  1592. bf = bf_last->bf_next;
  1593. bf_last->bf_next = NULL;
  1594. }
  1595. }
  1596. }
  1597. static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
  1598. struct ath_atx_tid *tid, struct sk_buff *skb)
  1599. {
  1600. struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
  1601. struct ath_frame_info *fi = get_frame_info(skb);
  1602. struct list_head bf_head;
  1603. struct ath_buf *bf = fi->bf;
  1604. INIT_LIST_HEAD(&bf_head);
  1605. list_add_tail(&bf->list, &bf_head);
  1606. bf->bf_state.bf_type = 0;
  1607. if (tid && (tx_info->flags & IEEE80211_TX_CTL_AMPDU)) {
  1608. bf->bf_state.bf_type = BUF_AMPDU;
  1609. ath_tx_addto_baw(sc, tid, bf);
  1610. }
  1611. bf->bf_next = NULL;
  1612. bf->bf_lastbf = bf;
  1613. ath_tx_fill_desc(sc, bf, txq, fi->framelen);
  1614. ath_tx_txqaddbuf(sc, txq, &bf_head, false);
  1615. TX_STAT_INC(txq->axq_qnum, queued);
  1616. }
  1617. static void setup_frame_info(struct ieee80211_hw *hw,
  1618. struct ieee80211_sta *sta,
  1619. struct sk_buff *skb,
  1620. int framelen)
  1621. {
  1622. struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
  1623. struct ieee80211_key_conf *hw_key = tx_info->control.hw_key;
  1624. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
  1625. const struct ieee80211_rate *rate;
  1626. struct ath_frame_info *fi = get_frame_info(skb);
  1627. struct ath_node *an = NULL;
  1628. enum ath9k_key_type keytype;
  1629. bool short_preamble = false;
  1630. /*
  1631. * We check if Short Preamble is needed for the CTS rate by
  1632. * checking the BSS's global flag.
  1633. * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
  1634. */
  1635. if (tx_info->control.vif &&
  1636. tx_info->control.vif->bss_conf.use_short_preamble)
  1637. short_preamble = true;
  1638. rate = ieee80211_get_rts_cts_rate(hw, tx_info);
  1639. keytype = ath9k_cmn_get_hw_crypto_keytype(skb);
  1640. if (sta)
  1641. an = (struct ath_node *) sta->drv_priv;
  1642. memset(fi, 0, sizeof(*fi));
  1643. if (hw_key)
  1644. fi->keyix = hw_key->hw_key_idx;
  1645. else if (an && ieee80211_is_data(hdr->frame_control) && an->ps_key > 0)
  1646. fi->keyix = an->ps_key;
  1647. else
  1648. fi->keyix = ATH9K_TXKEYIX_INVALID;
  1649. fi->keytype = keytype;
  1650. fi->framelen = framelen;
  1651. if (!rate)
  1652. return;
  1653. fi->rtscts_rate = rate->hw_value;
  1654. if (short_preamble)
  1655. fi->rtscts_rate |= rate->hw_value_short;
  1656. }
  1657. u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate)
  1658. {
  1659. struct ath_hw *ah = sc->sc_ah;
  1660. struct ath9k_channel *curchan = ah->curchan;
  1661. if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && IS_CHAN_5GHZ(curchan) &&
  1662. (chainmask == 0x7) && (rate < 0x90))
  1663. return 0x3;
  1664. else if (AR_SREV_9462(ah) && ath9k_hw_btcoex_is_enabled(ah) &&
  1665. IS_CCK_RATE(rate))
  1666. return 0x2;
  1667. else
  1668. return chainmask;
  1669. }
  1670. /*
  1671. * Assign a descriptor (and sequence number if necessary,
  1672. * and map buffer for DMA. Frees skb on error
  1673. */
  1674. static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
  1675. struct ath_txq *txq,
  1676. struct ath_atx_tid *tid,
  1677. struct sk_buff *skb)
  1678. {
  1679. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1680. struct ath_frame_info *fi = get_frame_info(skb);
  1681. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
  1682. struct ath_buf *bf;
  1683. int fragno;
  1684. u16 seqno;
  1685. bf = ath_tx_get_buffer(sc);
  1686. if (!bf) {
  1687. ath_dbg(common, XMIT, "TX buffers are full\n");
  1688. return NULL;
  1689. }
  1690. ATH_TXBUF_RESET(bf);
  1691. if (tid && ieee80211_is_data_present(hdr->frame_control)) {
  1692. fragno = le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG;
  1693. seqno = tid->seq_next;
  1694. hdr->seq_ctrl = cpu_to_le16(tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT);
  1695. if (fragno)
  1696. hdr->seq_ctrl |= cpu_to_le16(fragno);
  1697. if (!ieee80211_has_morefrags(hdr->frame_control))
  1698. INCR(tid->seq_next, IEEE80211_SEQ_MAX);
  1699. bf->bf_state.seqno = seqno;
  1700. }
  1701. bf->bf_mpdu = skb;
  1702. bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
  1703. skb->len, DMA_TO_DEVICE);
  1704. if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {
  1705. bf->bf_mpdu = NULL;
  1706. bf->bf_buf_addr = 0;
  1707. ath_err(ath9k_hw_common(sc->sc_ah),
  1708. "dma_mapping_error() on TX\n");
  1709. ath_tx_return_buffer(sc, bf);
  1710. return NULL;
  1711. }
  1712. fi->bf = bf;
  1713. return bf;
  1714. }
  1715. static int ath_tx_prepare(struct ieee80211_hw *hw, struct sk_buff *skb,
  1716. struct ath_tx_control *txctl)
  1717. {
  1718. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
  1719. struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
  1720. struct ieee80211_sta *sta = txctl->sta;
  1721. struct ieee80211_vif *vif = info->control.vif;
  1722. struct ath_vif *avp;
  1723. struct ath_softc *sc = hw->priv;
  1724. int frmlen = skb->len + FCS_LEN;
  1725. int padpos, padsize;
  1726. /* NOTE: sta can be NULL according to net/mac80211.h */
  1727. if (sta)
  1728. txctl->an = (struct ath_node *)sta->drv_priv;
  1729. else if (vif && ieee80211_is_data(hdr->frame_control)) {
  1730. avp = (void *)vif->drv_priv;
  1731. txctl->an = &avp->mcast_node;
  1732. }
  1733. if (info->control.hw_key)
  1734. frmlen += info->control.hw_key->icv_len;
  1735. /*
  1736. * As a temporary workaround, assign seq# here; this will likely need
  1737. * to be cleaned up to work better with Beacon transmission and virtual
  1738. * BSSes.
  1739. */
  1740. if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
  1741. if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
  1742. sc->tx.seq_no += 0x10;
  1743. hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
  1744. hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
  1745. }
  1746. if ((vif && vif->type != NL80211_IFTYPE_AP &&
  1747. vif->type != NL80211_IFTYPE_AP_VLAN) ||
  1748. !ieee80211_is_data(hdr->frame_control))
  1749. info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
  1750. /* Add the padding after the header if this is not already done */
  1751. padpos = ieee80211_hdrlen(hdr->frame_control);
  1752. padsize = padpos & 3;
  1753. if (padsize && skb->len > padpos) {
  1754. if (skb_headroom(skb) < padsize)
  1755. return -ENOMEM;
  1756. skb_push(skb, padsize);
  1757. memmove(skb->data, skb->data + padsize, padpos);
  1758. }
  1759. setup_frame_info(hw, sta, skb, frmlen);
  1760. return 0;
  1761. }
  1762. /* Upon failure caller should free skb */
  1763. int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
  1764. struct ath_tx_control *txctl)
  1765. {
  1766. struct ieee80211_hdr *hdr;
  1767. struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
  1768. struct ieee80211_sta *sta = txctl->sta;
  1769. struct ieee80211_vif *vif = info->control.vif;
  1770. struct ath_softc *sc = hw->priv;
  1771. struct ath_txq *txq = txctl->txq;
  1772. struct ath_atx_tid *tid = NULL;
  1773. struct ath_buf *bf;
  1774. int q;
  1775. int ret;
  1776. ret = ath_tx_prepare(hw, skb, txctl);
  1777. if (ret)
  1778. return ret;
  1779. hdr = (struct ieee80211_hdr *) skb->data;
  1780. /*
  1781. * At this point, the vif, hw_key and sta pointers in the tx control
  1782. * info are no longer valid (overwritten by the ath_frame_info data.
  1783. */
  1784. q = skb_get_queue_mapping(skb);
  1785. ath_txq_lock(sc, txq);
  1786. if (txq == sc->tx.txq_map[q] &&
  1787. ++txq->pending_frames > sc->tx.txq_max_pending[q] &&
  1788. !txq->stopped) {
  1789. ieee80211_stop_queue(sc->hw, q);
  1790. txq->stopped = true;
  1791. }
  1792. if (txctl->an && ieee80211_is_data_present(hdr->frame_control))
  1793. tid = ath_get_skb_tid(sc, txctl->an, skb);
  1794. if (info->flags & IEEE80211_TX_CTL_PS_RESPONSE) {
  1795. ath_txq_unlock(sc, txq);
  1796. txq = sc->tx.uapsdq;
  1797. ath_txq_lock(sc, txq);
  1798. } else if (txctl->an &&
  1799. ieee80211_is_data_present(hdr->frame_control)) {
  1800. WARN_ON(tid->ac->txq != txctl->txq);
  1801. if (info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT)
  1802. tid->ac->clear_ps_filter = true;
  1803. /*
  1804. * Add this frame to software queue for scheduling later
  1805. * for aggregation.
  1806. */
  1807. TX_STAT_INC(txq->axq_qnum, a_queued_sw);
  1808. __skb_queue_tail(&tid->buf_q, skb);
  1809. if (!txctl->an->sleeping)
  1810. ath_tx_queue_tid(txq, tid);
  1811. ath_txq_schedule(sc, txq);
  1812. goto out;
  1813. }
  1814. bf = ath_tx_setup_buffer(sc, txq, tid, skb);
  1815. if (!bf) {
  1816. ath_txq_skb_done(sc, txq, skb);
  1817. if (txctl->paprd)
  1818. dev_kfree_skb_any(skb);
  1819. else
  1820. ieee80211_free_txskb(sc->hw, skb);
  1821. goto out;
  1822. }
  1823. bf->bf_state.bfs_paprd = txctl->paprd;
  1824. if (txctl->paprd)
  1825. bf->bf_state.bfs_paprd_timestamp = jiffies;
  1826. ath_set_rates(vif, sta, bf);
  1827. ath_tx_send_normal(sc, txq, tid, skb);
  1828. out:
  1829. ath_txq_unlock(sc, txq);
  1830. return 0;
  1831. }
  1832. void ath_tx_cabq(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
  1833. struct sk_buff *skb)
  1834. {
  1835. struct ath_softc *sc = hw->priv;
  1836. struct ath_tx_control txctl = {
  1837. .txq = sc->beacon.cabq
  1838. };
  1839. struct ath_tx_info info = {};
  1840. struct ieee80211_hdr *hdr;
  1841. struct ath_buf *bf_tail = NULL;
  1842. struct ath_buf *bf;
  1843. LIST_HEAD(bf_q);
  1844. int duration = 0;
  1845. int max_duration;
  1846. max_duration =
  1847. sc->cur_beacon_conf.beacon_interval * 1000 *
  1848. sc->cur_beacon_conf.dtim_period / ATH_BCBUF;
  1849. do {
  1850. struct ath_frame_info *fi = get_frame_info(skb);
  1851. if (ath_tx_prepare(hw, skb, &txctl))
  1852. break;
  1853. bf = ath_tx_setup_buffer(sc, txctl.txq, NULL, skb);
  1854. if (!bf)
  1855. break;
  1856. bf->bf_lastbf = bf;
  1857. ath_set_rates(vif, NULL, bf);
  1858. ath_buf_set_rate(sc, bf, &info, fi->framelen, false);
  1859. duration += info.rates[0].PktDuration;
  1860. if (bf_tail)
  1861. bf_tail->bf_next = bf;
  1862. list_add_tail(&bf->list, &bf_q);
  1863. bf_tail = bf;
  1864. skb = NULL;
  1865. if (duration > max_duration)
  1866. break;
  1867. skb = ieee80211_get_buffered_bc(hw, vif);
  1868. } while(skb);
  1869. if (skb)
  1870. ieee80211_free_txskb(hw, skb);
  1871. if (list_empty(&bf_q))
  1872. return;
  1873. bf = list_first_entry(&bf_q, struct ath_buf, list);
  1874. hdr = (struct ieee80211_hdr *) bf->bf_mpdu->data;
  1875. if (hdr->frame_control & IEEE80211_FCTL_MOREDATA) {
  1876. hdr->frame_control &= ~IEEE80211_FCTL_MOREDATA;
  1877. dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
  1878. sizeof(*hdr), DMA_TO_DEVICE);
  1879. }
  1880. ath_txq_lock(sc, txctl.txq);
  1881. ath_tx_fill_desc(sc, bf, txctl.txq, 0);
  1882. ath_tx_txqaddbuf(sc, txctl.txq, &bf_q, false);
  1883. TX_STAT_INC(txctl.txq->axq_qnum, queued);
  1884. ath_txq_unlock(sc, txctl.txq);
  1885. }
  1886. /*****************/
  1887. /* TX Completion */
  1888. /*****************/
  1889. static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
  1890. int tx_flags, struct ath_txq *txq)
  1891. {
  1892. struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
  1893. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1894. struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
  1895. int padpos, padsize;
  1896. unsigned long flags;
  1897. ath_dbg(common, XMIT, "TX complete: skb: %p\n", skb);
  1898. if (sc->sc_ah->caldata)
  1899. set_bit(PAPRD_PACKET_SENT, &sc->sc_ah->caldata->cal_flags);
  1900. if (!(tx_flags & ATH_TX_ERROR))
  1901. /* Frame was ACKed */
  1902. tx_info->flags |= IEEE80211_TX_STAT_ACK;
  1903. padpos = ieee80211_hdrlen(hdr->frame_control);
  1904. padsize = padpos & 3;
  1905. if (padsize && skb->len>padpos+padsize) {
  1906. /*
  1907. * Remove MAC header padding before giving the frame back to
  1908. * mac80211.
  1909. */
  1910. memmove(skb->data + padsize, skb->data, padpos);
  1911. skb_pull(skb, padsize);
  1912. }
  1913. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  1914. if ((sc->ps_flags & PS_WAIT_FOR_TX_ACK) && !txq->axq_depth) {
  1915. sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK;
  1916. ath_dbg(common, PS,
  1917. "Going back to sleep after having received TX status (0x%lx)\n",
  1918. sc->ps_flags & (PS_WAIT_FOR_BEACON |
  1919. PS_WAIT_FOR_CAB |
  1920. PS_WAIT_FOR_PSPOLL_DATA |
  1921. PS_WAIT_FOR_TX_ACK));
  1922. }
  1923. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  1924. __skb_queue_tail(&txq->complete_q, skb);
  1925. ath_txq_skb_done(sc, txq, skb);
  1926. }
  1927. static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
  1928. struct ath_txq *txq, struct list_head *bf_q,
  1929. struct ath_tx_status *ts, int txok)
  1930. {
  1931. struct sk_buff *skb = bf->bf_mpdu;
  1932. struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
  1933. unsigned long flags;
  1934. int tx_flags = 0;
  1935. if (!txok)
  1936. tx_flags |= ATH_TX_ERROR;
  1937. if (ts->ts_status & ATH9K_TXERR_FILT)
  1938. tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
  1939. dma_unmap_single(sc->dev, bf->bf_buf_addr, skb->len, DMA_TO_DEVICE);
  1940. bf->bf_buf_addr = 0;
  1941. if (sc->tx99_state)
  1942. goto skip_tx_complete;
  1943. if (bf->bf_state.bfs_paprd) {
  1944. if (time_after(jiffies,
  1945. bf->bf_state.bfs_paprd_timestamp +
  1946. msecs_to_jiffies(ATH_PAPRD_TIMEOUT)))
  1947. dev_kfree_skb_any(skb);
  1948. else
  1949. complete(&sc->paprd_complete);
  1950. } else {
  1951. ath_debug_stat_tx(sc, bf, ts, txq, tx_flags);
  1952. ath_tx_complete(sc, skb, tx_flags, txq);
  1953. }
  1954. skip_tx_complete:
  1955. /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't
  1956. * accidentally reference it later.
  1957. */
  1958. bf->bf_mpdu = NULL;
  1959. /*
  1960. * Return the list of ath_buf of this mpdu to free queue
  1961. */
  1962. spin_lock_irqsave(&sc->tx.txbuflock, flags);
  1963. list_splice_tail_init(bf_q, &sc->tx.txbuf);
  1964. spin_unlock_irqrestore(&sc->tx.txbuflock, flags);
  1965. }
  1966. static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
  1967. struct ath_tx_status *ts, int nframes, int nbad,
  1968. int txok)
  1969. {
  1970. struct sk_buff *skb = bf->bf_mpdu;
  1971. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
  1972. struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
  1973. struct ieee80211_hw *hw = sc->hw;
  1974. struct ath_hw *ah = sc->sc_ah;
  1975. u8 i, tx_rateindex;
  1976. if (txok)
  1977. tx_info->status.ack_signal = ts->ts_rssi;
  1978. tx_rateindex = ts->ts_rateindex;
  1979. WARN_ON(tx_rateindex >= hw->max_rates);
  1980. if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
  1981. tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
  1982. BUG_ON(nbad > nframes);
  1983. }
  1984. tx_info->status.ampdu_len = nframes;
  1985. tx_info->status.ampdu_ack_len = nframes - nbad;
  1986. if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 &&
  1987. (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) == 0) {
  1988. /*
  1989. * If an underrun error is seen assume it as an excessive
  1990. * retry only if max frame trigger level has been reached
  1991. * (2 KB for single stream, and 4 KB for dual stream).
  1992. * Adjust the long retry as if the frame was tried
  1993. * hw->max_rate_tries times to affect how rate control updates
  1994. * PER for the failed rate.
  1995. * In case of congestion on the bus penalizing this type of
  1996. * underruns should help hardware actually transmit new frames
  1997. * successfully by eventually preferring slower rates.
  1998. * This itself should also alleviate congestion on the bus.
  1999. */
  2000. if (unlikely(ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN |
  2001. ATH9K_TX_DELIM_UNDERRUN)) &&
  2002. ieee80211_is_data(hdr->frame_control) &&
  2003. ah->tx_trig_level >= sc->sc_ah->config.max_txtrig_level)
  2004. tx_info->status.rates[tx_rateindex].count =
  2005. hw->max_rate_tries;
  2006. }
  2007. for (i = tx_rateindex + 1; i < hw->max_rates; i++) {
  2008. tx_info->status.rates[i].count = 0;
  2009. tx_info->status.rates[i].idx = -1;
  2010. }
  2011. tx_info->status.rates[tx_rateindex].count = ts->ts_longretry + 1;
  2012. }
  2013. static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
  2014. {
  2015. struct ath_hw *ah = sc->sc_ah;
  2016. struct ath_common *common = ath9k_hw_common(ah);
  2017. struct ath_buf *bf, *lastbf, *bf_held = NULL;
  2018. struct list_head bf_head;
  2019. struct ath_desc *ds;
  2020. struct ath_tx_status ts;
  2021. int status;
  2022. ath_dbg(common, QUEUE, "tx queue %d (%x), link %p\n",
  2023. txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
  2024. txq->axq_link);
  2025. ath_txq_lock(sc, txq);
  2026. for (;;) {
  2027. if (test_bit(SC_OP_HW_RESET, &sc->sc_flags))
  2028. break;
  2029. if (list_empty(&txq->axq_q)) {
  2030. txq->axq_link = NULL;
  2031. ath_txq_schedule(sc, txq);
  2032. break;
  2033. }
  2034. bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
  2035. /*
  2036. * There is a race condition that a BH gets scheduled
  2037. * after sw writes TxE and before hw re-load the last
  2038. * descriptor to get the newly chained one.
  2039. * Software must keep the last DONE descriptor as a
  2040. * holding descriptor - software does so by marking
  2041. * it with the STALE flag.
  2042. */
  2043. bf_held = NULL;
  2044. if (bf->bf_state.stale) {
  2045. bf_held = bf;
  2046. if (list_is_last(&bf_held->list, &txq->axq_q))
  2047. break;
  2048. bf = list_entry(bf_held->list.next, struct ath_buf,
  2049. list);
  2050. }
  2051. lastbf = bf->bf_lastbf;
  2052. ds = lastbf->bf_desc;
  2053. memset(&ts, 0, sizeof(ts));
  2054. status = ath9k_hw_txprocdesc(ah, ds, &ts);
  2055. if (status == -EINPROGRESS)
  2056. break;
  2057. TX_STAT_INC(txq->axq_qnum, txprocdesc);
  2058. /*
  2059. * Remove ath_buf's of the same transmit unit from txq,
  2060. * however leave the last descriptor back as the holding
  2061. * descriptor for hw.
  2062. */
  2063. lastbf->bf_state.stale = true;
  2064. INIT_LIST_HEAD(&bf_head);
  2065. if (!list_is_singular(&lastbf->list))
  2066. list_cut_position(&bf_head,
  2067. &txq->axq_q, lastbf->list.prev);
  2068. if (bf_held) {
  2069. list_del(&bf_held->list);
  2070. ath_tx_return_buffer(sc, bf_held);
  2071. }
  2072. ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
  2073. }
  2074. ath_txq_unlock_complete(sc, txq);
  2075. }
  2076. void ath_tx_tasklet(struct ath_softc *sc)
  2077. {
  2078. struct ath_hw *ah = sc->sc_ah;
  2079. u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1) & ah->intr_txqs;
  2080. int i;
  2081. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  2082. if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
  2083. ath_tx_processq(sc, &sc->tx.txq[i]);
  2084. }
  2085. }
  2086. void ath_tx_edma_tasklet(struct ath_softc *sc)
  2087. {
  2088. struct ath_tx_status ts;
  2089. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  2090. struct ath_hw *ah = sc->sc_ah;
  2091. struct ath_txq *txq;
  2092. struct ath_buf *bf, *lastbf;
  2093. struct list_head bf_head;
  2094. struct list_head *fifo_list;
  2095. int status;
  2096. for (;;) {
  2097. if (test_bit(SC_OP_HW_RESET, &sc->sc_flags))
  2098. break;
  2099. status = ath9k_hw_txprocdesc(ah, NULL, (void *)&ts);
  2100. if (status == -EINPROGRESS)
  2101. break;
  2102. if (status == -EIO) {
  2103. ath_dbg(common, XMIT, "Error processing tx status\n");
  2104. break;
  2105. }
  2106. /* Process beacon completions separately */
  2107. if (ts.qid == sc->beacon.beaconq) {
  2108. sc->beacon.tx_processed = true;
  2109. sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
  2110. ath9k_csa_is_finished(sc);
  2111. continue;
  2112. }
  2113. txq = &sc->tx.txq[ts.qid];
  2114. ath_txq_lock(sc, txq);
  2115. TX_STAT_INC(txq->axq_qnum, txprocdesc);
  2116. fifo_list = &txq->txq_fifo[txq->txq_tailidx];
  2117. if (list_empty(fifo_list)) {
  2118. ath_txq_unlock(sc, txq);
  2119. return;
  2120. }
  2121. bf = list_first_entry(fifo_list, struct ath_buf, list);
  2122. if (bf->bf_state.stale) {
  2123. list_del(&bf->list);
  2124. ath_tx_return_buffer(sc, bf);
  2125. bf = list_first_entry(fifo_list, struct ath_buf, list);
  2126. }
  2127. lastbf = bf->bf_lastbf;
  2128. INIT_LIST_HEAD(&bf_head);
  2129. if (list_is_last(&lastbf->list, fifo_list)) {
  2130. list_splice_tail_init(fifo_list, &bf_head);
  2131. INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
  2132. if (!list_empty(&txq->axq_q)) {
  2133. struct list_head bf_q;
  2134. INIT_LIST_HEAD(&bf_q);
  2135. txq->axq_link = NULL;
  2136. list_splice_tail_init(&txq->axq_q, &bf_q);
  2137. ath_tx_txqaddbuf(sc, txq, &bf_q, true);
  2138. }
  2139. } else {
  2140. lastbf->bf_state.stale = true;
  2141. if (bf != lastbf)
  2142. list_cut_position(&bf_head, fifo_list,
  2143. lastbf->list.prev);
  2144. }
  2145. ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
  2146. ath_txq_unlock_complete(sc, txq);
  2147. }
  2148. }
  2149. /*****************/
  2150. /* Init, Cleanup */
  2151. /*****************/
  2152. static int ath_txstatus_setup(struct ath_softc *sc, int size)
  2153. {
  2154. struct ath_descdma *dd = &sc->txsdma;
  2155. u8 txs_len = sc->sc_ah->caps.txs_len;
  2156. dd->dd_desc_len = size * txs_len;
  2157. dd->dd_desc = dmam_alloc_coherent(sc->dev, dd->dd_desc_len,
  2158. &dd->dd_desc_paddr, GFP_KERNEL);
  2159. if (!dd->dd_desc)
  2160. return -ENOMEM;
  2161. return 0;
  2162. }
  2163. static int ath_tx_edma_init(struct ath_softc *sc)
  2164. {
  2165. int err;
  2166. err = ath_txstatus_setup(sc, ATH_TXSTATUS_RING_SIZE);
  2167. if (!err)
  2168. ath9k_hw_setup_statusring(sc->sc_ah, sc->txsdma.dd_desc,
  2169. sc->txsdma.dd_desc_paddr,
  2170. ATH_TXSTATUS_RING_SIZE);
  2171. return err;
  2172. }
  2173. int ath_tx_init(struct ath_softc *sc, int nbufs)
  2174. {
  2175. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  2176. int error = 0;
  2177. spin_lock_init(&sc->tx.txbuflock);
  2178. error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
  2179. "tx", nbufs, 1, 1);
  2180. if (error != 0) {
  2181. ath_err(common,
  2182. "Failed to allocate tx descriptors: %d\n", error);
  2183. return error;
  2184. }
  2185. error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
  2186. "beacon", ATH_BCBUF, 1, 1);
  2187. if (error != 0) {
  2188. ath_err(common,
  2189. "Failed to allocate beacon descriptors: %d\n", error);
  2190. return error;
  2191. }
  2192. INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work);
  2193. if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  2194. error = ath_tx_edma_init(sc);
  2195. return error;
  2196. }
  2197. void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
  2198. {
  2199. struct ath_atx_tid *tid;
  2200. struct ath_atx_ac *ac;
  2201. int tidno, acno;
  2202. for (tidno = 0, tid = &an->tid[tidno];
  2203. tidno < IEEE80211_NUM_TIDS;
  2204. tidno++, tid++) {
  2205. tid->an = an;
  2206. tid->tidno = tidno;
  2207. tid->seq_start = tid->seq_next = 0;
  2208. tid->baw_size = WME_MAX_BA;
  2209. tid->baw_head = tid->baw_tail = 0;
  2210. tid->sched = false;
  2211. tid->paused = false;
  2212. tid->active = false;
  2213. __skb_queue_head_init(&tid->buf_q);
  2214. __skb_queue_head_init(&tid->retry_q);
  2215. acno = TID_TO_WME_AC(tidno);
  2216. tid->ac = &an->ac[acno];
  2217. }
  2218. for (acno = 0, ac = &an->ac[acno];
  2219. acno < IEEE80211_NUM_ACS; acno++, ac++) {
  2220. ac->sched = false;
  2221. ac->clear_ps_filter = true;
  2222. ac->txq = sc->tx.txq_map[acno];
  2223. INIT_LIST_HEAD(&ac->tid_q);
  2224. }
  2225. }
  2226. void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
  2227. {
  2228. struct ath_atx_ac *ac;
  2229. struct ath_atx_tid *tid;
  2230. struct ath_txq *txq;
  2231. int tidno;
  2232. for (tidno = 0, tid = &an->tid[tidno];
  2233. tidno < IEEE80211_NUM_TIDS; tidno++, tid++) {
  2234. ac = tid->ac;
  2235. txq = ac->txq;
  2236. ath_txq_lock(sc, txq);
  2237. if (tid->sched) {
  2238. list_del(&tid->list);
  2239. tid->sched = false;
  2240. }
  2241. if (ac->sched) {
  2242. list_del(&ac->list);
  2243. tid->ac->sched = false;
  2244. }
  2245. ath_tid_drain(sc, txq, tid);
  2246. tid->active = false;
  2247. ath_txq_unlock(sc, txq);
  2248. }
  2249. }
  2250. #ifdef CONFIG_ATH9K_TX99
  2251. int ath9k_tx99_send(struct ath_softc *sc, struct sk_buff *skb,
  2252. struct ath_tx_control *txctl)
  2253. {
  2254. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
  2255. struct ath_frame_info *fi = get_frame_info(skb);
  2256. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  2257. struct ath_buf *bf;
  2258. int padpos, padsize;
  2259. padpos = ieee80211_hdrlen(hdr->frame_control);
  2260. padsize = padpos & 3;
  2261. if (padsize && skb->len > padpos) {
  2262. if (skb_headroom(skb) < padsize) {
  2263. ath_dbg(common, XMIT,
  2264. "tx99 padding failed\n");
  2265. return -EINVAL;
  2266. }
  2267. skb_push(skb, padsize);
  2268. memmove(skb->data, skb->data + padsize, padpos);
  2269. }
  2270. fi->keyix = ATH9K_TXKEYIX_INVALID;
  2271. fi->framelen = skb->len + FCS_LEN;
  2272. fi->keytype = ATH9K_KEY_TYPE_CLEAR;
  2273. bf = ath_tx_setup_buffer(sc, txctl->txq, NULL, skb);
  2274. if (!bf) {
  2275. ath_dbg(common, XMIT, "tx99 buffer setup failed\n");
  2276. return -EINVAL;
  2277. }
  2278. ath_set_rates(sc->tx99_vif, NULL, bf);
  2279. ath9k_hw_set_desc_link(sc->sc_ah, bf->bf_desc, bf->bf_daddr);
  2280. ath9k_hw_tx99_start(sc->sc_ah, txctl->txq->axq_qnum);
  2281. ath_tx_send_normal(sc, txctl->txq, NULL, skb);
  2282. return 0;
  2283. }
  2284. #endif /* CONFIG_ATH9K_TX99 */