htc_drv_init.c 27 KB

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  1. /*
  2. * Copyright (c) 2010-2011 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  17. #include "htc.h"
  18. MODULE_AUTHOR("Atheros Communications");
  19. MODULE_LICENSE("Dual BSD/GPL");
  20. MODULE_DESCRIPTION("Atheros driver 802.11n HTC based wireless devices");
  21. static unsigned int ath9k_debug = ATH_DBG_DEFAULT;
  22. module_param_named(debug, ath9k_debug, uint, 0);
  23. MODULE_PARM_DESC(debug, "Debugging mask");
  24. int htc_modparam_nohwcrypt;
  25. module_param_named(nohwcrypt, htc_modparam_nohwcrypt, int, 0444);
  26. MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
  27. static int ath9k_htc_btcoex_enable;
  28. module_param_named(btcoex_enable, ath9k_htc_btcoex_enable, int, 0444);
  29. MODULE_PARM_DESC(btcoex_enable, "Enable wifi-BT coexistence");
  30. static int ath9k_ps_enable;
  31. module_param_named(ps_enable, ath9k_ps_enable, int, 0444);
  32. MODULE_PARM_DESC(ps_enable, "Enable WLAN PowerSave");
  33. #define CHAN2G(_freq, _idx) { \
  34. .center_freq = (_freq), \
  35. .hw_value = (_idx), \
  36. .max_power = 20, \
  37. }
  38. #define CHAN5G(_freq, _idx) { \
  39. .band = IEEE80211_BAND_5GHZ, \
  40. .center_freq = (_freq), \
  41. .hw_value = (_idx), \
  42. .max_power = 20, \
  43. }
  44. static struct ieee80211_channel ath9k_2ghz_channels[] = {
  45. CHAN2G(2412, 0), /* Channel 1 */
  46. CHAN2G(2417, 1), /* Channel 2 */
  47. CHAN2G(2422, 2), /* Channel 3 */
  48. CHAN2G(2427, 3), /* Channel 4 */
  49. CHAN2G(2432, 4), /* Channel 5 */
  50. CHAN2G(2437, 5), /* Channel 6 */
  51. CHAN2G(2442, 6), /* Channel 7 */
  52. CHAN2G(2447, 7), /* Channel 8 */
  53. CHAN2G(2452, 8), /* Channel 9 */
  54. CHAN2G(2457, 9), /* Channel 10 */
  55. CHAN2G(2462, 10), /* Channel 11 */
  56. CHAN2G(2467, 11), /* Channel 12 */
  57. CHAN2G(2472, 12), /* Channel 13 */
  58. CHAN2G(2484, 13), /* Channel 14 */
  59. };
  60. static struct ieee80211_channel ath9k_5ghz_channels[] = {
  61. /* _We_ call this UNII 1 */
  62. CHAN5G(5180, 14), /* Channel 36 */
  63. CHAN5G(5200, 15), /* Channel 40 */
  64. CHAN5G(5220, 16), /* Channel 44 */
  65. CHAN5G(5240, 17), /* Channel 48 */
  66. /* _We_ call this UNII 2 */
  67. CHAN5G(5260, 18), /* Channel 52 */
  68. CHAN5G(5280, 19), /* Channel 56 */
  69. CHAN5G(5300, 20), /* Channel 60 */
  70. CHAN5G(5320, 21), /* Channel 64 */
  71. /* _We_ call this "Middle band" */
  72. CHAN5G(5500, 22), /* Channel 100 */
  73. CHAN5G(5520, 23), /* Channel 104 */
  74. CHAN5G(5540, 24), /* Channel 108 */
  75. CHAN5G(5560, 25), /* Channel 112 */
  76. CHAN5G(5580, 26), /* Channel 116 */
  77. CHAN5G(5600, 27), /* Channel 120 */
  78. CHAN5G(5620, 28), /* Channel 124 */
  79. CHAN5G(5640, 29), /* Channel 128 */
  80. CHAN5G(5660, 30), /* Channel 132 */
  81. CHAN5G(5680, 31), /* Channel 136 */
  82. CHAN5G(5700, 32), /* Channel 140 */
  83. /* _We_ call this UNII 3 */
  84. CHAN5G(5745, 33), /* Channel 149 */
  85. CHAN5G(5765, 34), /* Channel 153 */
  86. CHAN5G(5785, 35), /* Channel 157 */
  87. CHAN5G(5805, 36), /* Channel 161 */
  88. CHAN5G(5825, 37), /* Channel 165 */
  89. };
  90. /* Atheros hardware rate code addition for short premble */
  91. #define SHPCHECK(__hw_rate, __flags) \
  92. ((__flags & IEEE80211_RATE_SHORT_PREAMBLE) ? (__hw_rate | 0x04) : 0)
  93. #define RATE(_bitrate, _hw_rate, _flags) { \
  94. .bitrate = (_bitrate), \
  95. .flags = (_flags), \
  96. .hw_value = (_hw_rate), \
  97. .hw_value_short = (SHPCHECK(_hw_rate, _flags)) \
  98. }
  99. static struct ieee80211_rate ath9k_legacy_rates[] = {
  100. RATE(10, 0x1b, 0),
  101. RATE(20, 0x1a, IEEE80211_RATE_SHORT_PREAMBLE), /* shortp : 0x1e */
  102. RATE(55, 0x19, IEEE80211_RATE_SHORT_PREAMBLE), /* shortp: 0x1d */
  103. RATE(110, 0x18, IEEE80211_RATE_SHORT_PREAMBLE), /* short: 0x1c */
  104. RATE(60, 0x0b, 0),
  105. RATE(90, 0x0f, 0),
  106. RATE(120, 0x0a, 0),
  107. RATE(180, 0x0e, 0),
  108. RATE(240, 0x09, 0),
  109. RATE(360, 0x0d, 0),
  110. RATE(480, 0x08, 0),
  111. RATE(540, 0x0c, 0),
  112. };
  113. #ifdef CONFIG_MAC80211_LEDS
  114. static const struct ieee80211_tpt_blink ath9k_htc_tpt_blink[] = {
  115. { .throughput = 0 * 1024, .blink_time = 334 },
  116. { .throughput = 1 * 1024, .blink_time = 260 },
  117. { .throughput = 5 * 1024, .blink_time = 220 },
  118. { .throughput = 10 * 1024, .blink_time = 190 },
  119. { .throughput = 20 * 1024, .blink_time = 170 },
  120. { .throughput = 50 * 1024, .blink_time = 150 },
  121. { .throughput = 70 * 1024, .blink_time = 130 },
  122. { .throughput = 100 * 1024, .blink_time = 110 },
  123. { .throughput = 200 * 1024, .blink_time = 80 },
  124. { .throughput = 300 * 1024, .blink_time = 50 },
  125. };
  126. #endif
  127. static int ath9k_htc_wait_for_target(struct ath9k_htc_priv *priv)
  128. {
  129. int time_left;
  130. if (atomic_read(&priv->htc->tgt_ready) > 0) {
  131. atomic_dec(&priv->htc->tgt_ready);
  132. return 0;
  133. }
  134. /* Firmware can take up to 50ms to get ready, to be safe use 1 second */
  135. time_left = wait_for_completion_timeout(&priv->htc->target_wait, HZ);
  136. if (!time_left) {
  137. dev_err(priv->dev, "ath9k_htc: Target is unresponsive\n");
  138. return -ETIMEDOUT;
  139. }
  140. atomic_dec(&priv->htc->tgt_ready);
  141. return 0;
  142. }
  143. static void ath9k_deinit_priv(struct ath9k_htc_priv *priv)
  144. {
  145. ath9k_hw_deinit(priv->ah);
  146. kfree(priv->ah);
  147. priv->ah = NULL;
  148. }
  149. static void ath9k_deinit_device(struct ath9k_htc_priv *priv)
  150. {
  151. struct ieee80211_hw *hw = priv->hw;
  152. wiphy_rfkill_stop_polling(hw->wiphy);
  153. ath9k_deinit_leds(priv);
  154. ieee80211_unregister_hw(hw);
  155. ath9k_rx_cleanup(priv);
  156. ath9k_tx_cleanup(priv);
  157. ath9k_deinit_priv(priv);
  158. }
  159. static inline int ath9k_htc_connect_svc(struct ath9k_htc_priv *priv,
  160. u16 service_id,
  161. void (*tx) (void *,
  162. struct sk_buff *,
  163. enum htc_endpoint_id,
  164. bool txok),
  165. enum htc_endpoint_id *ep_id)
  166. {
  167. struct htc_service_connreq req;
  168. memset(&req, 0, sizeof(struct htc_service_connreq));
  169. req.service_id = service_id;
  170. req.ep_callbacks.priv = priv;
  171. req.ep_callbacks.rx = ath9k_htc_rxep;
  172. req.ep_callbacks.tx = tx;
  173. return htc_connect_service(priv->htc, &req, ep_id);
  174. }
  175. static int ath9k_init_htc_services(struct ath9k_htc_priv *priv, u16 devid,
  176. u32 drv_info)
  177. {
  178. int ret;
  179. /* WMI CMD*/
  180. ret = ath9k_wmi_connect(priv->htc, priv->wmi, &priv->wmi_cmd_ep);
  181. if (ret)
  182. goto err;
  183. /* Beacon */
  184. ret = ath9k_htc_connect_svc(priv, WMI_BEACON_SVC, ath9k_htc_beaconep,
  185. &priv->beacon_ep);
  186. if (ret)
  187. goto err;
  188. /* CAB */
  189. ret = ath9k_htc_connect_svc(priv, WMI_CAB_SVC, ath9k_htc_txep,
  190. &priv->cab_ep);
  191. if (ret)
  192. goto err;
  193. /* UAPSD */
  194. ret = ath9k_htc_connect_svc(priv, WMI_UAPSD_SVC, ath9k_htc_txep,
  195. &priv->uapsd_ep);
  196. if (ret)
  197. goto err;
  198. /* MGMT */
  199. ret = ath9k_htc_connect_svc(priv, WMI_MGMT_SVC, ath9k_htc_txep,
  200. &priv->mgmt_ep);
  201. if (ret)
  202. goto err;
  203. /* DATA BE */
  204. ret = ath9k_htc_connect_svc(priv, WMI_DATA_BE_SVC, ath9k_htc_txep,
  205. &priv->data_be_ep);
  206. if (ret)
  207. goto err;
  208. /* DATA BK */
  209. ret = ath9k_htc_connect_svc(priv, WMI_DATA_BK_SVC, ath9k_htc_txep,
  210. &priv->data_bk_ep);
  211. if (ret)
  212. goto err;
  213. /* DATA VI */
  214. ret = ath9k_htc_connect_svc(priv, WMI_DATA_VI_SVC, ath9k_htc_txep,
  215. &priv->data_vi_ep);
  216. if (ret)
  217. goto err;
  218. /* DATA VO */
  219. ret = ath9k_htc_connect_svc(priv, WMI_DATA_VO_SVC, ath9k_htc_txep,
  220. &priv->data_vo_ep);
  221. if (ret)
  222. goto err;
  223. /*
  224. * Setup required credits before initializing HTC.
  225. * This is a bit hacky, but, since queuing is done in
  226. * the HIF layer, shouldn't matter much.
  227. */
  228. if (IS_AR7010_DEVICE(drv_info))
  229. priv->htc->credits = 45;
  230. else
  231. priv->htc->credits = 33;
  232. ret = htc_init(priv->htc);
  233. if (ret)
  234. goto err;
  235. dev_info(priv->dev, "ath9k_htc: HTC initialized with %d credits\n",
  236. priv->htc->credits);
  237. return 0;
  238. err:
  239. dev_err(priv->dev, "ath9k_htc: Unable to initialize HTC services\n");
  240. return ret;
  241. }
  242. static void ath9k_reg_notifier(struct wiphy *wiphy,
  243. struct regulatory_request *request)
  244. {
  245. struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
  246. struct ath9k_htc_priv *priv = hw->priv;
  247. ath_reg_notifier_apply(wiphy, request,
  248. ath9k_hw_regulatory(priv->ah));
  249. }
  250. static unsigned int ath9k_regread(void *hw_priv, u32 reg_offset)
  251. {
  252. struct ath_hw *ah = (struct ath_hw *) hw_priv;
  253. struct ath_common *common = ath9k_hw_common(ah);
  254. struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
  255. __be32 val, reg = cpu_to_be32(reg_offset);
  256. int r;
  257. r = ath9k_wmi_cmd(priv->wmi, WMI_REG_READ_CMDID,
  258. (u8 *) &reg, sizeof(reg),
  259. (u8 *) &val, sizeof(val),
  260. 100);
  261. if (unlikely(r)) {
  262. ath_dbg(common, WMI, "REGISTER READ FAILED: (0x%04x, %d)\n",
  263. reg_offset, r);
  264. return -EIO;
  265. }
  266. return be32_to_cpu(val);
  267. }
  268. static void ath9k_multi_regread(void *hw_priv, u32 *addr,
  269. u32 *val, u16 count)
  270. {
  271. struct ath_hw *ah = (struct ath_hw *) hw_priv;
  272. struct ath_common *common = ath9k_hw_common(ah);
  273. struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
  274. __be32 tmpaddr[8];
  275. __be32 tmpval[8];
  276. int i, ret;
  277. for (i = 0; i < count; i++) {
  278. tmpaddr[i] = cpu_to_be32(addr[i]);
  279. }
  280. ret = ath9k_wmi_cmd(priv->wmi, WMI_REG_READ_CMDID,
  281. (u8 *)tmpaddr , sizeof(u32) * count,
  282. (u8 *)tmpval, sizeof(u32) * count,
  283. 100);
  284. if (unlikely(ret)) {
  285. ath_dbg(common, WMI,
  286. "Multiple REGISTER READ FAILED (count: %d)\n", count);
  287. }
  288. for (i = 0; i < count; i++) {
  289. val[i] = be32_to_cpu(tmpval[i]);
  290. }
  291. }
  292. static void ath9k_regwrite_single(void *hw_priv, u32 val, u32 reg_offset)
  293. {
  294. struct ath_hw *ah = (struct ath_hw *) hw_priv;
  295. struct ath_common *common = ath9k_hw_common(ah);
  296. struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
  297. const __be32 buf[2] = {
  298. cpu_to_be32(reg_offset),
  299. cpu_to_be32(val),
  300. };
  301. int r;
  302. r = ath9k_wmi_cmd(priv->wmi, WMI_REG_WRITE_CMDID,
  303. (u8 *) &buf, sizeof(buf),
  304. (u8 *) &val, sizeof(val),
  305. 100);
  306. if (unlikely(r)) {
  307. ath_dbg(common, WMI, "REGISTER WRITE FAILED:(0x%04x, %d)\n",
  308. reg_offset, r);
  309. }
  310. }
  311. static void ath9k_regwrite_buffer(void *hw_priv, u32 val, u32 reg_offset)
  312. {
  313. struct ath_hw *ah = (struct ath_hw *) hw_priv;
  314. struct ath_common *common = ath9k_hw_common(ah);
  315. struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
  316. u32 rsp_status;
  317. int r;
  318. mutex_lock(&priv->wmi->multi_write_mutex);
  319. /* Store the register/value */
  320. priv->wmi->multi_write[priv->wmi->multi_write_idx].reg =
  321. cpu_to_be32(reg_offset);
  322. priv->wmi->multi_write[priv->wmi->multi_write_idx].val =
  323. cpu_to_be32(val);
  324. priv->wmi->multi_write_idx++;
  325. /* If the buffer is full, send it out. */
  326. if (priv->wmi->multi_write_idx == MAX_CMD_NUMBER) {
  327. r = ath9k_wmi_cmd(priv->wmi, WMI_REG_WRITE_CMDID,
  328. (u8 *) &priv->wmi->multi_write,
  329. sizeof(struct register_write) * priv->wmi->multi_write_idx,
  330. (u8 *) &rsp_status, sizeof(rsp_status),
  331. 100);
  332. if (unlikely(r)) {
  333. ath_dbg(common, WMI,
  334. "REGISTER WRITE FAILED, multi len: %d\n",
  335. priv->wmi->multi_write_idx);
  336. }
  337. priv->wmi->multi_write_idx = 0;
  338. }
  339. mutex_unlock(&priv->wmi->multi_write_mutex);
  340. }
  341. static void ath9k_regwrite(void *hw_priv, u32 val, u32 reg_offset)
  342. {
  343. struct ath_hw *ah = (struct ath_hw *) hw_priv;
  344. struct ath_common *common = ath9k_hw_common(ah);
  345. struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
  346. if (atomic_read(&priv->wmi->mwrite_cnt))
  347. ath9k_regwrite_buffer(hw_priv, val, reg_offset);
  348. else
  349. ath9k_regwrite_single(hw_priv, val, reg_offset);
  350. }
  351. static void ath9k_enable_regwrite_buffer(void *hw_priv)
  352. {
  353. struct ath_hw *ah = (struct ath_hw *) hw_priv;
  354. struct ath_common *common = ath9k_hw_common(ah);
  355. struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
  356. atomic_inc(&priv->wmi->mwrite_cnt);
  357. }
  358. static void ath9k_regwrite_flush(void *hw_priv)
  359. {
  360. struct ath_hw *ah = (struct ath_hw *) hw_priv;
  361. struct ath_common *common = ath9k_hw_common(ah);
  362. struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
  363. u32 rsp_status;
  364. int r;
  365. atomic_dec(&priv->wmi->mwrite_cnt);
  366. mutex_lock(&priv->wmi->multi_write_mutex);
  367. if (priv->wmi->multi_write_idx) {
  368. r = ath9k_wmi_cmd(priv->wmi, WMI_REG_WRITE_CMDID,
  369. (u8 *) &priv->wmi->multi_write,
  370. sizeof(struct register_write) * priv->wmi->multi_write_idx,
  371. (u8 *) &rsp_status, sizeof(rsp_status),
  372. 100);
  373. if (unlikely(r)) {
  374. ath_dbg(common, WMI,
  375. "REGISTER WRITE FAILED, multi len: %d\n",
  376. priv->wmi->multi_write_idx);
  377. }
  378. priv->wmi->multi_write_idx = 0;
  379. }
  380. mutex_unlock(&priv->wmi->multi_write_mutex);
  381. }
  382. static u32 ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr)
  383. {
  384. u32 val;
  385. val = ath9k_regread(hw_priv, reg_offset);
  386. val &= ~clr;
  387. val |= set;
  388. ath9k_regwrite(hw_priv, val, reg_offset);
  389. return val;
  390. }
  391. static void ath_usb_read_cachesize(struct ath_common *common, int *csz)
  392. {
  393. *csz = L1_CACHE_BYTES >> 2;
  394. }
  395. static bool ath_usb_eeprom_read(struct ath_common *common, u32 off, u16 *data)
  396. {
  397. struct ath_hw *ah = (struct ath_hw *) common->ah;
  398. (void)REG_READ(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S));
  399. if (!ath9k_hw_wait(ah,
  400. AR_EEPROM_STATUS_DATA,
  401. AR_EEPROM_STATUS_DATA_BUSY |
  402. AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0,
  403. AH_WAIT_TIMEOUT))
  404. return false;
  405. *data = MS(REG_READ(ah, AR_EEPROM_STATUS_DATA),
  406. AR_EEPROM_STATUS_DATA_VAL);
  407. return true;
  408. }
  409. static const struct ath_bus_ops ath9k_usb_bus_ops = {
  410. .ath_bus_type = ATH_USB,
  411. .read_cachesize = ath_usb_read_cachesize,
  412. .eeprom_read = ath_usb_eeprom_read,
  413. };
  414. static void setup_ht_cap(struct ath9k_htc_priv *priv,
  415. struct ieee80211_sta_ht_cap *ht_info)
  416. {
  417. struct ath_common *common = ath9k_hw_common(priv->ah);
  418. u8 tx_streams, rx_streams;
  419. int i;
  420. ht_info->ht_supported = true;
  421. ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
  422. IEEE80211_HT_CAP_SM_PS |
  423. IEEE80211_HT_CAP_SGI_40 |
  424. IEEE80211_HT_CAP_DSSSCCK40;
  425. if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_SGI_20)
  426. ht_info->cap |= IEEE80211_HT_CAP_SGI_20;
  427. ht_info->cap |= (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT);
  428. ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
  429. ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
  430. memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
  431. /* ath9k_htc supports only 1 or 2 stream devices */
  432. tx_streams = ath9k_cmn_count_streams(priv->ah->txchainmask, 2);
  433. rx_streams = ath9k_cmn_count_streams(priv->ah->rxchainmask, 2);
  434. ath_dbg(common, CONFIG, "TX streams %d, RX streams: %d\n",
  435. tx_streams, rx_streams);
  436. if (tx_streams >= 2)
  437. ht_info->cap |= IEEE80211_HT_CAP_TX_STBC;
  438. if (tx_streams != rx_streams) {
  439. ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
  440. ht_info->mcs.tx_params |= ((tx_streams - 1) <<
  441. IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
  442. }
  443. for (i = 0; i < rx_streams; i++)
  444. ht_info->mcs.rx_mask[i] = 0xff;
  445. ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED;
  446. }
  447. static int ath9k_init_queues(struct ath9k_htc_priv *priv)
  448. {
  449. struct ath_common *common = ath9k_hw_common(priv->ah);
  450. int i;
  451. for (i = 0; i < ARRAY_SIZE(priv->hwq_map); i++)
  452. priv->hwq_map[i] = -1;
  453. priv->beaconq = ath9k_hw_beaconq_setup(priv->ah);
  454. if (priv->beaconq == -1) {
  455. ath_err(common, "Unable to setup BEACON xmit queue\n");
  456. goto err;
  457. }
  458. priv->cabq = ath9k_htc_cabq_setup(priv);
  459. if (priv->cabq == -1) {
  460. ath_err(common, "Unable to setup CAB xmit queue\n");
  461. goto err;
  462. }
  463. if (!ath9k_htc_txq_setup(priv, IEEE80211_AC_BE)) {
  464. ath_err(common, "Unable to setup xmit queue for BE traffic\n");
  465. goto err;
  466. }
  467. if (!ath9k_htc_txq_setup(priv, IEEE80211_AC_BK)) {
  468. ath_err(common, "Unable to setup xmit queue for BK traffic\n");
  469. goto err;
  470. }
  471. if (!ath9k_htc_txq_setup(priv, IEEE80211_AC_VI)) {
  472. ath_err(common, "Unable to setup xmit queue for VI traffic\n");
  473. goto err;
  474. }
  475. if (!ath9k_htc_txq_setup(priv, IEEE80211_AC_VO)) {
  476. ath_err(common, "Unable to setup xmit queue for VO traffic\n");
  477. goto err;
  478. }
  479. return 0;
  480. err:
  481. return -EINVAL;
  482. }
  483. static void ath9k_init_channels_rates(struct ath9k_htc_priv *priv)
  484. {
  485. if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) {
  486. priv->sbands[IEEE80211_BAND_2GHZ].channels =
  487. ath9k_2ghz_channels;
  488. priv->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
  489. priv->sbands[IEEE80211_BAND_2GHZ].n_channels =
  490. ARRAY_SIZE(ath9k_2ghz_channels);
  491. priv->sbands[IEEE80211_BAND_2GHZ].bitrates = ath9k_legacy_rates;
  492. priv->sbands[IEEE80211_BAND_2GHZ].n_bitrates =
  493. ARRAY_SIZE(ath9k_legacy_rates);
  494. }
  495. if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) {
  496. priv->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_channels;
  497. priv->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
  498. priv->sbands[IEEE80211_BAND_5GHZ].n_channels =
  499. ARRAY_SIZE(ath9k_5ghz_channels);
  500. priv->sbands[IEEE80211_BAND_5GHZ].bitrates =
  501. ath9k_legacy_rates + 4;
  502. priv->sbands[IEEE80211_BAND_5GHZ].n_bitrates =
  503. ARRAY_SIZE(ath9k_legacy_rates) - 4;
  504. }
  505. }
  506. static void ath9k_init_misc(struct ath9k_htc_priv *priv)
  507. {
  508. struct ath_common *common = ath9k_hw_common(priv->ah);
  509. memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN);
  510. priv->ah->opmode = NL80211_IFTYPE_STATION;
  511. }
  512. static int ath9k_init_priv(struct ath9k_htc_priv *priv,
  513. u16 devid, char *product,
  514. u32 drv_info)
  515. {
  516. struct ath_hw *ah = NULL;
  517. struct ath_common *common;
  518. int i, ret = 0, csz = 0;
  519. set_bit(OP_INVALID, &priv->op_flags);
  520. ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
  521. if (!ah)
  522. return -ENOMEM;
  523. ah->hw_version.devid = devid;
  524. ah->hw_version.usbdev = drv_info;
  525. ah->ah_flags |= AH_USE_EEPROM;
  526. ah->reg_ops.read = ath9k_regread;
  527. ah->reg_ops.multi_read = ath9k_multi_regread;
  528. ah->reg_ops.write = ath9k_regwrite;
  529. ah->reg_ops.enable_write_buffer = ath9k_enable_regwrite_buffer;
  530. ah->reg_ops.write_flush = ath9k_regwrite_flush;
  531. ah->reg_ops.rmw = ath9k_reg_rmw;
  532. priv->ah = ah;
  533. common = ath9k_hw_common(ah);
  534. common->ops = &ah->reg_ops;
  535. common->bus_ops = &ath9k_usb_bus_ops;
  536. common->ah = ah;
  537. common->hw = priv->hw;
  538. common->priv = priv;
  539. common->debug_mask = ath9k_debug;
  540. common->btcoex_enabled = ath9k_htc_btcoex_enable == 1;
  541. spin_lock_init(&priv->beacon_lock);
  542. spin_lock_init(&priv->tx.tx_lock);
  543. mutex_init(&priv->mutex);
  544. mutex_init(&priv->htc_pm_lock);
  545. tasklet_init(&priv->rx_tasklet, ath9k_rx_tasklet,
  546. (unsigned long)priv);
  547. tasklet_init(&priv->tx_failed_tasklet, ath9k_tx_failed_tasklet,
  548. (unsigned long)priv);
  549. INIT_DELAYED_WORK(&priv->ani_work, ath9k_htc_ani_work);
  550. INIT_WORK(&priv->ps_work, ath9k_ps_work);
  551. INIT_WORK(&priv->fatal_work, ath9k_fatal_work);
  552. setup_timer(&priv->tx.cleanup_timer, ath9k_htc_tx_cleanup_timer,
  553. (unsigned long)priv);
  554. /*
  555. * Cache line size is used to size and align various
  556. * structures used to communicate with the hardware.
  557. */
  558. ath_read_cachesize(common, &csz);
  559. common->cachelsz = csz << 2; /* convert to bytes */
  560. ret = ath9k_hw_init(ah);
  561. if (ret) {
  562. ath_err(common,
  563. "Unable to initialize hardware; initialization status: %d\n",
  564. ret);
  565. goto err_hw;
  566. }
  567. ret = ath9k_init_queues(priv);
  568. if (ret)
  569. goto err_queues;
  570. for (i = 0; i < ATH9K_HTC_MAX_BCN_VIF; i++)
  571. priv->cur_beacon_conf.bslot[i] = NULL;
  572. ath9k_cmn_init_crypto(ah);
  573. ath9k_init_channels_rates(priv);
  574. ath9k_init_misc(priv);
  575. ath9k_htc_init_btcoex(priv, product);
  576. return 0;
  577. err_queues:
  578. ath9k_hw_deinit(ah);
  579. err_hw:
  580. kfree(ah);
  581. priv->ah = NULL;
  582. return ret;
  583. }
  584. static const struct ieee80211_iface_limit if_limits[] = {
  585. { .max = 2, .types = BIT(NL80211_IFTYPE_STATION) |
  586. BIT(NL80211_IFTYPE_P2P_CLIENT) },
  587. { .max = 2, .types = BIT(NL80211_IFTYPE_AP) |
  588. #ifdef CONFIG_MAC80211_MESH
  589. BIT(NL80211_IFTYPE_MESH_POINT) |
  590. #endif
  591. BIT(NL80211_IFTYPE_P2P_GO) },
  592. };
  593. static const struct ieee80211_iface_combination if_comb = {
  594. .limits = if_limits,
  595. .n_limits = ARRAY_SIZE(if_limits),
  596. .max_interfaces = 2,
  597. .num_different_channels = 1,
  598. };
  599. static void ath9k_set_hw_capab(struct ath9k_htc_priv *priv,
  600. struct ieee80211_hw *hw)
  601. {
  602. struct ath_common *common = ath9k_hw_common(priv->ah);
  603. struct base_eep_header *pBase;
  604. hw->flags = IEEE80211_HW_SIGNAL_DBM |
  605. IEEE80211_HW_AMPDU_AGGREGATION |
  606. IEEE80211_HW_SPECTRUM_MGMT |
  607. IEEE80211_HW_HAS_RATE_CONTROL |
  608. IEEE80211_HW_RX_INCLUDES_FCS |
  609. IEEE80211_HW_PS_NULLFUNC_STACK |
  610. IEEE80211_HW_REPORTS_TX_ACK_STATUS |
  611. IEEE80211_HW_MFP_CAPABLE |
  612. IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
  613. if (ath9k_ps_enable)
  614. hw->flags |= IEEE80211_HW_SUPPORTS_PS;
  615. hw->wiphy->interface_modes =
  616. BIT(NL80211_IFTYPE_STATION) |
  617. BIT(NL80211_IFTYPE_ADHOC) |
  618. BIT(NL80211_IFTYPE_AP) |
  619. BIT(NL80211_IFTYPE_P2P_GO) |
  620. BIT(NL80211_IFTYPE_P2P_CLIENT) |
  621. BIT(NL80211_IFTYPE_MESH_POINT);
  622. hw->wiphy->iface_combinations = &if_comb;
  623. hw->wiphy->n_iface_combinations = 1;
  624. hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
  625. hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN |
  626. WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL;
  627. hw->queues = 4;
  628. hw->max_listen_interval = 1;
  629. hw->vif_data_size = sizeof(struct ath9k_htc_vif);
  630. hw->sta_data_size = sizeof(struct ath9k_htc_sta);
  631. /* tx_frame_hdr is larger than tx_mgmt_hdr anyway */
  632. hw->extra_tx_headroom = sizeof(struct tx_frame_hdr) +
  633. sizeof(struct htc_frame_hdr) + 4;
  634. if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
  635. hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
  636. &priv->sbands[IEEE80211_BAND_2GHZ];
  637. if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
  638. hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
  639. &priv->sbands[IEEE80211_BAND_5GHZ];
  640. if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
  641. if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
  642. setup_ht_cap(priv,
  643. &priv->sbands[IEEE80211_BAND_2GHZ].ht_cap);
  644. if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
  645. setup_ht_cap(priv,
  646. &priv->sbands[IEEE80211_BAND_5GHZ].ht_cap);
  647. }
  648. pBase = ath9k_htc_get_eeprom_base(priv);
  649. if (pBase) {
  650. hw->wiphy->available_antennas_rx = pBase->rxMask;
  651. hw->wiphy->available_antennas_tx = pBase->txMask;
  652. }
  653. SET_IEEE80211_PERM_ADDR(hw, common->macaddr);
  654. }
  655. static int ath9k_init_firmware_version(struct ath9k_htc_priv *priv)
  656. {
  657. struct ieee80211_hw *hw = priv->hw;
  658. struct wmi_fw_version cmd_rsp;
  659. int ret;
  660. memset(&cmd_rsp, 0, sizeof(cmd_rsp));
  661. WMI_CMD(WMI_GET_FW_VERSION);
  662. if (ret)
  663. return -EINVAL;
  664. priv->fw_version_major = be16_to_cpu(cmd_rsp.major);
  665. priv->fw_version_minor = be16_to_cpu(cmd_rsp.minor);
  666. snprintf(hw->wiphy->fw_version, sizeof(hw->wiphy->fw_version), "%d.%d",
  667. priv->fw_version_major,
  668. priv->fw_version_minor);
  669. dev_info(priv->dev, "ath9k_htc: FW Version: %d.%d\n",
  670. priv->fw_version_major,
  671. priv->fw_version_minor);
  672. /*
  673. * Check if the available FW matches the driver's
  674. * required version.
  675. */
  676. if (priv->fw_version_major != MAJOR_VERSION_REQ ||
  677. priv->fw_version_minor < MINOR_VERSION_REQ) {
  678. dev_err(priv->dev, "ath9k_htc: Please upgrade to FW version %d.%d\n",
  679. MAJOR_VERSION_REQ, MINOR_VERSION_REQ);
  680. return -EINVAL;
  681. }
  682. return 0;
  683. }
  684. static int ath9k_init_device(struct ath9k_htc_priv *priv,
  685. u16 devid, char *product, u32 drv_info)
  686. {
  687. struct ieee80211_hw *hw = priv->hw;
  688. struct ath_common *common;
  689. struct ath_hw *ah;
  690. int error = 0;
  691. struct ath_regulatory *reg;
  692. char hw_name[64];
  693. /* Bring up device */
  694. error = ath9k_init_priv(priv, devid, product, drv_info);
  695. if (error != 0)
  696. goto err_init;
  697. ah = priv->ah;
  698. common = ath9k_hw_common(ah);
  699. ath9k_set_hw_capab(priv, hw);
  700. error = ath9k_init_firmware_version(priv);
  701. if (error != 0)
  702. goto err_fw;
  703. /* Initialize regulatory */
  704. error = ath_regd_init(&common->regulatory, priv->hw->wiphy,
  705. ath9k_reg_notifier);
  706. if (error)
  707. goto err_regd;
  708. reg = &common->regulatory;
  709. /* Setup TX */
  710. error = ath9k_tx_init(priv);
  711. if (error != 0)
  712. goto err_tx;
  713. /* Setup RX */
  714. error = ath9k_rx_init(priv);
  715. if (error != 0)
  716. goto err_rx;
  717. ath9k_hw_disable(priv->ah);
  718. #ifdef CONFIG_MAC80211_LEDS
  719. /* must be initialized before ieee80211_register_hw */
  720. priv->led_cdev.default_trigger = ieee80211_create_tpt_led_trigger(priv->hw,
  721. IEEE80211_TPT_LEDTRIG_FL_RADIO, ath9k_htc_tpt_blink,
  722. ARRAY_SIZE(ath9k_htc_tpt_blink));
  723. #endif
  724. /* Register with mac80211 */
  725. error = ieee80211_register_hw(hw);
  726. if (error)
  727. goto err_register;
  728. /* Handle world regulatory */
  729. if (!ath_is_world_regd(reg)) {
  730. error = regulatory_hint(hw->wiphy, reg->alpha2);
  731. if (error)
  732. goto err_world;
  733. }
  734. error = ath9k_htc_init_debug(priv->ah);
  735. if (error) {
  736. ath_err(common, "Unable to create debugfs files\n");
  737. goto err_world;
  738. }
  739. ath_dbg(common, CONFIG,
  740. "WMI:%d, BCN:%d, CAB:%d, UAPSD:%d, MGMT:%d, BE:%d, BK:%d, VI:%d, VO:%d\n",
  741. priv->wmi_cmd_ep,
  742. priv->beacon_ep,
  743. priv->cab_ep,
  744. priv->uapsd_ep,
  745. priv->mgmt_ep,
  746. priv->data_be_ep,
  747. priv->data_bk_ep,
  748. priv->data_vi_ep,
  749. priv->data_vo_ep);
  750. ath9k_hw_name(priv->ah, hw_name, sizeof(hw_name));
  751. wiphy_info(hw->wiphy, "%s\n", hw_name);
  752. ath9k_init_leds(priv);
  753. ath9k_start_rfkill_poll(priv);
  754. return 0;
  755. err_world:
  756. ieee80211_unregister_hw(hw);
  757. err_register:
  758. ath9k_rx_cleanup(priv);
  759. err_rx:
  760. ath9k_tx_cleanup(priv);
  761. err_tx:
  762. /* Nothing */
  763. err_regd:
  764. /* Nothing */
  765. err_fw:
  766. ath9k_deinit_priv(priv);
  767. err_init:
  768. return error;
  769. }
  770. int ath9k_htc_probe_device(struct htc_target *htc_handle, struct device *dev,
  771. u16 devid, char *product, u32 drv_info)
  772. {
  773. struct ieee80211_hw *hw;
  774. struct ath9k_htc_priv *priv;
  775. int ret;
  776. hw = ieee80211_alloc_hw(sizeof(struct ath9k_htc_priv), &ath9k_htc_ops);
  777. if (!hw)
  778. return -ENOMEM;
  779. priv = hw->priv;
  780. priv->hw = hw;
  781. priv->htc = htc_handle;
  782. priv->dev = dev;
  783. htc_handle->drv_priv = priv;
  784. SET_IEEE80211_DEV(hw, priv->dev);
  785. ret = ath9k_htc_wait_for_target(priv);
  786. if (ret)
  787. goto err_free;
  788. priv->wmi = ath9k_init_wmi(priv);
  789. if (!priv->wmi) {
  790. ret = -EINVAL;
  791. goto err_free;
  792. }
  793. ret = ath9k_init_htc_services(priv, devid, drv_info);
  794. if (ret)
  795. goto err_init;
  796. ret = ath9k_init_device(priv, devid, product, drv_info);
  797. if (ret)
  798. goto err_init;
  799. return 0;
  800. err_init:
  801. ath9k_deinit_wmi(priv);
  802. err_free:
  803. ieee80211_free_hw(hw);
  804. return ret;
  805. }
  806. void ath9k_htc_disconnect_device(struct htc_target *htc_handle, bool hotunplug)
  807. {
  808. if (htc_handle->drv_priv) {
  809. /* Check if the device has been yanked out. */
  810. if (hotunplug)
  811. htc_handle->drv_priv->ah->ah_flags |= AH_UNPLUGGED;
  812. ath9k_deinit_device(htc_handle->drv_priv);
  813. ath9k_deinit_wmi(htc_handle->drv_priv);
  814. ieee80211_free_hw(htc_handle->drv_priv->hw);
  815. }
  816. }
  817. #ifdef CONFIG_PM
  818. void ath9k_htc_suspend(struct htc_target *htc_handle)
  819. {
  820. ath9k_htc_setpower(htc_handle->drv_priv, ATH9K_PM_FULL_SLEEP);
  821. }
  822. int ath9k_htc_resume(struct htc_target *htc_handle)
  823. {
  824. struct ath9k_htc_priv *priv = htc_handle->drv_priv;
  825. int ret;
  826. ret = ath9k_htc_wait_for_target(priv);
  827. if (ret)
  828. return ret;
  829. ret = ath9k_init_htc_services(priv, priv->ah->hw_version.devid,
  830. priv->ah->hw_version.usbdev);
  831. ath9k_configure_leds(priv);
  832. return ret;
  833. }
  834. #endif
  835. static int __init ath9k_htc_init(void)
  836. {
  837. if (ath9k_hif_usb_init() < 0) {
  838. pr_err("No USB devices found, driver not installed\n");
  839. return -ENODEV;
  840. }
  841. return 0;
  842. }
  843. module_init(ath9k_htc_init);
  844. static void __exit ath9k_htc_exit(void)
  845. {
  846. ath9k_hif_usb_exit();
  847. pr_info("Driver unloaded\n");
  848. }
  849. module_exit(ath9k_htc_exit);