at86rf230.c 24 KB

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  1. /*
  2. * AT86RF230/RF231 driver
  3. *
  4. * Copyright (C) 2009-2012 Siemens AG
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2
  8. * as published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License along
  16. * with this program; if not, write to the Free Software Foundation, Inc.,
  17. * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  18. *
  19. * Written by:
  20. * Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
  21. * Alexander Smirnov <alex.bluesman.smirnov@gmail.com>
  22. */
  23. #include <linux/kernel.h>
  24. #include <linux/module.h>
  25. #include <linux/interrupt.h>
  26. #include <linux/gpio.h>
  27. #include <linux/delay.h>
  28. #include <linux/mutex.h>
  29. #include <linux/workqueue.h>
  30. #include <linux/spinlock.h>
  31. #include <linux/spi/spi.h>
  32. #include <linux/spi/at86rf230.h>
  33. #include <linux/skbuff.h>
  34. #include <net/mac802154.h>
  35. #include <net/wpan-phy.h>
  36. struct at86rf230_local {
  37. struct spi_device *spi;
  38. int rstn, slp_tr, dig2;
  39. u8 part;
  40. u8 vers;
  41. u8 buf[2];
  42. struct mutex bmux;
  43. struct work_struct irqwork;
  44. struct completion tx_complete;
  45. struct ieee802154_dev *dev;
  46. spinlock_t lock;
  47. bool irq_busy;
  48. bool is_tx;
  49. };
  50. #define RG_TRX_STATUS (0x01)
  51. #define SR_TRX_STATUS 0x01, 0x1f, 0
  52. #define SR_RESERVED_01_3 0x01, 0x20, 5
  53. #define SR_CCA_STATUS 0x01, 0x40, 6
  54. #define SR_CCA_DONE 0x01, 0x80, 7
  55. #define RG_TRX_STATE (0x02)
  56. #define SR_TRX_CMD 0x02, 0x1f, 0
  57. #define SR_TRAC_STATUS 0x02, 0xe0, 5
  58. #define RG_TRX_CTRL_0 (0x03)
  59. #define SR_CLKM_CTRL 0x03, 0x07, 0
  60. #define SR_CLKM_SHA_SEL 0x03, 0x08, 3
  61. #define SR_PAD_IO_CLKM 0x03, 0x30, 4
  62. #define SR_PAD_IO 0x03, 0xc0, 6
  63. #define RG_TRX_CTRL_1 (0x04)
  64. #define SR_IRQ_POLARITY 0x04, 0x01, 0
  65. #define SR_IRQ_MASK_MODE 0x04, 0x02, 1
  66. #define SR_SPI_CMD_MODE 0x04, 0x0c, 2
  67. #define SR_RX_BL_CTRL 0x04, 0x10, 4
  68. #define SR_TX_AUTO_CRC_ON 0x04, 0x20, 5
  69. #define SR_IRQ_2_EXT_EN 0x04, 0x40, 6
  70. #define SR_PA_EXT_EN 0x04, 0x80, 7
  71. #define RG_PHY_TX_PWR (0x05)
  72. #define SR_TX_PWR 0x05, 0x0f, 0
  73. #define SR_PA_LT 0x05, 0x30, 4
  74. #define SR_PA_BUF_LT 0x05, 0xc0, 6
  75. #define RG_PHY_RSSI (0x06)
  76. #define SR_RSSI 0x06, 0x1f, 0
  77. #define SR_RND_VALUE 0x06, 0x60, 5
  78. #define SR_RX_CRC_VALID 0x06, 0x80, 7
  79. #define RG_PHY_ED_LEVEL (0x07)
  80. #define SR_ED_LEVEL 0x07, 0xff, 0
  81. #define RG_PHY_CC_CCA (0x08)
  82. #define SR_CHANNEL 0x08, 0x1f, 0
  83. #define SR_CCA_MODE 0x08, 0x60, 5
  84. #define SR_CCA_REQUEST 0x08, 0x80, 7
  85. #define RG_CCA_THRES (0x09)
  86. #define SR_CCA_ED_THRES 0x09, 0x0f, 0
  87. #define SR_RESERVED_09_1 0x09, 0xf0, 4
  88. #define RG_RX_CTRL (0x0a)
  89. #define SR_PDT_THRES 0x0a, 0x0f, 0
  90. #define SR_RESERVED_0a_1 0x0a, 0xf0, 4
  91. #define RG_SFD_VALUE (0x0b)
  92. #define SR_SFD_VALUE 0x0b, 0xff, 0
  93. #define RG_TRX_CTRL_2 (0x0c)
  94. #define SR_OQPSK_DATA_RATE 0x0c, 0x03, 0
  95. #define SR_RESERVED_0c_2 0x0c, 0x7c, 2
  96. #define SR_RX_SAFE_MODE 0x0c, 0x80, 7
  97. #define RG_ANT_DIV (0x0d)
  98. #define SR_ANT_CTRL 0x0d, 0x03, 0
  99. #define SR_ANT_EXT_SW_EN 0x0d, 0x04, 2
  100. #define SR_ANT_DIV_EN 0x0d, 0x08, 3
  101. #define SR_RESERVED_0d_2 0x0d, 0x70, 4
  102. #define SR_ANT_SEL 0x0d, 0x80, 7
  103. #define RG_IRQ_MASK (0x0e)
  104. #define SR_IRQ_MASK 0x0e, 0xff, 0
  105. #define RG_IRQ_STATUS (0x0f)
  106. #define SR_IRQ_0_PLL_LOCK 0x0f, 0x01, 0
  107. #define SR_IRQ_1_PLL_UNLOCK 0x0f, 0x02, 1
  108. #define SR_IRQ_2_RX_START 0x0f, 0x04, 2
  109. #define SR_IRQ_3_TRX_END 0x0f, 0x08, 3
  110. #define SR_IRQ_4_CCA_ED_DONE 0x0f, 0x10, 4
  111. #define SR_IRQ_5_AMI 0x0f, 0x20, 5
  112. #define SR_IRQ_6_TRX_UR 0x0f, 0x40, 6
  113. #define SR_IRQ_7_BAT_LOW 0x0f, 0x80, 7
  114. #define RG_VREG_CTRL (0x10)
  115. #define SR_RESERVED_10_6 0x10, 0x03, 0
  116. #define SR_DVDD_OK 0x10, 0x04, 2
  117. #define SR_DVREG_EXT 0x10, 0x08, 3
  118. #define SR_RESERVED_10_3 0x10, 0x30, 4
  119. #define SR_AVDD_OK 0x10, 0x40, 6
  120. #define SR_AVREG_EXT 0x10, 0x80, 7
  121. #define RG_BATMON (0x11)
  122. #define SR_BATMON_VTH 0x11, 0x0f, 0
  123. #define SR_BATMON_HR 0x11, 0x10, 4
  124. #define SR_BATMON_OK 0x11, 0x20, 5
  125. #define SR_RESERVED_11_1 0x11, 0xc0, 6
  126. #define RG_XOSC_CTRL (0x12)
  127. #define SR_XTAL_TRIM 0x12, 0x0f, 0
  128. #define SR_XTAL_MODE 0x12, 0xf0, 4
  129. #define RG_RX_SYN (0x15)
  130. #define SR_RX_PDT_LEVEL 0x15, 0x0f, 0
  131. #define SR_RESERVED_15_2 0x15, 0x70, 4
  132. #define SR_RX_PDT_DIS 0x15, 0x80, 7
  133. #define RG_XAH_CTRL_1 (0x17)
  134. #define SR_RESERVED_17_8 0x17, 0x01, 0
  135. #define SR_AACK_PROM_MODE 0x17, 0x02, 1
  136. #define SR_AACK_ACK_TIME 0x17, 0x04, 2
  137. #define SR_RESERVED_17_5 0x17, 0x08, 3
  138. #define SR_AACK_UPLD_RES_FT 0x17, 0x10, 4
  139. #define SR_AACK_FLTR_RES_FT 0x17, 0x20, 5
  140. #define SR_RESERVED_17_2 0x17, 0x40, 6
  141. #define SR_RESERVED_17_1 0x17, 0x80, 7
  142. #define RG_FTN_CTRL (0x18)
  143. #define SR_RESERVED_18_2 0x18, 0x7f, 0
  144. #define SR_FTN_START 0x18, 0x80, 7
  145. #define RG_PLL_CF (0x1a)
  146. #define SR_RESERVED_1a_2 0x1a, 0x7f, 0
  147. #define SR_PLL_CF_START 0x1a, 0x80, 7
  148. #define RG_PLL_DCU (0x1b)
  149. #define SR_RESERVED_1b_3 0x1b, 0x3f, 0
  150. #define SR_RESERVED_1b_2 0x1b, 0x40, 6
  151. #define SR_PLL_DCU_START 0x1b, 0x80, 7
  152. #define RG_PART_NUM (0x1c)
  153. #define SR_PART_NUM 0x1c, 0xff, 0
  154. #define RG_VERSION_NUM (0x1d)
  155. #define SR_VERSION_NUM 0x1d, 0xff, 0
  156. #define RG_MAN_ID_0 (0x1e)
  157. #define SR_MAN_ID_0 0x1e, 0xff, 0
  158. #define RG_MAN_ID_1 (0x1f)
  159. #define SR_MAN_ID_1 0x1f, 0xff, 0
  160. #define RG_SHORT_ADDR_0 (0x20)
  161. #define SR_SHORT_ADDR_0 0x20, 0xff, 0
  162. #define RG_SHORT_ADDR_1 (0x21)
  163. #define SR_SHORT_ADDR_1 0x21, 0xff, 0
  164. #define RG_PAN_ID_0 (0x22)
  165. #define SR_PAN_ID_0 0x22, 0xff, 0
  166. #define RG_PAN_ID_1 (0x23)
  167. #define SR_PAN_ID_1 0x23, 0xff, 0
  168. #define RG_IEEE_ADDR_0 (0x24)
  169. #define SR_IEEE_ADDR_0 0x24, 0xff, 0
  170. #define RG_IEEE_ADDR_1 (0x25)
  171. #define SR_IEEE_ADDR_1 0x25, 0xff, 0
  172. #define RG_IEEE_ADDR_2 (0x26)
  173. #define SR_IEEE_ADDR_2 0x26, 0xff, 0
  174. #define RG_IEEE_ADDR_3 (0x27)
  175. #define SR_IEEE_ADDR_3 0x27, 0xff, 0
  176. #define RG_IEEE_ADDR_4 (0x28)
  177. #define SR_IEEE_ADDR_4 0x28, 0xff, 0
  178. #define RG_IEEE_ADDR_5 (0x29)
  179. #define SR_IEEE_ADDR_5 0x29, 0xff, 0
  180. #define RG_IEEE_ADDR_6 (0x2a)
  181. #define SR_IEEE_ADDR_6 0x2a, 0xff, 0
  182. #define RG_IEEE_ADDR_7 (0x2b)
  183. #define SR_IEEE_ADDR_7 0x2b, 0xff, 0
  184. #define RG_XAH_CTRL_0 (0x2c)
  185. #define SR_SLOTTED_OPERATION 0x2c, 0x01, 0
  186. #define SR_MAX_CSMA_RETRIES 0x2c, 0x0e, 1
  187. #define SR_MAX_FRAME_RETRIES 0x2c, 0xf0, 4
  188. #define RG_CSMA_SEED_0 (0x2d)
  189. #define SR_CSMA_SEED_0 0x2d, 0xff, 0
  190. #define RG_CSMA_SEED_1 (0x2e)
  191. #define SR_CSMA_SEED_1 0x2e, 0x07, 0
  192. #define SR_AACK_I_AM_COORD 0x2e, 0x08, 3
  193. #define SR_AACK_DIS_ACK 0x2e, 0x10, 4
  194. #define SR_AACK_SET_PD 0x2e, 0x20, 5
  195. #define SR_AACK_FVN_MODE 0x2e, 0xc0, 6
  196. #define RG_CSMA_BE (0x2f)
  197. #define SR_MIN_BE 0x2f, 0x0f, 0
  198. #define SR_MAX_BE 0x2f, 0xf0, 4
  199. #define CMD_REG 0x80
  200. #define CMD_REG_MASK 0x3f
  201. #define CMD_WRITE 0x40
  202. #define CMD_FB 0x20
  203. #define IRQ_BAT_LOW (1 << 7)
  204. #define IRQ_TRX_UR (1 << 6)
  205. #define IRQ_AMI (1 << 5)
  206. #define IRQ_CCA_ED (1 << 4)
  207. #define IRQ_TRX_END (1 << 3)
  208. #define IRQ_RX_START (1 << 2)
  209. #define IRQ_PLL_UNL (1 << 1)
  210. #define IRQ_PLL_LOCK (1 << 0)
  211. #define IRQ_ACTIVE_HIGH 0
  212. #define IRQ_ACTIVE_LOW 1
  213. #define STATE_P_ON 0x00 /* BUSY */
  214. #define STATE_BUSY_RX 0x01
  215. #define STATE_BUSY_TX 0x02
  216. #define STATE_FORCE_TRX_OFF 0x03
  217. #define STATE_FORCE_TX_ON 0x04 /* IDLE */
  218. /* 0x05 */ /* INVALID_PARAMETER */
  219. #define STATE_RX_ON 0x06
  220. /* 0x07 */ /* SUCCESS */
  221. #define STATE_TRX_OFF 0x08
  222. #define STATE_TX_ON 0x09
  223. /* 0x0a - 0x0e */ /* 0x0a - UNSUPPORTED_ATTRIBUTE */
  224. #define STATE_SLEEP 0x0F
  225. #define STATE_BUSY_RX_AACK 0x11
  226. #define STATE_BUSY_TX_ARET 0x12
  227. #define STATE_RX_AACK_ON 0x16
  228. #define STATE_TX_ARET_ON 0x19
  229. #define STATE_RX_ON_NOCLK 0x1C
  230. #define STATE_RX_AACK_ON_NOCLK 0x1D
  231. #define STATE_BUSY_RX_AACK_NOCLK 0x1E
  232. #define STATE_TRANSITION_IN_PROGRESS 0x1F
  233. static int
  234. __at86rf230_write(struct at86rf230_local *lp, u8 addr, u8 data)
  235. {
  236. u8 *buf = lp->buf;
  237. int status;
  238. struct spi_message msg;
  239. struct spi_transfer xfer = {
  240. .len = 2,
  241. .tx_buf = buf,
  242. };
  243. buf[0] = (addr & CMD_REG_MASK) | CMD_REG | CMD_WRITE;
  244. buf[1] = data;
  245. dev_vdbg(&lp->spi->dev, "buf[0] = %02x\n", buf[0]);
  246. dev_vdbg(&lp->spi->dev, "buf[1] = %02x\n", buf[1]);
  247. spi_message_init(&msg);
  248. spi_message_add_tail(&xfer, &msg);
  249. status = spi_sync(lp->spi, &msg);
  250. dev_vdbg(&lp->spi->dev, "status = %d\n", status);
  251. if (msg.status)
  252. status = msg.status;
  253. dev_vdbg(&lp->spi->dev, "status = %d\n", status);
  254. dev_vdbg(&lp->spi->dev, "buf[0] = %02x\n", buf[0]);
  255. dev_vdbg(&lp->spi->dev, "buf[1] = %02x\n", buf[1]);
  256. return status;
  257. }
  258. static int
  259. __at86rf230_read_subreg(struct at86rf230_local *lp,
  260. u8 addr, u8 mask, int shift, u8 *data)
  261. {
  262. u8 *buf = lp->buf;
  263. int status;
  264. struct spi_message msg;
  265. struct spi_transfer xfer = {
  266. .len = 2,
  267. .tx_buf = buf,
  268. .rx_buf = buf,
  269. };
  270. buf[0] = (addr & CMD_REG_MASK) | CMD_REG;
  271. buf[1] = 0xff;
  272. dev_vdbg(&lp->spi->dev, "buf[0] = %02x\n", buf[0]);
  273. spi_message_init(&msg);
  274. spi_message_add_tail(&xfer, &msg);
  275. status = spi_sync(lp->spi, &msg);
  276. dev_vdbg(&lp->spi->dev, "status = %d\n", status);
  277. if (msg.status)
  278. status = msg.status;
  279. dev_vdbg(&lp->spi->dev, "status = %d\n", status);
  280. dev_vdbg(&lp->spi->dev, "buf[0] = %02x\n", buf[0]);
  281. dev_vdbg(&lp->spi->dev, "buf[1] = %02x\n", buf[1]);
  282. if (status == 0)
  283. *data = buf[1];
  284. return status;
  285. }
  286. static int
  287. at86rf230_read_subreg(struct at86rf230_local *lp,
  288. u8 addr, u8 mask, int shift, u8 *data)
  289. {
  290. int status;
  291. mutex_lock(&lp->bmux);
  292. status = __at86rf230_read_subreg(lp, addr, mask, shift, data);
  293. mutex_unlock(&lp->bmux);
  294. return status;
  295. }
  296. static int
  297. at86rf230_write_subreg(struct at86rf230_local *lp,
  298. u8 addr, u8 mask, int shift, u8 data)
  299. {
  300. int status;
  301. u8 val;
  302. mutex_lock(&lp->bmux);
  303. status = __at86rf230_read_subreg(lp, addr, 0xff, 0, &val);
  304. if (status)
  305. goto out;
  306. val &= ~mask;
  307. val |= (data << shift) & mask;
  308. status = __at86rf230_write(lp, addr, val);
  309. out:
  310. mutex_unlock(&lp->bmux);
  311. return status;
  312. }
  313. static int
  314. at86rf230_write_fbuf(struct at86rf230_local *lp, u8 *data, u8 len)
  315. {
  316. u8 *buf = lp->buf;
  317. int status;
  318. struct spi_message msg;
  319. struct spi_transfer xfer_head = {
  320. .len = 2,
  321. .tx_buf = buf,
  322. };
  323. struct spi_transfer xfer_buf = {
  324. .len = len,
  325. .tx_buf = data,
  326. };
  327. mutex_lock(&lp->bmux);
  328. buf[0] = CMD_WRITE | CMD_FB;
  329. buf[1] = len + 2; /* 2 bytes for CRC that isn't written */
  330. dev_vdbg(&lp->spi->dev, "buf[0] = %02x\n", buf[0]);
  331. dev_vdbg(&lp->spi->dev, "buf[1] = %02x\n", buf[1]);
  332. spi_message_init(&msg);
  333. spi_message_add_tail(&xfer_head, &msg);
  334. spi_message_add_tail(&xfer_buf, &msg);
  335. status = spi_sync(lp->spi, &msg);
  336. dev_vdbg(&lp->spi->dev, "status = %d\n", status);
  337. if (msg.status)
  338. status = msg.status;
  339. dev_vdbg(&lp->spi->dev, "status = %d\n", status);
  340. dev_vdbg(&lp->spi->dev, "buf[0] = %02x\n", buf[0]);
  341. dev_vdbg(&lp->spi->dev, "buf[1] = %02x\n", buf[1]);
  342. mutex_unlock(&lp->bmux);
  343. return status;
  344. }
  345. static int
  346. at86rf230_read_fbuf(struct at86rf230_local *lp, u8 *data, u8 *len, u8 *lqi)
  347. {
  348. u8 *buf = lp->buf;
  349. int status;
  350. struct spi_message msg;
  351. struct spi_transfer xfer_head = {
  352. .len = 2,
  353. .tx_buf = buf,
  354. .rx_buf = buf,
  355. };
  356. struct spi_transfer xfer_head1 = {
  357. .len = 2,
  358. .tx_buf = buf,
  359. .rx_buf = buf,
  360. };
  361. struct spi_transfer xfer_buf = {
  362. .len = 0,
  363. .rx_buf = data,
  364. };
  365. mutex_lock(&lp->bmux);
  366. buf[0] = CMD_FB;
  367. buf[1] = 0x00;
  368. spi_message_init(&msg);
  369. spi_message_add_tail(&xfer_head, &msg);
  370. status = spi_sync(lp->spi, &msg);
  371. dev_vdbg(&lp->spi->dev, "status = %d\n", status);
  372. xfer_buf.len = *(buf + 1) + 1;
  373. *len = buf[1];
  374. buf[0] = CMD_FB;
  375. buf[1] = 0x00;
  376. spi_message_init(&msg);
  377. spi_message_add_tail(&xfer_head1, &msg);
  378. spi_message_add_tail(&xfer_buf, &msg);
  379. status = spi_sync(lp->spi, &msg);
  380. if (msg.status)
  381. status = msg.status;
  382. dev_vdbg(&lp->spi->dev, "status = %d\n", status);
  383. dev_vdbg(&lp->spi->dev, "buf[0] = %02x\n", buf[0]);
  384. dev_vdbg(&lp->spi->dev, "buf[1] = %02x\n", buf[1]);
  385. if (status) {
  386. if (lqi && (*len > lp->buf[1]))
  387. *lqi = data[lp->buf[1]];
  388. }
  389. mutex_unlock(&lp->bmux);
  390. return status;
  391. }
  392. static int
  393. at86rf230_ed(struct ieee802154_dev *dev, u8 *level)
  394. {
  395. might_sleep();
  396. BUG_ON(!level);
  397. *level = 0xbe;
  398. return 0;
  399. }
  400. static int
  401. at86rf230_state(struct ieee802154_dev *dev, int state)
  402. {
  403. struct at86rf230_local *lp = dev->priv;
  404. int rc;
  405. u8 val;
  406. u8 desired_status;
  407. might_sleep();
  408. if (state == STATE_FORCE_TX_ON)
  409. desired_status = STATE_TX_ON;
  410. else if (state == STATE_FORCE_TRX_OFF)
  411. desired_status = STATE_TRX_OFF;
  412. else
  413. desired_status = state;
  414. do {
  415. rc = at86rf230_read_subreg(lp, SR_TRX_STATUS, &val);
  416. if (rc)
  417. goto err;
  418. } while (val == STATE_TRANSITION_IN_PROGRESS);
  419. if (val == desired_status)
  420. return 0;
  421. /* state is equal to phy states */
  422. rc = at86rf230_write_subreg(lp, SR_TRX_CMD, state);
  423. if (rc)
  424. goto err;
  425. do {
  426. rc = at86rf230_read_subreg(lp, SR_TRX_STATUS, &val);
  427. if (rc)
  428. goto err;
  429. } while (val == STATE_TRANSITION_IN_PROGRESS);
  430. if (val == desired_status)
  431. return 0;
  432. pr_err("unexpected state change: %d, asked for %d\n", val, state);
  433. return -EBUSY;
  434. err:
  435. pr_err("error: %d\n", rc);
  436. return rc;
  437. }
  438. static int
  439. at86rf230_start(struct ieee802154_dev *dev)
  440. {
  441. struct at86rf230_local *lp = dev->priv;
  442. u8 rc;
  443. rc = at86rf230_write_subreg(lp, SR_RX_SAFE_MODE, 1);
  444. if (rc)
  445. return rc;
  446. return at86rf230_state(dev, STATE_RX_ON);
  447. }
  448. static void
  449. at86rf230_stop(struct ieee802154_dev *dev)
  450. {
  451. at86rf230_state(dev, STATE_FORCE_TRX_OFF);
  452. }
  453. static int
  454. at86rf230_channel(struct ieee802154_dev *dev, int page, int channel)
  455. {
  456. struct at86rf230_local *lp = dev->priv;
  457. int rc;
  458. might_sleep();
  459. if (page != 0 || channel < 11 || channel > 26) {
  460. WARN_ON(1);
  461. return -EINVAL;
  462. }
  463. rc = at86rf230_write_subreg(lp, SR_CHANNEL, channel);
  464. msleep(1); /* Wait for PLL */
  465. dev->phy->current_channel = channel;
  466. return 0;
  467. }
  468. static int
  469. at86rf230_xmit(struct ieee802154_dev *dev, struct sk_buff *skb)
  470. {
  471. struct at86rf230_local *lp = dev->priv;
  472. int rc;
  473. unsigned long flags;
  474. spin_lock_irqsave(&lp->lock, flags);
  475. if (lp->irq_busy) {
  476. spin_unlock_irqrestore(&lp->lock, flags);
  477. return -EBUSY;
  478. }
  479. spin_unlock_irqrestore(&lp->lock, flags);
  480. might_sleep();
  481. rc = at86rf230_state(dev, STATE_FORCE_TX_ON);
  482. if (rc)
  483. goto err;
  484. spin_lock_irqsave(&lp->lock, flags);
  485. lp->is_tx = 1;
  486. reinit_completion(&lp->tx_complete);
  487. spin_unlock_irqrestore(&lp->lock, flags);
  488. rc = at86rf230_write_fbuf(lp, skb->data, skb->len);
  489. if (rc)
  490. goto err_rx;
  491. rc = at86rf230_write_subreg(lp, SR_TRX_CMD, STATE_BUSY_TX);
  492. if (rc)
  493. goto err_rx;
  494. rc = wait_for_completion_interruptible(&lp->tx_complete);
  495. if (rc < 0)
  496. goto err_rx;
  497. rc = at86rf230_start(dev);
  498. return rc;
  499. err_rx:
  500. at86rf230_start(dev);
  501. err:
  502. pr_err("error: %d\n", rc);
  503. spin_lock_irqsave(&lp->lock, flags);
  504. lp->is_tx = 0;
  505. spin_unlock_irqrestore(&lp->lock, flags);
  506. return rc;
  507. }
  508. static int at86rf230_rx(struct at86rf230_local *lp)
  509. {
  510. u8 len = 128, lqi = 0;
  511. struct sk_buff *skb;
  512. skb = alloc_skb(len, GFP_KERNEL);
  513. if (!skb)
  514. return -ENOMEM;
  515. if (at86rf230_read_fbuf(lp, skb_put(skb, len), &len, &lqi))
  516. goto err;
  517. if (len < 2)
  518. goto err;
  519. skb_trim(skb, len - 2); /* We do not put CRC into the frame */
  520. ieee802154_rx_irqsafe(lp->dev, skb, lqi);
  521. dev_dbg(&lp->spi->dev, "READ_FBUF: %d %x\n", len, lqi);
  522. return 0;
  523. err:
  524. pr_debug("received frame is too small\n");
  525. kfree_skb(skb);
  526. return -EINVAL;
  527. }
  528. static int
  529. at86rf230_set_hw_addr_filt(struct ieee802154_dev *dev,
  530. struct ieee802154_hw_addr_filt *filt,
  531. unsigned long changed)
  532. {
  533. struct at86rf230_local *lp = dev->priv;
  534. if (changed & IEEE802515_AFILT_SADDR_CHANGED) {
  535. dev_vdbg(&lp->spi->dev,
  536. "at86rf230_set_hw_addr_filt called for saddr\n");
  537. __at86rf230_write(lp, RG_SHORT_ADDR_0, filt->short_addr);
  538. __at86rf230_write(lp, RG_SHORT_ADDR_1, filt->short_addr >> 8);
  539. }
  540. if (changed & IEEE802515_AFILT_PANID_CHANGED) {
  541. dev_vdbg(&lp->spi->dev,
  542. "at86rf230_set_hw_addr_filt called for pan id\n");
  543. __at86rf230_write(lp, RG_PAN_ID_0, filt->pan_id);
  544. __at86rf230_write(lp, RG_PAN_ID_1, filt->pan_id >> 8);
  545. }
  546. if (changed & IEEE802515_AFILT_IEEEADDR_CHANGED) {
  547. dev_vdbg(&lp->spi->dev,
  548. "at86rf230_set_hw_addr_filt called for IEEE addr\n");
  549. at86rf230_write_subreg(lp, SR_IEEE_ADDR_0, filt->ieee_addr[7]);
  550. at86rf230_write_subreg(lp, SR_IEEE_ADDR_1, filt->ieee_addr[6]);
  551. at86rf230_write_subreg(lp, SR_IEEE_ADDR_2, filt->ieee_addr[5]);
  552. at86rf230_write_subreg(lp, SR_IEEE_ADDR_3, filt->ieee_addr[4]);
  553. at86rf230_write_subreg(lp, SR_IEEE_ADDR_4, filt->ieee_addr[3]);
  554. at86rf230_write_subreg(lp, SR_IEEE_ADDR_5, filt->ieee_addr[2]);
  555. at86rf230_write_subreg(lp, SR_IEEE_ADDR_6, filt->ieee_addr[1]);
  556. at86rf230_write_subreg(lp, SR_IEEE_ADDR_7, filt->ieee_addr[0]);
  557. }
  558. if (changed & IEEE802515_AFILT_PANC_CHANGED) {
  559. dev_vdbg(&lp->spi->dev,
  560. "at86rf230_set_hw_addr_filt called for panc change\n");
  561. if (filt->pan_coord)
  562. at86rf230_write_subreg(lp, SR_AACK_I_AM_COORD, 1);
  563. else
  564. at86rf230_write_subreg(lp, SR_AACK_I_AM_COORD, 0);
  565. }
  566. return 0;
  567. }
  568. static struct ieee802154_ops at86rf230_ops = {
  569. .owner = THIS_MODULE,
  570. .xmit = at86rf230_xmit,
  571. .ed = at86rf230_ed,
  572. .set_channel = at86rf230_channel,
  573. .start = at86rf230_start,
  574. .stop = at86rf230_stop,
  575. .set_hw_addr_filt = at86rf230_set_hw_addr_filt,
  576. };
  577. static void at86rf230_irqwork(struct work_struct *work)
  578. {
  579. struct at86rf230_local *lp =
  580. container_of(work, struct at86rf230_local, irqwork);
  581. u8 status = 0, val;
  582. int rc;
  583. unsigned long flags;
  584. rc = at86rf230_read_subreg(lp, RG_IRQ_STATUS, 0xff, 0, &val);
  585. status |= val;
  586. status &= ~IRQ_PLL_LOCK; /* ignore */
  587. status &= ~IRQ_RX_START; /* ignore */
  588. status &= ~IRQ_AMI; /* ignore */
  589. status &= ~IRQ_TRX_UR; /* FIXME: possibly handle ???*/
  590. if (status & IRQ_TRX_END) {
  591. spin_lock_irqsave(&lp->lock, flags);
  592. status &= ~IRQ_TRX_END;
  593. if (lp->is_tx) {
  594. lp->is_tx = 0;
  595. spin_unlock_irqrestore(&lp->lock, flags);
  596. complete(&lp->tx_complete);
  597. } else {
  598. spin_unlock_irqrestore(&lp->lock, flags);
  599. at86rf230_rx(lp);
  600. }
  601. }
  602. spin_lock_irqsave(&lp->lock, flags);
  603. lp->irq_busy = 0;
  604. spin_unlock_irqrestore(&lp->lock, flags);
  605. }
  606. static void at86rf230_irqwork_level(struct work_struct *work)
  607. {
  608. struct at86rf230_local *lp =
  609. container_of(work, struct at86rf230_local, irqwork);
  610. at86rf230_irqwork(work);
  611. enable_irq(lp->spi->irq);
  612. }
  613. static irqreturn_t at86rf230_isr(int irq, void *data)
  614. {
  615. struct at86rf230_local *lp = data;
  616. unsigned long flags;
  617. spin_lock_irqsave(&lp->lock, flags);
  618. lp->irq_busy = 1;
  619. spin_unlock_irqrestore(&lp->lock, flags);
  620. schedule_work(&lp->irqwork);
  621. return IRQ_HANDLED;
  622. }
  623. static irqreturn_t at86rf230_isr_level(int irq, void *data)
  624. {
  625. disable_irq_nosync(irq);
  626. return at86rf230_isr(irq, data);
  627. }
  628. static int at86rf230_irq_polarity(struct at86rf230_local *lp, int pol)
  629. {
  630. return at86rf230_write_subreg(lp, SR_IRQ_POLARITY, pol);
  631. }
  632. static int at86rf230_hw_init(struct at86rf230_local *lp)
  633. {
  634. struct at86rf230_platform_data *pdata = lp->spi->dev.platform_data;
  635. int rc, irq_pol;
  636. u8 status;
  637. rc = at86rf230_read_subreg(lp, SR_TRX_STATUS, &status);
  638. if (rc)
  639. return rc;
  640. dev_info(&lp->spi->dev, "Status: %02x\n", status);
  641. if (status == STATE_P_ON) {
  642. rc = at86rf230_write_subreg(lp, SR_TRX_CMD, STATE_TRX_OFF);
  643. if (rc)
  644. return rc;
  645. msleep(1);
  646. rc = at86rf230_read_subreg(lp, SR_TRX_STATUS, &status);
  647. if (rc)
  648. return rc;
  649. dev_info(&lp->spi->dev, "Status: %02x\n", status);
  650. }
  651. /* configure irq polarity, defaults to high active */
  652. if (pdata->irq_type & (IRQF_TRIGGER_FALLING | IRQF_TRIGGER_LOW))
  653. irq_pol = IRQ_ACTIVE_LOW;
  654. else
  655. irq_pol = IRQ_ACTIVE_HIGH;
  656. rc = at86rf230_irq_polarity(lp, irq_pol);
  657. if (rc)
  658. return rc;
  659. rc = at86rf230_write_subreg(lp, SR_IRQ_MASK, IRQ_TRX_END);
  660. if (rc)
  661. return rc;
  662. /* CLKM changes are applied immediately */
  663. rc = at86rf230_write_subreg(lp, SR_CLKM_SHA_SEL, 0x00);
  664. if (rc)
  665. return rc;
  666. /* Turn CLKM Off */
  667. rc = at86rf230_write_subreg(lp, SR_CLKM_CTRL, 0x00);
  668. if (rc)
  669. return rc;
  670. /* Wait the next SLEEP cycle */
  671. msleep(100);
  672. rc = at86rf230_write_subreg(lp, SR_TRX_CMD, STATE_TX_ON);
  673. if (rc)
  674. return rc;
  675. msleep(1);
  676. rc = at86rf230_read_subreg(lp, SR_TRX_STATUS, &status);
  677. if (rc)
  678. return rc;
  679. dev_info(&lp->spi->dev, "Status: %02x\n", status);
  680. rc = at86rf230_read_subreg(lp, SR_DVDD_OK, &status);
  681. if (rc)
  682. return rc;
  683. if (!status) {
  684. dev_err(&lp->spi->dev, "DVDD error\n");
  685. return -EINVAL;
  686. }
  687. rc = at86rf230_read_subreg(lp, SR_AVDD_OK, &status);
  688. if (rc)
  689. return rc;
  690. if (!status) {
  691. dev_err(&lp->spi->dev, "AVDD error\n");
  692. return -EINVAL;
  693. }
  694. return 0;
  695. }
  696. static void at86rf230_fill_data(struct spi_device *spi)
  697. {
  698. struct at86rf230_local *lp = spi_get_drvdata(spi);
  699. struct at86rf230_platform_data *pdata = spi->dev.platform_data;
  700. lp->rstn = pdata->rstn;
  701. lp->slp_tr = pdata->slp_tr;
  702. lp->dig2 = pdata->dig2;
  703. }
  704. static int at86rf230_probe(struct spi_device *spi)
  705. {
  706. struct at86rf230_platform_data *pdata;
  707. struct ieee802154_dev *dev;
  708. struct at86rf230_local *lp;
  709. u8 man_id_0, man_id_1, status;
  710. irq_handler_t irq_handler;
  711. work_func_t irq_worker;
  712. int rc, supported = 0;
  713. const char *chip;
  714. if (!spi->irq) {
  715. dev_err(&spi->dev, "no IRQ specified\n");
  716. return -EINVAL;
  717. }
  718. pdata = spi->dev.platform_data;
  719. if (!pdata) {
  720. dev_err(&spi->dev, "no platform_data\n");
  721. return -EINVAL;
  722. }
  723. dev = ieee802154_alloc_device(sizeof(*lp), &at86rf230_ops);
  724. if (!dev)
  725. return -ENOMEM;
  726. lp = dev->priv;
  727. lp->dev = dev;
  728. lp->spi = spi;
  729. dev->parent = &spi->dev;
  730. dev->extra_tx_headroom = 0;
  731. /* We do support only 2.4 Ghz */
  732. dev->phy->channels_supported[0] = 0x7FFF800;
  733. dev->flags = IEEE802154_HW_OMIT_CKSUM;
  734. if (pdata->irq_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
  735. irq_worker = at86rf230_irqwork;
  736. irq_handler = at86rf230_isr;
  737. } else {
  738. irq_worker = at86rf230_irqwork_level;
  739. irq_handler = at86rf230_isr_level;
  740. }
  741. mutex_init(&lp->bmux);
  742. INIT_WORK(&lp->irqwork, irq_worker);
  743. spin_lock_init(&lp->lock);
  744. init_completion(&lp->tx_complete);
  745. spi_set_drvdata(spi, lp);
  746. at86rf230_fill_data(spi);
  747. rc = gpio_request(lp->rstn, "rstn");
  748. if (rc)
  749. goto err_rstn;
  750. if (gpio_is_valid(lp->slp_tr)) {
  751. rc = gpio_request(lp->slp_tr, "slp_tr");
  752. if (rc)
  753. goto err_slp_tr;
  754. }
  755. rc = gpio_direction_output(lp->rstn, 1);
  756. if (rc)
  757. goto err_gpio_dir;
  758. if (gpio_is_valid(lp->slp_tr)) {
  759. rc = gpio_direction_output(lp->slp_tr, 0);
  760. if (rc)
  761. goto err_gpio_dir;
  762. }
  763. /* Reset */
  764. msleep(1);
  765. gpio_set_value(lp->rstn, 0);
  766. msleep(1);
  767. gpio_set_value(lp->rstn, 1);
  768. msleep(1);
  769. rc = at86rf230_read_subreg(lp, SR_MAN_ID_0, &man_id_0);
  770. if (rc)
  771. goto err_gpio_dir;
  772. rc = at86rf230_read_subreg(lp, SR_MAN_ID_1, &man_id_1);
  773. if (rc)
  774. goto err_gpio_dir;
  775. if (man_id_1 != 0x00 || man_id_0 != 0x1f) {
  776. dev_err(&spi->dev, "Non-Atmel dev found (MAN_ID %02x %02x)\n",
  777. man_id_1, man_id_0);
  778. rc = -EINVAL;
  779. goto err_gpio_dir;
  780. }
  781. rc = at86rf230_read_subreg(lp, SR_PART_NUM, &lp->part);
  782. if (rc)
  783. goto err_gpio_dir;
  784. rc = at86rf230_read_subreg(lp, SR_VERSION_NUM, &lp->vers);
  785. if (rc)
  786. goto err_gpio_dir;
  787. switch (lp->part) {
  788. case 2:
  789. chip = "at86rf230";
  790. /* supported = 1; FIXME: should be easy to support; */
  791. break;
  792. case 3:
  793. chip = "at86rf231";
  794. supported = 1;
  795. break;
  796. default:
  797. chip = "UNKNOWN";
  798. break;
  799. }
  800. dev_info(&spi->dev, "Detected %s chip version %d\n", chip, lp->vers);
  801. if (!supported) {
  802. rc = -ENOTSUPP;
  803. goto err_gpio_dir;
  804. }
  805. rc = at86rf230_hw_init(lp);
  806. if (rc)
  807. goto err_gpio_dir;
  808. rc = request_irq(spi->irq, irq_handler,
  809. IRQF_SHARED | pdata->irq_type,
  810. dev_name(&spi->dev), lp);
  811. if (rc)
  812. goto err_gpio_dir;
  813. /* Read irq status register to reset irq line */
  814. rc = at86rf230_read_subreg(lp, RG_IRQ_STATUS, 0xff, 0, &status);
  815. if (rc)
  816. goto err_irq;
  817. rc = ieee802154_register_device(lp->dev);
  818. if (rc)
  819. goto err_irq;
  820. return rc;
  821. err_irq:
  822. free_irq(spi->irq, lp);
  823. flush_work(&lp->irqwork);
  824. err_gpio_dir:
  825. if (gpio_is_valid(lp->slp_tr))
  826. gpio_free(lp->slp_tr);
  827. err_slp_tr:
  828. gpio_free(lp->rstn);
  829. err_rstn:
  830. mutex_destroy(&lp->bmux);
  831. ieee802154_free_device(lp->dev);
  832. return rc;
  833. }
  834. static int at86rf230_remove(struct spi_device *spi)
  835. {
  836. struct at86rf230_local *lp = spi_get_drvdata(spi);
  837. ieee802154_unregister_device(lp->dev);
  838. free_irq(spi->irq, lp);
  839. flush_work(&lp->irqwork);
  840. if (gpio_is_valid(lp->slp_tr))
  841. gpio_free(lp->slp_tr);
  842. gpio_free(lp->rstn);
  843. mutex_destroy(&lp->bmux);
  844. ieee802154_free_device(lp->dev);
  845. dev_dbg(&spi->dev, "unregistered at86rf230\n");
  846. return 0;
  847. }
  848. static struct spi_driver at86rf230_driver = {
  849. .driver = {
  850. .name = "at86rf230",
  851. .owner = THIS_MODULE,
  852. },
  853. .probe = at86rf230_probe,
  854. .remove = at86rf230_remove,
  855. };
  856. module_spi_driver(at86rf230_driver);
  857. MODULE_DESCRIPTION("AT86RF230 Transceiver Driver");
  858. MODULE_LICENSE("GPL v2");