smsc911x.c 69 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628162916301631163216331634163516361637163816391640164116421643164416451646164716481649165016511652165316541655165616571658165916601661166216631664166516661667166816691670167116721673167416751676167716781679168016811682168316841685168616871688168916901691169216931694169516961697169816991700170117021703170417051706170717081709171017111712171317141715171617171718171917201721172217231724172517261727172817291730173117321733173417351736173717381739174017411742174317441745174617471748174917501751175217531754175517561757175817591760176117621763176417651766176717681769177017711772177317741775177617771778177917801781178217831784178517861787178817891790179117921793179417951796179717981799180018011802180318041805180618071808180918101811181218131814181518161817181818191820182118221823182418251826182718281829183018311832183318341835183618371838183918401841184218431844184518461847184818491850185118521853185418551856185718581859186018611862186318641865186618671868186918701871187218731874187518761877187818791880188118821883188418851886188718881889189018911892189318941895189618971898189919001901190219031904190519061907190819091910191119121913191419151916191719181919192019211922192319241925192619271928192919301931193219331934193519361937193819391940194119421943194419451946194719481949195019511952195319541955195619571958195919601961196219631964196519661967196819691970197119721973197419751976197719781979198019811982198319841985198619871988198919901991199219931994199519961997199819992000200120022003200420052006200720082009201020112012201320142015201620172018201920202021202220232024202520262027202820292030203120322033203420352036203720382039204020412042204320442045204620472048204920502051205220532054205520562057205820592060206120622063206420652066206720682069207020712072207320742075207620772078207920802081208220832084208520862087208820892090209120922093209420952096209720982099210021012102210321042105210621072108210921102111211221132114211521162117211821192120212121222123212421252126212721282129213021312132213321342135213621372138213921402141214221432144214521462147214821492150215121522153215421552156215721582159216021612162216321642165216621672168216921702171217221732174217521762177217821792180218121822183218421852186218721882189219021912192219321942195219621972198219922002201220222032204220522062207220822092210221122122213221422152216221722182219222022212222222322242225222622272228222922302231223222332234223522362237223822392240224122422243224422452246224722482249225022512252225322542255225622572258225922602261226222632264226522662267226822692270227122722273227422752276227722782279228022812282228322842285228622872288228922902291229222932294229522962297229822992300230123022303230423052306230723082309231023112312231323142315231623172318231923202321232223232324232523262327232823292330233123322333233423352336233723382339234023412342234323442345234623472348234923502351235223532354235523562357235823592360236123622363236423652366236723682369237023712372237323742375237623772378237923802381238223832384238523862387238823892390239123922393239423952396239723982399240024012402240324042405240624072408240924102411241224132414241524162417241824192420242124222423242424252426242724282429243024312432243324342435243624372438243924402441244224432444244524462447244824492450245124522453245424552456245724582459246024612462246324642465246624672468246924702471247224732474247524762477247824792480248124822483248424852486248724882489249024912492249324942495249624972498249925002501250225032504250525062507250825092510251125122513251425152516251725182519252025212522252325242525252625272528252925302531253225332534253525362537253825392540254125422543254425452546254725482549255025512552255325542555255625572558255925602561256225632564256525662567256825692570257125722573257425752576257725782579258025812582258325842585258625872588258925902591259225932594259525962597259825992600260126022603260426052606260726082609261026112612261326142615261626172618261926202621262226232624262526262627262826292630263126322633
  1. /***************************************************************************
  2. *
  3. * Copyright (C) 2004-2008 SMSC
  4. * Copyright (C) 2005-2008 ARM
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * as published by the Free Software Foundation; either version 2
  9. * of the License, or (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, see <http://www.gnu.org/licenses/>.
  18. *
  19. ***************************************************************************
  20. * Rewritten, heavily based on smsc911x simple driver by SMSC.
  21. * Partly uses io macros from smc91x.c by Nicolas Pitre
  22. *
  23. * Supported devices:
  24. * LAN9115, LAN9116, LAN9117, LAN9118
  25. * LAN9215, LAN9216, LAN9217, LAN9218
  26. * LAN9210, LAN9211
  27. * LAN9220, LAN9221
  28. * LAN89218
  29. *
  30. */
  31. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  32. #include <linux/crc32.h>
  33. #include <linux/clk.h>
  34. #include <linux/delay.h>
  35. #include <linux/errno.h>
  36. #include <linux/etherdevice.h>
  37. #include <linux/ethtool.h>
  38. #include <linux/init.h>
  39. #include <linux/interrupt.h>
  40. #include <linux/ioport.h>
  41. #include <linux/kernel.h>
  42. #include <linux/module.h>
  43. #include <linux/netdevice.h>
  44. #include <linux/platform_device.h>
  45. #include <linux/regulator/consumer.h>
  46. #include <linux/sched.h>
  47. #include <linux/timer.h>
  48. #include <linux/bug.h>
  49. #include <linux/bitops.h>
  50. #include <linux/irq.h>
  51. #include <linux/io.h>
  52. #include <linux/swab.h>
  53. #include <linux/phy.h>
  54. #include <linux/smsc911x.h>
  55. #include <linux/device.h>
  56. #include <linux/of.h>
  57. #include <linux/of_device.h>
  58. #include <linux/of_gpio.h>
  59. #include <linux/of_net.h>
  60. #include "smsc911x.h"
  61. #define SMSC_CHIPNAME "smsc911x"
  62. #define SMSC_MDIONAME "smsc911x-mdio"
  63. #define SMSC_DRV_VERSION "2008-10-21"
  64. MODULE_LICENSE("GPL");
  65. MODULE_VERSION(SMSC_DRV_VERSION);
  66. MODULE_ALIAS("platform:smsc911x");
  67. #if USE_DEBUG > 0
  68. static int debug = 16;
  69. #else
  70. static int debug = 3;
  71. #endif
  72. module_param(debug, int, 0);
  73. MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
  74. struct smsc911x_data;
  75. struct smsc911x_ops {
  76. u32 (*reg_read)(struct smsc911x_data *pdata, u32 reg);
  77. void (*reg_write)(struct smsc911x_data *pdata, u32 reg, u32 val);
  78. void (*rx_readfifo)(struct smsc911x_data *pdata,
  79. unsigned int *buf, unsigned int wordcount);
  80. void (*tx_writefifo)(struct smsc911x_data *pdata,
  81. unsigned int *buf, unsigned int wordcount);
  82. };
  83. #define SMSC911X_NUM_SUPPLIES 2
  84. struct smsc911x_data {
  85. void __iomem *ioaddr;
  86. unsigned int idrev;
  87. /* used to decide which workarounds apply */
  88. unsigned int generation;
  89. /* device configuration (copied from platform_data during probe) */
  90. struct smsc911x_platform_config config;
  91. /* This needs to be acquired before calling any of below:
  92. * smsc911x_mac_read(), smsc911x_mac_write()
  93. */
  94. spinlock_t mac_lock;
  95. /* spinlock to ensure register accesses are serialised */
  96. spinlock_t dev_lock;
  97. struct phy_device *phy_dev;
  98. struct mii_bus *mii_bus;
  99. int phy_irq[PHY_MAX_ADDR];
  100. unsigned int using_extphy;
  101. int last_duplex;
  102. int last_carrier;
  103. u32 msg_enable;
  104. unsigned int gpio_setting;
  105. unsigned int gpio_orig_setting;
  106. struct net_device *dev;
  107. struct napi_struct napi;
  108. unsigned int software_irq_signal;
  109. #ifdef USE_PHY_WORK_AROUND
  110. #define MIN_PACKET_SIZE (64)
  111. char loopback_tx_pkt[MIN_PACKET_SIZE];
  112. char loopback_rx_pkt[MIN_PACKET_SIZE];
  113. unsigned int resetcount;
  114. #endif
  115. /* Members for Multicast filter workaround */
  116. unsigned int multicast_update_pending;
  117. unsigned int set_bits_mask;
  118. unsigned int clear_bits_mask;
  119. unsigned int hashhi;
  120. unsigned int hashlo;
  121. /* register access functions */
  122. const struct smsc911x_ops *ops;
  123. /* regulators */
  124. struct regulator_bulk_data supplies[SMSC911X_NUM_SUPPLIES];
  125. /* clock */
  126. struct clk *clk;
  127. };
  128. /* Easy access to information */
  129. #define __smsc_shift(pdata, reg) ((reg) << ((pdata)->config.shift))
  130. static inline u32 __smsc911x_reg_read(struct smsc911x_data *pdata, u32 reg)
  131. {
  132. if (pdata->config.flags & SMSC911X_USE_32BIT)
  133. return readl(pdata->ioaddr + reg);
  134. if (pdata->config.flags & SMSC911X_USE_16BIT)
  135. return ((readw(pdata->ioaddr + reg) & 0xFFFF) |
  136. ((readw(pdata->ioaddr + reg + 2) & 0xFFFF) << 16));
  137. BUG();
  138. return 0;
  139. }
  140. static inline u32
  141. __smsc911x_reg_read_shift(struct smsc911x_data *pdata, u32 reg)
  142. {
  143. if (pdata->config.flags & SMSC911X_USE_32BIT)
  144. return readl(pdata->ioaddr + __smsc_shift(pdata, reg));
  145. if (pdata->config.flags & SMSC911X_USE_16BIT)
  146. return (readw(pdata->ioaddr +
  147. __smsc_shift(pdata, reg)) & 0xFFFF) |
  148. ((readw(pdata->ioaddr +
  149. __smsc_shift(pdata, reg + 2)) & 0xFFFF) << 16);
  150. BUG();
  151. return 0;
  152. }
  153. static inline u32 smsc911x_reg_read(struct smsc911x_data *pdata, u32 reg)
  154. {
  155. u32 data;
  156. unsigned long flags;
  157. spin_lock_irqsave(&pdata->dev_lock, flags);
  158. data = pdata->ops->reg_read(pdata, reg);
  159. spin_unlock_irqrestore(&pdata->dev_lock, flags);
  160. return data;
  161. }
  162. static inline void __smsc911x_reg_write(struct smsc911x_data *pdata, u32 reg,
  163. u32 val)
  164. {
  165. if (pdata->config.flags & SMSC911X_USE_32BIT) {
  166. writel(val, pdata->ioaddr + reg);
  167. return;
  168. }
  169. if (pdata->config.flags & SMSC911X_USE_16BIT) {
  170. writew(val & 0xFFFF, pdata->ioaddr + reg);
  171. writew((val >> 16) & 0xFFFF, pdata->ioaddr + reg + 2);
  172. return;
  173. }
  174. BUG();
  175. }
  176. static inline void
  177. __smsc911x_reg_write_shift(struct smsc911x_data *pdata, u32 reg, u32 val)
  178. {
  179. if (pdata->config.flags & SMSC911X_USE_32BIT) {
  180. writel(val, pdata->ioaddr + __smsc_shift(pdata, reg));
  181. return;
  182. }
  183. if (pdata->config.flags & SMSC911X_USE_16BIT) {
  184. writew(val & 0xFFFF,
  185. pdata->ioaddr + __smsc_shift(pdata, reg));
  186. writew((val >> 16) & 0xFFFF,
  187. pdata->ioaddr + __smsc_shift(pdata, reg + 2));
  188. return;
  189. }
  190. BUG();
  191. }
  192. static inline void smsc911x_reg_write(struct smsc911x_data *pdata, u32 reg,
  193. u32 val)
  194. {
  195. unsigned long flags;
  196. spin_lock_irqsave(&pdata->dev_lock, flags);
  197. pdata->ops->reg_write(pdata, reg, val);
  198. spin_unlock_irqrestore(&pdata->dev_lock, flags);
  199. }
  200. /* Writes a packet to the TX_DATA_FIFO */
  201. static inline void
  202. smsc911x_tx_writefifo(struct smsc911x_data *pdata, unsigned int *buf,
  203. unsigned int wordcount)
  204. {
  205. unsigned long flags;
  206. spin_lock_irqsave(&pdata->dev_lock, flags);
  207. if (pdata->config.flags & SMSC911X_SWAP_FIFO) {
  208. while (wordcount--)
  209. __smsc911x_reg_write(pdata, TX_DATA_FIFO,
  210. swab32(*buf++));
  211. goto out;
  212. }
  213. if (pdata->config.flags & SMSC911X_USE_32BIT) {
  214. iowrite32_rep(pdata->ioaddr + TX_DATA_FIFO, buf, wordcount);
  215. goto out;
  216. }
  217. if (pdata->config.flags & SMSC911X_USE_16BIT) {
  218. while (wordcount--)
  219. __smsc911x_reg_write(pdata, TX_DATA_FIFO, *buf++);
  220. goto out;
  221. }
  222. BUG();
  223. out:
  224. spin_unlock_irqrestore(&pdata->dev_lock, flags);
  225. }
  226. /* Writes a packet to the TX_DATA_FIFO - shifted version */
  227. static inline void
  228. smsc911x_tx_writefifo_shift(struct smsc911x_data *pdata, unsigned int *buf,
  229. unsigned int wordcount)
  230. {
  231. unsigned long flags;
  232. spin_lock_irqsave(&pdata->dev_lock, flags);
  233. if (pdata->config.flags & SMSC911X_SWAP_FIFO) {
  234. while (wordcount--)
  235. __smsc911x_reg_write_shift(pdata, TX_DATA_FIFO,
  236. swab32(*buf++));
  237. goto out;
  238. }
  239. if (pdata->config.flags & SMSC911X_USE_32BIT) {
  240. iowrite32_rep(pdata->ioaddr + __smsc_shift(pdata,
  241. TX_DATA_FIFO), buf, wordcount);
  242. goto out;
  243. }
  244. if (pdata->config.flags & SMSC911X_USE_16BIT) {
  245. while (wordcount--)
  246. __smsc911x_reg_write_shift(pdata,
  247. TX_DATA_FIFO, *buf++);
  248. goto out;
  249. }
  250. BUG();
  251. out:
  252. spin_unlock_irqrestore(&pdata->dev_lock, flags);
  253. }
  254. /* Reads a packet out of the RX_DATA_FIFO */
  255. static inline void
  256. smsc911x_rx_readfifo(struct smsc911x_data *pdata, unsigned int *buf,
  257. unsigned int wordcount)
  258. {
  259. unsigned long flags;
  260. spin_lock_irqsave(&pdata->dev_lock, flags);
  261. if (pdata->config.flags & SMSC911X_SWAP_FIFO) {
  262. while (wordcount--)
  263. *buf++ = swab32(__smsc911x_reg_read(pdata,
  264. RX_DATA_FIFO));
  265. goto out;
  266. }
  267. if (pdata->config.flags & SMSC911X_USE_32BIT) {
  268. ioread32_rep(pdata->ioaddr + RX_DATA_FIFO, buf, wordcount);
  269. goto out;
  270. }
  271. if (pdata->config.flags & SMSC911X_USE_16BIT) {
  272. while (wordcount--)
  273. *buf++ = __smsc911x_reg_read(pdata, RX_DATA_FIFO);
  274. goto out;
  275. }
  276. BUG();
  277. out:
  278. spin_unlock_irqrestore(&pdata->dev_lock, flags);
  279. }
  280. /* Reads a packet out of the RX_DATA_FIFO - shifted version */
  281. static inline void
  282. smsc911x_rx_readfifo_shift(struct smsc911x_data *pdata, unsigned int *buf,
  283. unsigned int wordcount)
  284. {
  285. unsigned long flags;
  286. spin_lock_irqsave(&pdata->dev_lock, flags);
  287. if (pdata->config.flags & SMSC911X_SWAP_FIFO) {
  288. while (wordcount--)
  289. *buf++ = swab32(__smsc911x_reg_read_shift(pdata,
  290. RX_DATA_FIFO));
  291. goto out;
  292. }
  293. if (pdata->config.flags & SMSC911X_USE_32BIT) {
  294. ioread32_rep(pdata->ioaddr + __smsc_shift(pdata,
  295. RX_DATA_FIFO), buf, wordcount);
  296. goto out;
  297. }
  298. if (pdata->config.flags & SMSC911X_USE_16BIT) {
  299. while (wordcount--)
  300. *buf++ = __smsc911x_reg_read_shift(pdata,
  301. RX_DATA_FIFO);
  302. goto out;
  303. }
  304. BUG();
  305. out:
  306. spin_unlock_irqrestore(&pdata->dev_lock, flags);
  307. }
  308. /*
  309. * enable regulator and clock resources.
  310. */
  311. static int smsc911x_enable_resources(struct platform_device *pdev)
  312. {
  313. struct net_device *ndev = platform_get_drvdata(pdev);
  314. struct smsc911x_data *pdata = netdev_priv(ndev);
  315. int ret = 0;
  316. ret = regulator_bulk_enable(ARRAY_SIZE(pdata->supplies),
  317. pdata->supplies);
  318. if (ret)
  319. netdev_err(ndev, "failed to enable regulators %d\n",
  320. ret);
  321. if (!IS_ERR(pdata->clk)) {
  322. ret = clk_prepare_enable(pdata->clk);
  323. if (ret < 0)
  324. netdev_err(ndev, "failed to enable clock %d\n", ret);
  325. }
  326. return ret;
  327. }
  328. /*
  329. * disable resources, currently just regulators.
  330. */
  331. static int smsc911x_disable_resources(struct platform_device *pdev)
  332. {
  333. struct net_device *ndev = platform_get_drvdata(pdev);
  334. struct smsc911x_data *pdata = netdev_priv(ndev);
  335. int ret = 0;
  336. ret = regulator_bulk_disable(ARRAY_SIZE(pdata->supplies),
  337. pdata->supplies);
  338. if (!IS_ERR(pdata->clk))
  339. clk_disable_unprepare(pdata->clk);
  340. return ret;
  341. }
  342. /*
  343. * Request resources, currently just regulators.
  344. *
  345. * The SMSC911x has two power pins: vddvario and vdd33a, in designs where
  346. * these are not always-on we need to request regulators to be turned on
  347. * before we can try to access the device registers.
  348. */
  349. static int smsc911x_request_resources(struct platform_device *pdev)
  350. {
  351. struct net_device *ndev = platform_get_drvdata(pdev);
  352. struct smsc911x_data *pdata = netdev_priv(ndev);
  353. int ret = 0;
  354. /* Request regulators */
  355. pdata->supplies[0].supply = "vdd33a";
  356. pdata->supplies[1].supply = "vddvario";
  357. ret = regulator_bulk_get(&pdev->dev,
  358. ARRAY_SIZE(pdata->supplies),
  359. pdata->supplies);
  360. if (ret)
  361. netdev_err(ndev, "couldn't get regulators %d\n",
  362. ret);
  363. /* Request clock */
  364. pdata->clk = clk_get(&pdev->dev, NULL);
  365. if (IS_ERR(pdata->clk))
  366. netdev_warn(ndev, "couldn't get clock %li\n", PTR_ERR(pdata->clk));
  367. return ret;
  368. }
  369. /*
  370. * Free resources, currently just regulators.
  371. *
  372. */
  373. static void smsc911x_free_resources(struct platform_device *pdev)
  374. {
  375. struct net_device *ndev = platform_get_drvdata(pdev);
  376. struct smsc911x_data *pdata = netdev_priv(ndev);
  377. /* Free regulators */
  378. regulator_bulk_free(ARRAY_SIZE(pdata->supplies),
  379. pdata->supplies);
  380. /* Free clock */
  381. if (!IS_ERR(pdata->clk)) {
  382. clk_put(pdata->clk);
  383. pdata->clk = NULL;
  384. }
  385. }
  386. /* waits for MAC not busy, with timeout. Only called by smsc911x_mac_read
  387. * and smsc911x_mac_write, so assumes mac_lock is held */
  388. static int smsc911x_mac_complete(struct smsc911x_data *pdata)
  389. {
  390. int i;
  391. u32 val;
  392. SMSC_ASSERT_MAC_LOCK(pdata);
  393. for (i = 0; i < 40; i++) {
  394. val = smsc911x_reg_read(pdata, MAC_CSR_CMD);
  395. if (!(val & MAC_CSR_CMD_CSR_BUSY_))
  396. return 0;
  397. }
  398. SMSC_WARN(pdata, hw, "Timed out waiting for MAC not BUSY. "
  399. "MAC_CSR_CMD: 0x%08X", val);
  400. return -EIO;
  401. }
  402. /* Fetches a MAC register value. Assumes mac_lock is acquired */
  403. static u32 smsc911x_mac_read(struct smsc911x_data *pdata, unsigned int offset)
  404. {
  405. unsigned int temp;
  406. SMSC_ASSERT_MAC_LOCK(pdata);
  407. temp = smsc911x_reg_read(pdata, MAC_CSR_CMD);
  408. if (unlikely(temp & MAC_CSR_CMD_CSR_BUSY_)) {
  409. SMSC_WARN(pdata, hw, "MAC busy at entry");
  410. return 0xFFFFFFFF;
  411. }
  412. /* Send the MAC cmd */
  413. smsc911x_reg_write(pdata, MAC_CSR_CMD, ((offset & 0xFF) |
  414. MAC_CSR_CMD_CSR_BUSY_ | MAC_CSR_CMD_R_NOT_W_));
  415. /* Workaround for hardware read-after-write restriction */
  416. temp = smsc911x_reg_read(pdata, BYTE_TEST);
  417. /* Wait for the read to complete */
  418. if (likely(smsc911x_mac_complete(pdata) == 0))
  419. return smsc911x_reg_read(pdata, MAC_CSR_DATA);
  420. SMSC_WARN(pdata, hw, "MAC busy after read");
  421. return 0xFFFFFFFF;
  422. }
  423. /* Set a mac register, mac_lock must be acquired before calling */
  424. static void smsc911x_mac_write(struct smsc911x_data *pdata,
  425. unsigned int offset, u32 val)
  426. {
  427. unsigned int temp;
  428. SMSC_ASSERT_MAC_LOCK(pdata);
  429. temp = smsc911x_reg_read(pdata, MAC_CSR_CMD);
  430. if (unlikely(temp & MAC_CSR_CMD_CSR_BUSY_)) {
  431. SMSC_WARN(pdata, hw,
  432. "smsc911x_mac_write failed, MAC busy at entry");
  433. return;
  434. }
  435. /* Send data to write */
  436. smsc911x_reg_write(pdata, MAC_CSR_DATA, val);
  437. /* Write the actual data */
  438. smsc911x_reg_write(pdata, MAC_CSR_CMD, ((offset & 0xFF) |
  439. MAC_CSR_CMD_CSR_BUSY_));
  440. /* Workaround for hardware read-after-write restriction */
  441. temp = smsc911x_reg_read(pdata, BYTE_TEST);
  442. /* Wait for the write to complete */
  443. if (likely(smsc911x_mac_complete(pdata) == 0))
  444. return;
  445. SMSC_WARN(pdata, hw, "smsc911x_mac_write failed, MAC busy after write");
  446. }
  447. /* Get a phy register */
  448. static int smsc911x_mii_read(struct mii_bus *bus, int phyaddr, int regidx)
  449. {
  450. struct smsc911x_data *pdata = (struct smsc911x_data *)bus->priv;
  451. unsigned long flags;
  452. unsigned int addr;
  453. int i, reg;
  454. spin_lock_irqsave(&pdata->mac_lock, flags);
  455. /* Confirm MII not busy */
  456. if (unlikely(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
  457. SMSC_WARN(pdata, hw, "MII is busy in smsc911x_mii_read???");
  458. reg = -EIO;
  459. goto out;
  460. }
  461. /* Set the address, index & direction (read from PHY) */
  462. addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6);
  463. smsc911x_mac_write(pdata, MII_ACC, addr);
  464. /* Wait for read to complete w/ timeout */
  465. for (i = 0; i < 100; i++)
  466. if (!(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
  467. reg = smsc911x_mac_read(pdata, MII_DATA);
  468. goto out;
  469. }
  470. SMSC_WARN(pdata, hw, "Timed out waiting for MII read to finish");
  471. reg = -EIO;
  472. out:
  473. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  474. return reg;
  475. }
  476. /* Set a phy register */
  477. static int smsc911x_mii_write(struct mii_bus *bus, int phyaddr, int regidx,
  478. u16 val)
  479. {
  480. struct smsc911x_data *pdata = (struct smsc911x_data *)bus->priv;
  481. unsigned long flags;
  482. unsigned int addr;
  483. int i, reg;
  484. spin_lock_irqsave(&pdata->mac_lock, flags);
  485. /* Confirm MII not busy */
  486. if (unlikely(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
  487. SMSC_WARN(pdata, hw, "MII is busy in smsc911x_mii_write???");
  488. reg = -EIO;
  489. goto out;
  490. }
  491. /* Put the data to write in the MAC */
  492. smsc911x_mac_write(pdata, MII_DATA, val);
  493. /* Set the address, index & direction (write to PHY) */
  494. addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6) |
  495. MII_ACC_MII_WRITE_;
  496. smsc911x_mac_write(pdata, MII_ACC, addr);
  497. /* Wait for write to complete w/ timeout */
  498. for (i = 0; i < 100; i++)
  499. if (!(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
  500. reg = 0;
  501. goto out;
  502. }
  503. SMSC_WARN(pdata, hw, "Timed out waiting for MII write to finish");
  504. reg = -EIO;
  505. out:
  506. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  507. return reg;
  508. }
  509. /* Switch to external phy. Assumes tx and rx are stopped. */
  510. static void smsc911x_phy_enable_external(struct smsc911x_data *pdata)
  511. {
  512. unsigned int hwcfg = smsc911x_reg_read(pdata, HW_CFG);
  513. /* Disable phy clocks to the MAC */
  514. hwcfg &= (~HW_CFG_PHY_CLK_SEL_);
  515. hwcfg |= HW_CFG_PHY_CLK_SEL_CLK_DIS_;
  516. smsc911x_reg_write(pdata, HW_CFG, hwcfg);
  517. udelay(10); /* Enough time for clocks to stop */
  518. /* Switch to external phy */
  519. hwcfg |= HW_CFG_EXT_PHY_EN_;
  520. smsc911x_reg_write(pdata, HW_CFG, hwcfg);
  521. /* Enable phy clocks to the MAC */
  522. hwcfg &= (~HW_CFG_PHY_CLK_SEL_);
  523. hwcfg |= HW_CFG_PHY_CLK_SEL_EXT_PHY_;
  524. smsc911x_reg_write(pdata, HW_CFG, hwcfg);
  525. udelay(10); /* Enough time for clocks to restart */
  526. hwcfg |= HW_CFG_SMI_SEL_;
  527. smsc911x_reg_write(pdata, HW_CFG, hwcfg);
  528. }
  529. /* Autodetects and enables external phy if present on supported chips.
  530. * autodetection can be overridden by specifying SMSC911X_FORCE_INTERNAL_PHY
  531. * or SMSC911X_FORCE_EXTERNAL_PHY in the platform_data flags. */
  532. static void smsc911x_phy_initialise_external(struct smsc911x_data *pdata)
  533. {
  534. unsigned int hwcfg = smsc911x_reg_read(pdata, HW_CFG);
  535. if (pdata->config.flags & SMSC911X_FORCE_INTERNAL_PHY) {
  536. SMSC_TRACE(pdata, hw, "Forcing internal PHY");
  537. pdata->using_extphy = 0;
  538. } else if (pdata->config.flags & SMSC911X_FORCE_EXTERNAL_PHY) {
  539. SMSC_TRACE(pdata, hw, "Forcing external PHY");
  540. smsc911x_phy_enable_external(pdata);
  541. pdata->using_extphy = 1;
  542. } else if (hwcfg & HW_CFG_EXT_PHY_DET_) {
  543. SMSC_TRACE(pdata, hw,
  544. "HW_CFG EXT_PHY_DET set, using external PHY");
  545. smsc911x_phy_enable_external(pdata);
  546. pdata->using_extphy = 1;
  547. } else {
  548. SMSC_TRACE(pdata, hw,
  549. "HW_CFG EXT_PHY_DET clear, using internal PHY");
  550. pdata->using_extphy = 0;
  551. }
  552. }
  553. /* Fetches a tx status out of the status fifo */
  554. static unsigned int smsc911x_tx_get_txstatus(struct smsc911x_data *pdata)
  555. {
  556. unsigned int result =
  557. smsc911x_reg_read(pdata, TX_FIFO_INF) & TX_FIFO_INF_TSUSED_;
  558. if (result != 0)
  559. result = smsc911x_reg_read(pdata, TX_STATUS_FIFO);
  560. return result;
  561. }
  562. /* Fetches the next rx status */
  563. static unsigned int smsc911x_rx_get_rxstatus(struct smsc911x_data *pdata)
  564. {
  565. unsigned int result =
  566. smsc911x_reg_read(pdata, RX_FIFO_INF) & RX_FIFO_INF_RXSUSED_;
  567. if (result != 0)
  568. result = smsc911x_reg_read(pdata, RX_STATUS_FIFO);
  569. return result;
  570. }
  571. #ifdef USE_PHY_WORK_AROUND
  572. static int smsc911x_phy_check_loopbackpkt(struct smsc911x_data *pdata)
  573. {
  574. unsigned int tries;
  575. u32 wrsz;
  576. u32 rdsz;
  577. ulong bufp;
  578. for (tries = 0; tries < 10; tries++) {
  579. unsigned int txcmd_a;
  580. unsigned int txcmd_b;
  581. unsigned int status;
  582. unsigned int pktlength;
  583. unsigned int i;
  584. /* Zero-out rx packet memory */
  585. memset(pdata->loopback_rx_pkt, 0, MIN_PACKET_SIZE);
  586. /* Write tx packet to 118 */
  587. txcmd_a = (u32)((ulong)pdata->loopback_tx_pkt & 0x03) << 16;
  588. txcmd_a |= TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_;
  589. txcmd_a |= MIN_PACKET_SIZE;
  590. txcmd_b = MIN_PACKET_SIZE << 16 | MIN_PACKET_SIZE;
  591. smsc911x_reg_write(pdata, TX_DATA_FIFO, txcmd_a);
  592. smsc911x_reg_write(pdata, TX_DATA_FIFO, txcmd_b);
  593. bufp = (ulong)pdata->loopback_tx_pkt & (~0x3);
  594. wrsz = MIN_PACKET_SIZE + 3;
  595. wrsz += (u32)((ulong)pdata->loopback_tx_pkt & 0x3);
  596. wrsz >>= 2;
  597. pdata->ops->tx_writefifo(pdata, (unsigned int *)bufp, wrsz);
  598. /* Wait till transmit is done */
  599. i = 60;
  600. do {
  601. udelay(5);
  602. status = smsc911x_tx_get_txstatus(pdata);
  603. } while ((i--) && (!status));
  604. if (!status) {
  605. SMSC_WARN(pdata, hw,
  606. "Failed to transmit during loopback test");
  607. continue;
  608. }
  609. if (status & TX_STS_ES_) {
  610. SMSC_WARN(pdata, hw,
  611. "Transmit encountered errors during loopback test");
  612. continue;
  613. }
  614. /* Wait till receive is done */
  615. i = 60;
  616. do {
  617. udelay(5);
  618. status = smsc911x_rx_get_rxstatus(pdata);
  619. } while ((i--) && (!status));
  620. if (!status) {
  621. SMSC_WARN(pdata, hw,
  622. "Failed to receive during loopback test");
  623. continue;
  624. }
  625. if (status & RX_STS_ES_) {
  626. SMSC_WARN(pdata, hw,
  627. "Receive encountered errors during loopback test");
  628. continue;
  629. }
  630. pktlength = ((status & 0x3FFF0000UL) >> 16);
  631. bufp = (ulong)pdata->loopback_rx_pkt;
  632. rdsz = pktlength + 3;
  633. rdsz += (u32)((ulong)pdata->loopback_rx_pkt & 0x3);
  634. rdsz >>= 2;
  635. pdata->ops->rx_readfifo(pdata, (unsigned int *)bufp, rdsz);
  636. if (pktlength != (MIN_PACKET_SIZE + 4)) {
  637. SMSC_WARN(pdata, hw, "Unexpected packet size "
  638. "during loop back test, size=%d, will retry",
  639. pktlength);
  640. } else {
  641. unsigned int j;
  642. int mismatch = 0;
  643. for (j = 0; j < MIN_PACKET_SIZE; j++) {
  644. if (pdata->loopback_tx_pkt[j]
  645. != pdata->loopback_rx_pkt[j]) {
  646. mismatch = 1;
  647. break;
  648. }
  649. }
  650. if (!mismatch) {
  651. SMSC_TRACE(pdata, hw, "Successfully verified "
  652. "loopback packet");
  653. return 0;
  654. } else {
  655. SMSC_WARN(pdata, hw, "Data mismatch "
  656. "during loop back test, will retry");
  657. }
  658. }
  659. }
  660. return -EIO;
  661. }
  662. static int smsc911x_phy_reset(struct smsc911x_data *pdata)
  663. {
  664. struct phy_device *phy_dev = pdata->phy_dev;
  665. unsigned int temp;
  666. unsigned int i = 100000;
  667. BUG_ON(!phy_dev);
  668. BUG_ON(!phy_dev->bus);
  669. SMSC_TRACE(pdata, hw, "Performing PHY BCR Reset");
  670. smsc911x_mii_write(phy_dev->bus, phy_dev->addr, MII_BMCR, BMCR_RESET);
  671. do {
  672. msleep(1);
  673. temp = smsc911x_mii_read(phy_dev->bus, phy_dev->addr,
  674. MII_BMCR);
  675. } while ((i--) && (temp & BMCR_RESET));
  676. if (temp & BMCR_RESET) {
  677. SMSC_WARN(pdata, hw, "PHY reset failed to complete");
  678. return -EIO;
  679. }
  680. /* Extra delay required because the phy may not be completed with
  681. * its reset when BMCR_RESET is cleared. Specs say 256 uS is
  682. * enough delay but using 1ms here to be safe */
  683. msleep(1);
  684. return 0;
  685. }
  686. static int smsc911x_phy_loopbacktest(struct net_device *dev)
  687. {
  688. struct smsc911x_data *pdata = netdev_priv(dev);
  689. struct phy_device *phy_dev = pdata->phy_dev;
  690. int result = -EIO;
  691. unsigned int i, val;
  692. unsigned long flags;
  693. /* Initialise tx packet using broadcast destination address */
  694. memset(pdata->loopback_tx_pkt, 0xff, ETH_ALEN);
  695. /* Use incrementing source address */
  696. for (i = 6; i < 12; i++)
  697. pdata->loopback_tx_pkt[i] = (char)i;
  698. /* Set length type field */
  699. pdata->loopback_tx_pkt[12] = 0x00;
  700. pdata->loopback_tx_pkt[13] = 0x00;
  701. for (i = 14; i < MIN_PACKET_SIZE; i++)
  702. pdata->loopback_tx_pkt[i] = (char)i;
  703. val = smsc911x_reg_read(pdata, HW_CFG);
  704. val &= HW_CFG_TX_FIF_SZ_;
  705. val |= HW_CFG_SF_;
  706. smsc911x_reg_write(pdata, HW_CFG, val);
  707. smsc911x_reg_write(pdata, TX_CFG, TX_CFG_TX_ON_);
  708. smsc911x_reg_write(pdata, RX_CFG,
  709. (u32)((ulong)pdata->loopback_rx_pkt & 0x03) << 8);
  710. for (i = 0; i < 10; i++) {
  711. /* Set PHY to 10/FD, no ANEG, and loopback mode */
  712. smsc911x_mii_write(phy_dev->bus, phy_dev->addr, MII_BMCR,
  713. BMCR_LOOPBACK | BMCR_FULLDPLX);
  714. /* Enable MAC tx/rx, FD */
  715. spin_lock_irqsave(&pdata->mac_lock, flags);
  716. smsc911x_mac_write(pdata, MAC_CR, MAC_CR_FDPX_
  717. | MAC_CR_TXEN_ | MAC_CR_RXEN_);
  718. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  719. if (smsc911x_phy_check_loopbackpkt(pdata) == 0) {
  720. result = 0;
  721. break;
  722. }
  723. pdata->resetcount++;
  724. /* Disable MAC rx */
  725. spin_lock_irqsave(&pdata->mac_lock, flags);
  726. smsc911x_mac_write(pdata, MAC_CR, 0);
  727. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  728. smsc911x_phy_reset(pdata);
  729. }
  730. /* Disable MAC */
  731. spin_lock_irqsave(&pdata->mac_lock, flags);
  732. smsc911x_mac_write(pdata, MAC_CR, 0);
  733. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  734. /* Cancel PHY loopback mode */
  735. smsc911x_mii_write(phy_dev->bus, phy_dev->addr, MII_BMCR, 0);
  736. smsc911x_reg_write(pdata, TX_CFG, 0);
  737. smsc911x_reg_write(pdata, RX_CFG, 0);
  738. return result;
  739. }
  740. #endif /* USE_PHY_WORK_AROUND */
  741. static void smsc911x_phy_update_flowcontrol(struct smsc911x_data *pdata)
  742. {
  743. struct phy_device *phy_dev = pdata->phy_dev;
  744. u32 afc = smsc911x_reg_read(pdata, AFC_CFG);
  745. u32 flow;
  746. unsigned long flags;
  747. if (phy_dev->duplex == DUPLEX_FULL) {
  748. u16 lcladv = phy_read(phy_dev, MII_ADVERTISE);
  749. u16 rmtadv = phy_read(phy_dev, MII_LPA);
  750. u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
  751. if (cap & FLOW_CTRL_RX)
  752. flow = 0xFFFF0002;
  753. else
  754. flow = 0;
  755. if (cap & FLOW_CTRL_TX)
  756. afc |= 0xF;
  757. else
  758. afc &= ~0xF;
  759. SMSC_TRACE(pdata, hw, "rx pause %s, tx pause %s",
  760. (cap & FLOW_CTRL_RX ? "enabled" : "disabled"),
  761. (cap & FLOW_CTRL_TX ? "enabled" : "disabled"));
  762. } else {
  763. SMSC_TRACE(pdata, hw, "half duplex");
  764. flow = 0;
  765. afc |= 0xF;
  766. }
  767. spin_lock_irqsave(&pdata->mac_lock, flags);
  768. smsc911x_mac_write(pdata, FLOW, flow);
  769. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  770. smsc911x_reg_write(pdata, AFC_CFG, afc);
  771. }
  772. /* Update link mode if anything has changed. Called periodically when the
  773. * PHY is in polling mode, even if nothing has changed. */
  774. static void smsc911x_phy_adjust_link(struct net_device *dev)
  775. {
  776. struct smsc911x_data *pdata = netdev_priv(dev);
  777. struct phy_device *phy_dev = pdata->phy_dev;
  778. unsigned long flags;
  779. int carrier;
  780. if (phy_dev->duplex != pdata->last_duplex) {
  781. unsigned int mac_cr;
  782. SMSC_TRACE(pdata, hw, "duplex state has changed");
  783. spin_lock_irqsave(&pdata->mac_lock, flags);
  784. mac_cr = smsc911x_mac_read(pdata, MAC_CR);
  785. if (phy_dev->duplex) {
  786. SMSC_TRACE(pdata, hw,
  787. "configuring for full duplex mode");
  788. mac_cr |= MAC_CR_FDPX_;
  789. } else {
  790. SMSC_TRACE(pdata, hw,
  791. "configuring for half duplex mode");
  792. mac_cr &= ~MAC_CR_FDPX_;
  793. }
  794. smsc911x_mac_write(pdata, MAC_CR, mac_cr);
  795. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  796. smsc911x_phy_update_flowcontrol(pdata);
  797. pdata->last_duplex = phy_dev->duplex;
  798. }
  799. carrier = netif_carrier_ok(dev);
  800. if (carrier != pdata->last_carrier) {
  801. SMSC_TRACE(pdata, hw, "carrier state has changed");
  802. if (carrier) {
  803. SMSC_TRACE(pdata, hw, "configuring for carrier OK");
  804. if ((pdata->gpio_orig_setting & GPIO_CFG_LED1_EN_) &&
  805. (!pdata->using_extphy)) {
  806. /* Restore original GPIO configuration */
  807. pdata->gpio_setting = pdata->gpio_orig_setting;
  808. smsc911x_reg_write(pdata, GPIO_CFG,
  809. pdata->gpio_setting);
  810. }
  811. } else {
  812. SMSC_TRACE(pdata, hw, "configuring for no carrier");
  813. /* Check global setting that LED1
  814. * usage is 10/100 indicator */
  815. pdata->gpio_setting = smsc911x_reg_read(pdata,
  816. GPIO_CFG);
  817. if ((pdata->gpio_setting & GPIO_CFG_LED1_EN_) &&
  818. (!pdata->using_extphy)) {
  819. /* Force 10/100 LED off, after saving
  820. * original GPIO configuration */
  821. pdata->gpio_orig_setting = pdata->gpio_setting;
  822. pdata->gpio_setting &= ~GPIO_CFG_LED1_EN_;
  823. pdata->gpio_setting |= (GPIO_CFG_GPIOBUF0_
  824. | GPIO_CFG_GPIODIR0_
  825. | GPIO_CFG_GPIOD0_);
  826. smsc911x_reg_write(pdata, GPIO_CFG,
  827. pdata->gpio_setting);
  828. }
  829. }
  830. pdata->last_carrier = carrier;
  831. }
  832. }
  833. static int smsc911x_mii_probe(struct net_device *dev)
  834. {
  835. struct smsc911x_data *pdata = netdev_priv(dev);
  836. struct phy_device *phydev = NULL;
  837. int ret;
  838. /* find the first phy */
  839. phydev = phy_find_first(pdata->mii_bus);
  840. if (!phydev) {
  841. netdev_err(dev, "no PHY found\n");
  842. return -ENODEV;
  843. }
  844. SMSC_TRACE(pdata, probe, "PHY: addr %d, phy_id 0x%08X",
  845. phydev->addr, phydev->phy_id);
  846. ret = phy_connect_direct(dev, phydev, &smsc911x_phy_adjust_link,
  847. pdata->config.phy_interface);
  848. if (ret) {
  849. netdev_err(dev, "Could not attach to PHY\n");
  850. return ret;
  851. }
  852. netdev_info(dev,
  853. "attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
  854. phydev->drv->name, dev_name(&phydev->dev), phydev->irq);
  855. /* mask with MAC supported features */
  856. phydev->supported &= (PHY_BASIC_FEATURES | SUPPORTED_Pause |
  857. SUPPORTED_Asym_Pause);
  858. phydev->advertising = phydev->supported;
  859. pdata->phy_dev = phydev;
  860. pdata->last_duplex = -1;
  861. pdata->last_carrier = -1;
  862. #ifdef USE_PHY_WORK_AROUND
  863. if (smsc911x_phy_loopbacktest(dev) < 0) {
  864. SMSC_WARN(pdata, hw, "Failed Loop Back Test");
  865. return -ENODEV;
  866. }
  867. SMSC_TRACE(pdata, hw, "Passed Loop Back Test");
  868. #endif /* USE_PHY_WORK_AROUND */
  869. SMSC_TRACE(pdata, hw, "phy initialised successfully");
  870. return 0;
  871. }
  872. static int smsc911x_mii_init(struct platform_device *pdev,
  873. struct net_device *dev)
  874. {
  875. struct smsc911x_data *pdata = netdev_priv(dev);
  876. int err = -ENXIO, i;
  877. pdata->mii_bus = mdiobus_alloc();
  878. if (!pdata->mii_bus) {
  879. err = -ENOMEM;
  880. goto err_out_1;
  881. }
  882. pdata->mii_bus->name = SMSC_MDIONAME;
  883. snprintf(pdata->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
  884. pdev->name, pdev->id);
  885. pdata->mii_bus->priv = pdata;
  886. pdata->mii_bus->read = smsc911x_mii_read;
  887. pdata->mii_bus->write = smsc911x_mii_write;
  888. pdata->mii_bus->irq = pdata->phy_irq;
  889. for (i = 0; i < PHY_MAX_ADDR; ++i)
  890. pdata->mii_bus->irq[i] = PHY_POLL;
  891. pdata->mii_bus->parent = &pdev->dev;
  892. switch (pdata->idrev & 0xFFFF0000) {
  893. case 0x01170000:
  894. case 0x01150000:
  895. case 0x117A0000:
  896. case 0x115A0000:
  897. /* External PHY supported, try to autodetect */
  898. smsc911x_phy_initialise_external(pdata);
  899. break;
  900. default:
  901. SMSC_TRACE(pdata, hw, "External PHY is not supported, "
  902. "using internal PHY");
  903. pdata->using_extphy = 0;
  904. break;
  905. }
  906. if (!pdata->using_extphy) {
  907. /* Mask all PHYs except ID 1 (internal) */
  908. pdata->mii_bus->phy_mask = ~(1 << 1);
  909. }
  910. if (mdiobus_register(pdata->mii_bus)) {
  911. SMSC_WARN(pdata, probe, "Error registering mii bus");
  912. goto err_out_free_bus_2;
  913. }
  914. if (smsc911x_mii_probe(dev) < 0) {
  915. SMSC_WARN(pdata, probe, "Error registering mii bus");
  916. goto err_out_unregister_bus_3;
  917. }
  918. return 0;
  919. err_out_unregister_bus_3:
  920. mdiobus_unregister(pdata->mii_bus);
  921. err_out_free_bus_2:
  922. mdiobus_free(pdata->mii_bus);
  923. err_out_1:
  924. return err;
  925. }
  926. /* Gets the number of tx statuses in the fifo */
  927. static unsigned int smsc911x_tx_get_txstatcount(struct smsc911x_data *pdata)
  928. {
  929. return (smsc911x_reg_read(pdata, TX_FIFO_INF)
  930. & TX_FIFO_INF_TSUSED_) >> 16;
  931. }
  932. /* Reads tx statuses and increments counters where necessary */
  933. static void smsc911x_tx_update_txcounters(struct net_device *dev)
  934. {
  935. struct smsc911x_data *pdata = netdev_priv(dev);
  936. unsigned int tx_stat;
  937. while ((tx_stat = smsc911x_tx_get_txstatus(pdata)) != 0) {
  938. if (unlikely(tx_stat & 0x80000000)) {
  939. /* In this driver the packet tag is used as the packet
  940. * length. Since a packet length can never reach the
  941. * size of 0x8000, this bit is reserved. It is worth
  942. * noting that the "reserved bit" in the warning above
  943. * does not reference a hardware defined reserved bit
  944. * but rather a driver defined one.
  945. */
  946. SMSC_WARN(pdata, hw, "Packet tag reserved bit is high");
  947. } else {
  948. if (unlikely(tx_stat & TX_STS_ES_)) {
  949. dev->stats.tx_errors++;
  950. } else {
  951. dev->stats.tx_packets++;
  952. dev->stats.tx_bytes += (tx_stat >> 16);
  953. }
  954. if (unlikely(tx_stat & TX_STS_EXCESS_COL_)) {
  955. dev->stats.collisions += 16;
  956. dev->stats.tx_aborted_errors += 1;
  957. } else {
  958. dev->stats.collisions +=
  959. ((tx_stat >> 3) & 0xF);
  960. }
  961. if (unlikely(tx_stat & TX_STS_LOST_CARRIER_))
  962. dev->stats.tx_carrier_errors += 1;
  963. if (unlikely(tx_stat & TX_STS_LATE_COL_)) {
  964. dev->stats.collisions++;
  965. dev->stats.tx_aborted_errors++;
  966. }
  967. }
  968. }
  969. }
  970. /* Increments the Rx error counters */
  971. static void
  972. smsc911x_rx_counterrors(struct net_device *dev, unsigned int rxstat)
  973. {
  974. int crc_err = 0;
  975. if (unlikely(rxstat & RX_STS_ES_)) {
  976. dev->stats.rx_errors++;
  977. if (unlikely(rxstat & RX_STS_CRC_ERR_)) {
  978. dev->stats.rx_crc_errors++;
  979. crc_err = 1;
  980. }
  981. }
  982. if (likely(!crc_err)) {
  983. if (unlikely((rxstat & RX_STS_FRAME_TYPE_) &&
  984. (rxstat & RX_STS_LENGTH_ERR_)))
  985. dev->stats.rx_length_errors++;
  986. if (rxstat & RX_STS_MCAST_)
  987. dev->stats.multicast++;
  988. }
  989. }
  990. /* Quickly dumps bad packets */
  991. static void
  992. smsc911x_rx_fastforward(struct smsc911x_data *pdata, unsigned int pktwords)
  993. {
  994. if (likely(pktwords >= 4)) {
  995. unsigned int timeout = 500;
  996. unsigned int val;
  997. smsc911x_reg_write(pdata, RX_DP_CTRL, RX_DP_CTRL_RX_FFWD_);
  998. do {
  999. udelay(1);
  1000. val = smsc911x_reg_read(pdata, RX_DP_CTRL);
  1001. } while ((val & RX_DP_CTRL_RX_FFWD_) && --timeout);
  1002. if (unlikely(timeout == 0))
  1003. SMSC_WARN(pdata, hw, "Timed out waiting for "
  1004. "RX FFWD to finish, RX_DP_CTRL: 0x%08X", val);
  1005. } else {
  1006. unsigned int temp;
  1007. while (pktwords--)
  1008. temp = smsc911x_reg_read(pdata, RX_DATA_FIFO);
  1009. }
  1010. }
  1011. /* NAPI poll function */
  1012. static int smsc911x_poll(struct napi_struct *napi, int budget)
  1013. {
  1014. struct smsc911x_data *pdata =
  1015. container_of(napi, struct smsc911x_data, napi);
  1016. struct net_device *dev = pdata->dev;
  1017. int npackets = 0;
  1018. while (npackets < budget) {
  1019. unsigned int pktlength;
  1020. unsigned int pktwords;
  1021. struct sk_buff *skb;
  1022. unsigned int rxstat = smsc911x_rx_get_rxstatus(pdata);
  1023. if (!rxstat) {
  1024. unsigned int temp;
  1025. /* We processed all packets available. Tell NAPI it can
  1026. * stop polling then re-enable rx interrupts */
  1027. smsc911x_reg_write(pdata, INT_STS, INT_STS_RSFL_);
  1028. napi_complete(napi);
  1029. temp = smsc911x_reg_read(pdata, INT_EN);
  1030. temp |= INT_EN_RSFL_EN_;
  1031. smsc911x_reg_write(pdata, INT_EN, temp);
  1032. break;
  1033. }
  1034. /* Count packet for NAPI scheduling, even if it has an error.
  1035. * Error packets still require cycles to discard */
  1036. npackets++;
  1037. pktlength = ((rxstat & 0x3FFF0000) >> 16);
  1038. pktwords = (pktlength + NET_IP_ALIGN + 3) >> 2;
  1039. smsc911x_rx_counterrors(dev, rxstat);
  1040. if (unlikely(rxstat & RX_STS_ES_)) {
  1041. SMSC_WARN(pdata, rx_err,
  1042. "Discarding packet with error bit set");
  1043. /* Packet has an error, discard it and continue with
  1044. * the next */
  1045. smsc911x_rx_fastforward(pdata, pktwords);
  1046. dev->stats.rx_dropped++;
  1047. continue;
  1048. }
  1049. skb = netdev_alloc_skb(dev, pktwords << 2);
  1050. if (unlikely(!skb)) {
  1051. SMSC_WARN(pdata, rx_err,
  1052. "Unable to allocate skb for rx packet");
  1053. /* Drop the packet and stop this polling iteration */
  1054. smsc911x_rx_fastforward(pdata, pktwords);
  1055. dev->stats.rx_dropped++;
  1056. break;
  1057. }
  1058. pdata->ops->rx_readfifo(pdata,
  1059. (unsigned int *)skb->data, pktwords);
  1060. /* Align IP on 16B boundary */
  1061. skb_reserve(skb, NET_IP_ALIGN);
  1062. skb_put(skb, pktlength - 4);
  1063. skb->protocol = eth_type_trans(skb, dev);
  1064. skb_checksum_none_assert(skb);
  1065. netif_receive_skb(skb);
  1066. /* Update counters */
  1067. dev->stats.rx_packets++;
  1068. dev->stats.rx_bytes += (pktlength - 4);
  1069. }
  1070. /* Return total received packets */
  1071. return npackets;
  1072. }
  1073. /* Returns hash bit number for given MAC address
  1074. * Example:
  1075. * 01 00 5E 00 00 01 -> returns bit number 31 */
  1076. static unsigned int smsc911x_hash(char addr[ETH_ALEN])
  1077. {
  1078. return (ether_crc(ETH_ALEN, addr) >> 26) & 0x3f;
  1079. }
  1080. static void smsc911x_rx_multicast_update(struct smsc911x_data *pdata)
  1081. {
  1082. /* Performs the multicast & mac_cr update. This is called when
  1083. * safe on the current hardware, and with the mac_lock held */
  1084. unsigned int mac_cr;
  1085. SMSC_ASSERT_MAC_LOCK(pdata);
  1086. mac_cr = smsc911x_mac_read(pdata, MAC_CR);
  1087. mac_cr |= pdata->set_bits_mask;
  1088. mac_cr &= ~(pdata->clear_bits_mask);
  1089. smsc911x_mac_write(pdata, MAC_CR, mac_cr);
  1090. smsc911x_mac_write(pdata, HASHH, pdata->hashhi);
  1091. smsc911x_mac_write(pdata, HASHL, pdata->hashlo);
  1092. SMSC_TRACE(pdata, hw, "maccr 0x%08X, HASHH 0x%08X, HASHL 0x%08X",
  1093. mac_cr, pdata->hashhi, pdata->hashlo);
  1094. }
  1095. static void smsc911x_rx_multicast_update_workaround(struct smsc911x_data *pdata)
  1096. {
  1097. unsigned int mac_cr;
  1098. /* This function is only called for older LAN911x devices
  1099. * (revA or revB), where MAC_CR, HASHH and HASHL should not
  1100. * be modified during Rx - newer devices immediately update the
  1101. * registers.
  1102. *
  1103. * This is called from interrupt context */
  1104. spin_lock(&pdata->mac_lock);
  1105. /* Check Rx has stopped */
  1106. if (smsc911x_mac_read(pdata, MAC_CR) & MAC_CR_RXEN_)
  1107. SMSC_WARN(pdata, drv, "Rx not stopped");
  1108. /* Perform the update - safe to do now Rx has stopped */
  1109. smsc911x_rx_multicast_update(pdata);
  1110. /* Re-enable Rx */
  1111. mac_cr = smsc911x_mac_read(pdata, MAC_CR);
  1112. mac_cr |= MAC_CR_RXEN_;
  1113. smsc911x_mac_write(pdata, MAC_CR, mac_cr);
  1114. pdata->multicast_update_pending = 0;
  1115. spin_unlock(&pdata->mac_lock);
  1116. }
  1117. static int smsc911x_phy_disable_energy_detect(struct smsc911x_data *pdata)
  1118. {
  1119. int rc = 0;
  1120. if (!pdata->phy_dev)
  1121. return rc;
  1122. rc = phy_read(pdata->phy_dev, MII_LAN83C185_CTRL_STATUS);
  1123. if (rc < 0) {
  1124. SMSC_WARN(pdata, drv, "Failed reading PHY control reg");
  1125. return rc;
  1126. }
  1127. /*
  1128. * If energy is detected the PHY is already awake so is not necessary
  1129. * to disable the energy detect power-down mode.
  1130. */
  1131. if ((rc & MII_LAN83C185_EDPWRDOWN) &&
  1132. !(rc & MII_LAN83C185_ENERGYON)) {
  1133. /* Disable energy detect mode for this SMSC Transceivers */
  1134. rc = phy_write(pdata->phy_dev, MII_LAN83C185_CTRL_STATUS,
  1135. rc & (~MII_LAN83C185_EDPWRDOWN));
  1136. if (rc < 0) {
  1137. SMSC_WARN(pdata, drv, "Failed writing PHY control reg");
  1138. return rc;
  1139. }
  1140. mdelay(1);
  1141. }
  1142. return 0;
  1143. }
  1144. static int smsc911x_phy_enable_energy_detect(struct smsc911x_data *pdata)
  1145. {
  1146. int rc = 0;
  1147. if (!pdata->phy_dev)
  1148. return rc;
  1149. rc = phy_read(pdata->phy_dev, MII_LAN83C185_CTRL_STATUS);
  1150. if (rc < 0) {
  1151. SMSC_WARN(pdata, drv, "Failed reading PHY control reg");
  1152. return rc;
  1153. }
  1154. /* Only enable if energy detect mode is already disabled */
  1155. if (!(rc & MII_LAN83C185_EDPWRDOWN)) {
  1156. mdelay(100);
  1157. /* Enable energy detect mode for this SMSC Transceivers */
  1158. rc = phy_write(pdata->phy_dev, MII_LAN83C185_CTRL_STATUS,
  1159. rc | MII_LAN83C185_EDPWRDOWN);
  1160. if (rc < 0) {
  1161. SMSC_WARN(pdata, drv, "Failed writing PHY control reg");
  1162. return rc;
  1163. }
  1164. mdelay(1);
  1165. }
  1166. return 0;
  1167. }
  1168. static int smsc911x_soft_reset(struct smsc911x_data *pdata)
  1169. {
  1170. unsigned int timeout;
  1171. unsigned int temp;
  1172. int ret;
  1173. /*
  1174. * LAN9210/LAN9211/LAN9220/LAN9221 chips have an internal PHY that
  1175. * are initialized in a Energy Detect Power-Down mode that prevents
  1176. * the MAC chip to be software reseted. So we have to wakeup the PHY
  1177. * before.
  1178. */
  1179. if (pdata->generation == 4) {
  1180. ret = smsc911x_phy_disable_energy_detect(pdata);
  1181. if (ret) {
  1182. SMSC_WARN(pdata, drv, "Failed to wakeup the PHY chip");
  1183. return ret;
  1184. }
  1185. }
  1186. /* Reset the LAN911x */
  1187. smsc911x_reg_write(pdata, HW_CFG, HW_CFG_SRST_);
  1188. timeout = 10;
  1189. do {
  1190. udelay(10);
  1191. temp = smsc911x_reg_read(pdata, HW_CFG);
  1192. } while ((--timeout) && (temp & HW_CFG_SRST_));
  1193. if (unlikely(temp & HW_CFG_SRST_)) {
  1194. SMSC_WARN(pdata, drv, "Failed to complete reset");
  1195. return -EIO;
  1196. }
  1197. if (pdata->generation == 4) {
  1198. ret = smsc911x_phy_enable_energy_detect(pdata);
  1199. if (ret) {
  1200. SMSC_WARN(pdata, drv, "Failed to wakeup the PHY chip");
  1201. return ret;
  1202. }
  1203. }
  1204. return 0;
  1205. }
  1206. /* Sets the device MAC address to dev_addr, called with mac_lock held */
  1207. static void
  1208. smsc911x_set_hw_mac_address(struct smsc911x_data *pdata, u8 dev_addr[6])
  1209. {
  1210. u32 mac_high16 = (dev_addr[5] << 8) | dev_addr[4];
  1211. u32 mac_low32 = (dev_addr[3] << 24) | (dev_addr[2] << 16) |
  1212. (dev_addr[1] << 8) | dev_addr[0];
  1213. SMSC_ASSERT_MAC_LOCK(pdata);
  1214. smsc911x_mac_write(pdata, ADDRH, mac_high16);
  1215. smsc911x_mac_write(pdata, ADDRL, mac_low32);
  1216. }
  1217. static void smsc911x_disable_irq_chip(struct net_device *dev)
  1218. {
  1219. struct smsc911x_data *pdata = netdev_priv(dev);
  1220. smsc911x_reg_write(pdata, INT_EN, 0);
  1221. smsc911x_reg_write(pdata, INT_STS, 0xFFFFFFFF);
  1222. }
  1223. static int smsc911x_open(struct net_device *dev)
  1224. {
  1225. struct smsc911x_data *pdata = netdev_priv(dev);
  1226. unsigned int timeout;
  1227. unsigned int temp;
  1228. unsigned int intcfg;
  1229. /* if the phy is not yet registered, retry later*/
  1230. if (!pdata->phy_dev) {
  1231. SMSC_WARN(pdata, hw, "phy_dev is NULL");
  1232. return -EAGAIN;
  1233. }
  1234. /* Reset the LAN911x */
  1235. if (smsc911x_soft_reset(pdata)) {
  1236. SMSC_WARN(pdata, hw, "soft reset failed");
  1237. return -EIO;
  1238. }
  1239. smsc911x_reg_write(pdata, HW_CFG, 0x00050000);
  1240. smsc911x_reg_write(pdata, AFC_CFG, 0x006E3740);
  1241. /* Increase the legal frame size of VLAN tagged frames to 1522 bytes */
  1242. spin_lock_irq(&pdata->mac_lock);
  1243. smsc911x_mac_write(pdata, VLAN1, ETH_P_8021Q);
  1244. spin_unlock_irq(&pdata->mac_lock);
  1245. /* Make sure EEPROM has finished loading before setting GPIO_CFG */
  1246. timeout = 50;
  1247. while ((smsc911x_reg_read(pdata, E2P_CMD) & E2P_CMD_EPC_BUSY_) &&
  1248. --timeout) {
  1249. udelay(10);
  1250. }
  1251. if (unlikely(timeout == 0))
  1252. SMSC_WARN(pdata, ifup,
  1253. "Timed out waiting for EEPROM busy bit to clear");
  1254. smsc911x_reg_write(pdata, GPIO_CFG, 0x70070000);
  1255. /* The soft reset above cleared the device's MAC address,
  1256. * restore it from local copy (set in probe) */
  1257. spin_lock_irq(&pdata->mac_lock);
  1258. smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
  1259. spin_unlock_irq(&pdata->mac_lock);
  1260. /* Initialise irqs, but leave all sources disabled */
  1261. smsc911x_disable_irq_chip(dev);
  1262. /* Set interrupt deassertion to 100uS */
  1263. intcfg = ((10 << 24) | INT_CFG_IRQ_EN_);
  1264. if (pdata->config.irq_polarity) {
  1265. SMSC_TRACE(pdata, ifup, "irq polarity: active high");
  1266. intcfg |= INT_CFG_IRQ_POL_;
  1267. } else {
  1268. SMSC_TRACE(pdata, ifup, "irq polarity: active low");
  1269. }
  1270. if (pdata->config.irq_type) {
  1271. SMSC_TRACE(pdata, ifup, "irq type: push-pull");
  1272. intcfg |= INT_CFG_IRQ_TYPE_;
  1273. } else {
  1274. SMSC_TRACE(pdata, ifup, "irq type: open drain");
  1275. }
  1276. smsc911x_reg_write(pdata, INT_CFG, intcfg);
  1277. SMSC_TRACE(pdata, ifup, "Testing irq handler using IRQ %d", dev->irq);
  1278. pdata->software_irq_signal = 0;
  1279. smp_wmb();
  1280. temp = smsc911x_reg_read(pdata, INT_EN);
  1281. temp |= INT_EN_SW_INT_EN_;
  1282. smsc911x_reg_write(pdata, INT_EN, temp);
  1283. timeout = 1000;
  1284. while (timeout--) {
  1285. if (pdata->software_irq_signal)
  1286. break;
  1287. msleep(1);
  1288. }
  1289. if (!pdata->software_irq_signal) {
  1290. netdev_warn(dev, "ISR failed signaling test (IRQ %d)\n",
  1291. dev->irq);
  1292. return -ENODEV;
  1293. }
  1294. SMSC_TRACE(pdata, ifup, "IRQ handler passed test using IRQ %d",
  1295. dev->irq);
  1296. netdev_info(dev, "SMSC911x/921x identified at %#08lx, IRQ: %d\n",
  1297. (unsigned long)pdata->ioaddr, dev->irq);
  1298. /* Reset the last known duplex and carrier */
  1299. pdata->last_duplex = -1;
  1300. pdata->last_carrier = -1;
  1301. /* Bring the PHY up */
  1302. phy_start(pdata->phy_dev);
  1303. temp = smsc911x_reg_read(pdata, HW_CFG);
  1304. /* Preserve TX FIFO size and external PHY configuration */
  1305. temp &= (HW_CFG_TX_FIF_SZ_|0x00000FFF);
  1306. temp |= HW_CFG_SF_;
  1307. smsc911x_reg_write(pdata, HW_CFG, temp);
  1308. temp = smsc911x_reg_read(pdata, FIFO_INT);
  1309. temp |= FIFO_INT_TX_AVAIL_LEVEL_;
  1310. temp &= ~(FIFO_INT_RX_STS_LEVEL_);
  1311. smsc911x_reg_write(pdata, FIFO_INT, temp);
  1312. /* set RX Data offset to 2 bytes for alignment */
  1313. smsc911x_reg_write(pdata, RX_CFG, (NET_IP_ALIGN << 8));
  1314. /* enable NAPI polling before enabling RX interrupts */
  1315. napi_enable(&pdata->napi);
  1316. temp = smsc911x_reg_read(pdata, INT_EN);
  1317. temp |= (INT_EN_TDFA_EN_ | INT_EN_RSFL_EN_ | INT_EN_RXSTOP_INT_EN_);
  1318. smsc911x_reg_write(pdata, INT_EN, temp);
  1319. spin_lock_irq(&pdata->mac_lock);
  1320. temp = smsc911x_mac_read(pdata, MAC_CR);
  1321. temp |= (MAC_CR_TXEN_ | MAC_CR_RXEN_ | MAC_CR_HBDIS_);
  1322. smsc911x_mac_write(pdata, MAC_CR, temp);
  1323. spin_unlock_irq(&pdata->mac_lock);
  1324. smsc911x_reg_write(pdata, TX_CFG, TX_CFG_TX_ON_);
  1325. netif_start_queue(dev);
  1326. return 0;
  1327. }
  1328. /* Entry point for stopping the interface */
  1329. static int smsc911x_stop(struct net_device *dev)
  1330. {
  1331. struct smsc911x_data *pdata = netdev_priv(dev);
  1332. unsigned int temp;
  1333. /* Disable all device interrupts */
  1334. temp = smsc911x_reg_read(pdata, INT_CFG);
  1335. temp &= ~INT_CFG_IRQ_EN_;
  1336. smsc911x_reg_write(pdata, INT_CFG, temp);
  1337. /* Stop Tx and Rx polling */
  1338. netif_stop_queue(dev);
  1339. napi_disable(&pdata->napi);
  1340. /* At this point all Rx and Tx activity is stopped */
  1341. dev->stats.rx_dropped += smsc911x_reg_read(pdata, RX_DROP);
  1342. smsc911x_tx_update_txcounters(dev);
  1343. /* Bring the PHY down */
  1344. if (pdata->phy_dev)
  1345. phy_stop(pdata->phy_dev);
  1346. SMSC_TRACE(pdata, ifdown, "Interface stopped");
  1347. return 0;
  1348. }
  1349. /* Entry point for transmitting a packet */
  1350. static int smsc911x_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
  1351. {
  1352. struct smsc911x_data *pdata = netdev_priv(dev);
  1353. unsigned int freespace;
  1354. unsigned int tx_cmd_a;
  1355. unsigned int tx_cmd_b;
  1356. unsigned int temp;
  1357. u32 wrsz;
  1358. ulong bufp;
  1359. freespace = smsc911x_reg_read(pdata, TX_FIFO_INF) & TX_FIFO_INF_TDFREE_;
  1360. if (unlikely(freespace < TX_FIFO_LOW_THRESHOLD))
  1361. SMSC_WARN(pdata, tx_err,
  1362. "Tx data fifo low, space available: %d", freespace);
  1363. /* Word alignment adjustment */
  1364. tx_cmd_a = (u32)((ulong)skb->data & 0x03) << 16;
  1365. tx_cmd_a |= TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_;
  1366. tx_cmd_a |= (unsigned int)skb->len;
  1367. tx_cmd_b = ((unsigned int)skb->len) << 16;
  1368. tx_cmd_b |= (unsigned int)skb->len;
  1369. smsc911x_reg_write(pdata, TX_DATA_FIFO, tx_cmd_a);
  1370. smsc911x_reg_write(pdata, TX_DATA_FIFO, tx_cmd_b);
  1371. bufp = (ulong)skb->data & (~0x3);
  1372. wrsz = (u32)skb->len + 3;
  1373. wrsz += (u32)((ulong)skb->data & 0x3);
  1374. wrsz >>= 2;
  1375. pdata->ops->tx_writefifo(pdata, (unsigned int *)bufp, wrsz);
  1376. freespace -= (skb->len + 32);
  1377. skb_tx_timestamp(skb);
  1378. dev_kfree_skb(skb);
  1379. if (unlikely(smsc911x_tx_get_txstatcount(pdata) >= 30))
  1380. smsc911x_tx_update_txcounters(dev);
  1381. if (freespace < TX_FIFO_LOW_THRESHOLD) {
  1382. netif_stop_queue(dev);
  1383. temp = smsc911x_reg_read(pdata, FIFO_INT);
  1384. temp &= 0x00FFFFFF;
  1385. temp |= 0x32000000;
  1386. smsc911x_reg_write(pdata, FIFO_INT, temp);
  1387. }
  1388. return NETDEV_TX_OK;
  1389. }
  1390. /* Entry point for getting status counters */
  1391. static struct net_device_stats *smsc911x_get_stats(struct net_device *dev)
  1392. {
  1393. struct smsc911x_data *pdata = netdev_priv(dev);
  1394. smsc911x_tx_update_txcounters(dev);
  1395. dev->stats.rx_dropped += smsc911x_reg_read(pdata, RX_DROP);
  1396. return &dev->stats;
  1397. }
  1398. /* Entry point for setting addressing modes */
  1399. static void smsc911x_set_multicast_list(struct net_device *dev)
  1400. {
  1401. struct smsc911x_data *pdata = netdev_priv(dev);
  1402. unsigned long flags;
  1403. if (dev->flags & IFF_PROMISC) {
  1404. /* Enabling promiscuous mode */
  1405. pdata->set_bits_mask = MAC_CR_PRMS_;
  1406. pdata->clear_bits_mask = (MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
  1407. pdata->hashhi = 0;
  1408. pdata->hashlo = 0;
  1409. } else if (dev->flags & IFF_ALLMULTI) {
  1410. /* Enabling all multicast mode */
  1411. pdata->set_bits_mask = MAC_CR_MCPAS_;
  1412. pdata->clear_bits_mask = (MAC_CR_PRMS_ | MAC_CR_HPFILT_);
  1413. pdata->hashhi = 0;
  1414. pdata->hashlo = 0;
  1415. } else if (!netdev_mc_empty(dev)) {
  1416. /* Enabling specific multicast addresses */
  1417. unsigned int hash_high = 0;
  1418. unsigned int hash_low = 0;
  1419. struct netdev_hw_addr *ha;
  1420. pdata->set_bits_mask = MAC_CR_HPFILT_;
  1421. pdata->clear_bits_mask = (MAC_CR_PRMS_ | MAC_CR_MCPAS_);
  1422. netdev_for_each_mc_addr(ha, dev) {
  1423. unsigned int bitnum = smsc911x_hash(ha->addr);
  1424. unsigned int mask = 0x01 << (bitnum & 0x1F);
  1425. if (bitnum & 0x20)
  1426. hash_high |= mask;
  1427. else
  1428. hash_low |= mask;
  1429. }
  1430. pdata->hashhi = hash_high;
  1431. pdata->hashlo = hash_low;
  1432. } else {
  1433. /* Enabling local MAC address only */
  1434. pdata->set_bits_mask = 0;
  1435. pdata->clear_bits_mask =
  1436. (MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
  1437. pdata->hashhi = 0;
  1438. pdata->hashlo = 0;
  1439. }
  1440. spin_lock_irqsave(&pdata->mac_lock, flags);
  1441. if (pdata->generation <= 1) {
  1442. /* Older hardware revision - cannot change these flags while
  1443. * receiving data */
  1444. if (!pdata->multicast_update_pending) {
  1445. unsigned int temp;
  1446. SMSC_TRACE(pdata, hw, "scheduling mcast update");
  1447. pdata->multicast_update_pending = 1;
  1448. /* Request the hardware to stop, then perform the
  1449. * update when we get an RX_STOP interrupt */
  1450. temp = smsc911x_mac_read(pdata, MAC_CR);
  1451. temp &= ~(MAC_CR_RXEN_);
  1452. smsc911x_mac_write(pdata, MAC_CR, temp);
  1453. } else {
  1454. /* There is another update pending, this should now
  1455. * use the newer values */
  1456. }
  1457. } else {
  1458. /* Newer hardware revision - can write immediately */
  1459. smsc911x_rx_multicast_update(pdata);
  1460. }
  1461. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  1462. }
  1463. static irqreturn_t smsc911x_irqhandler(int irq, void *dev_id)
  1464. {
  1465. struct net_device *dev = dev_id;
  1466. struct smsc911x_data *pdata = netdev_priv(dev);
  1467. u32 intsts = smsc911x_reg_read(pdata, INT_STS);
  1468. u32 inten = smsc911x_reg_read(pdata, INT_EN);
  1469. int serviced = IRQ_NONE;
  1470. u32 temp;
  1471. if (unlikely(intsts & inten & INT_STS_SW_INT_)) {
  1472. temp = smsc911x_reg_read(pdata, INT_EN);
  1473. temp &= (~INT_EN_SW_INT_EN_);
  1474. smsc911x_reg_write(pdata, INT_EN, temp);
  1475. smsc911x_reg_write(pdata, INT_STS, INT_STS_SW_INT_);
  1476. pdata->software_irq_signal = 1;
  1477. smp_wmb();
  1478. serviced = IRQ_HANDLED;
  1479. }
  1480. if (unlikely(intsts & inten & INT_STS_RXSTOP_INT_)) {
  1481. /* Called when there is a multicast update scheduled and
  1482. * it is now safe to complete the update */
  1483. SMSC_TRACE(pdata, intr, "RX Stop interrupt");
  1484. smsc911x_reg_write(pdata, INT_STS, INT_STS_RXSTOP_INT_);
  1485. if (pdata->multicast_update_pending)
  1486. smsc911x_rx_multicast_update_workaround(pdata);
  1487. serviced = IRQ_HANDLED;
  1488. }
  1489. if (intsts & inten & INT_STS_TDFA_) {
  1490. temp = smsc911x_reg_read(pdata, FIFO_INT);
  1491. temp |= FIFO_INT_TX_AVAIL_LEVEL_;
  1492. smsc911x_reg_write(pdata, FIFO_INT, temp);
  1493. smsc911x_reg_write(pdata, INT_STS, INT_STS_TDFA_);
  1494. netif_wake_queue(dev);
  1495. serviced = IRQ_HANDLED;
  1496. }
  1497. if (unlikely(intsts & inten & INT_STS_RXE_)) {
  1498. SMSC_TRACE(pdata, intr, "RX Error interrupt");
  1499. smsc911x_reg_write(pdata, INT_STS, INT_STS_RXE_);
  1500. serviced = IRQ_HANDLED;
  1501. }
  1502. if (likely(intsts & inten & INT_STS_RSFL_)) {
  1503. if (likely(napi_schedule_prep(&pdata->napi))) {
  1504. /* Disable Rx interrupts */
  1505. temp = smsc911x_reg_read(pdata, INT_EN);
  1506. temp &= (~INT_EN_RSFL_EN_);
  1507. smsc911x_reg_write(pdata, INT_EN, temp);
  1508. /* Schedule a NAPI poll */
  1509. __napi_schedule(&pdata->napi);
  1510. } else {
  1511. SMSC_WARN(pdata, rx_err, "napi_schedule_prep failed");
  1512. }
  1513. serviced = IRQ_HANDLED;
  1514. }
  1515. return serviced;
  1516. }
  1517. #ifdef CONFIG_NET_POLL_CONTROLLER
  1518. static void smsc911x_poll_controller(struct net_device *dev)
  1519. {
  1520. disable_irq(dev->irq);
  1521. smsc911x_irqhandler(0, dev);
  1522. enable_irq(dev->irq);
  1523. }
  1524. #endif /* CONFIG_NET_POLL_CONTROLLER */
  1525. static int smsc911x_set_mac_address(struct net_device *dev, void *p)
  1526. {
  1527. struct smsc911x_data *pdata = netdev_priv(dev);
  1528. struct sockaddr *addr = p;
  1529. /* On older hardware revisions we cannot change the mac address
  1530. * registers while receiving data. Newer devices can safely change
  1531. * this at any time. */
  1532. if (pdata->generation <= 1 && netif_running(dev))
  1533. return -EBUSY;
  1534. if (!is_valid_ether_addr(addr->sa_data))
  1535. return -EADDRNOTAVAIL;
  1536. memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
  1537. spin_lock_irq(&pdata->mac_lock);
  1538. smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
  1539. spin_unlock_irq(&pdata->mac_lock);
  1540. netdev_info(dev, "MAC Address: %pM\n", dev->dev_addr);
  1541. return 0;
  1542. }
  1543. /* Standard ioctls for mii-tool */
  1544. static int smsc911x_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  1545. {
  1546. struct smsc911x_data *pdata = netdev_priv(dev);
  1547. if (!netif_running(dev) || !pdata->phy_dev)
  1548. return -EINVAL;
  1549. return phy_mii_ioctl(pdata->phy_dev, ifr, cmd);
  1550. }
  1551. static int
  1552. smsc911x_ethtool_getsettings(struct net_device *dev, struct ethtool_cmd *cmd)
  1553. {
  1554. struct smsc911x_data *pdata = netdev_priv(dev);
  1555. cmd->maxtxpkt = 1;
  1556. cmd->maxrxpkt = 1;
  1557. return phy_ethtool_gset(pdata->phy_dev, cmd);
  1558. }
  1559. static int
  1560. smsc911x_ethtool_setsettings(struct net_device *dev, struct ethtool_cmd *cmd)
  1561. {
  1562. struct smsc911x_data *pdata = netdev_priv(dev);
  1563. return phy_ethtool_sset(pdata->phy_dev, cmd);
  1564. }
  1565. static void smsc911x_ethtool_getdrvinfo(struct net_device *dev,
  1566. struct ethtool_drvinfo *info)
  1567. {
  1568. strlcpy(info->driver, SMSC_CHIPNAME, sizeof(info->driver));
  1569. strlcpy(info->version, SMSC_DRV_VERSION, sizeof(info->version));
  1570. strlcpy(info->bus_info, dev_name(dev->dev.parent),
  1571. sizeof(info->bus_info));
  1572. }
  1573. static int smsc911x_ethtool_nwayreset(struct net_device *dev)
  1574. {
  1575. struct smsc911x_data *pdata = netdev_priv(dev);
  1576. return phy_start_aneg(pdata->phy_dev);
  1577. }
  1578. static u32 smsc911x_ethtool_getmsglevel(struct net_device *dev)
  1579. {
  1580. struct smsc911x_data *pdata = netdev_priv(dev);
  1581. return pdata->msg_enable;
  1582. }
  1583. static void smsc911x_ethtool_setmsglevel(struct net_device *dev, u32 level)
  1584. {
  1585. struct smsc911x_data *pdata = netdev_priv(dev);
  1586. pdata->msg_enable = level;
  1587. }
  1588. static int smsc911x_ethtool_getregslen(struct net_device *dev)
  1589. {
  1590. return (((E2P_DATA - ID_REV) / 4 + 1) + (WUCSR - MAC_CR) + 1 + 32) *
  1591. sizeof(u32);
  1592. }
  1593. static void
  1594. smsc911x_ethtool_getregs(struct net_device *dev, struct ethtool_regs *regs,
  1595. void *buf)
  1596. {
  1597. struct smsc911x_data *pdata = netdev_priv(dev);
  1598. struct phy_device *phy_dev = pdata->phy_dev;
  1599. unsigned long flags;
  1600. unsigned int i;
  1601. unsigned int j = 0;
  1602. u32 *data = buf;
  1603. regs->version = pdata->idrev;
  1604. for (i = ID_REV; i <= E2P_DATA; i += (sizeof(u32)))
  1605. data[j++] = smsc911x_reg_read(pdata, i);
  1606. for (i = MAC_CR; i <= WUCSR; i++) {
  1607. spin_lock_irqsave(&pdata->mac_lock, flags);
  1608. data[j++] = smsc911x_mac_read(pdata, i);
  1609. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  1610. }
  1611. for (i = 0; i <= 31; i++)
  1612. data[j++] = smsc911x_mii_read(phy_dev->bus, phy_dev->addr, i);
  1613. }
  1614. static void smsc911x_eeprom_enable_access(struct smsc911x_data *pdata)
  1615. {
  1616. unsigned int temp = smsc911x_reg_read(pdata, GPIO_CFG);
  1617. temp &= ~GPIO_CFG_EEPR_EN_;
  1618. smsc911x_reg_write(pdata, GPIO_CFG, temp);
  1619. msleep(1);
  1620. }
  1621. static int smsc911x_eeprom_send_cmd(struct smsc911x_data *pdata, u32 op)
  1622. {
  1623. int timeout = 100;
  1624. u32 e2cmd;
  1625. SMSC_TRACE(pdata, drv, "op 0x%08x", op);
  1626. if (smsc911x_reg_read(pdata, E2P_CMD) & E2P_CMD_EPC_BUSY_) {
  1627. SMSC_WARN(pdata, drv, "Busy at start");
  1628. return -EBUSY;
  1629. }
  1630. e2cmd = op | E2P_CMD_EPC_BUSY_;
  1631. smsc911x_reg_write(pdata, E2P_CMD, e2cmd);
  1632. do {
  1633. msleep(1);
  1634. e2cmd = smsc911x_reg_read(pdata, E2P_CMD);
  1635. } while ((e2cmd & E2P_CMD_EPC_BUSY_) && (--timeout));
  1636. if (!timeout) {
  1637. SMSC_TRACE(pdata, drv, "TIMED OUT");
  1638. return -EAGAIN;
  1639. }
  1640. if (e2cmd & E2P_CMD_EPC_TIMEOUT_) {
  1641. SMSC_TRACE(pdata, drv, "Error occurred during eeprom operation");
  1642. return -EINVAL;
  1643. }
  1644. return 0;
  1645. }
  1646. static int smsc911x_eeprom_read_location(struct smsc911x_data *pdata,
  1647. u8 address, u8 *data)
  1648. {
  1649. u32 op = E2P_CMD_EPC_CMD_READ_ | address;
  1650. int ret;
  1651. SMSC_TRACE(pdata, drv, "address 0x%x", address);
  1652. ret = smsc911x_eeprom_send_cmd(pdata, op);
  1653. if (!ret)
  1654. data[address] = smsc911x_reg_read(pdata, E2P_DATA);
  1655. return ret;
  1656. }
  1657. static int smsc911x_eeprom_write_location(struct smsc911x_data *pdata,
  1658. u8 address, u8 data)
  1659. {
  1660. u32 op = E2P_CMD_EPC_CMD_ERASE_ | address;
  1661. u32 temp;
  1662. int ret;
  1663. SMSC_TRACE(pdata, drv, "address 0x%x, data 0x%x", address, data);
  1664. ret = smsc911x_eeprom_send_cmd(pdata, op);
  1665. if (!ret) {
  1666. op = E2P_CMD_EPC_CMD_WRITE_ | address;
  1667. smsc911x_reg_write(pdata, E2P_DATA, (u32)data);
  1668. /* Workaround for hardware read-after-write restriction */
  1669. temp = smsc911x_reg_read(pdata, BYTE_TEST);
  1670. ret = smsc911x_eeprom_send_cmd(pdata, op);
  1671. }
  1672. return ret;
  1673. }
  1674. static int smsc911x_ethtool_get_eeprom_len(struct net_device *dev)
  1675. {
  1676. return SMSC911X_EEPROM_SIZE;
  1677. }
  1678. static int smsc911x_ethtool_get_eeprom(struct net_device *dev,
  1679. struct ethtool_eeprom *eeprom, u8 *data)
  1680. {
  1681. struct smsc911x_data *pdata = netdev_priv(dev);
  1682. u8 eeprom_data[SMSC911X_EEPROM_SIZE];
  1683. int len;
  1684. int i;
  1685. smsc911x_eeprom_enable_access(pdata);
  1686. len = min(eeprom->len, SMSC911X_EEPROM_SIZE);
  1687. for (i = 0; i < len; i++) {
  1688. int ret = smsc911x_eeprom_read_location(pdata, i, eeprom_data);
  1689. if (ret < 0) {
  1690. eeprom->len = 0;
  1691. return ret;
  1692. }
  1693. }
  1694. memcpy(data, &eeprom_data[eeprom->offset], len);
  1695. eeprom->len = len;
  1696. return 0;
  1697. }
  1698. static int smsc911x_ethtool_set_eeprom(struct net_device *dev,
  1699. struct ethtool_eeprom *eeprom, u8 *data)
  1700. {
  1701. int ret;
  1702. struct smsc911x_data *pdata = netdev_priv(dev);
  1703. smsc911x_eeprom_enable_access(pdata);
  1704. smsc911x_eeprom_send_cmd(pdata, E2P_CMD_EPC_CMD_EWEN_);
  1705. ret = smsc911x_eeprom_write_location(pdata, eeprom->offset, *data);
  1706. smsc911x_eeprom_send_cmd(pdata, E2P_CMD_EPC_CMD_EWDS_);
  1707. /* Single byte write, according to man page */
  1708. eeprom->len = 1;
  1709. return ret;
  1710. }
  1711. static const struct ethtool_ops smsc911x_ethtool_ops = {
  1712. .get_settings = smsc911x_ethtool_getsettings,
  1713. .set_settings = smsc911x_ethtool_setsettings,
  1714. .get_link = ethtool_op_get_link,
  1715. .get_drvinfo = smsc911x_ethtool_getdrvinfo,
  1716. .nway_reset = smsc911x_ethtool_nwayreset,
  1717. .get_msglevel = smsc911x_ethtool_getmsglevel,
  1718. .set_msglevel = smsc911x_ethtool_setmsglevel,
  1719. .get_regs_len = smsc911x_ethtool_getregslen,
  1720. .get_regs = smsc911x_ethtool_getregs,
  1721. .get_eeprom_len = smsc911x_ethtool_get_eeprom_len,
  1722. .get_eeprom = smsc911x_ethtool_get_eeprom,
  1723. .set_eeprom = smsc911x_ethtool_set_eeprom,
  1724. .get_ts_info = ethtool_op_get_ts_info,
  1725. };
  1726. static const struct net_device_ops smsc911x_netdev_ops = {
  1727. .ndo_open = smsc911x_open,
  1728. .ndo_stop = smsc911x_stop,
  1729. .ndo_start_xmit = smsc911x_hard_start_xmit,
  1730. .ndo_get_stats = smsc911x_get_stats,
  1731. .ndo_set_rx_mode = smsc911x_set_multicast_list,
  1732. .ndo_do_ioctl = smsc911x_do_ioctl,
  1733. .ndo_change_mtu = eth_change_mtu,
  1734. .ndo_validate_addr = eth_validate_addr,
  1735. .ndo_set_mac_address = smsc911x_set_mac_address,
  1736. #ifdef CONFIG_NET_POLL_CONTROLLER
  1737. .ndo_poll_controller = smsc911x_poll_controller,
  1738. #endif
  1739. };
  1740. /* copies the current mac address from hardware to dev->dev_addr */
  1741. static void smsc911x_read_mac_address(struct net_device *dev)
  1742. {
  1743. struct smsc911x_data *pdata = netdev_priv(dev);
  1744. u32 mac_high16 = smsc911x_mac_read(pdata, ADDRH);
  1745. u32 mac_low32 = smsc911x_mac_read(pdata, ADDRL);
  1746. dev->dev_addr[0] = (u8)(mac_low32);
  1747. dev->dev_addr[1] = (u8)(mac_low32 >> 8);
  1748. dev->dev_addr[2] = (u8)(mac_low32 >> 16);
  1749. dev->dev_addr[3] = (u8)(mac_low32 >> 24);
  1750. dev->dev_addr[4] = (u8)(mac_high16);
  1751. dev->dev_addr[5] = (u8)(mac_high16 >> 8);
  1752. }
  1753. /* Initializing private device structures, only called from probe */
  1754. static int smsc911x_init(struct net_device *dev)
  1755. {
  1756. struct smsc911x_data *pdata = netdev_priv(dev);
  1757. unsigned int byte_test, mask;
  1758. unsigned int to = 100;
  1759. SMSC_TRACE(pdata, probe, "Driver Parameters:");
  1760. SMSC_TRACE(pdata, probe, "LAN base: 0x%08lX",
  1761. (unsigned long)pdata->ioaddr);
  1762. SMSC_TRACE(pdata, probe, "IRQ: %d", dev->irq);
  1763. SMSC_TRACE(pdata, probe, "PHY will be autodetected.");
  1764. spin_lock_init(&pdata->dev_lock);
  1765. spin_lock_init(&pdata->mac_lock);
  1766. if (pdata->ioaddr == NULL) {
  1767. SMSC_WARN(pdata, probe, "pdata->ioaddr: 0x00000000");
  1768. return -ENODEV;
  1769. }
  1770. /*
  1771. * poll the READY bit in PMT_CTRL. Any other access to the device is
  1772. * forbidden while this bit isn't set. Try for 100ms
  1773. *
  1774. * Note that this test is done before the WORD_SWAP register is
  1775. * programmed. So in some configurations the READY bit is at 16 before
  1776. * WORD_SWAP is written to. This issue is worked around by waiting
  1777. * until either bit 0 or bit 16 gets set in PMT_CTRL.
  1778. *
  1779. * SMSC has confirmed that checking bit 16 (marked as reserved in
  1780. * the datasheet) is fine since these bits "will either never be set
  1781. * or can only go high after READY does (so also indicate the device
  1782. * is ready)".
  1783. */
  1784. mask = PMT_CTRL_READY_ | swahw32(PMT_CTRL_READY_);
  1785. while (!(smsc911x_reg_read(pdata, PMT_CTRL) & mask) && --to)
  1786. udelay(1000);
  1787. if (to == 0) {
  1788. netdev_err(dev, "Device not READY in 100ms aborting\n");
  1789. return -ENODEV;
  1790. }
  1791. /* Check byte ordering */
  1792. byte_test = smsc911x_reg_read(pdata, BYTE_TEST);
  1793. SMSC_TRACE(pdata, probe, "BYTE_TEST: 0x%08X", byte_test);
  1794. if (byte_test == 0x43218765) {
  1795. SMSC_TRACE(pdata, probe, "BYTE_TEST looks swapped, "
  1796. "applying WORD_SWAP");
  1797. smsc911x_reg_write(pdata, WORD_SWAP, 0xffffffff);
  1798. /* 1 dummy read of BYTE_TEST is needed after a write to
  1799. * WORD_SWAP before its contents are valid */
  1800. byte_test = smsc911x_reg_read(pdata, BYTE_TEST);
  1801. byte_test = smsc911x_reg_read(pdata, BYTE_TEST);
  1802. }
  1803. if (byte_test != 0x87654321) {
  1804. SMSC_WARN(pdata, drv, "BYTE_TEST: 0x%08X", byte_test);
  1805. if (((byte_test >> 16) & 0xFFFF) == (byte_test & 0xFFFF)) {
  1806. SMSC_WARN(pdata, probe,
  1807. "top 16 bits equal to bottom 16 bits");
  1808. SMSC_TRACE(pdata, probe,
  1809. "This may mean the chip is set "
  1810. "for 32 bit while the bus is reading 16 bit");
  1811. }
  1812. return -ENODEV;
  1813. }
  1814. /* Default generation to zero (all workarounds apply) */
  1815. pdata->generation = 0;
  1816. pdata->idrev = smsc911x_reg_read(pdata, ID_REV);
  1817. switch (pdata->idrev & 0xFFFF0000) {
  1818. case 0x01180000:
  1819. case 0x01170000:
  1820. case 0x01160000:
  1821. case 0x01150000:
  1822. case 0x218A0000:
  1823. /* LAN911[5678] family */
  1824. pdata->generation = pdata->idrev & 0x0000FFFF;
  1825. break;
  1826. case 0x118A0000:
  1827. case 0x117A0000:
  1828. case 0x116A0000:
  1829. case 0x115A0000:
  1830. /* LAN921[5678] family */
  1831. pdata->generation = 3;
  1832. break;
  1833. case 0x92100000:
  1834. case 0x92110000:
  1835. case 0x92200000:
  1836. case 0x92210000:
  1837. /* LAN9210/LAN9211/LAN9220/LAN9221 */
  1838. pdata->generation = 4;
  1839. break;
  1840. default:
  1841. SMSC_WARN(pdata, probe, "LAN911x not identified, idrev: 0x%08X",
  1842. pdata->idrev);
  1843. return -ENODEV;
  1844. }
  1845. SMSC_TRACE(pdata, probe,
  1846. "LAN911x identified, idrev: 0x%08X, generation: %d",
  1847. pdata->idrev, pdata->generation);
  1848. if (pdata->generation == 0)
  1849. SMSC_WARN(pdata, probe,
  1850. "This driver is not intended for this chip revision");
  1851. /* workaround for platforms without an eeprom, where the mac address
  1852. * is stored elsewhere and set by the bootloader. This saves the
  1853. * mac address before resetting the device */
  1854. if (pdata->config.flags & SMSC911X_SAVE_MAC_ADDRESS) {
  1855. spin_lock_irq(&pdata->mac_lock);
  1856. smsc911x_read_mac_address(dev);
  1857. spin_unlock_irq(&pdata->mac_lock);
  1858. }
  1859. /* Reset the LAN911x */
  1860. if (smsc911x_soft_reset(pdata))
  1861. return -ENODEV;
  1862. ether_setup(dev);
  1863. dev->flags |= IFF_MULTICAST;
  1864. netif_napi_add(dev, &pdata->napi, smsc911x_poll, SMSC_NAPI_WEIGHT);
  1865. dev->netdev_ops = &smsc911x_netdev_ops;
  1866. dev->ethtool_ops = &smsc911x_ethtool_ops;
  1867. return 0;
  1868. }
  1869. static int smsc911x_drv_remove(struct platform_device *pdev)
  1870. {
  1871. struct net_device *dev;
  1872. struct smsc911x_data *pdata;
  1873. struct resource *res;
  1874. dev = platform_get_drvdata(pdev);
  1875. BUG_ON(!dev);
  1876. pdata = netdev_priv(dev);
  1877. BUG_ON(!pdata);
  1878. BUG_ON(!pdata->ioaddr);
  1879. BUG_ON(!pdata->phy_dev);
  1880. SMSC_TRACE(pdata, ifdown, "Stopping driver");
  1881. phy_disconnect(pdata->phy_dev);
  1882. pdata->phy_dev = NULL;
  1883. mdiobus_unregister(pdata->mii_bus);
  1884. mdiobus_free(pdata->mii_bus);
  1885. unregister_netdev(dev);
  1886. free_irq(dev->irq, dev);
  1887. res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
  1888. "smsc911x-memory");
  1889. if (!res)
  1890. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1891. release_mem_region(res->start, resource_size(res));
  1892. iounmap(pdata->ioaddr);
  1893. (void)smsc911x_disable_resources(pdev);
  1894. smsc911x_free_resources(pdev);
  1895. free_netdev(dev);
  1896. return 0;
  1897. }
  1898. /* standard register acces */
  1899. static const struct smsc911x_ops standard_smsc911x_ops = {
  1900. .reg_read = __smsc911x_reg_read,
  1901. .reg_write = __smsc911x_reg_write,
  1902. .rx_readfifo = smsc911x_rx_readfifo,
  1903. .tx_writefifo = smsc911x_tx_writefifo,
  1904. };
  1905. /* shifted register access */
  1906. static const struct smsc911x_ops shifted_smsc911x_ops = {
  1907. .reg_read = __smsc911x_reg_read_shift,
  1908. .reg_write = __smsc911x_reg_write_shift,
  1909. .rx_readfifo = smsc911x_rx_readfifo_shift,
  1910. .tx_writefifo = smsc911x_tx_writefifo_shift,
  1911. };
  1912. #ifdef CONFIG_OF
  1913. static int smsc911x_probe_config_dt(struct smsc911x_platform_config *config,
  1914. struct device_node *np)
  1915. {
  1916. const char *mac;
  1917. u32 width = 0;
  1918. if (!np)
  1919. return -ENODEV;
  1920. config->phy_interface = of_get_phy_mode(np);
  1921. mac = of_get_mac_address(np);
  1922. if (mac)
  1923. memcpy(config->mac, mac, ETH_ALEN);
  1924. of_property_read_u32(np, "reg-shift", &config->shift);
  1925. of_property_read_u32(np, "reg-io-width", &width);
  1926. if (width == 4)
  1927. config->flags |= SMSC911X_USE_32BIT;
  1928. else
  1929. config->flags |= SMSC911X_USE_16BIT;
  1930. if (of_get_property(np, "smsc,irq-active-high", NULL))
  1931. config->irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH;
  1932. if (of_get_property(np, "smsc,irq-push-pull", NULL))
  1933. config->irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL;
  1934. if (of_get_property(np, "smsc,force-internal-phy", NULL))
  1935. config->flags |= SMSC911X_FORCE_INTERNAL_PHY;
  1936. if (of_get_property(np, "smsc,force-external-phy", NULL))
  1937. config->flags |= SMSC911X_FORCE_EXTERNAL_PHY;
  1938. if (of_get_property(np, "smsc,save-mac-address", NULL))
  1939. config->flags |= SMSC911X_SAVE_MAC_ADDRESS;
  1940. return 0;
  1941. }
  1942. #else
  1943. static inline int smsc911x_probe_config_dt(
  1944. struct smsc911x_platform_config *config,
  1945. struct device_node *np)
  1946. {
  1947. return -ENODEV;
  1948. }
  1949. #endif /* CONFIG_OF */
  1950. static int smsc911x_drv_probe(struct platform_device *pdev)
  1951. {
  1952. struct device_node *np = pdev->dev.of_node;
  1953. struct net_device *dev;
  1954. struct smsc911x_data *pdata;
  1955. struct smsc911x_platform_config *config = dev_get_platdata(&pdev->dev);
  1956. struct resource *res, *irq_res;
  1957. unsigned int intcfg = 0;
  1958. int res_size, irq_flags;
  1959. int retval;
  1960. pr_info("Driver version %s\n", SMSC_DRV_VERSION);
  1961. res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
  1962. "smsc911x-memory");
  1963. if (!res)
  1964. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1965. if (!res) {
  1966. pr_warn("Could not allocate resource\n");
  1967. retval = -ENODEV;
  1968. goto out_0;
  1969. }
  1970. res_size = resource_size(res);
  1971. irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  1972. if (!irq_res) {
  1973. pr_warn("Could not allocate irq resource\n");
  1974. retval = -ENODEV;
  1975. goto out_0;
  1976. }
  1977. if (!request_mem_region(res->start, res_size, SMSC_CHIPNAME)) {
  1978. retval = -EBUSY;
  1979. goto out_0;
  1980. }
  1981. dev = alloc_etherdev(sizeof(struct smsc911x_data));
  1982. if (!dev) {
  1983. retval = -ENOMEM;
  1984. goto out_release_io_1;
  1985. }
  1986. SET_NETDEV_DEV(dev, &pdev->dev);
  1987. pdata = netdev_priv(dev);
  1988. dev->irq = irq_res->start;
  1989. irq_flags = irq_res->flags & IRQF_TRIGGER_MASK;
  1990. pdata->ioaddr = ioremap_nocache(res->start, res_size);
  1991. pdata->dev = dev;
  1992. pdata->msg_enable = ((1 << debug) - 1);
  1993. platform_set_drvdata(pdev, dev);
  1994. retval = smsc911x_request_resources(pdev);
  1995. if (retval)
  1996. goto out_request_resources_fail;
  1997. retval = smsc911x_enable_resources(pdev);
  1998. if (retval)
  1999. goto out_enable_resources_fail;
  2000. if (pdata->ioaddr == NULL) {
  2001. SMSC_WARN(pdata, probe, "Error smsc911x base address invalid");
  2002. retval = -ENOMEM;
  2003. goto out_disable_resources;
  2004. }
  2005. retval = smsc911x_probe_config_dt(&pdata->config, np);
  2006. if (retval && config) {
  2007. /* copy config parameters across to pdata */
  2008. memcpy(&pdata->config, config, sizeof(pdata->config));
  2009. retval = 0;
  2010. }
  2011. if (retval) {
  2012. SMSC_WARN(pdata, probe, "Error smsc911x config not found");
  2013. goto out_disable_resources;
  2014. }
  2015. /* assume standard, non-shifted, access to HW registers */
  2016. pdata->ops = &standard_smsc911x_ops;
  2017. /* apply the right access if shifting is needed */
  2018. if (pdata->config.shift)
  2019. pdata->ops = &shifted_smsc911x_ops;
  2020. retval = smsc911x_init(dev);
  2021. if (retval < 0)
  2022. goto out_disable_resources;
  2023. /* configure irq polarity and type before connecting isr */
  2024. if (pdata->config.irq_polarity == SMSC911X_IRQ_POLARITY_ACTIVE_HIGH)
  2025. intcfg |= INT_CFG_IRQ_POL_;
  2026. if (pdata->config.irq_type == SMSC911X_IRQ_TYPE_PUSH_PULL)
  2027. intcfg |= INT_CFG_IRQ_TYPE_;
  2028. smsc911x_reg_write(pdata, INT_CFG, intcfg);
  2029. /* Ensure interrupts are globally disabled before connecting ISR */
  2030. smsc911x_disable_irq_chip(dev);
  2031. retval = request_irq(dev->irq, smsc911x_irqhandler,
  2032. irq_flags | IRQF_SHARED, dev->name, dev);
  2033. if (retval) {
  2034. SMSC_WARN(pdata, probe,
  2035. "Unable to claim requested irq: %d", dev->irq);
  2036. goto out_disable_resources;
  2037. }
  2038. retval = register_netdev(dev);
  2039. if (retval) {
  2040. SMSC_WARN(pdata, probe, "Error %i registering device", retval);
  2041. goto out_free_irq;
  2042. } else {
  2043. SMSC_TRACE(pdata, probe,
  2044. "Network interface: \"%s\"", dev->name);
  2045. }
  2046. retval = smsc911x_mii_init(pdev, dev);
  2047. if (retval) {
  2048. SMSC_WARN(pdata, probe, "Error %i initialising mii", retval);
  2049. goto out_unregister_netdev_5;
  2050. }
  2051. spin_lock_irq(&pdata->mac_lock);
  2052. /* Check if mac address has been specified when bringing interface up */
  2053. if (is_valid_ether_addr(dev->dev_addr)) {
  2054. smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
  2055. SMSC_TRACE(pdata, probe,
  2056. "MAC Address is specified by configuration");
  2057. } else if (is_valid_ether_addr(pdata->config.mac)) {
  2058. memcpy(dev->dev_addr, pdata->config.mac, ETH_ALEN);
  2059. SMSC_TRACE(pdata, probe,
  2060. "MAC Address specified by platform data");
  2061. } else {
  2062. /* Try reading mac address from device. if EEPROM is present
  2063. * it will already have been set */
  2064. smsc_get_mac(dev);
  2065. if (is_valid_ether_addr(dev->dev_addr)) {
  2066. /* eeprom values are valid so use them */
  2067. SMSC_TRACE(pdata, probe,
  2068. "Mac Address is read from LAN911x EEPROM");
  2069. } else {
  2070. /* eeprom values are invalid, generate random MAC */
  2071. eth_hw_addr_random(dev);
  2072. smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
  2073. SMSC_TRACE(pdata, probe,
  2074. "MAC Address is set to eth_random_addr");
  2075. }
  2076. }
  2077. spin_unlock_irq(&pdata->mac_lock);
  2078. netdev_info(dev, "MAC Address: %pM\n", dev->dev_addr);
  2079. return 0;
  2080. out_unregister_netdev_5:
  2081. unregister_netdev(dev);
  2082. out_free_irq:
  2083. free_irq(dev->irq, dev);
  2084. out_disable_resources:
  2085. (void)smsc911x_disable_resources(pdev);
  2086. out_enable_resources_fail:
  2087. smsc911x_free_resources(pdev);
  2088. out_request_resources_fail:
  2089. iounmap(pdata->ioaddr);
  2090. free_netdev(dev);
  2091. out_release_io_1:
  2092. release_mem_region(res->start, resource_size(res));
  2093. out_0:
  2094. return retval;
  2095. }
  2096. #ifdef CONFIG_PM
  2097. /* This implementation assumes the devices remains powered on its VDDVARIO
  2098. * pins during suspend. */
  2099. /* TODO: implement freeze/thaw callbacks for hibernation.*/
  2100. static int smsc911x_suspend(struct device *dev)
  2101. {
  2102. struct net_device *ndev = dev_get_drvdata(dev);
  2103. struct smsc911x_data *pdata = netdev_priv(ndev);
  2104. /* enable wake on LAN, energy detection and the external PME
  2105. * signal. */
  2106. smsc911x_reg_write(pdata, PMT_CTRL,
  2107. PMT_CTRL_PM_MODE_D1_ | PMT_CTRL_WOL_EN_ |
  2108. PMT_CTRL_ED_EN_ | PMT_CTRL_PME_EN_);
  2109. return 0;
  2110. }
  2111. static int smsc911x_resume(struct device *dev)
  2112. {
  2113. struct net_device *ndev = dev_get_drvdata(dev);
  2114. struct smsc911x_data *pdata = netdev_priv(ndev);
  2115. unsigned int to = 100;
  2116. /* Note 3.11 from the datasheet:
  2117. * "When the LAN9220 is in a power saving state, a write of any
  2118. * data to the BYTE_TEST register will wake-up the device."
  2119. */
  2120. smsc911x_reg_write(pdata, BYTE_TEST, 0);
  2121. /* poll the READY bit in PMT_CTRL. Any other access to the device is
  2122. * forbidden while this bit isn't set. Try for 100ms and return -EIO
  2123. * if it failed. */
  2124. while (!(smsc911x_reg_read(pdata, PMT_CTRL) & PMT_CTRL_READY_) && --to)
  2125. udelay(1000);
  2126. return (to == 0) ? -EIO : 0;
  2127. }
  2128. static const struct dev_pm_ops smsc911x_pm_ops = {
  2129. .suspend = smsc911x_suspend,
  2130. .resume = smsc911x_resume,
  2131. };
  2132. #define SMSC911X_PM_OPS (&smsc911x_pm_ops)
  2133. #else
  2134. #define SMSC911X_PM_OPS NULL
  2135. #endif
  2136. #ifdef CONFIG_OF
  2137. static const struct of_device_id smsc911x_dt_ids[] = {
  2138. { .compatible = "smsc,lan9115", },
  2139. { /* sentinel */ }
  2140. };
  2141. MODULE_DEVICE_TABLE(of, smsc911x_dt_ids);
  2142. #endif
  2143. static struct platform_driver smsc911x_driver = {
  2144. .probe = smsc911x_drv_probe,
  2145. .remove = smsc911x_drv_remove,
  2146. .driver = {
  2147. .name = SMSC_CHIPNAME,
  2148. .owner = THIS_MODULE,
  2149. .pm = SMSC911X_PM_OPS,
  2150. .of_match_table = of_match_ptr(smsc911x_dt_ids),
  2151. },
  2152. };
  2153. /* Entry point for loading the module */
  2154. static int __init smsc911x_init_module(void)
  2155. {
  2156. SMSC_INITIALIZE();
  2157. return platform_driver_register(&smsc911x_driver);
  2158. }
  2159. /* entry point for unloading the module */
  2160. static void __exit smsc911x_cleanup_module(void)
  2161. {
  2162. platform_driver_unregister(&smsc911x_driver);
  2163. }
  2164. module_init(smsc911x_init_module);
  2165. module_exit(smsc911x_cleanup_module);