mcdi.c 49 KB

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  1. /****************************************************************************
  2. * Driver for Solarflare network controllers and boards
  3. * Copyright 2008-2013 Solarflare Communications Inc.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License version 2 as published
  7. * by the Free Software Foundation, incorporated herein by reference.
  8. */
  9. #include <linux/delay.h>
  10. #include <asm/cmpxchg.h>
  11. #include "net_driver.h"
  12. #include "nic.h"
  13. #include "io.h"
  14. #include "farch_regs.h"
  15. #include "mcdi_pcol.h"
  16. #include "phy.h"
  17. /**************************************************************************
  18. *
  19. * Management-Controller-to-Driver Interface
  20. *
  21. **************************************************************************
  22. */
  23. #define MCDI_RPC_TIMEOUT (10 * HZ)
  24. /* A reboot/assertion causes the MCDI status word to be set after the
  25. * command word is set or a REBOOT event is sent. If we notice a reboot
  26. * via these mechanisms then wait 250ms for the status word to be set.
  27. */
  28. #define MCDI_STATUS_DELAY_US 100
  29. #define MCDI_STATUS_DELAY_COUNT 2500
  30. #define MCDI_STATUS_SLEEP_MS \
  31. (MCDI_STATUS_DELAY_US * MCDI_STATUS_DELAY_COUNT / 1000)
  32. #define SEQ_MASK \
  33. EFX_MASK32(EFX_WIDTH(MCDI_HEADER_SEQ))
  34. struct efx_mcdi_async_param {
  35. struct list_head list;
  36. unsigned int cmd;
  37. size_t inlen;
  38. size_t outlen;
  39. bool quiet;
  40. efx_mcdi_async_completer *complete;
  41. unsigned long cookie;
  42. /* followed by request/response buffer */
  43. };
  44. static void efx_mcdi_timeout_async(unsigned long context);
  45. static int efx_mcdi_drv_attach(struct efx_nic *efx, bool driver_operating,
  46. bool *was_attached_out);
  47. static bool efx_mcdi_poll_once(struct efx_nic *efx);
  48. static inline struct efx_mcdi_iface *efx_mcdi(struct efx_nic *efx)
  49. {
  50. EFX_BUG_ON_PARANOID(!efx->mcdi);
  51. return &efx->mcdi->iface;
  52. }
  53. int efx_mcdi_init(struct efx_nic *efx)
  54. {
  55. struct efx_mcdi_iface *mcdi;
  56. bool already_attached;
  57. int rc;
  58. efx->mcdi = kzalloc(sizeof(*efx->mcdi), GFP_KERNEL);
  59. if (!efx->mcdi)
  60. return -ENOMEM;
  61. mcdi = efx_mcdi(efx);
  62. mcdi->efx = efx;
  63. init_waitqueue_head(&mcdi->wq);
  64. spin_lock_init(&mcdi->iface_lock);
  65. mcdi->state = MCDI_STATE_QUIESCENT;
  66. mcdi->mode = MCDI_MODE_POLL;
  67. spin_lock_init(&mcdi->async_lock);
  68. INIT_LIST_HEAD(&mcdi->async_list);
  69. setup_timer(&mcdi->async_timer, efx_mcdi_timeout_async,
  70. (unsigned long)mcdi);
  71. (void) efx_mcdi_poll_reboot(efx);
  72. mcdi->new_epoch = true;
  73. /* Recover from a failed assertion before probing */
  74. rc = efx_mcdi_handle_assertion(efx);
  75. if (rc)
  76. return rc;
  77. /* Let the MC (and BMC, if this is a LOM) know that the driver
  78. * is loaded. We should do this before we reset the NIC.
  79. */
  80. rc = efx_mcdi_drv_attach(efx, true, &already_attached);
  81. if (rc) {
  82. netif_err(efx, probe, efx->net_dev,
  83. "Unable to register driver with MCPU\n");
  84. return rc;
  85. }
  86. if (already_attached)
  87. /* Not a fatal error */
  88. netif_err(efx, probe, efx->net_dev,
  89. "Host already registered with MCPU\n");
  90. if (efx->mcdi->fn_flags &
  91. (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY))
  92. efx->primary = efx;
  93. return 0;
  94. }
  95. void efx_mcdi_fini(struct efx_nic *efx)
  96. {
  97. if (!efx->mcdi)
  98. return;
  99. BUG_ON(efx->mcdi->iface.state != MCDI_STATE_QUIESCENT);
  100. /* Relinquish the device (back to the BMC, if this is a LOM) */
  101. efx_mcdi_drv_attach(efx, false, NULL);
  102. kfree(efx->mcdi);
  103. }
  104. static void efx_mcdi_send_request(struct efx_nic *efx, unsigned cmd,
  105. const efx_dword_t *inbuf, size_t inlen)
  106. {
  107. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  108. efx_dword_t hdr[2];
  109. size_t hdr_len;
  110. u32 xflags, seqno;
  111. BUG_ON(mcdi->state == MCDI_STATE_QUIESCENT);
  112. /* Serialise with efx_mcdi_ev_cpl() and efx_mcdi_ev_death() */
  113. spin_lock_bh(&mcdi->iface_lock);
  114. ++mcdi->seqno;
  115. spin_unlock_bh(&mcdi->iface_lock);
  116. seqno = mcdi->seqno & SEQ_MASK;
  117. xflags = 0;
  118. if (mcdi->mode == MCDI_MODE_EVENTS)
  119. xflags |= MCDI_HEADER_XFLAGS_EVREQ;
  120. if (efx->type->mcdi_max_ver == 1) {
  121. /* MCDI v1 */
  122. EFX_POPULATE_DWORD_7(hdr[0],
  123. MCDI_HEADER_RESPONSE, 0,
  124. MCDI_HEADER_RESYNC, 1,
  125. MCDI_HEADER_CODE, cmd,
  126. MCDI_HEADER_DATALEN, inlen,
  127. MCDI_HEADER_SEQ, seqno,
  128. MCDI_HEADER_XFLAGS, xflags,
  129. MCDI_HEADER_NOT_EPOCH, !mcdi->new_epoch);
  130. hdr_len = 4;
  131. } else {
  132. /* MCDI v2 */
  133. BUG_ON(inlen > MCDI_CTL_SDU_LEN_MAX_V2);
  134. EFX_POPULATE_DWORD_7(hdr[0],
  135. MCDI_HEADER_RESPONSE, 0,
  136. MCDI_HEADER_RESYNC, 1,
  137. MCDI_HEADER_CODE, MC_CMD_V2_EXTN,
  138. MCDI_HEADER_DATALEN, 0,
  139. MCDI_HEADER_SEQ, seqno,
  140. MCDI_HEADER_XFLAGS, xflags,
  141. MCDI_HEADER_NOT_EPOCH, !mcdi->new_epoch);
  142. EFX_POPULATE_DWORD_2(hdr[1],
  143. MC_CMD_V2_EXTN_IN_EXTENDED_CMD, cmd,
  144. MC_CMD_V2_EXTN_IN_ACTUAL_LEN, inlen);
  145. hdr_len = 8;
  146. }
  147. efx->type->mcdi_request(efx, hdr, hdr_len, inbuf, inlen);
  148. mcdi->new_epoch = false;
  149. }
  150. static int efx_mcdi_errno(unsigned int mcdi_err)
  151. {
  152. switch (mcdi_err) {
  153. case 0:
  154. return 0;
  155. #define TRANSLATE_ERROR(name) \
  156. case MC_CMD_ERR_ ## name: \
  157. return -name;
  158. TRANSLATE_ERROR(EPERM);
  159. TRANSLATE_ERROR(ENOENT);
  160. TRANSLATE_ERROR(EINTR);
  161. TRANSLATE_ERROR(EAGAIN);
  162. TRANSLATE_ERROR(EACCES);
  163. TRANSLATE_ERROR(EBUSY);
  164. TRANSLATE_ERROR(EINVAL);
  165. TRANSLATE_ERROR(EDEADLK);
  166. TRANSLATE_ERROR(ENOSYS);
  167. TRANSLATE_ERROR(ETIME);
  168. TRANSLATE_ERROR(EALREADY);
  169. TRANSLATE_ERROR(ENOSPC);
  170. #undef TRANSLATE_ERROR
  171. case MC_CMD_ERR_ENOTSUP:
  172. return -EOPNOTSUPP;
  173. case MC_CMD_ERR_ALLOC_FAIL:
  174. return -ENOBUFS;
  175. case MC_CMD_ERR_MAC_EXIST:
  176. return -EADDRINUSE;
  177. default:
  178. return -EPROTO;
  179. }
  180. }
  181. static void efx_mcdi_read_response_header(struct efx_nic *efx)
  182. {
  183. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  184. unsigned int respseq, respcmd, error;
  185. efx_dword_t hdr;
  186. efx->type->mcdi_read_response(efx, &hdr, 0, 4);
  187. respseq = EFX_DWORD_FIELD(hdr, MCDI_HEADER_SEQ);
  188. respcmd = EFX_DWORD_FIELD(hdr, MCDI_HEADER_CODE);
  189. error = EFX_DWORD_FIELD(hdr, MCDI_HEADER_ERROR);
  190. if (respcmd != MC_CMD_V2_EXTN) {
  191. mcdi->resp_hdr_len = 4;
  192. mcdi->resp_data_len = EFX_DWORD_FIELD(hdr, MCDI_HEADER_DATALEN);
  193. } else {
  194. efx->type->mcdi_read_response(efx, &hdr, 4, 4);
  195. mcdi->resp_hdr_len = 8;
  196. mcdi->resp_data_len =
  197. EFX_DWORD_FIELD(hdr, MC_CMD_V2_EXTN_IN_ACTUAL_LEN);
  198. }
  199. if (error && mcdi->resp_data_len == 0) {
  200. netif_err(efx, hw, efx->net_dev, "MC rebooted\n");
  201. mcdi->resprc = -EIO;
  202. } else if ((respseq ^ mcdi->seqno) & SEQ_MASK) {
  203. netif_err(efx, hw, efx->net_dev,
  204. "MC response mismatch tx seq 0x%x rx seq 0x%x\n",
  205. respseq, mcdi->seqno);
  206. mcdi->resprc = -EIO;
  207. } else if (error) {
  208. efx->type->mcdi_read_response(efx, &hdr, mcdi->resp_hdr_len, 4);
  209. mcdi->resprc =
  210. efx_mcdi_errno(EFX_DWORD_FIELD(hdr, EFX_DWORD_0));
  211. } else {
  212. mcdi->resprc = 0;
  213. }
  214. }
  215. static bool efx_mcdi_poll_once(struct efx_nic *efx)
  216. {
  217. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  218. rmb();
  219. if (!efx->type->mcdi_poll_response(efx))
  220. return false;
  221. spin_lock_bh(&mcdi->iface_lock);
  222. efx_mcdi_read_response_header(efx);
  223. spin_unlock_bh(&mcdi->iface_lock);
  224. return true;
  225. }
  226. static int efx_mcdi_poll(struct efx_nic *efx)
  227. {
  228. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  229. unsigned long time, finish;
  230. unsigned int spins;
  231. int rc;
  232. /* Check for a reboot atomically with respect to efx_mcdi_copyout() */
  233. rc = efx_mcdi_poll_reboot(efx);
  234. if (rc) {
  235. spin_lock_bh(&mcdi->iface_lock);
  236. mcdi->resprc = rc;
  237. mcdi->resp_hdr_len = 0;
  238. mcdi->resp_data_len = 0;
  239. spin_unlock_bh(&mcdi->iface_lock);
  240. return 0;
  241. }
  242. /* Poll for completion. Poll quickly (once a us) for the 1st jiffy,
  243. * because generally mcdi responses are fast. After that, back off
  244. * and poll once a jiffy (approximately)
  245. */
  246. spins = TICK_USEC;
  247. finish = jiffies + MCDI_RPC_TIMEOUT;
  248. while (1) {
  249. if (spins != 0) {
  250. --spins;
  251. udelay(1);
  252. } else {
  253. schedule_timeout_uninterruptible(1);
  254. }
  255. time = jiffies;
  256. if (efx_mcdi_poll_once(efx))
  257. break;
  258. if (time_after(time, finish))
  259. return -ETIMEDOUT;
  260. }
  261. /* Return rc=0 like wait_event_timeout() */
  262. return 0;
  263. }
  264. /* Test and clear MC-rebooted flag for this port/function; reset
  265. * software state as necessary.
  266. */
  267. int efx_mcdi_poll_reboot(struct efx_nic *efx)
  268. {
  269. if (!efx->mcdi)
  270. return 0;
  271. return efx->type->mcdi_poll_reboot(efx);
  272. }
  273. static bool efx_mcdi_acquire_async(struct efx_mcdi_iface *mcdi)
  274. {
  275. return cmpxchg(&mcdi->state,
  276. MCDI_STATE_QUIESCENT, MCDI_STATE_RUNNING_ASYNC) ==
  277. MCDI_STATE_QUIESCENT;
  278. }
  279. static void efx_mcdi_acquire_sync(struct efx_mcdi_iface *mcdi)
  280. {
  281. /* Wait until the interface becomes QUIESCENT and we win the race
  282. * to mark it RUNNING_SYNC.
  283. */
  284. wait_event(mcdi->wq,
  285. cmpxchg(&mcdi->state,
  286. MCDI_STATE_QUIESCENT, MCDI_STATE_RUNNING_SYNC) ==
  287. MCDI_STATE_QUIESCENT);
  288. }
  289. static int efx_mcdi_await_completion(struct efx_nic *efx)
  290. {
  291. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  292. if (wait_event_timeout(mcdi->wq, mcdi->state == MCDI_STATE_COMPLETED,
  293. MCDI_RPC_TIMEOUT) == 0)
  294. return -ETIMEDOUT;
  295. /* Check if efx_mcdi_set_mode() switched us back to polled completions.
  296. * In which case, poll for completions directly. If efx_mcdi_ev_cpl()
  297. * completed the request first, then we'll just end up completing the
  298. * request again, which is safe.
  299. *
  300. * We need an smp_rmb() to synchronise with efx_mcdi_mode_poll(), which
  301. * wait_event_timeout() implicitly provides.
  302. */
  303. if (mcdi->mode == MCDI_MODE_POLL)
  304. return efx_mcdi_poll(efx);
  305. return 0;
  306. }
  307. /* If the interface is RUNNING_SYNC, switch to COMPLETED and wake the
  308. * requester. Return whether this was done. Does not take any locks.
  309. */
  310. static bool efx_mcdi_complete_sync(struct efx_mcdi_iface *mcdi)
  311. {
  312. if (cmpxchg(&mcdi->state,
  313. MCDI_STATE_RUNNING_SYNC, MCDI_STATE_COMPLETED) ==
  314. MCDI_STATE_RUNNING_SYNC) {
  315. wake_up(&mcdi->wq);
  316. return true;
  317. }
  318. return false;
  319. }
  320. static void efx_mcdi_release(struct efx_mcdi_iface *mcdi)
  321. {
  322. if (mcdi->mode == MCDI_MODE_EVENTS) {
  323. struct efx_mcdi_async_param *async;
  324. struct efx_nic *efx = mcdi->efx;
  325. /* Process the asynchronous request queue */
  326. spin_lock_bh(&mcdi->async_lock);
  327. async = list_first_entry_or_null(
  328. &mcdi->async_list, struct efx_mcdi_async_param, list);
  329. if (async) {
  330. mcdi->state = MCDI_STATE_RUNNING_ASYNC;
  331. efx_mcdi_send_request(efx, async->cmd,
  332. (const efx_dword_t *)(async + 1),
  333. async->inlen);
  334. mod_timer(&mcdi->async_timer,
  335. jiffies + MCDI_RPC_TIMEOUT);
  336. }
  337. spin_unlock_bh(&mcdi->async_lock);
  338. if (async)
  339. return;
  340. }
  341. mcdi->state = MCDI_STATE_QUIESCENT;
  342. wake_up(&mcdi->wq);
  343. }
  344. /* If the interface is RUNNING_ASYNC, switch to COMPLETED, call the
  345. * asynchronous completion function, and release the interface.
  346. * Return whether this was done. Must be called in bh-disabled
  347. * context. Will take iface_lock and async_lock.
  348. */
  349. static bool efx_mcdi_complete_async(struct efx_mcdi_iface *mcdi, bool timeout)
  350. {
  351. struct efx_nic *efx = mcdi->efx;
  352. struct efx_mcdi_async_param *async;
  353. size_t hdr_len, data_len, err_len;
  354. efx_dword_t *outbuf;
  355. MCDI_DECLARE_BUF_OUT_OR_ERR(errbuf, 0);
  356. int rc;
  357. if (cmpxchg(&mcdi->state,
  358. MCDI_STATE_RUNNING_ASYNC, MCDI_STATE_COMPLETED) !=
  359. MCDI_STATE_RUNNING_ASYNC)
  360. return false;
  361. spin_lock(&mcdi->iface_lock);
  362. if (timeout) {
  363. /* Ensure that if the completion event arrives later,
  364. * the seqno check in efx_mcdi_ev_cpl() will fail
  365. */
  366. ++mcdi->seqno;
  367. ++mcdi->credits;
  368. rc = -ETIMEDOUT;
  369. hdr_len = 0;
  370. data_len = 0;
  371. } else {
  372. rc = mcdi->resprc;
  373. hdr_len = mcdi->resp_hdr_len;
  374. data_len = mcdi->resp_data_len;
  375. }
  376. spin_unlock(&mcdi->iface_lock);
  377. /* Stop the timer. In case the timer function is running, we
  378. * must wait for it to return so that there is no possibility
  379. * of it aborting the next request.
  380. */
  381. if (!timeout)
  382. del_timer_sync(&mcdi->async_timer);
  383. spin_lock(&mcdi->async_lock);
  384. async = list_first_entry(&mcdi->async_list,
  385. struct efx_mcdi_async_param, list);
  386. list_del(&async->list);
  387. spin_unlock(&mcdi->async_lock);
  388. outbuf = (efx_dword_t *)(async + 1);
  389. efx->type->mcdi_read_response(efx, outbuf, hdr_len,
  390. min(async->outlen, data_len));
  391. if (!timeout && rc && !async->quiet) {
  392. err_len = min(sizeof(errbuf), data_len);
  393. efx->type->mcdi_read_response(efx, errbuf, hdr_len,
  394. sizeof(errbuf));
  395. efx_mcdi_display_error(efx, async->cmd, async->inlen, errbuf,
  396. err_len, rc);
  397. }
  398. async->complete(efx, async->cookie, rc, outbuf, data_len);
  399. kfree(async);
  400. efx_mcdi_release(mcdi);
  401. return true;
  402. }
  403. static void efx_mcdi_ev_cpl(struct efx_nic *efx, unsigned int seqno,
  404. unsigned int datalen, unsigned int mcdi_err)
  405. {
  406. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  407. bool wake = false;
  408. spin_lock(&mcdi->iface_lock);
  409. if ((seqno ^ mcdi->seqno) & SEQ_MASK) {
  410. if (mcdi->credits)
  411. /* The request has been cancelled */
  412. --mcdi->credits;
  413. else
  414. netif_err(efx, hw, efx->net_dev,
  415. "MC response mismatch tx seq 0x%x rx "
  416. "seq 0x%x\n", seqno, mcdi->seqno);
  417. } else {
  418. if (efx->type->mcdi_max_ver >= 2) {
  419. /* MCDI v2 responses don't fit in an event */
  420. efx_mcdi_read_response_header(efx);
  421. } else {
  422. mcdi->resprc = efx_mcdi_errno(mcdi_err);
  423. mcdi->resp_hdr_len = 4;
  424. mcdi->resp_data_len = datalen;
  425. }
  426. wake = true;
  427. }
  428. spin_unlock(&mcdi->iface_lock);
  429. if (wake) {
  430. if (!efx_mcdi_complete_async(mcdi, false))
  431. (void) efx_mcdi_complete_sync(mcdi);
  432. /* If the interface isn't RUNNING_ASYNC or
  433. * RUNNING_SYNC then we've received a duplicate
  434. * completion after we've already transitioned back to
  435. * QUIESCENT. [A subsequent invocation would increment
  436. * seqno, so would have failed the seqno check].
  437. */
  438. }
  439. }
  440. static void efx_mcdi_timeout_async(unsigned long context)
  441. {
  442. struct efx_mcdi_iface *mcdi = (struct efx_mcdi_iface *)context;
  443. efx_mcdi_complete_async(mcdi, true);
  444. }
  445. static int
  446. efx_mcdi_check_supported(struct efx_nic *efx, unsigned int cmd, size_t inlen)
  447. {
  448. if (efx->type->mcdi_max_ver < 0 ||
  449. (efx->type->mcdi_max_ver < 2 &&
  450. cmd > MC_CMD_CMD_SPACE_ESCAPE_7))
  451. return -EINVAL;
  452. if (inlen > MCDI_CTL_SDU_LEN_MAX_V2 ||
  453. (efx->type->mcdi_max_ver < 2 &&
  454. inlen > MCDI_CTL_SDU_LEN_MAX_V1))
  455. return -EMSGSIZE;
  456. return 0;
  457. }
  458. static int _efx_mcdi_rpc_finish(struct efx_nic *efx, unsigned cmd, size_t inlen,
  459. efx_dword_t *outbuf, size_t outlen,
  460. size_t *outlen_actual, bool quiet)
  461. {
  462. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  463. MCDI_DECLARE_BUF_OUT_OR_ERR(errbuf, 0);
  464. int rc;
  465. if (mcdi->mode == MCDI_MODE_POLL)
  466. rc = efx_mcdi_poll(efx);
  467. else
  468. rc = efx_mcdi_await_completion(efx);
  469. if (rc != 0) {
  470. netif_err(efx, hw, efx->net_dev,
  471. "MC command 0x%x inlen %d mode %d timed out\n",
  472. cmd, (int)inlen, mcdi->mode);
  473. if (mcdi->mode == MCDI_MODE_EVENTS && efx_mcdi_poll_once(efx)) {
  474. netif_err(efx, hw, efx->net_dev,
  475. "MCDI request was completed without an event\n");
  476. rc = 0;
  477. }
  478. /* Close the race with efx_mcdi_ev_cpl() executing just too late
  479. * and completing a request we've just cancelled, by ensuring
  480. * that the seqno check therein fails.
  481. */
  482. spin_lock_bh(&mcdi->iface_lock);
  483. ++mcdi->seqno;
  484. ++mcdi->credits;
  485. spin_unlock_bh(&mcdi->iface_lock);
  486. }
  487. if (rc != 0) {
  488. if (outlen_actual)
  489. *outlen_actual = 0;
  490. } else {
  491. size_t hdr_len, data_len, err_len;
  492. /* At the very least we need a memory barrier here to ensure
  493. * we pick up changes from efx_mcdi_ev_cpl(). Protect against
  494. * a spurious efx_mcdi_ev_cpl() running concurrently by
  495. * acquiring the iface_lock. */
  496. spin_lock_bh(&mcdi->iface_lock);
  497. rc = mcdi->resprc;
  498. hdr_len = mcdi->resp_hdr_len;
  499. data_len = mcdi->resp_data_len;
  500. err_len = min(sizeof(errbuf), data_len);
  501. spin_unlock_bh(&mcdi->iface_lock);
  502. BUG_ON(rc > 0);
  503. efx->type->mcdi_read_response(efx, outbuf, hdr_len,
  504. min(outlen, data_len));
  505. if (outlen_actual)
  506. *outlen_actual = data_len;
  507. efx->type->mcdi_read_response(efx, errbuf, hdr_len, err_len);
  508. if (cmd == MC_CMD_REBOOT && rc == -EIO) {
  509. /* Don't reset if MC_CMD_REBOOT returns EIO */
  510. } else if (rc == -EIO || rc == -EINTR) {
  511. netif_err(efx, hw, efx->net_dev, "MC fatal error %d\n",
  512. -rc);
  513. efx_schedule_reset(efx, RESET_TYPE_MC_FAILURE);
  514. } else if (rc && !quiet) {
  515. efx_mcdi_display_error(efx, cmd, inlen, errbuf, err_len,
  516. rc);
  517. }
  518. if (rc == -EIO || rc == -EINTR) {
  519. msleep(MCDI_STATUS_SLEEP_MS);
  520. efx_mcdi_poll_reboot(efx);
  521. mcdi->new_epoch = true;
  522. }
  523. }
  524. efx_mcdi_release(mcdi);
  525. return rc;
  526. }
  527. static int _efx_mcdi_rpc(struct efx_nic *efx, unsigned cmd,
  528. const efx_dword_t *inbuf, size_t inlen,
  529. efx_dword_t *outbuf, size_t outlen,
  530. size_t *outlen_actual, bool quiet)
  531. {
  532. int rc;
  533. rc = efx_mcdi_rpc_start(efx, cmd, inbuf, inlen);
  534. if (rc) {
  535. if (outlen_actual)
  536. *outlen_actual = 0;
  537. return rc;
  538. }
  539. return _efx_mcdi_rpc_finish(efx, cmd, inlen, outbuf, outlen,
  540. outlen_actual, quiet);
  541. }
  542. int efx_mcdi_rpc(struct efx_nic *efx, unsigned cmd,
  543. const efx_dword_t *inbuf, size_t inlen,
  544. efx_dword_t *outbuf, size_t outlen,
  545. size_t *outlen_actual)
  546. {
  547. return _efx_mcdi_rpc(efx, cmd, inbuf, inlen, outbuf, outlen,
  548. outlen_actual, false);
  549. }
  550. /* Normally, on receiving an error code in the MCDI response,
  551. * efx_mcdi_rpc will log an error message containing (among other
  552. * things) the raw error code, by means of efx_mcdi_display_error.
  553. * This _quiet version suppresses that; if the caller wishes to log
  554. * the error conditionally on the return code, it should call this
  555. * function and is then responsible for calling efx_mcdi_display_error
  556. * as needed.
  557. */
  558. int efx_mcdi_rpc_quiet(struct efx_nic *efx, unsigned cmd,
  559. const efx_dword_t *inbuf, size_t inlen,
  560. efx_dword_t *outbuf, size_t outlen,
  561. size_t *outlen_actual)
  562. {
  563. return _efx_mcdi_rpc(efx, cmd, inbuf, inlen, outbuf, outlen,
  564. outlen_actual, true);
  565. }
  566. int efx_mcdi_rpc_start(struct efx_nic *efx, unsigned cmd,
  567. const efx_dword_t *inbuf, size_t inlen)
  568. {
  569. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  570. int rc;
  571. rc = efx_mcdi_check_supported(efx, cmd, inlen);
  572. if (rc)
  573. return rc;
  574. if (efx->mc_bist_for_other_fn)
  575. return -ENETDOWN;
  576. efx_mcdi_acquire_sync(mcdi);
  577. efx_mcdi_send_request(efx, cmd, inbuf, inlen);
  578. return 0;
  579. }
  580. static int _efx_mcdi_rpc_async(struct efx_nic *efx, unsigned int cmd,
  581. const efx_dword_t *inbuf, size_t inlen,
  582. size_t outlen,
  583. efx_mcdi_async_completer *complete,
  584. unsigned long cookie, bool quiet)
  585. {
  586. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  587. struct efx_mcdi_async_param *async;
  588. int rc;
  589. rc = efx_mcdi_check_supported(efx, cmd, inlen);
  590. if (rc)
  591. return rc;
  592. if (efx->mc_bist_for_other_fn)
  593. return -ENETDOWN;
  594. async = kmalloc(sizeof(*async) + ALIGN(max(inlen, outlen), 4),
  595. GFP_ATOMIC);
  596. if (!async)
  597. return -ENOMEM;
  598. async->cmd = cmd;
  599. async->inlen = inlen;
  600. async->outlen = outlen;
  601. async->quiet = quiet;
  602. async->complete = complete;
  603. async->cookie = cookie;
  604. memcpy(async + 1, inbuf, inlen);
  605. spin_lock_bh(&mcdi->async_lock);
  606. if (mcdi->mode == MCDI_MODE_EVENTS) {
  607. list_add_tail(&async->list, &mcdi->async_list);
  608. /* If this is at the front of the queue, try to start it
  609. * immediately
  610. */
  611. if (mcdi->async_list.next == &async->list &&
  612. efx_mcdi_acquire_async(mcdi)) {
  613. efx_mcdi_send_request(efx, cmd, inbuf, inlen);
  614. mod_timer(&mcdi->async_timer,
  615. jiffies + MCDI_RPC_TIMEOUT);
  616. }
  617. } else {
  618. kfree(async);
  619. rc = -ENETDOWN;
  620. }
  621. spin_unlock_bh(&mcdi->async_lock);
  622. return rc;
  623. }
  624. /**
  625. * efx_mcdi_rpc_async - Schedule an MCDI command to run asynchronously
  626. * @efx: NIC through which to issue the command
  627. * @cmd: Command type number
  628. * @inbuf: Command parameters
  629. * @inlen: Length of command parameters, in bytes
  630. * @outlen: Length to allocate for response buffer, in bytes
  631. * @complete: Function to be called on completion or cancellation.
  632. * @cookie: Arbitrary value to be passed to @complete.
  633. *
  634. * This function does not sleep and therefore may be called in atomic
  635. * context. It will fail if event queues are disabled or if MCDI
  636. * event completions have been disabled due to an error.
  637. *
  638. * If it succeeds, the @complete function will be called exactly once
  639. * in atomic context, when one of the following occurs:
  640. * (a) the completion event is received (in NAPI context)
  641. * (b) event queues are disabled (in the process that disables them)
  642. * (c) the request times-out (in timer context)
  643. */
  644. int
  645. efx_mcdi_rpc_async(struct efx_nic *efx, unsigned int cmd,
  646. const efx_dword_t *inbuf, size_t inlen, size_t outlen,
  647. efx_mcdi_async_completer *complete, unsigned long cookie)
  648. {
  649. return _efx_mcdi_rpc_async(efx, cmd, inbuf, inlen, outlen, complete,
  650. cookie, false);
  651. }
  652. int efx_mcdi_rpc_async_quiet(struct efx_nic *efx, unsigned int cmd,
  653. const efx_dword_t *inbuf, size_t inlen,
  654. size_t outlen, efx_mcdi_async_completer *complete,
  655. unsigned long cookie)
  656. {
  657. return _efx_mcdi_rpc_async(efx, cmd, inbuf, inlen, outlen, complete,
  658. cookie, true);
  659. }
  660. int efx_mcdi_rpc_finish(struct efx_nic *efx, unsigned cmd, size_t inlen,
  661. efx_dword_t *outbuf, size_t outlen,
  662. size_t *outlen_actual)
  663. {
  664. return _efx_mcdi_rpc_finish(efx, cmd, inlen, outbuf, outlen,
  665. outlen_actual, false);
  666. }
  667. int efx_mcdi_rpc_finish_quiet(struct efx_nic *efx, unsigned cmd, size_t inlen,
  668. efx_dword_t *outbuf, size_t outlen,
  669. size_t *outlen_actual)
  670. {
  671. return _efx_mcdi_rpc_finish(efx, cmd, inlen, outbuf, outlen,
  672. outlen_actual, true);
  673. }
  674. void efx_mcdi_display_error(struct efx_nic *efx, unsigned cmd,
  675. size_t inlen, efx_dword_t *outbuf,
  676. size_t outlen, int rc)
  677. {
  678. int code = 0, err_arg = 0;
  679. if (outlen >= MC_CMD_ERR_CODE_OFST + 4)
  680. code = MCDI_DWORD(outbuf, ERR_CODE);
  681. if (outlen >= MC_CMD_ERR_ARG_OFST + 4)
  682. err_arg = MCDI_DWORD(outbuf, ERR_ARG);
  683. netif_err(efx, hw, efx->net_dev,
  684. "MC command 0x%x inlen %d failed rc=%d (raw=%d) arg=%d\n",
  685. cmd, (int)inlen, rc, code, err_arg);
  686. }
  687. /* Switch to polled MCDI completions. This can be called in various
  688. * error conditions with various locks held, so it must be lockless.
  689. * Caller is responsible for flushing asynchronous requests later.
  690. */
  691. void efx_mcdi_mode_poll(struct efx_nic *efx)
  692. {
  693. struct efx_mcdi_iface *mcdi;
  694. if (!efx->mcdi)
  695. return;
  696. mcdi = efx_mcdi(efx);
  697. if (mcdi->mode == MCDI_MODE_POLL)
  698. return;
  699. /* We can switch from event completion to polled completion, because
  700. * mcdi requests are always completed in shared memory. We do this by
  701. * switching the mode to POLL'd then completing the request.
  702. * efx_mcdi_await_completion() will then call efx_mcdi_poll().
  703. *
  704. * We need an smp_wmb() to synchronise with efx_mcdi_await_completion(),
  705. * which efx_mcdi_complete_sync() provides for us.
  706. */
  707. mcdi->mode = MCDI_MODE_POLL;
  708. efx_mcdi_complete_sync(mcdi);
  709. }
  710. /* Flush any running or queued asynchronous requests, after event processing
  711. * is stopped
  712. */
  713. void efx_mcdi_flush_async(struct efx_nic *efx)
  714. {
  715. struct efx_mcdi_async_param *async, *next;
  716. struct efx_mcdi_iface *mcdi;
  717. if (!efx->mcdi)
  718. return;
  719. mcdi = efx_mcdi(efx);
  720. /* We must be in polling mode so no more requests can be queued */
  721. BUG_ON(mcdi->mode != MCDI_MODE_POLL);
  722. del_timer_sync(&mcdi->async_timer);
  723. /* If a request is still running, make sure we give the MC
  724. * time to complete it so that the response won't overwrite our
  725. * next request.
  726. */
  727. if (mcdi->state == MCDI_STATE_RUNNING_ASYNC) {
  728. efx_mcdi_poll(efx);
  729. mcdi->state = MCDI_STATE_QUIESCENT;
  730. }
  731. /* Nothing else will access the async list now, so it is safe
  732. * to walk it without holding async_lock. If we hold it while
  733. * calling a completer then lockdep may warn that we have
  734. * acquired locks in the wrong order.
  735. */
  736. list_for_each_entry_safe(async, next, &mcdi->async_list, list) {
  737. async->complete(efx, async->cookie, -ENETDOWN, NULL, 0);
  738. list_del(&async->list);
  739. kfree(async);
  740. }
  741. }
  742. void efx_mcdi_mode_event(struct efx_nic *efx)
  743. {
  744. struct efx_mcdi_iface *mcdi;
  745. if (!efx->mcdi)
  746. return;
  747. mcdi = efx_mcdi(efx);
  748. if (mcdi->mode == MCDI_MODE_EVENTS)
  749. return;
  750. /* We can't switch from polled to event completion in the middle of a
  751. * request, because the completion method is specified in the request.
  752. * So acquire the interface to serialise the requestors. We don't need
  753. * to acquire the iface_lock to change the mode here, but we do need a
  754. * write memory barrier ensure that efx_mcdi_rpc() sees it, which
  755. * efx_mcdi_acquire() provides.
  756. */
  757. efx_mcdi_acquire_sync(mcdi);
  758. mcdi->mode = MCDI_MODE_EVENTS;
  759. efx_mcdi_release(mcdi);
  760. }
  761. static void efx_mcdi_ev_death(struct efx_nic *efx, int rc)
  762. {
  763. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  764. /* If there is an outstanding MCDI request, it has been terminated
  765. * either by a BADASSERT or REBOOT event. If the mcdi interface is
  766. * in polled mode, then do nothing because the MC reboot handler will
  767. * set the header correctly. However, if the mcdi interface is waiting
  768. * for a CMDDONE event it won't receive it [and since all MCDI events
  769. * are sent to the same queue, we can't be racing with
  770. * efx_mcdi_ev_cpl()]
  771. *
  772. * If there is an outstanding asynchronous request, we can't
  773. * complete it now (efx_mcdi_complete() would deadlock). The
  774. * reset process will take care of this.
  775. *
  776. * There's a race here with efx_mcdi_send_request(), because
  777. * we might receive a REBOOT event *before* the request has
  778. * been copied out. In polled mode (during startup) this is
  779. * irrelevant, because efx_mcdi_complete_sync() is ignored. In
  780. * event mode, this condition is just an edge-case of
  781. * receiving a REBOOT event after posting the MCDI
  782. * request. Did the mc reboot before or after the copyout? The
  783. * best we can do always is just return failure.
  784. */
  785. spin_lock(&mcdi->iface_lock);
  786. if (efx_mcdi_complete_sync(mcdi)) {
  787. if (mcdi->mode == MCDI_MODE_EVENTS) {
  788. mcdi->resprc = rc;
  789. mcdi->resp_hdr_len = 0;
  790. mcdi->resp_data_len = 0;
  791. ++mcdi->credits;
  792. }
  793. } else {
  794. int count;
  795. /* Consume the status word since efx_mcdi_rpc_finish() won't */
  796. for (count = 0; count < MCDI_STATUS_DELAY_COUNT; ++count) {
  797. if (efx_mcdi_poll_reboot(efx))
  798. break;
  799. udelay(MCDI_STATUS_DELAY_US);
  800. }
  801. mcdi->new_epoch = true;
  802. /* Nobody was waiting for an MCDI request, so trigger a reset */
  803. efx_schedule_reset(efx, RESET_TYPE_MC_FAILURE);
  804. }
  805. spin_unlock(&mcdi->iface_lock);
  806. }
  807. /* The MC is going down in to BIST mode. set the BIST flag to block
  808. * new MCDI, cancel any outstanding MCDI and and schedule a BIST-type reset
  809. * (which doesn't actually execute a reset, it waits for the controlling
  810. * function to reset it).
  811. */
  812. static void efx_mcdi_ev_bist(struct efx_nic *efx)
  813. {
  814. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  815. spin_lock(&mcdi->iface_lock);
  816. efx->mc_bist_for_other_fn = true;
  817. if (efx_mcdi_complete_sync(mcdi)) {
  818. if (mcdi->mode == MCDI_MODE_EVENTS) {
  819. mcdi->resprc = -EIO;
  820. mcdi->resp_hdr_len = 0;
  821. mcdi->resp_data_len = 0;
  822. ++mcdi->credits;
  823. }
  824. }
  825. mcdi->new_epoch = true;
  826. efx_schedule_reset(efx, RESET_TYPE_MC_BIST);
  827. spin_unlock(&mcdi->iface_lock);
  828. }
  829. /* Called from falcon_process_eventq for MCDI events */
  830. void efx_mcdi_process_event(struct efx_channel *channel,
  831. efx_qword_t *event)
  832. {
  833. struct efx_nic *efx = channel->efx;
  834. int code = EFX_QWORD_FIELD(*event, MCDI_EVENT_CODE);
  835. u32 data = EFX_QWORD_FIELD(*event, MCDI_EVENT_DATA);
  836. switch (code) {
  837. case MCDI_EVENT_CODE_BADSSERT:
  838. netif_err(efx, hw, efx->net_dev,
  839. "MC watchdog or assertion failure at 0x%x\n", data);
  840. efx_mcdi_ev_death(efx, -EINTR);
  841. break;
  842. case MCDI_EVENT_CODE_PMNOTICE:
  843. netif_info(efx, wol, efx->net_dev, "MCDI PM event.\n");
  844. break;
  845. case MCDI_EVENT_CODE_CMDDONE:
  846. efx_mcdi_ev_cpl(efx,
  847. MCDI_EVENT_FIELD(*event, CMDDONE_SEQ),
  848. MCDI_EVENT_FIELD(*event, CMDDONE_DATALEN),
  849. MCDI_EVENT_FIELD(*event, CMDDONE_ERRNO));
  850. break;
  851. case MCDI_EVENT_CODE_LINKCHANGE:
  852. efx_mcdi_process_link_change(efx, event);
  853. break;
  854. case MCDI_EVENT_CODE_SENSOREVT:
  855. efx_mcdi_sensor_event(efx, event);
  856. break;
  857. case MCDI_EVENT_CODE_SCHEDERR:
  858. netif_dbg(efx, hw, efx->net_dev,
  859. "MC Scheduler alert (0x%x)\n", data);
  860. break;
  861. case MCDI_EVENT_CODE_REBOOT:
  862. case MCDI_EVENT_CODE_MC_REBOOT:
  863. netif_info(efx, hw, efx->net_dev, "MC Reboot\n");
  864. efx_mcdi_ev_death(efx, -EIO);
  865. break;
  866. case MCDI_EVENT_CODE_MC_BIST:
  867. netif_info(efx, hw, efx->net_dev, "MC entered BIST mode\n");
  868. efx_mcdi_ev_bist(efx);
  869. break;
  870. case MCDI_EVENT_CODE_MAC_STATS_DMA:
  871. /* MAC stats are gather lazily. We can ignore this. */
  872. break;
  873. case MCDI_EVENT_CODE_FLR:
  874. efx_sriov_flr(efx, MCDI_EVENT_FIELD(*event, FLR_VF));
  875. break;
  876. case MCDI_EVENT_CODE_PTP_RX:
  877. case MCDI_EVENT_CODE_PTP_FAULT:
  878. case MCDI_EVENT_CODE_PTP_PPS:
  879. efx_ptp_event(efx, event);
  880. break;
  881. case MCDI_EVENT_CODE_PTP_TIME:
  882. efx_time_sync_event(channel, event);
  883. break;
  884. case MCDI_EVENT_CODE_TX_FLUSH:
  885. case MCDI_EVENT_CODE_RX_FLUSH:
  886. /* Two flush events will be sent: one to the same event
  887. * queue as completions, and one to event queue 0.
  888. * In the latter case the {RX,TX}_FLUSH_TO_DRIVER
  889. * flag will be set, and we should ignore the event
  890. * because we want to wait for all completions.
  891. */
  892. BUILD_BUG_ON(MCDI_EVENT_TX_FLUSH_TO_DRIVER_LBN !=
  893. MCDI_EVENT_RX_FLUSH_TO_DRIVER_LBN);
  894. if (!MCDI_EVENT_FIELD(*event, TX_FLUSH_TO_DRIVER))
  895. efx_ef10_handle_drain_event(efx);
  896. break;
  897. case MCDI_EVENT_CODE_TX_ERR:
  898. case MCDI_EVENT_CODE_RX_ERR:
  899. netif_err(efx, hw, efx->net_dev,
  900. "%s DMA error (event: "EFX_QWORD_FMT")\n",
  901. code == MCDI_EVENT_CODE_TX_ERR ? "TX" : "RX",
  902. EFX_QWORD_VAL(*event));
  903. efx_schedule_reset(efx, RESET_TYPE_DMA_ERROR);
  904. break;
  905. default:
  906. netif_err(efx, hw, efx->net_dev, "Unknown MCDI event 0x%x\n",
  907. code);
  908. }
  909. }
  910. /**************************************************************************
  911. *
  912. * Specific request functions
  913. *
  914. **************************************************************************
  915. */
  916. void efx_mcdi_print_fwver(struct efx_nic *efx, char *buf, size_t len)
  917. {
  918. MCDI_DECLARE_BUF(outbuf,
  919. max(MC_CMD_GET_VERSION_OUT_LEN,
  920. MC_CMD_GET_CAPABILITIES_OUT_LEN));
  921. size_t outlength;
  922. const __le16 *ver_words;
  923. size_t offset;
  924. int rc;
  925. BUILD_BUG_ON(MC_CMD_GET_VERSION_IN_LEN != 0);
  926. rc = efx_mcdi_rpc(efx, MC_CMD_GET_VERSION, NULL, 0,
  927. outbuf, sizeof(outbuf), &outlength);
  928. if (rc)
  929. goto fail;
  930. if (outlength < MC_CMD_GET_VERSION_OUT_LEN) {
  931. rc = -EIO;
  932. goto fail;
  933. }
  934. ver_words = (__le16 *)MCDI_PTR(outbuf, GET_VERSION_OUT_VERSION);
  935. offset = snprintf(buf, len, "%u.%u.%u.%u",
  936. le16_to_cpu(ver_words[0]), le16_to_cpu(ver_words[1]),
  937. le16_to_cpu(ver_words[2]), le16_to_cpu(ver_words[3]));
  938. /* EF10 may have multiple datapath firmware variants within a
  939. * single version. Report which variants are running.
  940. */
  941. if (efx_nic_rev(efx) >= EFX_REV_HUNT_A0) {
  942. BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN != 0);
  943. rc = efx_mcdi_rpc(efx, MC_CMD_GET_CAPABILITIES, NULL, 0,
  944. outbuf, sizeof(outbuf), &outlength);
  945. if (rc || outlength < MC_CMD_GET_CAPABILITIES_OUT_LEN)
  946. offset += snprintf(
  947. buf + offset, len - offset, " rx? tx?");
  948. else
  949. offset += snprintf(
  950. buf + offset, len - offset, " rx%x tx%x",
  951. MCDI_WORD(outbuf,
  952. GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID),
  953. MCDI_WORD(outbuf,
  954. GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID));
  955. /* It's theoretically possible for the string to exceed 31
  956. * characters, though in practice the first three version
  957. * components are short enough that this doesn't happen.
  958. */
  959. if (WARN_ON(offset >= len))
  960. buf[0] = 0;
  961. }
  962. return;
  963. fail:
  964. netif_err(efx, probe, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  965. buf[0] = 0;
  966. }
  967. static int efx_mcdi_drv_attach(struct efx_nic *efx, bool driver_operating,
  968. bool *was_attached)
  969. {
  970. MCDI_DECLARE_BUF(inbuf, MC_CMD_DRV_ATTACH_IN_LEN);
  971. MCDI_DECLARE_BUF(outbuf, MC_CMD_DRV_ATTACH_EXT_OUT_LEN);
  972. size_t outlen;
  973. int rc;
  974. MCDI_SET_DWORD(inbuf, DRV_ATTACH_IN_NEW_STATE,
  975. driver_operating ? 1 : 0);
  976. MCDI_SET_DWORD(inbuf, DRV_ATTACH_IN_UPDATE, 1);
  977. MCDI_SET_DWORD(inbuf, DRV_ATTACH_IN_FIRMWARE_ID, MC_CMD_FW_LOW_LATENCY);
  978. rc = efx_mcdi_rpc(efx, MC_CMD_DRV_ATTACH, inbuf, sizeof(inbuf),
  979. outbuf, sizeof(outbuf), &outlen);
  980. if (rc)
  981. goto fail;
  982. if (outlen < MC_CMD_DRV_ATTACH_OUT_LEN) {
  983. rc = -EIO;
  984. goto fail;
  985. }
  986. if (driver_operating) {
  987. if (outlen >= MC_CMD_DRV_ATTACH_EXT_OUT_LEN) {
  988. efx->mcdi->fn_flags =
  989. MCDI_DWORD(outbuf,
  990. DRV_ATTACH_EXT_OUT_FUNC_FLAGS);
  991. } else {
  992. /* Synthesise flags for Siena */
  993. efx->mcdi->fn_flags =
  994. 1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL |
  995. 1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_TRUSTED |
  996. (efx_port_num(efx) == 0) <<
  997. MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY;
  998. }
  999. }
  1000. /* We currently assume we have control of the external link
  1001. * and are completely trusted by firmware. Abort probing
  1002. * if that's not true for this function.
  1003. */
  1004. if (driver_operating &&
  1005. (efx->mcdi->fn_flags &
  1006. (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL |
  1007. 1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_TRUSTED)) !=
  1008. (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL |
  1009. 1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_TRUSTED)) {
  1010. netif_err(efx, probe, efx->net_dev,
  1011. "This driver version only supports one function per port\n");
  1012. return -ENODEV;
  1013. }
  1014. if (was_attached != NULL)
  1015. *was_attached = MCDI_DWORD(outbuf, DRV_ATTACH_OUT_OLD_STATE);
  1016. return 0;
  1017. fail:
  1018. netif_err(efx, probe, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  1019. return rc;
  1020. }
  1021. int efx_mcdi_get_board_cfg(struct efx_nic *efx, u8 *mac_address,
  1022. u16 *fw_subtype_list, u32 *capabilities)
  1023. {
  1024. MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_BOARD_CFG_OUT_LENMAX);
  1025. size_t outlen, i;
  1026. int port_num = efx_port_num(efx);
  1027. int rc;
  1028. BUILD_BUG_ON(MC_CMD_GET_BOARD_CFG_IN_LEN != 0);
  1029. rc = efx_mcdi_rpc(efx, MC_CMD_GET_BOARD_CFG, NULL, 0,
  1030. outbuf, sizeof(outbuf), &outlen);
  1031. if (rc)
  1032. goto fail;
  1033. if (outlen < MC_CMD_GET_BOARD_CFG_OUT_LENMIN) {
  1034. rc = -EIO;
  1035. goto fail;
  1036. }
  1037. if (mac_address)
  1038. memcpy(mac_address,
  1039. port_num ?
  1040. MCDI_PTR(outbuf, GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1) :
  1041. MCDI_PTR(outbuf, GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0),
  1042. ETH_ALEN);
  1043. if (fw_subtype_list) {
  1044. for (i = 0;
  1045. i < MCDI_VAR_ARRAY_LEN(outlen,
  1046. GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST);
  1047. i++)
  1048. fw_subtype_list[i] = MCDI_ARRAY_WORD(
  1049. outbuf, GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST, i);
  1050. for (; i < MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MAXNUM; i++)
  1051. fw_subtype_list[i] = 0;
  1052. }
  1053. if (capabilities) {
  1054. if (port_num)
  1055. *capabilities = MCDI_DWORD(outbuf,
  1056. GET_BOARD_CFG_OUT_CAPABILITIES_PORT1);
  1057. else
  1058. *capabilities = MCDI_DWORD(outbuf,
  1059. GET_BOARD_CFG_OUT_CAPABILITIES_PORT0);
  1060. }
  1061. return 0;
  1062. fail:
  1063. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d len=%d\n",
  1064. __func__, rc, (int)outlen);
  1065. return rc;
  1066. }
  1067. int efx_mcdi_log_ctrl(struct efx_nic *efx, bool evq, bool uart, u32 dest_evq)
  1068. {
  1069. MCDI_DECLARE_BUF(inbuf, MC_CMD_LOG_CTRL_IN_LEN);
  1070. u32 dest = 0;
  1071. int rc;
  1072. if (uart)
  1073. dest |= MC_CMD_LOG_CTRL_IN_LOG_DEST_UART;
  1074. if (evq)
  1075. dest |= MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ;
  1076. MCDI_SET_DWORD(inbuf, LOG_CTRL_IN_LOG_DEST, dest);
  1077. MCDI_SET_DWORD(inbuf, LOG_CTRL_IN_LOG_DEST_EVQ, dest_evq);
  1078. BUILD_BUG_ON(MC_CMD_LOG_CTRL_OUT_LEN != 0);
  1079. rc = efx_mcdi_rpc(efx, MC_CMD_LOG_CTRL, inbuf, sizeof(inbuf),
  1080. NULL, 0, NULL);
  1081. return rc;
  1082. }
  1083. int efx_mcdi_nvram_types(struct efx_nic *efx, u32 *nvram_types_out)
  1084. {
  1085. MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_TYPES_OUT_LEN);
  1086. size_t outlen;
  1087. int rc;
  1088. BUILD_BUG_ON(MC_CMD_NVRAM_TYPES_IN_LEN != 0);
  1089. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_TYPES, NULL, 0,
  1090. outbuf, sizeof(outbuf), &outlen);
  1091. if (rc)
  1092. goto fail;
  1093. if (outlen < MC_CMD_NVRAM_TYPES_OUT_LEN) {
  1094. rc = -EIO;
  1095. goto fail;
  1096. }
  1097. *nvram_types_out = MCDI_DWORD(outbuf, NVRAM_TYPES_OUT_TYPES);
  1098. return 0;
  1099. fail:
  1100. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n",
  1101. __func__, rc);
  1102. return rc;
  1103. }
  1104. int efx_mcdi_nvram_info(struct efx_nic *efx, unsigned int type,
  1105. size_t *size_out, size_t *erase_size_out,
  1106. bool *protected_out)
  1107. {
  1108. MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_INFO_IN_LEN);
  1109. MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_INFO_OUT_LEN);
  1110. size_t outlen;
  1111. int rc;
  1112. MCDI_SET_DWORD(inbuf, NVRAM_INFO_IN_TYPE, type);
  1113. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_INFO, inbuf, sizeof(inbuf),
  1114. outbuf, sizeof(outbuf), &outlen);
  1115. if (rc)
  1116. goto fail;
  1117. if (outlen < MC_CMD_NVRAM_INFO_OUT_LEN) {
  1118. rc = -EIO;
  1119. goto fail;
  1120. }
  1121. *size_out = MCDI_DWORD(outbuf, NVRAM_INFO_OUT_SIZE);
  1122. *erase_size_out = MCDI_DWORD(outbuf, NVRAM_INFO_OUT_ERASESIZE);
  1123. *protected_out = !!(MCDI_DWORD(outbuf, NVRAM_INFO_OUT_FLAGS) &
  1124. (1 << MC_CMD_NVRAM_INFO_OUT_PROTECTED_LBN));
  1125. return 0;
  1126. fail:
  1127. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  1128. return rc;
  1129. }
  1130. static int efx_mcdi_nvram_test(struct efx_nic *efx, unsigned int type)
  1131. {
  1132. MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_TEST_IN_LEN);
  1133. MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_TEST_OUT_LEN);
  1134. int rc;
  1135. MCDI_SET_DWORD(inbuf, NVRAM_TEST_IN_TYPE, type);
  1136. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_TEST, inbuf, sizeof(inbuf),
  1137. outbuf, sizeof(outbuf), NULL);
  1138. if (rc)
  1139. return rc;
  1140. switch (MCDI_DWORD(outbuf, NVRAM_TEST_OUT_RESULT)) {
  1141. case MC_CMD_NVRAM_TEST_PASS:
  1142. case MC_CMD_NVRAM_TEST_NOTSUPP:
  1143. return 0;
  1144. default:
  1145. return -EIO;
  1146. }
  1147. }
  1148. int efx_mcdi_nvram_test_all(struct efx_nic *efx)
  1149. {
  1150. u32 nvram_types;
  1151. unsigned int type;
  1152. int rc;
  1153. rc = efx_mcdi_nvram_types(efx, &nvram_types);
  1154. if (rc)
  1155. goto fail1;
  1156. type = 0;
  1157. while (nvram_types != 0) {
  1158. if (nvram_types & 1) {
  1159. rc = efx_mcdi_nvram_test(efx, type);
  1160. if (rc)
  1161. goto fail2;
  1162. }
  1163. type++;
  1164. nvram_types >>= 1;
  1165. }
  1166. return 0;
  1167. fail2:
  1168. netif_err(efx, hw, efx->net_dev, "%s: failed type=%u\n",
  1169. __func__, type);
  1170. fail1:
  1171. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  1172. return rc;
  1173. }
  1174. static int efx_mcdi_read_assertion(struct efx_nic *efx)
  1175. {
  1176. MCDI_DECLARE_BUF(inbuf, MC_CMD_GET_ASSERTS_IN_LEN);
  1177. MCDI_DECLARE_BUF_OUT_OR_ERR(outbuf, MC_CMD_GET_ASSERTS_OUT_LEN);
  1178. unsigned int flags, index;
  1179. const char *reason;
  1180. size_t outlen;
  1181. int retry;
  1182. int rc;
  1183. /* Attempt to read any stored assertion state before we reboot
  1184. * the mcfw out of the assertion handler. Retry twice, once
  1185. * because a boot-time assertion might cause this command to fail
  1186. * with EINTR. And once again because GET_ASSERTS can race with
  1187. * MC_CMD_REBOOT running on the other port. */
  1188. retry = 2;
  1189. do {
  1190. MCDI_SET_DWORD(inbuf, GET_ASSERTS_IN_CLEAR, 1);
  1191. rc = efx_mcdi_rpc_quiet(efx, MC_CMD_GET_ASSERTS,
  1192. inbuf, MC_CMD_GET_ASSERTS_IN_LEN,
  1193. outbuf, sizeof(outbuf), &outlen);
  1194. } while ((rc == -EINTR || rc == -EIO) && retry-- > 0);
  1195. if (rc) {
  1196. efx_mcdi_display_error(efx, MC_CMD_GET_ASSERTS,
  1197. MC_CMD_GET_ASSERTS_IN_LEN, outbuf,
  1198. outlen, rc);
  1199. return rc;
  1200. }
  1201. if (outlen < MC_CMD_GET_ASSERTS_OUT_LEN)
  1202. return -EIO;
  1203. /* Print out any recorded assertion state */
  1204. flags = MCDI_DWORD(outbuf, GET_ASSERTS_OUT_GLOBAL_FLAGS);
  1205. if (flags == MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS)
  1206. return 0;
  1207. reason = (flags == MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL)
  1208. ? "system-level assertion"
  1209. : (flags == MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL)
  1210. ? "thread-level assertion"
  1211. : (flags == MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED)
  1212. ? "watchdog reset"
  1213. : "unknown assertion";
  1214. netif_err(efx, hw, efx->net_dev,
  1215. "MCPU %s at PC = 0x%.8x in thread 0x%.8x\n", reason,
  1216. MCDI_DWORD(outbuf, GET_ASSERTS_OUT_SAVED_PC_OFFS),
  1217. MCDI_DWORD(outbuf, GET_ASSERTS_OUT_THREAD_OFFS));
  1218. /* Print out the registers */
  1219. for (index = 0;
  1220. index < MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_NUM;
  1221. index++)
  1222. netif_err(efx, hw, efx->net_dev, "R%.2d (?): 0x%.8x\n",
  1223. 1 + index,
  1224. MCDI_ARRAY_DWORD(outbuf, GET_ASSERTS_OUT_GP_REGS_OFFS,
  1225. index));
  1226. return 0;
  1227. }
  1228. static void efx_mcdi_exit_assertion(struct efx_nic *efx)
  1229. {
  1230. MCDI_DECLARE_BUF(inbuf, MC_CMD_REBOOT_IN_LEN);
  1231. /* If the MC is running debug firmware, it might now be
  1232. * waiting for a debugger to attach, but we just want it to
  1233. * reboot. We set a flag that makes the command a no-op if it
  1234. * has already done so. We don't know what return code to
  1235. * expect (0 or -EIO), so ignore it.
  1236. */
  1237. BUILD_BUG_ON(MC_CMD_REBOOT_OUT_LEN != 0);
  1238. MCDI_SET_DWORD(inbuf, REBOOT_IN_FLAGS,
  1239. MC_CMD_REBOOT_FLAGS_AFTER_ASSERTION);
  1240. (void) efx_mcdi_rpc(efx, MC_CMD_REBOOT, inbuf, MC_CMD_REBOOT_IN_LEN,
  1241. NULL, 0, NULL);
  1242. }
  1243. int efx_mcdi_handle_assertion(struct efx_nic *efx)
  1244. {
  1245. int rc;
  1246. rc = efx_mcdi_read_assertion(efx);
  1247. if (rc)
  1248. return rc;
  1249. efx_mcdi_exit_assertion(efx);
  1250. return 0;
  1251. }
  1252. void efx_mcdi_set_id_led(struct efx_nic *efx, enum efx_led_mode mode)
  1253. {
  1254. MCDI_DECLARE_BUF(inbuf, MC_CMD_SET_ID_LED_IN_LEN);
  1255. int rc;
  1256. BUILD_BUG_ON(EFX_LED_OFF != MC_CMD_LED_OFF);
  1257. BUILD_BUG_ON(EFX_LED_ON != MC_CMD_LED_ON);
  1258. BUILD_BUG_ON(EFX_LED_DEFAULT != MC_CMD_LED_DEFAULT);
  1259. BUILD_BUG_ON(MC_CMD_SET_ID_LED_OUT_LEN != 0);
  1260. MCDI_SET_DWORD(inbuf, SET_ID_LED_IN_STATE, mode);
  1261. rc = efx_mcdi_rpc(efx, MC_CMD_SET_ID_LED, inbuf, sizeof(inbuf),
  1262. NULL, 0, NULL);
  1263. }
  1264. static int efx_mcdi_reset_func(struct efx_nic *efx)
  1265. {
  1266. MCDI_DECLARE_BUF(inbuf, MC_CMD_ENTITY_RESET_IN_LEN);
  1267. int rc;
  1268. BUILD_BUG_ON(MC_CMD_ENTITY_RESET_OUT_LEN != 0);
  1269. MCDI_POPULATE_DWORD_1(inbuf, ENTITY_RESET_IN_FLAG,
  1270. ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET, 1);
  1271. rc = efx_mcdi_rpc(efx, MC_CMD_ENTITY_RESET, inbuf, sizeof(inbuf),
  1272. NULL, 0, NULL);
  1273. return rc;
  1274. }
  1275. static int efx_mcdi_reset_mc(struct efx_nic *efx)
  1276. {
  1277. MCDI_DECLARE_BUF(inbuf, MC_CMD_REBOOT_IN_LEN);
  1278. int rc;
  1279. BUILD_BUG_ON(MC_CMD_REBOOT_OUT_LEN != 0);
  1280. MCDI_SET_DWORD(inbuf, REBOOT_IN_FLAGS, 0);
  1281. rc = efx_mcdi_rpc(efx, MC_CMD_REBOOT, inbuf, sizeof(inbuf),
  1282. NULL, 0, NULL);
  1283. /* White is black, and up is down */
  1284. if (rc == -EIO)
  1285. return 0;
  1286. if (rc == 0)
  1287. rc = -EIO;
  1288. return rc;
  1289. }
  1290. enum reset_type efx_mcdi_map_reset_reason(enum reset_type reason)
  1291. {
  1292. return RESET_TYPE_RECOVER_OR_ALL;
  1293. }
  1294. int efx_mcdi_reset(struct efx_nic *efx, enum reset_type method)
  1295. {
  1296. int rc;
  1297. /* Recover from a failed assertion pre-reset */
  1298. rc = efx_mcdi_handle_assertion(efx);
  1299. if (rc)
  1300. return rc;
  1301. if (method == RESET_TYPE_WORLD)
  1302. return efx_mcdi_reset_mc(efx);
  1303. else
  1304. return efx_mcdi_reset_func(efx);
  1305. }
  1306. static int efx_mcdi_wol_filter_set(struct efx_nic *efx, u32 type,
  1307. const u8 *mac, int *id_out)
  1308. {
  1309. MCDI_DECLARE_BUF(inbuf, MC_CMD_WOL_FILTER_SET_IN_LEN);
  1310. MCDI_DECLARE_BUF(outbuf, MC_CMD_WOL_FILTER_SET_OUT_LEN);
  1311. size_t outlen;
  1312. int rc;
  1313. MCDI_SET_DWORD(inbuf, WOL_FILTER_SET_IN_WOL_TYPE, type);
  1314. MCDI_SET_DWORD(inbuf, WOL_FILTER_SET_IN_FILTER_MODE,
  1315. MC_CMD_FILTER_MODE_SIMPLE);
  1316. memcpy(MCDI_PTR(inbuf, WOL_FILTER_SET_IN_MAGIC_MAC), mac, ETH_ALEN);
  1317. rc = efx_mcdi_rpc(efx, MC_CMD_WOL_FILTER_SET, inbuf, sizeof(inbuf),
  1318. outbuf, sizeof(outbuf), &outlen);
  1319. if (rc)
  1320. goto fail;
  1321. if (outlen < MC_CMD_WOL_FILTER_SET_OUT_LEN) {
  1322. rc = -EIO;
  1323. goto fail;
  1324. }
  1325. *id_out = (int)MCDI_DWORD(outbuf, WOL_FILTER_SET_OUT_FILTER_ID);
  1326. return 0;
  1327. fail:
  1328. *id_out = -1;
  1329. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  1330. return rc;
  1331. }
  1332. int
  1333. efx_mcdi_wol_filter_set_magic(struct efx_nic *efx, const u8 *mac, int *id_out)
  1334. {
  1335. return efx_mcdi_wol_filter_set(efx, MC_CMD_WOL_TYPE_MAGIC, mac, id_out);
  1336. }
  1337. int efx_mcdi_wol_filter_get_magic(struct efx_nic *efx, int *id_out)
  1338. {
  1339. MCDI_DECLARE_BUF(outbuf, MC_CMD_WOL_FILTER_GET_OUT_LEN);
  1340. size_t outlen;
  1341. int rc;
  1342. rc = efx_mcdi_rpc(efx, MC_CMD_WOL_FILTER_GET, NULL, 0,
  1343. outbuf, sizeof(outbuf), &outlen);
  1344. if (rc)
  1345. goto fail;
  1346. if (outlen < MC_CMD_WOL_FILTER_GET_OUT_LEN) {
  1347. rc = -EIO;
  1348. goto fail;
  1349. }
  1350. *id_out = (int)MCDI_DWORD(outbuf, WOL_FILTER_GET_OUT_FILTER_ID);
  1351. return 0;
  1352. fail:
  1353. *id_out = -1;
  1354. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  1355. return rc;
  1356. }
  1357. int efx_mcdi_wol_filter_remove(struct efx_nic *efx, int id)
  1358. {
  1359. MCDI_DECLARE_BUF(inbuf, MC_CMD_WOL_FILTER_REMOVE_IN_LEN);
  1360. int rc;
  1361. MCDI_SET_DWORD(inbuf, WOL_FILTER_REMOVE_IN_FILTER_ID, (u32)id);
  1362. rc = efx_mcdi_rpc(efx, MC_CMD_WOL_FILTER_REMOVE, inbuf, sizeof(inbuf),
  1363. NULL, 0, NULL);
  1364. return rc;
  1365. }
  1366. int efx_mcdi_flush_rxqs(struct efx_nic *efx)
  1367. {
  1368. struct efx_channel *channel;
  1369. struct efx_rx_queue *rx_queue;
  1370. MCDI_DECLARE_BUF(inbuf,
  1371. MC_CMD_FLUSH_RX_QUEUES_IN_LEN(EFX_MAX_CHANNELS));
  1372. int rc, count;
  1373. BUILD_BUG_ON(EFX_MAX_CHANNELS >
  1374. MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MAXNUM);
  1375. count = 0;
  1376. efx_for_each_channel(channel, efx) {
  1377. efx_for_each_channel_rx_queue(rx_queue, channel) {
  1378. if (rx_queue->flush_pending) {
  1379. rx_queue->flush_pending = false;
  1380. atomic_dec(&efx->rxq_flush_pending);
  1381. MCDI_SET_ARRAY_DWORD(
  1382. inbuf, FLUSH_RX_QUEUES_IN_QID_OFST,
  1383. count, efx_rx_queue_index(rx_queue));
  1384. count++;
  1385. }
  1386. }
  1387. }
  1388. rc = efx_mcdi_rpc(efx, MC_CMD_FLUSH_RX_QUEUES, inbuf,
  1389. MC_CMD_FLUSH_RX_QUEUES_IN_LEN(count), NULL, 0, NULL);
  1390. WARN_ON(rc < 0);
  1391. return rc;
  1392. }
  1393. int efx_mcdi_wol_filter_reset(struct efx_nic *efx)
  1394. {
  1395. int rc;
  1396. rc = efx_mcdi_rpc(efx, MC_CMD_WOL_FILTER_RESET, NULL, 0, NULL, 0, NULL);
  1397. return rc;
  1398. }
  1399. int efx_mcdi_set_workaround(struct efx_nic *efx, u32 type, bool enabled)
  1400. {
  1401. MCDI_DECLARE_BUF(inbuf, MC_CMD_WORKAROUND_IN_LEN);
  1402. BUILD_BUG_ON(MC_CMD_WORKAROUND_OUT_LEN != 0);
  1403. MCDI_SET_DWORD(inbuf, WORKAROUND_IN_TYPE, type);
  1404. MCDI_SET_DWORD(inbuf, WORKAROUND_IN_ENABLED, enabled);
  1405. return efx_mcdi_rpc(efx, MC_CMD_WORKAROUND, inbuf, sizeof(inbuf),
  1406. NULL, 0, NULL);
  1407. }
  1408. #ifdef CONFIG_SFC_MTD
  1409. #define EFX_MCDI_NVRAM_LEN_MAX 128
  1410. static int efx_mcdi_nvram_update_start(struct efx_nic *efx, unsigned int type)
  1411. {
  1412. MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_UPDATE_START_IN_LEN);
  1413. int rc;
  1414. MCDI_SET_DWORD(inbuf, NVRAM_UPDATE_START_IN_TYPE, type);
  1415. BUILD_BUG_ON(MC_CMD_NVRAM_UPDATE_START_OUT_LEN != 0);
  1416. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_UPDATE_START, inbuf, sizeof(inbuf),
  1417. NULL, 0, NULL);
  1418. return rc;
  1419. }
  1420. static int efx_mcdi_nvram_read(struct efx_nic *efx, unsigned int type,
  1421. loff_t offset, u8 *buffer, size_t length)
  1422. {
  1423. MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_READ_IN_LEN);
  1424. MCDI_DECLARE_BUF(outbuf,
  1425. MC_CMD_NVRAM_READ_OUT_LEN(EFX_MCDI_NVRAM_LEN_MAX));
  1426. size_t outlen;
  1427. int rc;
  1428. MCDI_SET_DWORD(inbuf, NVRAM_READ_IN_TYPE, type);
  1429. MCDI_SET_DWORD(inbuf, NVRAM_READ_IN_OFFSET, offset);
  1430. MCDI_SET_DWORD(inbuf, NVRAM_READ_IN_LENGTH, length);
  1431. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_READ, inbuf, sizeof(inbuf),
  1432. outbuf, sizeof(outbuf), &outlen);
  1433. if (rc)
  1434. return rc;
  1435. memcpy(buffer, MCDI_PTR(outbuf, NVRAM_READ_OUT_READ_BUFFER), length);
  1436. return 0;
  1437. }
  1438. static int efx_mcdi_nvram_write(struct efx_nic *efx, unsigned int type,
  1439. loff_t offset, const u8 *buffer, size_t length)
  1440. {
  1441. MCDI_DECLARE_BUF(inbuf,
  1442. MC_CMD_NVRAM_WRITE_IN_LEN(EFX_MCDI_NVRAM_LEN_MAX));
  1443. int rc;
  1444. MCDI_SET_DWORD(inbuf, NVRAM_WRITE_IN_TYPE, type);
  1445. MCDI_SET_DWORD(inbuf, NVRAM_WRITE_IN_OFFSET, offset);
  1446. MCDI_SET_DWORD(inbuf, NVRAM_WRITE_IN_LENGTH, length);
  1447. memcpy(MCDI_PTR(inbuf, NVRAM_WRITE_IN_WRITE_BUFFER), buffer, length);
  1448. BUILD_BUG_ON(MC_CMD_NVRAM_WRITE_OUT_LEN != 0);
  1449. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_WRITE, inbuf,
  1450. ALIGN(MC_CMD_NVRAM_WRITE_IN_LEN(length), 4),
  1451. NULL, 0, NULL);
  1452. return rc;
  1453. }
  1454. static int efx_mcdi_nvram_erase(struct efx_nic *efx, unsigned int type,
  1455. loff_t offset, size_t length)
  1456. {
  1457. MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_ERASE_IN_LEN);
  1458. int rc;
  1459. MCDI_SET_DWORD(inbuf, NVRAM_ERASE_IN_TYPE, type);
  1460. MCDI_SET_DWORD(inbuf, NVRAM_ERASE_IN_OFFSET, offset);
  1461. MCDI_SET_DWORD(inbuf, NVRAM_ERASE_IN_LENGTH, length);
  1462. BUILD_BUG_ON(MC_CMD_NVRAM_ERASE_OUT_LEN != 0);
  1463. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_ERASE, inbuf, sizeof(inbuf),
  1464. NULL, 0, NULL);
  1465. return rc;
  1466. }
  1467. static int efx_mcdi_nvram_update_finish(struct efx_nic *efx, unsigned int type)
  1468. {
  1469. MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_UPDATE_FINISH_IN_LEN);
  1470. int rc;
  1471. MCDI_SET_DWORD(inbuf, NVRAM_UPDATE_FINISH_IN_TYPE, type);
  1472. BUILD_BUG_ON(MC_CMD_NVRAM_UPDATE_FINISH_OUT_LEN != 0);
  1473. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_UPDATE_FINISH, inbuf, sizeof(inbuf),
  1474. NULL, 0, NULL);
  1475. return rc;
  1476. }
  1477. int efx_mcdi_mtd_read(struct mtd_info *mtd, loff_t start,
  1478. size_t len, size_t *retlen, u8 *buffer)
  1479. {
  1480. struct efx_mcdi_mtd_partition *part = to_efx_mcdi_mtd_partition(mtd);
  1481. struct efx_nic *efx = mtd->priv;
  1482. loff_t offset = start;
  1483. loff_t end = min_t(loff_t, start + len, mtd->size);
  1484. size_t chunk;
  1485. int rc = 0;
  1486. while (offset < end) {
  1487. chunk = min_t(size_t, end - offset, EFX_MCDI_NVRAM_LEN_MAX);
  1488. rc = efx_mcdi_nvram_read(efx, part->nvram_type, offset,
  1489. buffer, chunk);
  1490. if (rc)
  1491. goto out;
  1492. offset += chunk;
  1493. buffer += chunk;
  1494. }
  1495. out:
  1496. *retlen = offset - start;
  1497. return rc;
  1498. }
  1499. int efx_mcdi_mtd_erase(struct mtd_info *mtd, loff_t start, size_t len)
  1500. {
  1501. struct efx_mcdi_mtd_partition *part = to_efx_mcdi_mtd_partition(mtd);
  1502. struct efx_nic *efx = mtd->priv;
  1503. loff_t offset = start & ~((loff_t)(mtd->erasesize - 1));
  1504. loff_t end = min_t(loff_t, start + len, mtd->size);
  1505. size_t chunk = part->common.mtd.erasesize;
  1506. int rc = 0;
  1507. if (!part->updating) {
  1508. rc = efx_mcdi_nvram_update_start(efx, part->nvram_type);
  1509. if (rc)
  1510. goto out;
  1511. part->updating = true;
  1512. }
  1513. /* The MCDI interface can in fact do multiple erase blocks at once;
  1514. * but erasing may be slow, so we make multiple calls here to avoid
  1515. * tripping the MCDI RPC timeout. */
  1516. while (offset < end) {
  1517. rc = efx_mcdi_nvram_erase(efx, part->nvram_type, offset,
  1518. chunk);
  1519. if (rc)
  1520. goto out;
  1521. offset += chunk;
  1522. }
  1523. out:
  1524. return rc;
  1525. }
  1526. int efx_mcdi_mtd_write(struct mtd_info *mtd, loff_t start,
  1527. size_t len, size_t *retlen, const u8 *buffer)
  1528. {
  1529. struct efx_mcdi_mtd_partition *part = to_efx_mcdi_mtd_partition(mtd);
  1530. struct efx_nic *efx = mtd->priv;
  1531. loff_t offset = start;
  1532. loff_t end = min_t(loff_t, start + len, mtd->size);
  1533. size_t chunk;
  1534. int rc = 0;
  1535. if (!part->updating) {
  1536. rc = efx_mcdi_nvram_update_start(efx, part->nvram_type);
  1537. if (rc)
  1538. goto out;
  1539. part->updating = true;
  1540. }
  1541. while (offset < end) {
  1542. chunk = min_t(size_t, end - offset, EFX_MCDI_NVRAM_LEN_MAX);
  1543. rc = efx_mcdi_nvram_write(efx, part->nvram_type, offset,
  1544. buffer, chunk);
  1545. if (rc)
  1546. goto out;
  1547. offset += chunk;
  1548. buffer += chunk;
  1549. }
  1550. out:
  1551. *retlen = offset - start;
  1552. return rc;
  1553. }
  1554. int efx_mcdi_mtd_sync(struct mtd_info *mtd)
  1555. {
  1556. struct efx_mcdi_mtd_partition *part = to_efx_mcdi_mtd_partition(mtd);
  1557. struct efx_nic *efx = mtd->priv;
  1558. int rc = 0;
  1559. if (part->updating) {
  1560. part->updating = false;
  1561. rc = efx_mcdi_nvram_update_finish(efx, part->nvram_type);
  1562. }
  1563. return rc;
  1564. }
  1565. void efx_mcdi_mtd_rename(struct efx_mtd_partition *part)
  1566. {
  1567. struct efx_mcdi_mtd_partition *mcdi_part =
  1568. container_of(part, struct efx_mcdi_mtd_partition, common);
  1569. struct efx_nic *efx = part->mtd.priv;
  1570. snprintf(part->name, sizeof(part->name), "%s %s:%02x",
  1571. efx->name, part->type_name, mcdi_part->fw_subtype);
  1572. }
  1573. #endif /* CONFIG_SFC_MTD */