intel-mid-touch.c 15 KB

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  1. /*
  2. * Intel MID Resistive Touch Screen Driver
  3. *
  4. * Copyright (C) 2008 Intel Corp
  5. *
  6. * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; version 2 of the License.
  11. *
  12. * This program is distributed in the hope that it will be useful, but
  13. * WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  15. * General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along
  18. * with this program; if not, write to the Free Software Foundation, Inc.,
  19. * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  20. *
  21. * Questions/Comments/Bug fixes to Sreedhara (sreedhara.ds@intel.com)
  22. * Ramesh Agarwal (ramesh.agarwal@intel.com)
  23. * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  24. *
  25. * TODO:
  26. * review conversion of r/m/w sequences
  27. */
  28. #include <linux/module.h>
  29. #include <linux/input.h>
  30. #include <linux/interrupt.h>
  31. #include <linux/err.h>
  32. #include <linux/param.h>
  33. #include <linux/slab.h>
  34. #include <linux/platform_device.h>
  35. #include <linux/irq.h>
  36. #include <linux/delay.h>
  37. #include <asm/intel_scu_ipc.h>
  38. /* PMIC Interrupt registers */
  39. #define PMIC_REG_ID1 0x00 /* PMIC ID1 register */
  40. /* PMIC Interrupt registers */
  41. #define PMIC_REG_INT 0x04 /* PMIC interrupt register */
  42. #define PMIC_REG_MINT 0x05 /* PMIC interrupt mask register */
  43. /* ADC Interrupt registers */
  44. #define PMIC_REG_ADCINT 0x5F /* ADC interrupt register */
  45. #define PMIC_REG_MADCINT 0x60 /* ADC interrupt mask register */
  46. /* ADC Control registers */
  47. #define PMIC_REG_ADCCNTL1 0x61 /* ADC control register */
  48. /* ADC Channel Selection registers */
  49. #define PMICADDR0 0xA4
  50. #define END_OF_CHANNEL 0x1F
  51. /* ADC Result register */
  52. #define PMIC_REG_ADCSNS0H 0x64
  53. /* ADC channels for touch screen */
  54. #define MRST_TS_CHAN10 0xA /* Touch screen X+ connection */
  55. #define MRST_TS_CHAN11 0xB /* Touch screen X- connection */
  56. #define MRST_TS_CHAN12 0xC /* Touch screen Y+ connection */
  57. #define MRST_TS_CHAN13 0xD /* Touch screen Y- connection */
  58. /* Touch screen channel BIAS constants */
  59. #define MRST_XBIAS 0x20
  60. #define MRST_YBIAS 0x40
  61. #define MRST_ZBIAS 0x80
  62. /* Touch screen coordinates */
  63. #define MRST_X_MIN 10
  64. #define MRST_X_MAX 1024
  65. #define MRST_X_FUZZ 5
  66. #define MRST_Y_MIN 10
  67. #define MRST_Y_MAX 1024
  68. #define MRST_Y_FUZZ 5
  69. #define MRST_PRESSURE_MIN 0
  70. #define MRST_PRESSURE_NOMINAL 50
  71. #define MRST_PRESSURE_MAX 100
  72. #define WAIT_ADC_COMPLETION 10 /* msec */
  73. /* PMIC ADC round robin delays */
  74. #define ADC_LOOP_DELAY0 0x0 /* Continuous loop */
  75. #define ADC_LOOP_DELAY1 0x1 /* 4.5 ms approximate */
  76. /* PMIC Vendor Identifiers */
  77. #define PMIC_VENDOR_FS 0 /* PMIC vendor FreeScale */
  78. #define PMIC_VENDOR_MAXIM 1 /* PMIC vendor MAXIM */
  79. #define PMIC_VENDOR_NEC 2 /* PMIC vendor NEC */
  80. #define MRSTOUCH_MAX_CHANNELS 32 /* Maximum ADC channels */
  81. /* Touch screen device structure */
  82. struct mrstouch_dev {
  83. struct device *dev; /* device associated with touch screen */
  84. struct input_dev *input;
  85. char phys[32];
  86. u16 asr; /* Address selection register */
  87. int irq;
  88. unsigned int vendor; /* PMIC vendor */
  89. unsigned int rev; /* PMIC revision */
  90. int (*read_prepare)(struct mrstouch_dev *tsdev);
  91. int (*read)(struct mrstouch_dev *tsdev, u16 *x, u16 *y, u16 *z);
  92. int (*read_finish)(struct mrstouch_dev *tsdev);
  93. };
  94. /*************************** NEC and Maxim Interface ************************/
  95. static int mrstouch_nec_adc_read_prepare(struct mrstouch_dev *tsdev)
  96. {
  97. return intel_scu_ipc_update_register(PMIC_REG_MADCINT, 0, 0x20);
  98. }
  99. /*
  100. * Enables PENDET interrupt.
  101. */
  102. static int mrstouch_nec_adc_read_finish(struct mrstouch_dev *tsdev)
  103. {
  104. int err;
  105. err = intel_scu_ipc_update_register(PMIC_REG_MADCINT, 0x20, 0x20);
  106. if (!err)
  107. err = intel_scu_ipc_update_register(PMIC_REG_ADCCNTL1, 0, 0x05);
  108. return err;
  109. }
  110. /*
  111. * Reads PMIC ADC touch screen result
  112. * Reads ADC storage registers for higher 7 and lower 3 bits and
  113. * converts the two readings into a single value and turns off gain bit
  114. */
  115. static int mrstouch_ts_chan_read(u16 offset, u16 chan, u16 *vp, u16 *vm)
  116. {
  117. int err;
  118. u16 result;
  119. u32 res;
  120. result = PMIC_REG_ADCSNS0H + offset;
  121. if (chan == MRST_TS_CHAN12)
  122. result += 4;
  123. err = intel_scu_ipc_ioread32(result, &res);
  124. if (err)
  125. return err;
  126. /* Mash the bits up */
  127. *vp = (res & 0xFF) << 3; /* Highest 7 bits */
  128. *vp |= (res >> 8) & 0x07; /* Lower 3 bits */
  129. *vp &= 0x3FF;
  130. res >>= 16;
  131. *vm = (res & 0xFF) << 3; /* Highest 7 bits */
  132. *vm |= (res >> 8) & 0x07; /* Lower 3 bits */
  133. *vm &= 0x3FF;
  134. return 0;
  135. }
  136. /*
  137. * Enables X, Y and Z bias values
  138. * Enables YPYM for X channels and XPXM for Y channels
  139. */
  140. static int mrstouch_ts_bias_set(uint offset, uint bias)
  141. {
  142. int count;
  143. u16 chan, start;
  144. u16 reg[4];
  145. u8 data[4];
  146. chan = PMICADDR0 + offset;
  147. start = MRST_TS_CHAN10;
  148. for (count = 0; count <= 3; count++) {
  149. reg[count] = chan++;
  150. data[count] = bias | (start + count);
  151. }
  152. return intel_scu_ipc_writev(reg, data, 4);
  153. }
  154. /* To read touch screen channel values */
  155. static int mrstouch_nec_adc_read(struct mrstouch_dev *tsdev,
  156. u16 *x, u16 *y, u16 *z)
  157. {
  158. int err;
  159. u16 xm, ym, zm;
  160. /* configure Y bias for X channels */
  161. err = mrstouch_ts_bias_set(tsdev->asr, MRST_YBIAS);
  162. if (err)
  163. goto ipc_error;
  164. msleep(WAIT_ADC_COMPLETION);
  165. /* read x+ and x- channels */
  166. err = mrstouch_ts_chan_read(tsdev->asr, MRST_TS_CHAN10, x, &xm);
  167. if (err)
  168. goto ipc_error;
  169. /* configure x bias for y channels */
  170. err = mrstouch_ts_bias_set(tsdev->asr, MRST_XBIAS);
  171. if (err)
  172. goto ipc_error;
  173. msleep(WAIT_ADC_COMPLETION);
  174. /* read y+ and y- channels */
  175. err = mrstouch_ts_chan_read(tsdev->asr, MRST_TS_CHAN12, y, &ym);
  176. if (err)
  177. goto ipc_error;
  178. /* configure z bias for x and y channels */
  179. err = mrstouch_ts_bias_set(tsdev->asr, MRST_ZBIAS);
  180. if (err)
  181. goto ipc_error;
  182. msleep(WAIT_ADC_COMPLETION);
  183. /* read z+ and z- channels */
  184. err = mrstouch_ts_chan_read(tsdev->asr, MRST_TS_CHAN10, z, &zm);
  185. if (err)
  186. goto ipc_error;
  187. return 0;
  188. ipc_error:
  189. dev_err(tsdev->dev, "ipc error during adc read\n");
  190. return err;
  191. }
  192. /*************************** Freescale Interface ************************/
  193. static int mrstouch_fs_adc_read_prepare(struct mrstouch_dev *tsdev)
  194. {
  195. int err, count;
  196. u16 chan;
  197. u16 reg[5];
  198. u8 data[5];
  199. /* Stop the ADC */
  200. err = intel_scu_ipc_update_register(PMIC_REG_MADCINT, 0x00, 0x02);
  201. if (err)
  202. goto ipc_error;
  203. chan = PMICADDR0 + tsdev->asr;
  204. /* Set X BIAS */
  205. for (count = 0; count <= 3; count++) {
  206. reg[count] = chan++;
  207. data[count] = 0x2A;
  208. }
  209. reg[count] = chan++; /* Dummy */
  210. data[count] = 0;
  211. err = intel_scu_ipc_writev(reg, data, 5);
  212. if (err)
  213. goto ipc_error;
  214. msleep(WAIT_ADC_COMPLETION);
  215. /* Set Y BIAS */
  216. for (count = 0; count <= 3; count++) {
  217. reg[count] = chan++;
  218. data[count] = 0x4A;
  219. }
  220. reg[count] = chan++; /* Dummy */
  221. data[count] = 0;
  222. err = intel_scu_ipc_writev(reg, data, 5);
  223. if (err)
  224. goto ipc_error;
  225. msleep(WAIT_ADC_COMPLETION);
  226. /* Set Z BIAS */
  227. err = intel_scu_ipc_iowrite32(chan + 2, 0x8A8A8A8A);
  228. if (err)
  229. goto ipc_error;
  230. msleep(WAIT_ADC_COMPLETION);
  231. return 0;
  232. ipc_error:
  233. dev_err(tsdev->dev, "ipc error during %s\n", __func__);
  234. return err;
  235. }
  236. static int mrstouch_fs_adc_read(struct mrstouch_dev *tsdev,
  237. u16 *x, u16 *y, u16 *z)
  238. {
  239. int err;
  240. u16 result;
  241. u16 reg[4];
  242. u8 data[4];
  243. result = PMIC_REG_ADCSNS0H + tsdev->asr;
  244. reg[0] = result + 4;
  245. reg[1] = result + 5;
  246. reg[2] = result + 16;
  247. reg[3] = result + 17;
  248. err = intel_scu_ipc_readv(reg, data, 4);
  249. if (err)
  250. goto ipc_error;
  251. *x = data[0] << 3; /* Higher 7 bits */
  252. *x |= data[1] & 0x7; /* Lower 3 bits */
  253. *x &= 0x3FF;
  254. *y = data[2] << 3; /* Higher 7 bits */
  255. *y |= data[3] & 0x7; /* Lower 3 bits */
  256. *y &= 0x3FF;
  257. /* Read Z value */
  258. reg[0] = result + 28;
  259. reg[1] = result + 29;
  260. err = intel_scu_ipc_readv(reg, data, 4);
  261. if (err)
  262. goto ipc_error;
  263. *z = data[0] << 3; /* Higher 7 bits */
  264. *z |= data[1] & 0x7; /* Lower 3 bits */
  265. *z &= 0x3FF;
  266. return 0;
  267. ipc_error:
  268. dev_err(tsdev->dev, "ipc error during %s\n", __func__);
  269. return err;
  270. }
  271. static int mrstouch_fs_adc_read_finish(struct mrstouch_dev *tsdev)
  272. {
  273. int err, count;
  274. u16 chan;
  275. u16 reg[5];
  276. u8 data[5];
  277. /* Clear all TS channels */
  278. chan = PMICADDR0 + tsdev->asr;
  279. for (count = 0; count <= 4; count++) {
  280. reg[count] = chan++;
  281. data[count] = 0;
  282. }
  283. err = intel_scu_ipc_writev(reg, data, 5);
  284. if (err)
  285. goto ipc_error;
  286. for (count = 0; count <= 4; count++) {
  287. reg[count] = chan++;
  288. data[count] = 0;
  289. }
  290. err = intel_scu_ipc_writev(reg, data, 5);
  291. if (err)
  292. goto ipc_error;
  293. err = intel_scu_ipc_iowrite32(chan + 2, 0x00000000);
  294. if (err)
  295. goto ipc_error;
  296. /* Start ADC */
  297. err = intel_scu_ipc_update_register(PMIC_REG_MADCINT, 0x02, 0x02);
  298. if (err)
  299. goto ipc_error;
  300. return 0;
  301. ipc_error:
  302. dev_err(tsdev->dev, "ipc error during %s\n", __func__);
  303. return err;
  304. }
  305. static void mrstouch_report_event(struct input_dev *input,
  306. unsigned int x, unsigned int y, unsigned int z)
  307. {
  308. if (z > MRST_PRESSURE_NOMINAL) {
  309. /* Pen touched, report button touch and coordinates */
  310. input_report_key(input, BTN_TOUCH, 1);
  311. input_report_abs(input, ABS_X, x);
  312. input_report_abs(input, ABS_Y, y);
  313. } else {
  314. input_report_key(input, BTN_TOUCH, 0);
  315. }
  316. input_report_abs(input, ABS_PRESSURE, z);
  317. input_sync(input);
  318. }
  319. /* PENDET interrupt handler */
  320. static irqreturn_t mrstouch_pendet_irq(int irq, void *dev_id)
  321. {
  322. struct mrstouch_dev *tsdev = dev_id;
  323. u16 x, y, z;
  324. /*
  325. * Should we lower thread priority? Probably not, since we are
  326. * not spinning but sleeping...
  327. */
  328. if (tsdev->read_prepare(tsdev))
  329. goto out;
  330. do {
  331. if (tsdev->read(tsdev, &x, &y, &z))
  332. break;
  333. mrstouch_report_event(tsdev->input, x, y, z);
  334. } while (z > MRST_PRESSURE_NOMINAL);
  335. tsdev->read_finish(tsdev);
  336. out:
  337. return IRQ_HANDLED;
  338. }
  339. /* Utility to read PMIC ID */
  340. static int mrstouch_read_pmic_id(uint *vendor, uint *rev)
  341. {
  342. int err;
  343. u8 r;
  344. err = intel_scu_ipc_ioread8(PMIC_REG_ID1, &r);
  345. if (err)
  346. return err;
  347. *vendor = r & 0x7;
  348. *rev = (r >> 3) & 0x7;
  349. return 0;
  350. }
  351. /*
  352. * Parse ADC channels to find end of the channel configured by other ADC user
  353. * NEC and MAXIM requires 4 channels and FreeScale needs 18 channels
  354. */
  355. static int mrstouch_chan_parse(struct mrstouch_dev *tsdev)
  356. {
  357. int found = 0;
  358. int err, i;
  359. u8 r8;
  360. for (i = 0; i < MRSTOUCH_MAX_CHANNELS; i++) {
  361. err = intel_scu_ipc_ioread8(PMICADDR0 + i, &r8);
  362. if (err)
  363. return err;
  364. if (r8 == END_OF_CHANNEL) {
  365. found = i;
  366. break;
  367. }
  368. }
  369. if (tsdev->vendor == PMIC_VENDOR_FS) {
  370. if (found > MRSTOUCH_MAX_CHANNELS - 18)
  371. return -ENOSPC;
  372. } else {
  373. if (found > MRSTOUCH_MAX_CHANNELS - 4)
  374. return -ENOSPC;
  375. }
  376. return found;
  377. }
  378. /*
  379. * Writes touch screen channels to ADC address selection registers
  380. */
  381. static int mrstouch_ts_chan_set(uint offset)
  382. {
  383. u16 chan;
  384. int ret, count;
  385. chan = PMICADDR0 + offset;
  386. for (count = 0; count <= 3; count++) {
  387. ret = intel_scu_ipc_iowrite8(chan++, MRST_TS_CHAN10 + count);
  388. if (ret)
  389. return ret;
  390. }
  391. return intel_scu_ipc_iowrite8(chan++, END_OF_CHANNEL);
  392. }
  393. /* Initialize ADC */
  394. static int mrstouch_adc_init(struct mrstouch_dev *tsdev)
  395. {
  396. int err, start;
  397. u8 ra, rm;
  398. err = mrstouch_read_pmic_id(&tsdev->vendor, &tsdev->rev);
  399. if (err) {
  400. dev_err(tsdev->dev, "Unable to read PMIC id\n");
  401. return err;
  402. }
  403. switch (tsdev->vendor) {
  404. case PMIC_VENDOR_NEC:
  405. case PMIC_VENDOR_MAXIM:
  406. tsdev->read_prepare = mrstouch_nec_adc_read_prepare;
  407. tsdev->read = mrstouch_nec_adc_read;
  408. tsdev->read_finish = mrstouch_nec_adc_read_finish;
  409. break;
  410. case PMIC_VENDOR_FS:
  411. tsdev->read_prepare = mrstouch_fs_adc_read_prepare;
  412. tsdev->read = mrstouch_fs_adc_read;
  413. tsdev->read_finish = mrstouch_fs_adc_read_finish;
  414. break;
  415. default:
  416. dev_err(tsdev->dev,
  417. "Unsupported touchscreen: %d\n", tsdev->vendor);
  418. return -ENXIO;
  419. }
  420. start = mrstouch_chan_parse(tsdev);
  421. if (start < 0) {
  422. dev_err(tsdev->dev, "Unable to parse channels\n");
  423. return start;
  424. }
  425. tsdev->asr = start;
  426. /*
  427. * ADC power on, start, enable PENDET and set loop delay
  428. * ADC loop delay is set to 4.5 ms approximately
  429. * Loop delay more than this results in jitter in adc readings
  430. * Setting loop delay to 0 (continuous loop) in MAXIM stops PENDET
  431. * interrupt generation sometimes.
  432. */
  433. if (tsdev->vendor == PMIC_VENDOR_FS) {
  434. ra = 0xE0 | ADC_LOOP_DELAY0;
  435. rm = 0x5;
  436. } else {
  437. /* NEC and MAXIm not consistent with loop delay 0 */
  438. ra = 0xE0 | ADC_LOOP_DELAY1;
  439. rm = 0x0;
  440. /* configure touch screen channels */
  441. err = mrstouch_ts_chan_set(tsdev->asr);
  442. if (err)
  443. return err;
  444. }
  445. err = intel_scu_ipc_update_register(PMIC_REG_ADCCNTL1, ra, 0xE7);
  446. if (err)
  447. return err;
  448. err = intel_scu_ipc_update_register(PMIC_REG_MADCINT, rm, 0x03);
  449. if (err)
  450. return err;
  451. return 0;
  452. }
  453. /* Probe function for touch screen driver */
  454. static int mrstouch_probe(struct platform_device *pdev)
  455. {
  456. struct mrstouch_dev *tsdev;
  457. struct input_dev *input;
  458. int err;
  459. int irq;
  460. irq = platform_get_irq(pdev, 0);
  461. if (irq < 0) {
  462. dev_err(&pdev->dev, "no interrupt assigned\n");
  463. return -EINVAL;
  464. }
  465. tsdev = kzalloc(sizeof(struct mrstouch_dev), GFP_KERNEL);
  466. input = input_allocate_device();
  467. if (!tsdev || !input) {
  468. dev_err(&pdev->dev, "unable to allocate memory\n");
  469. err = -ENOMEM;
  470. goto err_free_mem;
  471. }
  472. tsdev->dev = &pdev->dev;
  473. tsdev->input = input;
  474. tsdev->irq = irq;
  475. snprintf(tsdev->phys, sizeof(tsdev->phys),
  476. "%s/input0", dev_name(tsdev->dev));
  477. err = mrstouch_adc_init(tsdev);
  478. if (err) {
  479. dev_err(&pdev->dev, "ADC initialization failed\n");
  480. goto err_free_mem;
  481. }
  482. input->name = "mrst_touchscreen";
  483. input->phys = tsdev->phys;
  484. input->dev.parent = tsdev->dev;
  485. input->id.vendor = tsdev->vendor;
  486. input->id.version = tsdev->rev;
  487. input->evbit[0] = BIT_MASK(EV_KEY) | BIT_MASK(EV_ABS);
  488. input->keybit[BIT_WORD(BTN_TOUCH)] = BIT_MASK(BTN_TOUCH);
  489. input_set_abs_params(tsdev->input, ABS_X,
  490. MRST_X_MIN, MRST_X_MAX, MRST_X_FUZZ, 0);
  491. input_set_abs_params(tsdev->input, ABS_Y,
  492. MRST_Y_MIN, MRST_Y_MAX, MRST_Y_FUZZ, 0);
  493. input_set_abs_params(tsdev->input, ABS_PRESSURE,
  494. MRST_PRESSURE_MIN, MRST_PRESSURE_MAX, 0, 0);
  495. err = request_threaded_irq(tsdev->irq, NULL, mrstouch_pendet_irq,
  496. IRQF_ONESHOT, "mrstouch", tsdev);
  497. if (err) {
  498. dev_err(tsdev->dev, "unable to allocate irq\n");
  499. goto err_free_mem;
  500. }
  501. err = input_register_device(tsdev->input);
  502. if (err) {
  503. dev_err(tsdev->dev, "unable to register input device\n");
  504. goto err_free_irq;
  505. }
  506. platform_set_drvdata(pdev, tsdev);
  507. return 0;
  508. err_free_irq:
  509. free_irq(tsdev->irq, tsdev);
  510. err_free_mem:
  511. input_free_device(input);
  512. kfree(tsdev);
  513. return err;
  514. }
  515. static int mrstouch_remove(struct platform_device *pdev)
  516. {
  517. struct mrstouch_dev *tsdev = platform_get_drvdata(pdev);
  518. free_irq(tsdev->irq, tsdev);
  519. input_unregister_device(tsdev->input);
  520. kfree(tsdev);
  521. return 0;
  522. }
  523. static struct platform_driver mrstouch_driver = {
  524. .driver = {
  525. .name = "pmic_touch",
  526. .owner = THIS_MODULE,
  527. },
  528. .probe = mrstouch_probe,
  529. .remove = mrstouch_remove,
  530. };
  531. module_platform_driver(mrstouch_driver);
  532. MODULE_AUTHOR("Sreedhara Murthy. D.S, sreedhara.ds@intel.com");
  533. MODULE_DESCRIPTION("Intel Moorestown Resistive Touch Screen Driver");
  534. MODULE_LICENSE("GPL");