mr.c 24 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079
  1. /*
  2. * Copyright (c) 2013, Mellanox Technologies inc. All rights reserved.
  3. *
  4. * This software is available to you under a choice of one of two
  5. * licenses. You may choose to be licensed under the terms of the GNU
  6. * General Public License (GPL) Version 2, available from the file
  7. * COPYING in the main directory of this source tree, or the
  8. * OpenIB.org BSD license below:
  9. *
  10. * Redistribution and use in source and binary forms, with or
  11. * without modification, are permitted provided that the following
  12. * conditions are met:
  13. *
  14. * - Redistributions of source code must retain the above
  15. * copyright notice, this list of conditions and the following
  16. * disclaimer.
  17. *
  18. * - Redistributions in binary form must reproduce the above
  19. * copyright notice, this list of conditions and the following
  20. * disclaimer in the documentation and/or other materials
  21. * provided with the distribution.
  22. *
  23. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30. * SOFTWARE.
  31. */
  32. #include <linux/kref.h>
  33. #include <linux/random.h>
  34. #include <linux/debugfs.h>
  35. #include <linux/export.h>
  36. #include <linux/delay.h>
  37. #include <rdma/ib_umem.h>
  38. #include "mlx5_ib.h"
  39. enum {
  40. MAX_PENDING_REG_MR = 8,
  41. };
  42. enum {
  43. MLX5_UMR_ALIGN = 2048
  44. };
  45. static __be64 *mr_align(__be64 *ptr, int align)
  46. {
  47. unsigned long mask = align - 1;
  48. return (__be64 *)(((unsigned long)ptr + mask) & ~mask);
  49. }
  50. static int order2idx(struct mlx5_ib_dev *dev, int order)
  51. {
  52. struct mlx5_mr_cache *cache = &dev->cache;
  53. if (order < cache->ent[0].order)
  54. return 0;
  55. else
  56. return order - cache->ent[0].order;
  57. }
  58. static void reg_mr_callback(int status, void *context)
  59. {
  60. struct mlx5_ib_mr *mr = context;
  61. struct mlx5_ib_dev *dev = mr->dev;
  62. struct mlx5_mr_cache *cache = &dev->cache;
  63. int c = order2idx(dev, mr->order);
  64. struct mlx5_cache_ent *ent = &cache->ent[c];
  65. u8 key;
  66. unsigned long flags;
  67. spin_lock_irqsave(&ent->lock, flags);
  68. ent->pending--;
  69. spin_unlock_irqrestore(&ent->lock, flags);
  70. if (status) {
  71. mlx5_ib_warn(dev, "async reg mr failed. status %d\n", status);
  72. kfree(mr);
  73. dev->fill_delay = 1;
  74. mod_timer(&dev->delay_timer, jiffies + HZ);
  75. return;
  76. }
  77. if (mr->out.hdr.status) {
  78. mlx5_ib_warn(dev, "failed - status %d, syndorme 0x%x\n",
  79. mr->out.hdr.status,
  80. be32_to_cpu(mr->out.hdr.syndrome));
  81. kfree(mr);
  82. dev->fill_delay = 1;
  83. mod_timer(&dev->delay_timer, jiffies + HZ);
  84. return;
  85. }
  86. spin_lock_irqsave(&dev->mdev.priv.mkey_lock, flags);
  87. key = dev->mdev.priv.mkey_key++;
  88. spin_unlock_irqrestore(&dev->mdev.priv.mkey_lock, flags);
  89. mr->mmr.key = mlx5_idx_to_mkey(be32_to_cpu(mr->out.mkey) & 0xffffff) | key;
  90. cache->last_add = jiffies;
  91. spin_lock_irqsave(&ent->lock, flags);
  92. list_add_tail(&mr->list, &ent->head);
  93. ent->cur++;
  94. ent->size++;
  95. spin_unlock_irqrestore(&ent->lock, flags);
  96. }
  97. static int add_keys(struct mlx5_ib_dev *dev, int c, int num)
  98. {
  99. struct mlx5_mr_cache *cache = &dev->cache;
  100. struct mlx5_cache_ent *ent = &cache->ent[c];
  101. struct mlx5_create_mkey_mbox_in *in;
  102. struct mlx5_ib_mr *mr;
  103. int npages = 1 << ent->order;
  104. int err = 0;
  105. int i;
  106. in = kzalloc(sizeof(*in), GFP_KERNEL);
  107. if (!in)
  108. return -ENOMEM;
  109. for (i = 0; i < num; i++) {
  110. if (ent->pending >= MAX_PENDING_REG_MR) {
  111. err = -EAGAIN;
  112. break;
  113. }
  114. mr = kzalloc(sizeof(*mr), GFP_KERNEL);
  115. if (!mr) {
  116. err = -ENOMEM;
  117. break;
  118. }
  119. mr->order = ent->order;
  120. mr->umred = 1;
  121. mr->dev = dev;
  122. in->seg.status = 1 << 6;
  123. in->seg.xlt_oct_size = cpu_to_be32((npages + 1) / 2);
  124. in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
  125. in->seg.flags = MLX5_ACCESS_MODE_MTT | MLX5_PERM_UMR_EN;
  126. in->seg.log2_page_size = 12;
  127. spin_lock_irq(&ent->lock);
  128. ent->pending++;
  129. spin_unlock_irq(&ent->lock);
  130. err = mlx5_core_create_mkey(&dev->mdev, &mr->mmr, in,
  131. sizeof(*in), reg_mr_callback,
  132. mr, &mr->out);
  133. if (err) {
  134. mlx5_ib_warn(dev, "create mkey failed %d\n", err);
  135. kfree(mr);
  136. break;
  137. }
  138. }
  139. kfree(in);
  140. return err;
  141. }
  142. static void remove_keys(struct mlx5_ib_dev *dev, int c, int num)
  143. {
  144. struct mlx5_mr_cache *cache = &dev->cache;
  145. struct mlx5_cache_ent *ent = &cache->ent[c];
  146. struct mlx5_ib_mr *mr;
  147. int err;
  148. int i;
  149. for (i = 0; i < num; i++) {
  150. spin_lock_irq(&ent->lock);
  151. if (list_empty(&ent->head)) {
  152. spin_unlock_irq(&ent->lock);
  153. return;
  154. }
  155. mr = list_first_entry(&ent->head, struct mlx5_ib_mr, list);
  156. list_del(&mr->list);
  157. ent->cur--;
  158. ent->size--;
  159. spin_unlock_irq(&ent->lock);
  160. err = mlx5_core_destroy_mkey(&dev->mdev, &mr->mmr);
  161. if (err)
  162. mlx5_ib_warn(dev, "failed destroy mkey\n");
  163. else
  164. kfree(mr);
  165. }
  166. }
  167. static ssize_t size_write(struct file *filp, const char __user *buf,
  168. size_t count, loff_t *pos)
  169. {
  170. struct mlx5_cache_ent *ent = filp->private_data;
  171. struct mlx5_ib_dev *dev = ent->dev;
  172. char lbuf[20];
  173. u32 var;
  174. int err;
  175. int c;
  176. if (copy_from_user(lbuf, buf, sizeof(lbuf)))
  177. return -EFAULT;
  178. c = order2idx(dev, ent->order);
  179. lbuf[sizeof(lbuf) - 1] = 0;
  180. if (sscanf(lbuf, "%u", &var) != 1)
  181. return -EINVAL;
  182. if (var < ent->limit)
  183. return -EINVAL;
  184. if (var > ent->size) {
  185. do {
  186. err = add_keys(dev, c, var - ent->size);
  187. if (err && err != -EAGAIN)
  188. return err;
  189. usleep_range(3000, 5000);
  190. } while (err);
  191. } else if (var < ent->size) {
  192. remove_keys(dev, c, ent->size - var);
  193. }
  194. return count;
  195. }
  196. static ssize_t size_read(struct file *filp, char __user *buf, size_t count,
  197. loff_t *pos)
  198. {
  199. struct mlx5_cache_ent *ent = filp->private_data;
  200. char lbuf[20];
  201. int err;
  202. if (*pos)
  203. return 0;
  204. err = snprintf(lbuf, sizeof(lbuf), "%d\n", ent->size);
  205. if (err < 0)
  206. return err;
  207. if (copy_to_user(buf, lbuf, err))
  208. return -EFAULT;
  209. *pos += err;
  210. return err;
  211. }
  212. static const struct file_operations size_fops = {
  213. .owner = THIS_MODULE,
  214. .open = simple_open,
  215. .write = size_write,
  216. .read = size_read,
  217. };
  218. static ssize_t limit_write(struct file *filp, const char __user *buf,
  219. size_t count, loff_t *pos)
  220. {
  221. struct mlx5_cache_ent *ent = filp->private_data;
  222. struct mlx5_ib_dev *dev = ent->dev;
  223. char lbuf[20];
  224. u32 var;
  225. int err;
  226. int c;
  227. if (copy_from_user(lbuf, buf, sizeof(lbuf)))
  228. return -EFAULT;
  229. c = order2idx(dev, ent->order);
  230. lbuf[sizeof(lbuf) - 1] = 0;
  231. if (sscanf(lbuf, "%u", &var) != 1)
  232. return -EINVAL;
  233. if (var > ent->size)
  234. return -EINVAL;
  235. ent->limit = var;
  236. if (ent->cur < ent->limit) {
  237. err = add_keys(dev, c, 2 * ent->limit - ent->cur);
  238. if (err)
  239. return err;
  240. }
  241. return count;
  242. }
  243. static ssize_t limit_read(struct file *filp, char __user *buf, size_t count,
  244. loff_t *pos)
  245. {
  246. struct mlx5_cache_ent *ent = filp->private_data;
  247. char lbuf[20];
  248. int err;
  249. if (*pos)
  250. return 0;
  251. err = snprintf(lbuf, sizeof(lbuf), "%d\n", ent->limit);
  252. if (err < 0)
  253. return err;
  254. if (copy_to_user(buf, lbuf, err))
  255. return -EFAULT;
  256. *pos += err;
  257. return err;
  258. }
  259. static const struct file_operations limit_fops = {
  260. .owner = THIS_MODULE,
  261. .open = simple_open,
  262. .write = limit_write,
  263. .read = limit_read,
  264. };
  265. static int someone_adding(struct mlx5_mr_cache *cache)
  266. {
  267. int i;
  268. for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) {
  269. if (cache->ent[i].cur < cache->ent[i].limit)
  270. return 1;
  271. }
  272. return 0;
  273. }
  274. static void __cache_work_func(struct mlx5_cache_ent *ent)
  275. {
  276. struct mlx5_ib_dev *dev = ent->dev;
  277. struct mlx5_mr_cache *cache = &dev->cache;
  278. int i = order2idx(dev, ent->order);
  279. int err;
  280. if (cache->stopped)
  281. return;
  282. ent = &dev->cache.ent[i];
  283. if (ent->cur < 2 * ent->limit && !dev->fill_delay) {
  284. err = add_keys(dev, i, 1);
  285. if (ent->cur < 2 * ent->limit) {
  286. if (err == -EAGAIN) {
  287. mlx5_ib_dbg(dev, "returned eagain, order %d\n",
  288. i + 2);
  289. queue_delayed_work(cache->wq, &ent->dwork,
  290. msecs_to_jiffies(3));
  291. } else if (err) {
  292. mlx5_ib_warn(dev, "command failed order %d, err %d\n",
  293. i + 2, err);
  294. queue_delayed_work(cache->wq, &ent->dwork,
  295. msecs_to_jiffies(1000));
  296. } else {
  297. queue_work(cache->wq, &ent->work);
  298. }
  299. }
  300. } else if (ent->cur > 2 * ent->limit) {
  301. if (!someone_adding(cache) &&
  302. time_after(jiffies, cache->last_add + 300 * HZ)) {
  303. remove_keys(dev, i, 1);
  304. if (ent->cur > ent->limit)
  305. queue_work(cache->wq, &ent->work);
  306. } else {
  307. queue_delayed_work(cache->wq, &ent->dwork, 300 * HZ);
  308. }
  309. }
  310. }
  311. static void delayed_cache_work_func(struct work_struct *work)
  312. {
  313. struct mlx5_cache_ent *ent;
  314. ent = container_of(work, struct mlx5_cache_ent, dwork.work);
  315. __cache_work_func(ent);
  316. }
  317. static void cache_work_func(struct work_struct *work)
  318. {
  319. struct mlx5_cache_ent *ent;
  320. ent = container_of(work, struct mlx5_cache_ent, work);
  321. __cache_work_func(ent);
  322. }
  323. static struct mlx5_ib_mr *alloc_cached_mr(struct mlx5_ib_dev *dev, int order)
  324. {
  325. struct mlx5_mr_cache *cache = &dev->cache;
  326. struct mlx5_ib_mr *mr = NULL;
  327. struct mlx5_cache_ent *ent;
  328. int c;
  329. int i;
  330. c = order2idx(dev, order);
  331. if (c < 0 || c >= MAX_MR_CACHE_ENTRIES) {
  332. mlx5_ib_warn(dev, "order %d, cache index %d\n", order, c);
  333. return NULL;
  334. }
  335. for (i = c; i < MAX_MR_CACHE_ENTRIES; i++) {
  336. ent = &cache->ent[i];
  337. mlx5_ib_dbg(dev, "order %d, cache index %d\n", ent->order, i);
  338. spin_lock_irq(&ent->lock);
  339. if (!list_empty(&ent->head)) {
  340. mr = list_first_entry(&ent->head, struct mlx5_ib_mr,
  341. list);
  342. list_del(&mr->list);
  343. ent->cur--;
  344. spin_unlock_irq(&ent->lock);
  345. if (ent->cur < ent->limit)
  346. queue_work(cache->wq, &ent->work);
  347. break;
  348. }
  349. spin_unlock_irq(&ent->lock);
  350. queue_work(cache->wq, &ent->work);
  351. if (mr)
  352. break;
  353. }
  354. if (!mr)
  355. cache->ent[c].miss++;
  356. return mr;
  357. }
  358. static void free_cached_mr(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr)
  359. {
  360. struct mlx5_mr_cache *cache = &dev->cache;
  361. struct mlx5_cache_ent *ent;
  362. int shrink = 0;
  363. int c;
  364. c = order2idx(dev, mr->order);
  365. if (c < 0 || c >= MAX_MR_CACHE_ENTRIES) {
  366. mlx5_ib_warn(dev, "order %d, cache index %d\n", mr->order, c);
  367. return;
  368. }
  369. ent = &cache->ent[c];
  370. spin_lock_irq(&ent->lock);
  371. list_add_tail(&mr->list, &ent->head);
  372. ent->cur++;
  373. if (ent->cur > 2 * ent->limit)
  374. shrink = 1;
  375. spin_unlock_irq(&ent->lock);
  376. if (shrink)
  377. queue_work(cache->wq, &ent->work);
  378. }
  379. static void clean_keys(struct mlx5_ib_dev *dev, int c)
  380. {
  381. struct mlx5_mr_cache *cache = &dev->cache;
  382. struct mlx5_cache_ent *ent = &cache->ent[c];
  383. struct mlx5_ib_mr *mr;
  384. int err;
  385. cancel_delayed_work(&ent->dwork);
  386. while (1) {
  387. spin_lock_irq(&ent->lock);
  388. if (list_empty(&ent->head)) {
  389. spin_unlock_irq(&ent->lock);
  390. return;
  391. }
  392. mr = list_first_entry(&ent->head, struct mlx5_ib_mr, list);
  393. list_del(&mr->list);
  394. ent->cur--;
  395. ent->size--;
  396. spin_unlock_irq(&ent->lock);
  397. err = mlx5_core_destroy_mkey(&dev->mdev, &mr->mmr);
  398. if (err)
  399. mlx5_ib_warn(dev, "failed destroy mkey\n");
  400. else
  401. kfree(mr);
  402. }
  403. }
  404. static int mlx5_mr_cache_debugfs_init(struct mlx5_ib_dev *dev)
  405. {
  406. struct mlx5_mr_cache *cache = &dev->cache;
  407. struct mlx5_cache_ent *ent;
  408. int i;
  409. if (!mlx5_debugfs_root)
  410. return 0;
  411. cache->root = debugfs_create_dir("mr_cache", dev->mdev.priv.dbg_root);
  412. if (!cache->root)
  413. return -ENOMEM;
  414. for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) {
  415. ent = &cache->ent[i];
  416. sprintf(ent->name, "%d", ent->order);
  417. ent->dir = debugfs_create_dir(ent->name, cache->root);
  418. if (!ent->dir)
  419. return -ENOMEM;
  420. ent->fsize = debugfs_create_file("size", 0600, ent->dir, ent,
  421. &size_fops);
  422. if (!ent->fsize)
  423. return -ENOMEM;
  424. ent->flimit = debugfs_create_file("limit", 0600, ent->dir, ent,
  425. &limit_fops);
  426. if (!ent->flimit)
  427. return -ENOMEM;
  428. ent->fcur = debugfs_create_u32("cur", 0400, ent->dir,
  429. &ent->cur);
  430. if (!ent->fcur)
  431. return -ENOMEM;
  432. ent->fmiss = debugfs_create_u32("miss", 0600, ent->dir,
  433. &ent->miss);
  434. if (!ent->fmiss)
  435. return -ENOMEM;
  436. }
  437. return 0;
  438. }
  439. static void mlx5_mr_cache_debugfs_cleanup(struct mlx5_ib_dev *dev)
  440. {
  441. if (!mlx5_debugfs_root)
  442. return;
  443. debugfs_remove_recursive(dev->cache.root);
  444. }
  445. static void delay_time_func(unsigned long ctx)
  446. {
  447. struct mlx5_ib_dev *dev = (struct mlx5_ib_dev *)ctx;
  448. dev->fill_delay = 0;
  449. }
  450. int mlx5_mr_cache_init(struct mlx5_ib_dev *dev)
  451. {
  452. struct mlx5_mr_cache *cache = &dev->cache;
  453. struct mlx5_cache_ent *ent;
  454. int limit;
  455. int err;
  456. int i;
  457. cache->wq = create_singlethread_workqueue("mkey_cache");
  458. if (!cache->wq) {
  459. mlx5_ib_warn(dev, "failed to create work queue\n");
  460. return -ENOMEM;
  461. }
  462. setup_timer(&dev->delay_timer, delay_time_func, (unsigned long)dev);
  463. for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) {
  464. INIT_LIST_HEAD(&cache->ent[i].head);
  465. spin_lock_init(&cache->ent[i].lock);
  466. ent = &cache->ent[i];
  467. INIT_LIST_HEAD(&ent->head);
  468. spin_lock_init(&ent->lock);
  469. ent->order = i + 2;
  470. ent->dev = dev;
  471. if (dev->mdev.profile->mask & MLX5_PROF_MASK_MR_CACHE)
  472. limit = dev->mdev.profile->mr_cache[i].limit;
  473. else
  474. limit = 0;
  475. INIT_WORK(&ent->work, cache_work_func);
  476. INIT_DELAYED_WORK(&ent->dwork, delayed_cache_work_func);
  477. ent->limit = limit;
  478. queue_work(cache->wq, &ent->work);
  479. }
  480. err = mlx5_mr_cache_debugfs_init(dev);
  481. if (err)
  482. mlx5_ib_warn(dev, "cache debugfs failure\n");
  483. return 0;
  484. }
  485. int mlx5_mr_cache_cleanup(struct mlx5_ib_dev *dev)
  486. {
  487. int i;
  488. dev->cache.stopped = 1;
  489. flush_workqueue(dev->cache.wq);
  490. mlx5_mr_cache_debugfs_cleanup(dev);
  491. for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++)
  492. clean_keys(dev, i);
  493. destroy_workqueue(dev->cache.wq);
  494. del_timer_sync(&dev->delay_timer);
  495. return 0;
  496. }
  497. struct ib_mr *mlx5_ib_get_dma_mr(struct ib_pd *pd, int acc)
  498. {
  499. struct mlx5_ib_dev *dev = to_mdev(pd->device);
  500. struct mlx5_core_dev *mdev = &dev->mdev;
  501. struct mlx5_create_mkey_mbox_in *in;
  502. struct mlx5_mkey_seg *seg;
  503. struct mlx5_ib_mr *mr;
  504. int err;
  505. mr = kzalloc(sizeof(*mr), GFP_KERNEL);
  506. if (!mr)
  507. return ERR_PTR(-ENOMEM);
  508. in = kzalloc(sizeof(*in), GFP_KERNEL);
  509. if (!in) {
  510. err = -ENOMEM;
  511. goto err_free;
  512. }
  513. seg = &in->seg;
  514. seg->flags = convert_access(acc) | MLX5_ACCESS_MODE_PA;
  515. seg->flags_pd = cpu_to_be32(to_mpd(pd)->pdn | MLX5_MKEY_LEN64);
  516. seg->qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
  517. seg->start_addr = 0;
  518. err = mlx5_core_create_mkey(mdev, &mr->mmr, in, sizeof(*in), NULL, NULL,
  519. NULL);
  520. if (err)
  521. goto err_in;
  522. kfree(in);
  523. mr->ibmr.lkey = mr->mmr.key;
  524. mr->ibmr.rkey = mr->mmr.key;
  525. mr->umem = NULL;
  526. return &mr->ibmr;
  527. err_in:
  528. kfree(in);
  529. err_free:
  530. kfree(mr);
  531. return ERR_PTR(err);
  532. }
  533. static int get_octo_len(u64 addr, u64 len, int page_size)
  534. {
  535. u64 offset;
  536. int npages;
  537. offset = addr & (page_size - 1);
  538. npages = ALIGN(len + offset, page_size) >> ilog2(page_size);
  539. return (npages + 1) / 2;
  540. }
  541. static int use_umr(int order)
  542. {
  543. return order <= 17;
  544. }
  545. static void prep_umr_reg_wqe(struct ib_pd *pd, struct ib_send_wr *wr,
  546. struct ib_sge *sg, u64 dma, int n, u32 key,
  547. int page_shift, u64 virt_addr, u64 len,
  548. int access_flags)
  549. {
  550. struct mlx5_ib_dev *dev = to_mdev(pd->device);
  551. struct ib_mr *mr = dev->umrc.mr;
  552. sg->addr = dma;
  553. sg->length = ALIGN(sizeof(u64) * n, 64);
  554. sg->lkey = mr->lkey;
  555. wr->next = NULL;
  556. wr->send_flags = 0;
  557. wr->sg_list = sg;
  558. if (n)
  559. wr->num_sge = 1;
  560. else
  561. wr->num_sge = 0;
  562. wr->opcode = MLX5_IB_WR_UMR;
  563. wr->wr.fast_reg.page_list_len = n;
  564. wr->wr.fast_reg.page_shift = page_shift;
  565. wr->wr.fast_reg.rkey = key;
  566. wr->wr.fast_reg.iova_start = virt_addr;
  567. wr->wr.fast_reg.length = len;
  568. wr->wr.fast_reg.access_flags = access_flags;
  569. wr->wr.fast_reg.page_list = (struct ib_fast_reg_page_list *)pd;
  570. }
  571. static void prep_umr_unreg_wqe(struct mlx5_ib_dev *dev,
  572. struct ib_send_wr *wr, u32 key)
  573. {
  574. wr->send_flags = MLX5_IB_SEND_UMR_UNREG;
  575. wr->opcode = MLX5_IB_WR_UMR;
  576. wr->wr.fast_reg.rkey = key;
  577. }
  578. void mlx5_umr_cq_handler(struct ib_cq *cq, void *cq_context)
  579. {
  580. struct mlx5_ib_mr *mr;
  581. struct ib_wc wc;
  582. int err;
  583. while (1) {
  584. err = ib_poll_cq(cq, 1, &wc);
  585. if (err < 0) {
  586. pr_warn("poll cq error %d\n", err);
  587. return;
  588. }
  589. if (err == 0)
  590. break;
  591. mr = (struct mlx5_ib_mr *)(unsigned long)wc.wr_id;
  592. mr->status = wc.status;
  593. complete(&mr->done);
  594. }
  595. ib_req_notify_cq(cq, IB_CQ_NEXT_COMP);
  596. }
  597. static struct mlx5_ib_mr *reg_umr(struct ib_pd *pd, struct ib_umem *umem,
  598. u64 virt_addr, u64 len, int npages,
  599. int page_shift, int order, int access_flags)
  600. {
  601. struct mlx5_ib_dev *dev = to_mdev(pd->device);
  602. struct device *ddev = dev->ib_dev.dma_device;
  603. struct umr_common *umrc = &dev->umrc;
  604. struct ib_send_wr wr, *bad;
  605. struct mlx5_ib_mr *mr;
  606. struct ib_sge sg;
  607. int size = sizeof(u64) * npages;
  608. int err;
  609. int i;
  610. for (i = 0; i < 1; i++) {
  611. mr = alloc_cached_mr(dev, order);
  612. if (mr)
  613. break;
  614. err = add_keys(dev, order2idx(dev, order), 1);
  615. if (err && err != -EAGAIN) {
  616. mlx5_ib_warn(dev, "add_keys failed, err %d\n", err);
  617. break;
  618. }
  619. }
  620. if (!mr)
  621. return ERR_PTR(-EAGAIN);
  622. mr->pas = kmalloc(size + MLX5_UMR_ALIGN - 1, GFP_KERNEL);
  623. if (!mr->pas) {
  624. err = -ENOMEM;
  625. goto error;
  626. }
  627. mlx5_ib_populate_pas(dev, umem, page_shift,
  628. mr_align(mr->pas, MLX5_UMR_ALIGN), 1);
  629. mr->dma = dma_map_single(ddev, mr_align(mr->pas, MLX5_UMR_ALIGN), size,
  630. DMA_TO_DEVICE);
  631. if (dma_mapping_error(ddev, mr->dma)) {
  632. kfree(mr->pas);
  633. err = -ENOMEM;
  634. goto error;
  635. }
  636. memset(&wr, 0, sizeof(wr));
  637. wr.wr_id = (u64)(unsigned long)mr;
  638. prep_umr_reg_wqe(pd, &wr, &sg, mr->dma, npages, mr->mmr.key, page_shift, virt_addr, len, access_flags);
  639. /* We serialize polls so one process does not kidnap another's
  640. * completion. This is not a problem since wr is completed in
  641. * around 1 usec
  642. */
  643. down(&umrc->sem);
  644. init_completion(&mr->done);
  645. err = ib_post_send(umrc->qp, &wr, &bad);
  646. if (err) {
  647. mlx5_ib_warn(dev, "post send failed, err %d\n", err);
  648. up(&umrc->sem);
  649. goto error;
  650. }
  651. wait_for_completion(&mr->done);
  652. up(&umrc->sem);
  653. dma_unmap_single(ddev, mr->dma, size, DMA_TO_DEVICE);
  654. kfree(mr->pas);
  655. if (mr->status != IB_WC_SUCCESS) {
  656. mlx5_ib_warn(dev, "reg umr failed\n");
  657. err = -EFAULT;
  658. goto error;
  659. }
  660. return mr;
  661. error:
  662. free_cached_mr(dev, mr);
  663. return ERR_PTR(err);
  664. }
  665. static struct mlx5_ib_mr *reg_create(struct ib_pd *pd, u64 virt_addr,
  666. u64 length, struct ib_umem *umem,
  667. int npages, int page_shift,
  668. int access_flags)
  669. {
  670. struct mlx5_ib_dev *dev = to_mdev(pd->device);
  671. struct mlx5_create_mkey_mbox_in *in;
  672. struct mlx5_ib_mr *mr;
  673. int inlen;
  674. int err;
  675. mr = kzalloc(sizeof(*mr), GFP_KERNEL);
  676. if (!mr)
  677. return ERR_PTR(-ENOMEM);
  678. inlen = sizeof(*in) + sizeof(*in->pas) * ((npages + 1) / 2) * 2;
  679. in = mlx5_vzalloc(inlen);
  680. if (!in) {
  681. err = -ENOMEM;
  682. goto err_1;
  683. }
  684. mlx5_ib_populate_pas(dev, umem, page_shift, in->pas, 0);
  685. in->seg.flags = convert_access(access_flags) |
  686. MLX5_ACCESS_MODE_MTT;
  687. in->seg.flags_pd = cpu_to_be32(to_mpd(pd)->pdn);
  688. in->seg.start_addr = cpu_to_be64(virt_addr);
  689. in->seg.len = cpu_to_be64(length);
  690. in->seg.bsfs_octo_size = 0;
  691. in->seg.xlt_oct_size = cpu_to_be32(get_octo_len(virt_addr, length, 1 << page_shift));
  692. in->seg.log2_page_size = page_shift;
  693. in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
  694. in->xlat_oct_act_size = cpu_to_be32(get_octo_len(virt_addr, length,
  695. 1 << page_shift));
  696. err = mlx5_core_create_mkey(&dev->mdev, &mr->mmr, in, inlen, NULL,
  697. NULL, NULL);
  698. if (err) {
  699. mlx5_ib_warn(dev, "create mkey failed\n");
  700. goto err_2;
  701. }
  702. mr->umem = umem;
  703. mlx5_vfree(in);
  704. mlx5_ib_dbg(dev, "mkey = 0x%x\n", mr->mmr.key);
  705. return mr;
  706. err_2:
  707. mlx5_vfree(in);
  708. err_1:
  709. kfree(mr);
  710. return ERR_PTR(err);
  711. }
  712. struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
  713. u64 virt_addr, int access_flags,
  714. struct ib_udata *udata)
  715. {
  716. struct mlx5_ib_dev *dev = to_mdev(pd->device);
  717. struct mlx5_ib_mr *mr = NULL;
  718. struct ib_umem *umem;
  719. int page_shift;
  720. int npages;
  721. int ncont;
  722. int order;
  723. int err;
  724. mlx5_ib_dbg(dev, "start 0x%llx, virt_addr 0x%llx, length 0x%llx\n",
  725. start, virt_addr, length);
  726. umem = ib_umem_get(pd->uobject->context, start, length, access_flags,
  727. 0);
  728. if (IS_ERR(umem)) {
  729. mlx5_ib_dbg(dev, "umem get failed\n");
  730. return (void *)umem;
  731. }
  732. mlx5_ib_cont_pages(umem, start, &npages, &page_shift, &ncont, &order);
  733. if (!npages) {
  734. mlx5_ib_warn(dev, "avoid zero region\n");
  735. err = -EINVAL;
  736. goto error;
  737. }
  738. mlx5_ib_dbg(dev, "npages %d, ncont %d, order %d, page_shift %d\n",
  739. npages, ncont, order, page_shift);
  740. if (use_umr(order)) {
  741. mr = reg_umr(pd, umem, virt_addr, length, ncont, page_shift,
  742. order, access_flags);
  743. if (PTR_ERR(mr) == -EAGAIN) {
  744. mlx5_ib_dbg(dev, "cache empty for order %d", order);
  745. mr = NULL;
  746. }
  747. }
  748. if (!mr)
  749. mr = reg_create(pd, virt_addr, length, umem, ncont, page_shift,
  750. access_flags);
  751. if (IS_ERR(mr)) {
  752. err = PTR_ERR(mr);
  753. goto error;
  754. }
  755. mlx5_ib_dbg(dev, "mkey 0x%x\n", mr->mmr.key);
  756. mr->umem = umem;
  757. mr->npages = npages;
  758. spin_lock(&dev->mr_lock);
  759. dev->mdev.priv.reg_pages += npages;
  760. spin_unlock(&dev->mr_lock);
  761. mr->ibmr.lkey = mr->mmr.key;
  762. mr->ibmr.rkey = mr->mmr.key;
  763. return &mr->ibmr;
  764. error:
  765. ib_umem_release(umem);
  766. return ERR_PTR(err);
  767. }
  768. static int unreg_umr(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr)
  769. {
  770. struct umr_common *umrc = &dev->umrc;
  771. struct ib_send_wr wr, *bad;
  772. int err;
  773. memset(&wr, 0, sizeof(wr));
  774. wr.wr_id = (u64)(unsigned long)mr;
  775. prep_umr_unreg_wqe(dev, &wr, mr->mmr.key);
  776. down(&umrc->sem);
  777. init_completion(&mr->done);
  778. err = ib_post_send(umrc->qp, &wr, &bad);
  779. if (err) {
  780. up(&umrc->sem);
  781. mlx5_ib_dbg(dev, "err %d\n", err);
  782. goto error;
  783. }
  784. wait_for_completion(&mr->done);
  785. up(&umrc->sem);
  786. if (mr->status != IB_WC_SUCCESS) {
  787. mlx5_ib_warn(dev, "unreg umr failed\n");
  788. err = -EFAULT;
  789. goto error;
  790. }
  791. return 0;
  792. error:
  793. return err;
  794. }
  795. int mlx5_ib_dereg_mr(struct ib_mr *ibmr)
  796. {
  797. struct mlx5_ib_dev *dev = to_mdev(ibmr->device);
  798. struct mlx5_ib_mr *mr = to_mmr(ibmr);
  799. struct ib_umem *umem = mr->umem;
  800. int npages = mr->npages;
  801. int umred = mr->umred;
  802. int err;
  803. if (!umred) {
  804. err = mlx5_core_destroy_mkey(&dev->mdev, &mr->mmr);
  805. if (err) {
  806. mlx5_ib_warn(dev, "failed to destroy mkey 0x%x (%d)\n",
  807. mr->mmr.key, err);
  808. return err;
  809. }
  810. } else {
  811. err = unreg_umr(dev, mr);
  812. if (err) {
  813. mlx5_ib_warn(dev, "failed unregister\n");
  814. return err;
  815. }
  816. free_cached_mr(dev, mr);
  817. }
  818. if (umem) {
  819. ib_umem_release(umem);
  820. spin_lock(&dev->mr_lock);
  821. dev->mdev.priv.reg_pages -= npages;
  822. spin_unlock(&dev->mr_lock);
  823. }
  824. if (!umred)
  825. kfree(mr);
  826. return 0;
  827. }
  828. struct ib_mr *mlx5_ib_alloc_fast_reg_mr(struct ib_pd *pd,
  829. int max_page_list_len)
  830. {
  831. struct mlx5_ib_dev *dev = to_mdev(pd->device);
  832. struct mlx5_create_mkey_mbox_in *in;
  833. struct mlx5_ib_mr *mr;
  834. int err;
  835. mr = kzalloc(sizeof(*mr), GFP_KERNEL);
  836. if (!mr)
  837. return ERR_PTR(-ENOMEM);
  838. in = kzalloc(sizeof(*in), GFP_KERNEL);
  839. if (!in) {
  840. err = -ENOMEM;
  841. goto err_free;
  842. }
  843. in->seg.status = 1 << 6; /* free */
  844. in->seg.xlt_oct_size = cpu_to_be32((max_page_list_len + 1) / 2);
  845. in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
  846. in->seg.flags = MLX5_PERM_UMR_EN | MLX5_ACCESS_MODE_MTT;
  847. in->seg.flags_pd = cpu_to_be32(to_mpd(pd)->pdn);
  848. /*
  849. * TBD not needed - issue 197292 */
  850. in->seg.log2_page_size = PAGE_SHIFT;
  851. err = mlx5_core_create_mkey(&dev->mdev, &mr->mmr, in, sizeof(*in), NULL,
  852. NULL, NULL);
  853. kfree(in);
  854. if (err)
  855. goto err_free;
  856. mr->ibmr.lkey = mr->mmr.key;
  857. mr->ibmr.rkey = mr->mmr.key;
  858. mr->umem = NULL;
  859. return &mr->ibmr;
  860. err_free:
  861. kfree(mr);
  862. return ERR_PTR(err);
  863. }
  864. struct ib_fast_reg_page_list *mlx5_ib_alloc_fast_reg_page_list(struct ib_device *ibdev,
  865. int page_list_len)
  866. {
  867. struct mlx5_ib_fast_reg_page_list *mfrpl;
  868. int size = page_list_len * sizeof(u64);
  869. mfrpl = kmalloc(sizeof(*mfrpl), GFP_KERNEL);
  870. if (!mfrpl)
  871. return ERR_PTR(-ENOMEM);
  872. mfrpl->ibfrpl.page_list = kmalloc(size, GFP_KERNEL);
  873. if (!mfrpl->ibfrpl.page_list)
  874. goto err_free;
  875. mfrpl->mapped_page_list = dma_alloc_coherent(ibdev->dma_device,
  876. size, &mfrpl->map,
  877. GFP_KERNEL);
  878. if (!mfrpl->mapped_page_list)
  879. goto err_free;
  880. WARN_ON(mfrpl->map & 0x3f);
  881. return &mfrpl->ibfrpl;
  882. err_free:
  883. kfree(mfrpl->ibfrpl.page_list);
  884. kfree(mfrpl);
  885. return ERR_PTR(-ENOMEM);
  886. }
  887. void mlx5_ib_free_fast_reg_page_list(struct ib_fast_reg_page_list *page_list)
  888. {
  889. struct mlx5_ib_fast_reg_page_list *mfrpl = to_mfrpl(page_list);
  890. struct mlx5_ib_dev *dev = to_mdev(page_list->device);
  891. int size = page_list->max_page_list_len * sizeof(u64);
  892. dma_free_coherent(&dev->mdev.pdev->dev, size, mfrpl->mapped_page_list,
  893. mfrpl->map);
  894. kfree(mfrpl->ibfrpl.page_list);
  895. kfree(mfrpl);
  896. }