main.c 38 KB

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  1. /*
  2. * Copyright (c) 2013, Mellanox Technologies inc. All rights reserved.
  3. *
  4. * This software is available to you under a choice of one of two
  5. * licenses. You may choose to be licensed under the terms of the GNU
  6. * General Public License (GPL) Version 2, available from the file
  7. * COPYING in the main directory of this source tree, or the
  8. * OpenIB.org BSD license below:
  9. *
  10. * Redistribution and use in source and binary forms, with or
  11. * without modification, are permitted provided that the following
  12. * conditions are met:
  13. *
  14. * - Redistributions of source code must retain the above
  15. * copyright notice, this list of conditions and the following
  16. * disclaimer.
  17. *
  18. * - Redistributions in binary form must reproduce the above
  19. * copyright notice, this list of conditions and the following
  20. * disclaimer in the documentation and/or other materials
  21. * provided with the distribution.
  22. *
  23. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30. * SOFTWARE.
  31. */
  32. #include <asm-generic/kmap_types.h>
  33. #include <linux/module.h>
  34. #include <linux/init.h>
  35. #include <linux/errno.h>
  36. #include <linux/pci.h>
  37. #include <linux/dma-mapping.h>
  38. #include <linux/slab.h>
  39. #include <linux/io-mapping.h>
  40. #include <linux/sched.h>
  41. #include <rdma/ib_user_verbs.h>
  42. #include <rdma/ib_smi.h>
  43. #include <rdma/ib_umem.h>
  44. #include "user.h"
  45. #include "mlx5_ib.h"
  46. #define DRIVER_NAME "mlx5_ib"
  47. #define DRIVER_VERSION "2.2-1"
  48. #define DRIVER_RELDATE "Feb 2014"
  49. MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
  50. MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
  51. MODULE_LICENSE("Dual BSD/GPL");
  52. MODULE_VERSION(DRIVER_VERSION);
  53. static int prof_sel = 2;
  54. module_param_named(prof_sel, prof_sel, int, 0444);
  55. MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
  56. static char mlx5_version[] =
  57. DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
  58. DRIVER_VERSION " (" DRIVER_RELDATE ")\n";
  59. static struct mlx5_profile profile[] = {
  60. [0] = {
  61. .mask = 0,
  62. },
  63. [1] = {
  64. .mask = MLX5_PROF_MASK_QP_SIZE,
  65. .log_max_qp = 12,
  66. },
  67. [2] = {
  68. .mask = MLX5_PROF_MASK_QP_SIZE |
  69. MLX5_PROF_MASK_MR_CACHE,
  70. .log_max_qp = 17,
  71. .mr_cache[0] = {
  72. .size = 500,
  73. .limit = 250
  74. },
  75. .mr_cache[1] = {
  76. .size = 500,
  77. .limit = 250
  78. },
  79. .mr_cache[2] = {
  80. .size = 500,
  81. .limit = 250
  82. },
  83. .mr_cache[3] = {
  84. .size = 500,
  85. .limit = 250
  86. },
  87. .mr_cache[4] = {
  88. .size = 500,
  89. .limit = 250
  90. },
  91. .mr_cache[5] = {
  92. .size = 500,
  93. .limit = 250
  94. },
  95. .mr_cache[6] = {
  96. .size = 500,
  97. .limit = 250
  98. },
  99. .mr_cache[7] = {
  100. .size = 500,
  101. .limit = 250
  102. },
  103. .mr_cache[8] = {
  104. .size = 500,
  105. .limit = 250
  106. },
  107. .mr_cache[9] = {
  108. .size = 500,
  109. .limit = 250
  110. },
  111. .mr_cache[10] = {
  112. .size = 500,
  113. .limit = 250
  114. },
  115. .mr_cache[11] = {
  116. .size = 500,
  117. .limit = 250
  118. },
  119. .mr_cache[12] = {
  120. .size = 64,
  121. .limit = 32
  122. },
  123. .mr_cache[13] = {
  124. .size = 32,
  125. .limit = 16
  126. },
  127. .mr_cache[14] = {
  128. .size = 16,
  129. .limit = 8
  130. },
  131. .mr_cache[15] = {
  132. .size = 8,
  133. .limit = 4
  134. },
  135. },
  136. };
  137. int mlx5_vector2eqn(struct mlx5_ib_dev *dev, int vector, int *eqn, int *irqn)
  138. {
  139. struct mlx5_eq_table *table = &dev->mdev.priv.eq_table;
  140. struct mlx5_eq *eq, *n;
  141. int err = -ENOENT;
  142. spin_lock(&table->lock);
  143. list_for_each_entry_safe(eq, n, &dev->eqs_list, list) {
  144. if (eq->index == vector) {
  145. *eqn = eq->eqn;
  146. *irqn = eq->irqn;
  147. err = 0;
  148. break;
  149. }
  150. }
  151. spin_unlock(&table->lock);
  152. return err;
  153. }
  154. static int alloc_comp_eqs(struct mlx5_ib_dev *dev)
  155. {
  156. struct mlx5_eq_table *table = &dev->mdev.priv.eq_table;
  157. char name[MLX5_MAX_EQ_NAME];
  158. struct mlx5_eq *eq, *n;
  159. int ncomp_vec;
  160. int nent;
  161. int err;
  162. int i;
  163. INIT_LIST_HEAD(&dev->eqs_list);
  164. ncomp_vec = table->num_comp_vectors;
  165. nent = MLX5_COMP_EQ_SIZE;
  166. for (i = 0; i < ncomp_vec; i++) {
  167. eq = kzalloc(sizeof(*eq), GFP_KERNEL);
  168. if (!eq) {
  169. err = -ENOMEM;
  170. goto clean;
  171. }
  172. snprintf(name, MLX5_MAX_EQ_NAME, "mlx5_comp%d", i);
  173. err = mlx5_create_map_eq(&dev->mdev, eq,
  174. i + MLX5_EQ_VEC_COMP_BASE, nent, 0,
  175. name, &dev->mdev.priv.uuari.uars[0]);
  176. if (err) {
  177. kfree(eq);
  178. goto clean;
  179. }
  180. mlx5_ib_dbg(dev, "allocated completion EQN %d\n", eq->eqn);
  181. eq->index = i;
  182. spin_lock(&table->lock);
  183. list_add_tail(&eq->list, &dev->eqs_list);
  184. spin_unlock(&table->lock);
  185. }
  186. dev->num_comp_vectors = ncomp_vec;
  187. return 0;
  188. clean:
  189. spin_lock(&table->lock);
  190. list_for_each_entry_safe(eq, n, &dev->eqs_list, list) {
  191. list_del(&eq->list);
  192. spin_unlock(&table->lock);
  193. if (mlx5_destroy_unmap_eq(&dev->mdev, eq))
  194. mlx5_ib_warn(dev, "failed to destroy EQ 0x%x\n", eq->eqn);
  195. kfree(eq);
  196. spin_lock(&table->lock);
  197. }
  198. spin_unlock(&table->lock);
  199. return err;
  200. }
  201. static void free_comp_eqs(struct mlx5_ib_dev *dev)
  202. {
  203. struct mlx5_eq_table *table = &dev->mdev.priv.eq_table;
  204. struct mlx5_eq *eq, *n;
  205. spin_lock(&table->lock);
  206. list_for_each_entry_safe(eq, n, &dev->eqs_list, list) {
  207. list_del(&eq->list);
  208. spin_unlock(&table->lock);
  209. if (mlx5_destroy_unmap_eq(&dev->mdev, eq))
  210. mlx5_ib_warn(dev, "failed to destroy EQ 0x%x\n", eq->eqn);
  211. kfree(eq);
  212. spin_lock(&table->lock);
  213. }
  214. spin_unlock(&table->lock);
  215. }
  216. static int mlx5_ib_query_device(struct ib_device *ibdev,
  217. struct ib_device_attr *props)
  218. {
  219. struct mlx5_ib_dev *dev = to_mdev(ibdev);
  220. struct ib_smp *in_mad = NULL;
  221. struct ib_smp *out_mad = NULL;
  222. int err = -ENOMEM;
  223. int max_rq_sg;
  224. int max_sq_sg;
  225. u64 flags;
  226. in_mad = kzalloc(sizeof(*in_mad), GFP_KERNEL);
  227. out_mad = kmalloc(sizeof(*out_mad), GFP_KERNEL);
  228. if (!in_mad || !out_mad)
  229. goto out;
  230. init_query_mad(in_mad);
  231. in_mad->attr_id = IB_SMP_ATTR_NODE_INFO;
  232. err = mlx5_MAD_IFC(to_mdev(ibdev), 1, 1, 1, NULL, NULL, in_mad, out_mad);
  233. if (err)
  234. goto out;
  235. memset(props, 0, sizeof(*props));
  236. props->fw_ver = ((u64)fw_rev_maj(&dev->mdev) << 32) |
  237. (fw_rev_min(&dev->mdev) << 16) |
  238. fw_rev_sub(&dev->mdev);
  239. props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
  240. IB_DEVICE_PORT_ACTIVE_EVENT |
  241. IB_DEVICE_SYS_IMAGE_GUID |
  242. IB_DEVICE_RC_RNR_NAK_GEN;
  243. flags = dev->mdev.caps.flags;
  244. if (flags & MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR)
  245. props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
  246. if (flags & MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR)
  247. props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
  248. if (flags & MLX5_DEV_CAP_FLAG_APM)
  249. props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
  250. props->device_cap_flags |= IB_DEVICE_LOCAL_DMA_LKEY;
  251. if (flags & MLX5_DEV_CAP_FLAG_XRC)
  252. props->device_cap_flags |= IB_DEVICE_XRC;
  253. props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
  254. props->vendor_id = be32_to_cpup((__be32 *)(out_mad->data + 36)) &
  255. 0xffffff;
  256. props->vendor_part_id = be16_to_cpup((__be16 *)(out_mad->data + 30));
  257. props->hw_ver = be32_to_cpup((__be32 *)(out_mad->data + 32));
  258. memcpy(&props->sys_image_guid, out_mad->data + 4, 8);
  259. props->max_mr_size = ~0ull;
  260. props->page_size_cap = dev->mdev.caps.min_page_sz;
  261. props->max_qp = 1 << dev->mdev.caps.log_max_qp;
  262. props->max_qp_wr = dev->mdev.caps.max_wqes;
  263. max_rq_sg = dev->mdev.caps.max_rq_desc_sz / sizeof(struct mlx5_wqe_data_seg);
  264. max_sq_sg = (dev->mdev.caps.max_sq_desc_sz - sizeof(struct mlx5_wqe_ctrl_seg)) /
  265. sizeof(struct mlx5_wqe_data_seg);
  266. props->max_sge = min(max_rq_sg, max_sq_sg);
  267. props->max_cq = 1 << dev->mdev.caps.log_max_cq;
  268. props->max_cqe = dev->mdev.caps.max_cqes - 1;
  269. props->max_mr = 1 << dev->mdev.caps.log_max_mkey;
  270. props->max_pd = 1 << dev->mdev.caps.log_max_pd;
  271. props->max_qp_rd_atom = dev->mdev.caps.max_ra_req_qp;
  272. props->max_qp_init_rd_atom = dev->mdev.caps.max_ra_res_qp;
  273. props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
  274. props->max_srq = 1 << dev->mdev.caps.log_max_srq;
  275. props->max_srq_wr = dev->mdev.caps.max_srq_wqes - 1;
  276. props->max_srq_sge = max_rq_sg - 1;
  277. props->max_fast_reg_page_list_len = (unsigned int)-1;
  278. props->local_ca_ack_delay = dev->mdev.caps.local_ca_ack_delay;
  279. props->atomic_cap = IB_ATOMIC_NONE;
  280. props->masked_atomic_cap = IB_ATOMIC_NONE;
  281. props->max_pkeys = be16_to_cpup((__be16 *)(out_mad->data + 28));
  282. props->max_mcast_grp = 1 << dev->mdev.caps.log_max_mcg;
  283. props->max_mcast_qp_attach = dev->mdev.caps.max_qp_mcg;
  284. props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
  285. props->max_mcast_grp;
  286. props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
  287. out:
  288. kfree(in_mad);
  289. kfree(out_mad);
  290. return err;
  291. }
  292. int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
  293. struct ib_port_attr *props)
  294. {
  295. struct mlx5_ib_dev *dev = to_mdev(ibdev);
  296. struct ib_smp *in_mad = NULL;
  297. struct ib_smp *out_mad = NULL;
  298. int ext_active_speed;
  299. int err = -ENOMEM;
  300. if (port < 1 || port > dev->mdev.caps.num_ports) {
  301. mlx5_ib_warn(dev, "invalid port number %d\n", port);
  302. return -EINVAL;
  303. }
  304. in_mad = kzalloc(sizeof(*in_mad), GFP_KERNEL);
  305. out_mad = kmalloc(sizeof(*out_mad), GFP_KERNEL);
  306. if (!in_mad || !out_mad)
  307. goto out;
  308. memset(props, 0, sizeof(*props));
  309. init_query_mad(in_mad);
  310. in_mad->attr_id = IB_SMP_ATTR_PORT_INFO;
  311. in_mad->attr_mod = cpu_to_be32(port);
  312. err = mlx5_MAD_IFC(dev, 1, 1, port, NULL, NULL, in_mad, out_mad);
  313. if (err) {
  314. mlx5_ib_warn(dev, "err %d\n", err);
  315. goto out;
  316. }
  317. props->lid = be16_to_cpup((__be16 *)(out_mad->data + 16));
  318. props->lmc = out_mad->data[34] & 0x7;
  319. props->sm_lid = be16_to_cpup((__be16 *)(out_mad->data + 18));
  320. props->sm_sl = out_mad->data[36] & 0xf;
  321. props->state = out_mad->data[32] & 0xf;
  322. props->phys_state = out_mad->data[33] >> 4;
  323. props->port_cap_flags = be32_to_cpup((__be32 *)(out_mad->data + 20));
  324. props->gid_tbl_len = out_mad->data[50];
  325. props->max_msg_sz = 1 << to_mdev(ibdev)->mdev.caps.log_max_msg;
  326. props->pkey_tbl_len = to_mdev(ibdev)->mdev.caps.port[port - 1].pkey_table_len;
  327. props->bad_pkey_cntr = be16_to_cpup((__be16 *)(out_mad->data + 46));
  328. props->qkey_viol_cntr = be16_to_cpup((__be16 *)(out_mad->data + 48));
  329. props->active_width = out_mad->data[31] & 0xf;
  330. props->active_speed = out_mad->data[35] >> 4;
  331. props->max_mtu = out_mad->data[41] & 0xf;
  332. props->active_mtu = out_mad->data[36] >> 4;
  333. props->subnet_timeout = out_mad->data[51] & 0x1f;
  334. props->max_vl_num = out_mad->data[37] >> 4;
  335. props->init_type_reply = out_mad->data[41] >> 4;
  336. /* Check if extended speeds (EDR/FDR/...) are supported */
  337. if (props->port_cap_flags & IB_PORT_EXTENDED_SPEEDS_SUP) {
  338. ext_active_speed = out_mad->data[62] >> 4;
  339. switch (ext_active_speed) {
  340. case 1:
  341. props->active_speed = 16; /* FDR */
  342. break;
  343. case 2:
  344. props->active_speed = 32; /* EDR */
  345. break;
  346. }
  347. }
  348. /* If reported active speed is QDR, check if is FDR-10 */
  349. if (props->active_speed == 4) {
  350. if (dev->mdev.caps.ext_port_cap[port - 1] &
  351. MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO) {
  352. init_query_mad(in_mad);
  353. in_mad->attr_id = MLX5_ATTR_EXTENDED_PORT_INFO;
  354. in_mad->attr_mod = cpu_to_be32(port);
  355. err = mlx5_MAD_IFC(dev, 1, 1, port,
  356. NULL, NULL, in_mad, out_mad);
  357. if (err)
  358. goto out;
  359. /* Checking LinkSpeedActive for FDR-10 */
  360. if (out_mad->data[15] & 0x1)
  361. props->active_speed = 8;
  362. }
  363. }
  364. out:
  365. kfree(in_mad);
  366. kfree(out_mad);
  367. return err;
  368. }
  369. static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
  370. union ib_gid *gid)
  371. {
  372. struct ib_smp *in_mad = NULL;
  373. struct ib_smp *out_mad = NULL;
  374. int err = -ENOMEM;
  375. in_mad = kzalloc(sizeof(*in_mad), GFP_KERNEL);
  376. out_mad = kmalloc(sizeof(*out_mad), GFP_KERNEL);
  377. if (!in_mad || !out_mad)
  378. goto out;
  379. init_query_mad(in_mad);
  380. in_mad->attr_id = IB_SMP_ATTR_PORT_INFO;
  381. in_mad->attr_mod = cpu_to_be32(port);
  382. err = mlx5_MAD_IFC(to_mdev(ibdev), 1, 1, port, NULL, NULL, in_mad, out_mad);
  383. if (err)
  384. goto out;
  385. memcpy(gid->raw, out_mad->data + 8, 8);
  386. init_query_mad(in_mad);
  387. in_mad->attr_id = IB_SMP_ATTR_GUID_INFO;
  388. in_mad->attr_mod = cpu_to_be32(index / 8);
  389. err = mlx5_MAD_IFC(to_mdev(ibdev), 1, 1, port, NULL, NULL, in_mad, out_mad);
  390. if (err)
  391. goto out;
  392. memcpy(gid->raw + 8, out_mad->data + (index % 8) * 8, 8);
  393. out:
  394. kfree(in_mad);
  395. kfree(out_mad);
  396. return err;
  397. }
  398. static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
  399. u16 *pkey)
  400. {
  401. struct ib_smp *in_mad = NULL;
  402. struct ib_smp *out_mad = NULL;
  403. int err = -ENOMEM;
  404. in_mad = kzalloc(sizeof(*in_mad), GFP_KERNEL);
  405. out_mad = kmalloc(sizeof(*out_mad), GFP_KERNEL);
  406. if (!in_mad || !out_mad)
  407. goto out;
  408. init_query_mad(in_mad);
  409. in_mad->attr_id = IB_SMP_ATTR_PKEY_TABLE;
  410. in_mad->attr_mod = cpu_to_be32(index / 32);
  411. err = mlx5_MAD_IFC(to_mdev(ibdev), 1, 1, port, NULL, NULL, in_mad, out_mad);
  412. if (err)
  413. goto out;
  414. *pkey = be16_to_cpu(((__be16 *)out_mad->data)[index % 32]);
  415. out:
  416. kfree(in_mad);
  417. kfree(out_mad);
  418. return err;
  419. }
  420. struct mlx5_reg_node_desc {
  421. u8 desc[64];
  422. };
  423. static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
  424. struct ib_device_modify *props)
  425. {
  426. struct mlx5_ib_dev *dev = to_mdev(ibdev);
  427. struct mlx5_reg_node_desc in;
  428. struct mlx5_reg_node_desc out;
  429. int err;
  430. if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
  431. return -EOPNOTSUPP;
  432. if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
  433. return 0;
  434. /*
  435. * If possible, pass node desc to FW, so it can generate
  436. * a 144 trap. If cmd fails, just ignore.
  437. */
  438. memcpy(&in, props->node_desc, 64);
  439. err = mlx5_core_access_reg(&dev->mdev, &in, sizeof(in), &out,
  440. sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
  441. if (err)
  442. return err;
  443. memcpy(ibdev->node_desc, props->node_desc, 64);
  444. return err;
  445. }
  446. static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
  447. struct ib_port_modify *props)
  448. {
  449. struct mlx5_ib_dev *dev = to_mdev(ibdev);
  450. struct ib_port_attr attr;
  451. u32 tmp;
  452. int err;
  453. mutex_lock(&dev->cap_mask_mutex);
  454. err = mlx5_ib_query_port(ibdev, port, &attr);
  455. if (err)
  456. goto out;
  457. tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
  458. ~props->clr_port_cap_mask;
  459. err = mlx5_set_port_caps(&dev->mdev, port, tmp);
  460. out:
  461. mutex_unlock(&dev->cap_mask_mutex);
  462. return err;
  463. }
  464. static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
  465. struct ib_udata *udata)
  466. {
  467. struct mlx5_ib_dev *dev = to_mdev(ibdev);
  468. struct mlx5_ib_alloc_ucontext_req_v2 req;
  469. struct mlx5_ib_alloc_ucontext_resp resp;
  470. struct mlx5_ib_ucontext *context;
  471. struct mlx5_uuar_info *uuari;
  472. struct mlx5_uar *uars;
  473. int gross_uuars;
  474. int num_uars;
  475. int ver;
  476. int uuarn;
  477. int err;
  478. int i;
  479. int reqlen;
  480. if (!dev->ib_active)
  481. return ERR_PTR(-EAGAIN);
  482. memset(&req, 0, sizeof(req));
  483. reqlen = udata->inlen - sizeof(struct ib_uverbs_cmd_hdr);
  484. if (reqlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
  485. ver = 0;
  486. else if (reqlen == sizeof(struct mlx5_ib_alloc_ucontext_req_v2))
  487. ver = 2;
  488. else
  489. return ERR_PTR(-EINVAL);
  490. err = ib_copy_from_udata(&req, udata, reqlen);
  491. if (err)
  492. return ERR_PTR(err);
  493. if (req.flags || req.reserved)
  494. return ERR_PTR(-EINVAL);
  495. if (req.total_num_uuars > MLX5_MAX_UUARS)
  496. return ERR_PTR(-ENOMEM);
  497. if (req.total_num_uuars == 0)
  498. return ERR_PTR(-EINVAL);
  499. req.total_num_uuars = ALIGN(req.total_num_uuars,
  500. MLX5_NON_FP_BF_REGS_PER_PAGE);
  501. if (req.num_low_latency_uuars > req.total_num_uuars - 1)
  502. return ERR_PTR(-EINVAL);
  503. num_uars = req.total_num_uuars / MLX5_NON_FP_BF_REGS_PER_PAGE;
  504. gross_uuars = num_uars * MLX5_BF_REGS_PER_PAGE;
  505. resp.qp_tab_size = 1 << dev->mdev.caps.log_max_qp;
  506. resp.bf_reg_size = dev->mdev.caps.bf_reg_size;
  507. resp.cache_line_size = L1_CACHE_BYTES;
  508. resp.max_sq_desc_sz = dev->mdev.caps.max_sq_desc_sz;
  509. resp.max_rq_desc_sz = dev->mdev.caps.max_rq_desc_sz;
  510. resp.max_send_wqebb = dev->mdev.caps.max_wqes;
  511. resp.max_recv_wr = dev->mdev.caps.max_wqes;
  512. resp.max_srq_recv_wr = dev->mdev.caps.max_srq_wqes;
  513. context = kzalloc(sizeof(*context), GFP_KERNEL);
  514. if (!context)
  515. return ERR_PTR(-ENOMEM);
  516. uuari = &context->uuari;
  517. mutex_init(&uuari->lock);
  518. uars = kcalloc(num_uars, sizeof(*uars), GFP_KERNEL);
  519. if (!uars) {
  520. err = -ENOMEM;
  521. goto out_ctx;
  522. }
  523. uuari->bitmap = kcalloc(BITS_TO_LONGS(gross_uuars),
  524. sizeof(*uuari->bitmap),
  525. GFP_KERNEL);
  526. if (!uuari->bitmap) {
  527. err = -ENOMEM;
  528. goto out_uar_ctx;
  529. }
  530. /*
  531. * clear all fast path uuars
  532. */
  533. for (i = 0; i < gross_uuars; i++) {
  534. uuarn = i & 3;
  535. if (uuarn == 2 || uuarn == 3)
  536. set_bit(i, uuari->bitmap);
  537. }
  538. uuari->count = kcalloc(gross_uuars, sizeof(*uuari->count), GFP_KERNEL);
  539. if (!uuari->count) {
  540. err = -ENOMEM;
  541. goto out_bitmap;
  542. }
  543. for (i = 0; i < num_uars; i++) {
  544. err = mlx5_cmd_alloc_uar(&dev->mdev, &uars[i].index);
  545. if (err)
  546. goto out_count;
  547. }
  548. INIT_LIST_HEAD(&context->db_page_list);
  549. mutex_init(&context->db_page_mutex);
  550. resp.tot_uuars = req.total_num_uuars;
  551. resp.num_ports = dev->mdev.caps.num_ports;
  552. err = ib_copy_to_udata(udata, &resp,
  553. sizeof(resp) - sizeof(resp.reserved));
  554. if (err)
  555. goto out_uars;
  556. uuari->ver = ver;
  557. uuari->num_low_latency_uuars = req.num_low_latency_uuars;
  558. uuari->uars = uars;
  559. uuari->num_uars = num_uars;
  560. return &context->ibucontext;
  561. out_uars:
  562. for (i--; i >= 0; i--)
  563. mlx5_cmd_free_uar(&dev->mdev, uars[i].index);
  564. out_count:
  565. kfree(uuari->count);
  566. out_bitmap:
  567. kfree(uuari->bitmap);
  568. out_uar_ctx:
  569. kfree(uars);
  570. out_ctx:
  571. kfree(context);
  572. return ERR_PTR(err);
  573. }
  574. static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
  575. {
  576. struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
  577. struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
  578. struct mlx5_uuar_info *uuari = &context->uuari;
  579. int i;
  580. for (i = 0; i < uuari->num_uars; i++) {
  581. if (mlx5_cmd_free_uar(&dev->mdev, uuari->uars[i].index))
  582. mlx5_ib_warn(dev, "failed to free UAR 0x%x\n", uuari->uars[i].index);
  583. }
  584. kfree(uuari->count);
  585. kfree(uuari->bitmap);
  586. kfree(uuari->uars);
  587. kfree(context);
  588. return 0;
  589. }
  590. static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, int index)
  591. {
  592. return (pci_resource_start(dev->mdev.pdev, 0) >> PAGE_SHIFT) + index;
  593. }
  594. static int get_command(unsigned long offset)
  595. {
  596. return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
  597. }
  598. static int get_arg(unsigned long offset)
  599. {
  600. return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
  601. }
  602. static int get_index(unsigned long offset)
  603. {
  604. return get_arg(offset);
  605. }
  606. static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
  607. {
  608. struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
  609. struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
  610. struct mlx5_uuar_info *uuari = &context->uuari;
  611. unsigned long command;
  612. unsigned long idx;
  613. phys_addr_t pfn;
  614. command = get_command(vma->vm_pgoff);
  615. switch (command) {
  616. case MLX5_IB_MMAP_REGULAR_PAGE:
  617. if (vma->vm_end - vma->vm_start != PAGE_SIZE)
  618. return -EINVAL;
  619. idx = get_index(vma->vm_pgoff);
  620. pfn = uar_index2pfn(dev, uuari->uars[idx].index);
  621. mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn 0x%llx\n", idx,
  622. (unsigned long long)pfn);
  623. if (idx >= uuari->num_uars)
  624. return -EINVAL;
  625. vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
  626. if (io_remap_pfn_range(vma, vma->vm_start, pfn,
  627. PAGE_SIZE, vma->vm_page_prot))
  628. return -EAGAIN;
  629. mlx5_ib_dbg(dev, "mapped WC at 0x%lx, PA 0x%llx\n",
  630. vma->vm_start,
  631. (unsigned long long)pfn << PAGE_SHIFT);
  632. break;
  633. case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
  634. return -ENOSYS;
  635. default:
  636. return -EINVAL;
  637. }
  638. return 0;
  639. }
  640. static int alloc_pa_mkey(struct mlx5_ib_dev *dev, u32 *key, u32 pdn)
  641. {
  642. struct mlx5_create_mkey_mbox_in *in;
  643. struct mlx5_mkey_seg *seg;
  644. struct mlx5_core_mr mr;
  645. int err;
  646. in = kzalloc(sizeof(*in), GFP_KERNEL);
  647. if (!in)
  648. return -ENOMEM;
  649. seg = &in->seg;
  650. seg->flags = MLX5_PERM_LOCAL_READ | MLX5_ACCESS_MODE_PA;
  651. seg->flags_pd = cpu_to_be32(pdn | MLX5_MKEY_LEN64);
  652. seg->qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
  653. seg->start_addr = 0;
  654. err = mlx5_core_create_mkey(&dev->mdev, &mr, in, sizeof(*in),
  655. NULL, NULL, NULL);
  656. if (err) {
  657. mlx5_ib_warn(dev, "failed to create mkey, %d\n", err);
  658. goto err_in;
  659. }
  660. kfree(in);
  661. *key = mr.key;
  662. return 0;
  663. err_in:
  664. kfree(in);
  665. return err;
  666. }
  667. static void free_pa_mkey(struct mlx5_ib_dev *dev, u32 key)
  668. {
  669. struct mlx5_core_mr mr;
  670. int err;
  671. memset(&mr, 0, sizeof(mr));
  672. mr.key = key;
  673. err = mlx5_core_destroy_mkey(&dev->mdev, &mr);
  674. if (err)
  675. mlx5_ib_warn(dev, "failed to destroy mkey 0x%x\n", key);
  676. }
  677. static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
  678. struct ib_ucontext *context,
  679. struct ib_udata *udata)
  680. {
  681. struct mlx5_ib_alloc_pd_resp resp;
  682. struct mlx5_ib_pd *pd;
  683. int err;
  684. pd = kmalloc(sizeof(*pd), GFP_KERNEL);
  685. if (!pd)
  686. return ERR_PTR(-ENOMEM);
  687. err = mlx5_core_alloc_pd(&to_mdev(ibdev)->mdev, &pd->pdn);
  688. if (err) {
  689. kfree(pd);
  690. return ERR_PTR(err);
  691. }
  692. if (context) {
  693. resp.pdn = pd->pdn;
  694. if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
  695. mlx5_core_dealloc_pd(&to_mdev(ibdev)->mdev, pd->pdn);
  696. kfree(pd);
  697. return ERR_PTR(-EFAULT);
  698. }
  699. } else {
  700. err = alloc_pa_mkey(to_mdev(ibdev), &pd->pa_lkey, pd->pdn);
  701. if (err) {
  702. mlx5_core_dealloc_pd(&to_mdev(ibdev)->mdev, pd->pdn);
  703. kfree(pd);
  704. return ERR_PTR(err);
  705. }
  706. }
  707. return &pd->ibpd;
  708. }
  709. static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
  710. {
  711. struct mlx5_ib_dev *mdev = to_mdev(pd->device);
  712. struct mlx5_ib_pd *mpd = to_mpd(pd);
  713. if (!pd->uobject)
  714. free_pa_mkey(mdev, mpd->pa_lkey);
  715. mlx5_core_dealloc_pd(&mdev->mdev, mpd->pdn);
  716. kfree(mpd);
  717. return 0;
  718. }
  719. static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
  720. {
  721. struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
  722. int err;
  723. err = mlx5_core_attach_mcg(&dev->mdev, gid, ibqp->qp_num);
  724. if (err)
  725. mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
  726. ibqp->qp_num, gid->raw);
  727. return err;
  728. }
  729. static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
  730. {
  731. struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
  732. int err;
  733. err = mlx5_core_detach_mcg(&dev->mdev, gid, ibqp->qp_num);
  734. if (err)
  735. mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
  736. ibqp->qp_num, gid->raw);
  737. return err;
  738. }
  739. static int init_node_data(struct mlx5_ib_dev *dev)
  740. {
  741. struct ib_smp *in_mad = NULL;
  742. struct ib_smp *out_mad = NULL;
  743. int err = -ENOMEM;
  744. in_mad = kzalloc(sizeof(*in_mad), GFP_KERNEL);
  745. out_mad = kmalloc(sizeof(*out_mad), GFP_KERNEL);
  746. if (!in_mad || !out_mad)
  747. goto out;
  748. init_query_mad(in_mad);
  749. in_mad->attr_id = IB_SMP_ATTR_NODE_DESC;
  750. err = mlx5_MAD_IFC(dev, 1, 1, 1, NULL, NULL, in_mad, out_mad);
  751. if (err)
  752. goto out;
  753. memcpy(dev->ib_dev.node_desc, out_mad->data, 64);
  754. in_mad->attr_id = IB_SMP_ATTR_NODE_INFO;
  755. err = mlx5_MAD_IFC(dev, 1, 1, 1, NULL, NULL, in_mad, out_mad);
  756. if (err)
  757. goto out;
  758. dev->mdev.rev_id = be32_to_cpup((__be32 *)(out_mad->data + 32));
  759. memcpy(&dev->ib_dev.node_guid, out_mad->data + 12, 8);
  760. out:
  761. kfree(in_mad);
  762. kfree(out_mad);
  763. return err;
  764. }
  765. static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr,
  766. char *buf)
  767. {
  768. struct mlx5_ib_dev *dev =
  769. container_of(device, struct mlx5_ib_dev, ib_dev.dev);
  770. return sprintf(buf, "%d\n", dev->mdev.priv.fw_pages);
  771. }
  772. static ssize_t show_reg_pages(struct device *device,
  773. struct device_attribute *attr, char *buf)
  774. {
  775. struct mlx5_ib_dev *dev =
  776. container_of(device, struct mlx5_ib_dev, ib_dev.dev);
  777. return sprintf(buf, "%d\n", dev->mdev.priv.reg_pages);
  778. }
  779. static ssize_t show_hca(struct device *device, struct device_attribute *attr,
  780. char *buf)
  781. {
  782. struct mlx5_ib_dev *dev =
  783. container_of(device, struct mlx5_ib_dev, ib_dev.dev);
  784. return sprintf(buf, "MT%d\n", dev->mdev.pdev->device);
  785. }
  786. static ssize_t show_fw_ver(struct device *device, struct device_attribute *attr,
  787. char *buf)
  788. {
  789. struct mlx5_ib_dev *dev =
  790. container_of(device, struct mlx5_ib_dev, ib_dev.dev);
  791. return sprintf(buf, "%d.%d.%d\n", fw_rev_maj(&dev->mdev),
  792. fw_rev_min(&dev->mdev), fw_rev_sub(&dev->mdev));
  793. }
  794. static ssize_t show_rev(struct device *device, struct device_attribute *attr,
  795. char *buf)
  796. {
  797. struct mlx5_ib_dev *dev =
  798. container_of(device, struct mlx5_ib_dev, ib_dev.dev);
  799. return sprintf(buf, "%x\n", dev->mdev.rev_id);
  800. }
  801. static ssize_t show_board(struct device *device, struct device_attribute *attr,
  802. char *buf)
  803. {
  804. struct mlx5_ib_dev *dev =
  805. container_of(device, struct mlx5_ib_dev, ib_dev.dev);
  806. return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
  807. dev->mdev.board_id);
  808. }
  809. static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
  810. static DEVICE_ATTR(fw_ver, S_IRUGO, show_fw_ver, NULL);
  811. static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
  812. static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
  813. static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL);
  814. static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL);
  815. static struct device_attribute *mlx5_class_attributes[] = {
  816. &dev_attr_hw_rev,
  817. &dev_attr_fw_ver,
  818. &dev_attr_hca_type,
  819. &dev_attr_board_id,
  820. &dev_attr_fw_pages,
  821. &dev_attr_reg_pages,
  822. };
  823. static void mlx5_ib_event(struct mlx5_core_dev *dev, enum mlx5_dev_event event,
  824. void *data)
  825. {
  826. struct mlx5_ib_dev *ibdev = container_of(dev, struct mlx5_ib_dev, mdev);
  827. struct ib_event ibev;
  828. u8 port = 0;
  829. switch (event) {
  830. case MLX5_DEV_EVENT_SYS_ERROR:
  831. ibdev->ib_active = false;
  832. ibev.event = IB_EVENT_DEVICE_FATAL;
  833. break;
  834. case MLX5_DEV_EVENT_PORT_UP:
  835. ibev.event = IB_EVENT_PORT_ACTIVE;
  836. port = *(u8 *)data;
  837. break;
  838. case MLX5_DEV_EVENT_PORT_DOWN:
  839. ibev.event = IB_EVENT_PORT_ERR;
  840. port = *(u8 *)data;
  841. break;
  842. case MLX5_DEV_EVENT_PORT_INITIALIZED:
  843. /* not used by ULPs */
  844. return;
  845. case MLX5_DEV_EVENT_LID_CHANGE:
  846. ibev.event = IB_EVENT_LID_CHANGE;
  847. port = *(u8 *)data;
  848. break;
  849. case MLX5_DEV_EVENT_PKEY_CHANGE:
  850. ibev.event = IB_EVENT_PKEY_CHANGE;
  851. port = *(u8 *)data;
  852. break;
  853. case MLX5_DEV_EVENT_GUID_CHANGE:
  854. ibev.event = IB_EVENT_GID_CHANGE;
  855. port = *(u8 *)data;
  856. break;
  857. case MLX5_DEV_EVENT_CLIENT_REREG:
  858. ibev.event = IB_EVENT_CLIENT_REREGISTER;
  859. port = *(u8 *)data;
  860. break;
  861. }
  862. ibev.device = &ibdev->ib_dev;
  863. ibev.element.port_num = port;
  864. if (port < 1 || port > ibdev->num_ports) {
  865. mlx5_ib_warn(ibdev, "warning: event on port %d\n", port);
  866. return;
  867. }
  868. if (ibdev->ib_active)
  869. ib_dispatch_event(&ibev);
  870. }
  871. static void get_ext_port_caps(struct mlx5_ib_dev *dev)
  872. {
  873. int port;
  874. for (port = 1; port <= dev->mdev.caps.num_ports; port++)
  875. mlx5_query_ext_port_caps(dev, port);
  876. }
  877. static int get_port_caps(struct mlx5_ib_dev *dev)
  878. {
  879. struct ib_device_attr *dprops = NULL;
  880. struct ib_port_attr *pprops = NULL;
  881. int err = 0;
  882. int port;
  883. pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
  884. if (!pprops)
  885. goto out;
  886. dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
  887. if (!dprops)
  888. goto out;
  889. err = mlx5_ib_query_device(&dev->ib_dev, dprops);
  890. if (err) {
  891. mlx5_ib_warn(dev, "query_device failed %d\n", err);
  892. goto out;
  893. }
  894. for (port = 1; port <= dev->mdev.caps.num_ports; port++) {
  895. err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
  896. if (err) {
  897. mlx5_ib_warn(dev, "query_port %d failed %d\n", port, err);
  898. break;
  899. }
  900. dev->mdev.caps.port[port - 1].pkey_table_len = dprops->max_pkeys;
  901. dev->mdev.caps.port[port - 1].gid_table_len = pprops->gid_tbl_len;
  902. mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n",
  903. dprops->max_pkeys, pprops->gid_tbl_len);
  904. }
  905. out:
  906. kfree(pprops);
  907. kfree(dprops);
  908. return err;
  909. }
  910. static void destroy_umrc_res(struct mlx5_ib_dev *dev)
  911. {
  912. int err;
  913. err = mlx5_mr_cache_cleanup(dev);
  914. if (err)
  915. mlx5_ib_warn(dev, "mr cache cleanup failed\n");
  916. mlx5_ib_destroy_qp(dev->umrc.qp);
  917. ib_destroy_cq(dev->umrc.cq);
  918. ib_dereg_mr(dev->umrc.mr);
  919. ib_dealloc_pd(dev->umrc.pd);
  920. }
  921. enum {
  922. MAX_UMR_WR = 128,
  923. };
  924. static int create_umr_res(struct mlx5_ib_dev *dev)
  925. {
  926. struct ib_qp_init_attr *init_attr = NULL;
  927. struct ib_qp_attr *attr = NULL;
  928. struct ib_pd *pd;
  929. struct ib_cq *cq;
  930. struct ib_qp *qp;
  931. struct ib_mr *mr;
  932. int ret;
  933. attr = kzalloc(sizeof(*attr), GFP_KERNEL);
  934. init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
  935. if (!attr || !init_attr) {
  936. ret = -ENOMEM;
  937. goto error_0;
  938. }
  939. pd = ib_alloc_pd(&dev->ib_dev);
  940. if (IS_ERR(pd)) {
  941. mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
  942. ret = PTR_ERR(pd);
  943. goto error_0;
  944. }
  945. mr = ib_get_dma_mr(pd, IB_ACCESS_LOCAL_WRITE);
  946. if (IS_ERR(mr)) {
  947. mlx5_ib_dbg(dev, "Couldn't create DMA MR for sync UMR QP\n");
  948. ret = PTR_ERR(mr);
  949. goto error_1;
  950. }
  951. cq = ib_create_cq(&dev->ib_dev, mlx5_umr_cq_handler, NULL, NULL, 128,
  952. 0);
  953. if (IS_ERR(cq)) {
  954. mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
  955. ret = PTR_ERR(cq);
  956. goto error_2;
  957. }
  958. ib_req_notify_cq(cq, IB_CQ_NEXT_COMP);
  959. init_attr->send_cq = cq;
  960. init_attr->recv_cq = cq;
  961. init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
  962. init_attr->cap.max_send_wr = MAX_UMR_WR;
  963. init_attr->cap.max_send_sge = 1;
  964. init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
  965. init_attr->port_num = 1;
  966. qp = mlx5_ib_create_qp(pd, init_attr, NULL);
  967. if (IS_ERR(qp)) {
  968. mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
  969. ret = PTR_ERR(qp);
  970. goto error_3;
  971. }
  972. qp->device = &dev->ib_dev;
  973. qp->real_qp = qp;
  974. qp->uobject = NULL;
  975. qp->qp_type = MLX5_IB_QPT_REG_UMR;
  976. attr->qp_state = IB_QPS_INIT;
  977. attr->port_num = 1;
  978. ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
  979. IB_QP_PORT, NULL);
  980. if (ret) {
  981. mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
  982. goto error_4;
  983. }
  984. memset(attr, 0, sizeof(*attr));
  985. attr->qp_state = IB_QPS_RTR;
  986. attr->path_mtu = IB_MTU_256;
  987. ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
  988. if (ret) {
  989. mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
  990. goto error_4;
  991. }
  992. memset(attr, 0, sizeof(*attr));
  993. attr->qp_state = IB_QPS_RTS;
  994. ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
  995. if (ret) {
  996. mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
  997. goto error_4;
  998. }
  999. dev->umrc.qp = qp;
  1000. dev->umrc.cq = cq;
  1001. dev->umrc.mr = mr;
  1002. dev->umrc.pd = pd;
  1003. sema_init(&dev->umrc.sem, MAX_UMR_WR);
  1004. ret = mlx5_mr_cache_init(dev);
  1005. if (ret) {
  1006. mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
  1007. goto error_4;
  1008. }
  1009. kfree(attr);
  1010. kfree(init_attr);
  1011. return 0;
  1012. error_4:
  1013. mlx5_ib_destroy_qp(qp);
  1014. error_3:
  1015. ib_destroy_cq(cq);
  1016. error_2:
  1017. ib_dereg_mr(mr);
  1018. error_1:
  1019. ib_dealloc_pd(pd);
  1020. error_0:
  1021. kfree(attr);
  1022. kfree(init_attr);
  1023. return ret;
  1024. }
  1025. static int create_dev_resources(struct mlx5_ib_resources *devr)
  1026. {
  1027. struct ib_srq_init_attr attr;
  1028. struct mlx5_ib_dev *dev;
  1029. int ret = 0;
  1030. dev = container_of(devr, struct mlx5_ib_dev, devr);
  1031. devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
  1032. if (IS_ERR(devr->p0)) {
  1033. ret = PTR_ERR(devr->p0);
  1034. goto error0;
  1035. }
  1036. devr->p0->device = &dev->ib_dev;
  1037. devr->p0->uobject = NULL;
  1038. atomic_set(&devr->p0->usecnt, 0);
  1039. devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, 1, 0, NULL, NULL);
  1040. if (IS_ERR(devr->c0)) {
  1041. ret = PTR_ERR(devr->c0);
  1042. goto error1;
  1043. }
  1044. devr->c0->device = &dev->ib_dev;
  1045. devr->c0->uobject = NULL;
  1046. devr->c0->comp_handler = NULL;
  1047. devr->c0->event_handler = NULL;
  1048. devr->c0->cq_context = NULL;
  1049. atomic_set(&devr->c0->usecnt, 0);
  1050. devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
  1051. if (IS_ERR(devr->x0)) {
  1052. ret = PTR_ERR(devr->x0);
  1053. goto error2;
  1054. }
  1055. devr->x0->device = &dev->ib_dev;
  1056. devr->x0->inode = NULL;
  1057. atomic_set(&devr->x0->usecnt, 0);
  1058. mutex_init(&devr->x0->tgt_qp_mutex);
  1059. INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
  1060. devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
  1061. if (IS_ERR(devr->x1)) {
  1062. ret = PTR_ERR(devr->x1);
  1063. goto error3;
  1064. }
  1065. devr->x1->device = &dev->ib_dev;
  1066. devr->x1->inode = NULL;
  1067. atomic_set(&devr->x1->usecnt, 0);
  1068. mutex_init(&devr->x1->tgt_qp_mutex);
  1069. INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
  1070. memset(&attr, 0, sizeof(attr));
  1071. attr.attr.max_sge = 1;
  1072. attr.attr.max_wr = 1;
  1073. attr.srq_type = IB_SRQT_XRC;
  1074. attr.ext.xrc.cq = devr->c0;
  1075. attr.ext.xrc.xrcd = devr->x0;
  1076. devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
  1077. if (IS_ERR(devr->s0)) {
  1078. ret = PTR_ERR(devr->s0);
  1079. goto error4;
  1080. }
  1081. devr->s0->device = &dev->ib_dev;
  1082. devr->s0->pd = devr->p0;
  1083. devr->s0->uobject = NULL;
  1084. devr->s0->event_handler = NULL;
  1085. devr->s0->srq_context = NULL;
  1086. devr->s0->srq_type = IB_SRQT_XRC;
  1087. devr->s0->ext.xrc.xrcd = devr->x0;
  1088. devr->s0->ext.xrc.cq = devr->c0;
  1089. atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
  1090. atomic_inc(&devr->s0->ext.xrc.cq->usecnt);
  1091. atomic_inc(&devr->p0->usecnt);
  1092. atomic_set(&devr->s0->usecnt, 0);
  1093. return 0;
  1094. error4:
  1095. mlx5_ib_dealloc_xrcd(devr->x1);
  1096. error3:
  1097. mlx5_ib_dealloc_xrcd(devr->x0);
  1098. error2:
  1099. mlx5_ib_destroy_cq(devr->c0);
  1100. error1:
  1101. mlx5_ib_dealloc_pd(devr->p0);
  1102. error0:
  1103. return ret;
  1104. }
  1105. static void destroy_dev_resources(struct mlx5_ib_resources *devr)
  1106. {
  1107. mlx5_ib_destroy_srq(devr->s0);
  1108. mlx5_ib_dealloc_xrcd(devr->x0);
  1109. mlx5_ib_dealloc_xrcd(devr->x1);
  1110. mlx5_ib_destroy_cq(devr->c0);
  1111. mlx5_ib_dealloc_pd(devr->p0);
  1112. }
  1113. static int init_one(struct pci_dev *pdev,
  1114. const struct pci_device_id *id)
  1115. {
  1116. struct mlx5_core_dev *mdev;
  1117. struct mlx5_ib_dev *dev;
  1118. int err;
  1119. int i;
  1120. printk_once(KERN_INFO "%s", mlx5_version);
  1121. dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
  1122. if (!dev)
  1123. return -ENOMEM;
  1124. mdev = &dev->mdev;
  1125. mdev->event = mlx5_ib_event;
  1126. if (prof_sel >= ARRAY_SIZE(profile)) {
  1127. pr_warn("selected pofile out of range, selceting default\n");
  1128. prof_sel = 0;
  1129. }
  1130. mdev->profile = &profile[prof_sel];
  1131. err = mlx5_dev_init(mdev, pdev);
  1132. if (err)
  1133. goto err_free;
  1134. err = get_port_caps(dev);
  1135. if (err)
  1136. goto err_cleanup;
  1137. get_ext_port_caps(dev);
  1138. err = alloc_comp_eqs(dev);
  1139. if (err)
  1140. goto err_cleanup;
  1141. MLX5_INIT_DOORBELL_LOCK(&dev->uar_lock);
  1142. strlcpy(dev->ib_dev.name, "mlx5_%d", IB_DEVICE_NAME_MAX);
  1143. dev->ib_dev.owner = THIS_MODULE;
  1144. dev->ib_dev.node_type = RDMA_NODE_IB_CA;
  1145. dev->ib_dev.local_dma_lkey = mdev->caps.reserved_lkey;
  1146. dev->num_ports = mdev->caps.num_ports;
  1147. dev->ib_dev.phys_port_cnt = dev->num_ports;
  1148. dev->ib_dev.num_comp_vectors = dev->num_comp_vectors;
  1149. dev->ib_dev.dma_device = &mdev->pdev->dev;
  1150. dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION;
  1151. dev->ib_dev.uverbs_cmd_mask =
  1152. (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
  1153. (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
  1154. (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
  1155. (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
  1156. (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
  1157. (1ull << IB_USER_VERBS_CMD_REG_MR) |
  1158. (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
  1159. (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
  1160. (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
  1161. (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
  1162. (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
  1163. (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
  1164. (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
  1165. (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
  1166. (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
  1167. (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
  1168. (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
  1169. (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
  1170. (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
  1171. (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
  1172. (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
  1173. (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
  1174. (1ull << IB_USER_VERBS_CMD_OPEN_QP);
  1175. dev->ib_dev.query_device = mlx5_ib_query_device;
  1176. dev->ib_dev.query_port = mlx5_ib_query_port;
  1177. dev->ib_dev.query_gid = mlx5_ib_query_gid;
  1178. dev->ib_dev.query_pkey = mlx5_ib_query_pkey;
  1179. dev->ib_dev.modify_device = mlx5_ib_modify_device;
  1180. dev->ib_dev.modify_port = mlx5_ib_modify_port;
  1181. dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext;
  1182. dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext;
  1183. dev->ib_dev.mmap = mlx5_ib_mmap;
  1184. dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd;
  1185. dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd;
  1186. dev->ib_dev.create_ah = mlx5_ib_create_ah;
  1187. dev->ib_dev.query_ah = mlx5_ib_query_ah;
  1188. dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah;
  1189. dev->ib_dev.create_srq = mlx5_ib_create_srq;
  1190. dev->ib_dev.modify_srq = mlx5_ib_modify_srq;
  1191. dev->ib_dev.query_srq = mlx5_ib_query_srq;
  1192. dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq;
  1193. dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv;
  1194. dev->ib_dev.create_qp = mlx5_ib_create_qp;
  1195. dev->ib_dev.modify_qp = mlx5_ib_modify_qp;
  1196. dev->ib_dev.query_qp = mlx5_ib_query_qp;
  1197. dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp;
  1198. dev->ib_dev.post_send = mlx5_ib_post_send;
  1199. dev->ib_dev.post_recv = mlx5_ib_post_recv;
  1200. dev->ib_dev.create_cq = mlx5_ib_create_cq;
  1201. dev->ib_dev.modify_cq = mlx5_ib_modify_cq;
  1202. dev->ib_dev.resize_cq = mlx5_ib_resize_cq;
  1203. dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq;
  1204. dev->ib_dev.poll_cq = mlx5_ib_poll_cq;
  1205. dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq;
  1206. dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr;
  1207. dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr;
  1208. dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr;
  1209. dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach;
  1210. dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach;
  1211. dev->ib_dev.process_mad = mlx5_ib_process_mad;
  1212. dev->ib_dev.alloc_fast_reg_mr = mlx5_ib_alloc_fast_reg_mr;
  1213. dev->ib_dev.alloc_fast_reg_page_list = mlx5_ib_alloc_fast_reg_page_list;
  1214. dev->ib_dev.free_fast_reg_page_list = mlx5_ib_free_fast_reg_page_list;
  1215. if (mdev->caps.flags & MLX5_DEV_CAP_FLAG_XRC) {
  1216. dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd;
  1217. dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd;
  1218. dev->ib_dev.uverbs_cmd_mask |=
  1219. (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
  1220. (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
  1221. }
  1222. err = init_node_data(dev);
  1223. if (err)
  1224. goto err_eqs;
  1225. mutex_init(&dev->cap_mask_mutex);
  1226. spin_lock_init(&dev->mr_lock);
  1227. err = create_dev_resources(&dev->devr);
  1228. if (err)
  1229. goto err_eqs;
  1230. err = ib_register_device(&dev->ib_dev, NULL);
  1231. if (err)
  1232. goto err_rsrc;
  1233. err = create_umr_res(dev);
  1234. if (err)
  1235. goto err_dev;
  1236. for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) {
  1237. err = device_create_file(&dev->ib_dev.dev,
  1238. mlx5_class_attributes[i]);
  1239. if (err)
  1240. goto err_umrc;
  1241. }
  1242. dev->ib_active = true;
  1243. return 0;
  1244. err_umrc:
  1245. destroy_umrc_res(dev);
  1246. err_dev:
  1247. ib_unregister_device(&dev->ib_dev);
  1248. err_rsrc:
  1249. destroy_dev_resources(&dev->devr);
  1250. err_eqs:
  1251. free_comp_eqs(dev);
  1252. err_cleanup:
  1253. mlx5_dev_cleanup(mdev);
  1254. err_free:
  1255. ib_dealloc_device((struct ib_device *)dev);
  1256. return err;
  1257. }
  1258. static void remove_one(struct pci_dev *pdev)
  1259. {
  1260. struct mlx5_ib_dev *dev = mlx5_pci2ibdev(pdev);
  1261. destroy_umrc_res(dev);
  1262. ib_unregister_device(&dev->ib_dev);
  1263. destroy_dev_resources(&dev->devr);
  1264. free_comp_eqs(dev);
  1265. mlx5_dev_cleanup(&dev->mdev);
  1266. ib_dealloc_device(&dev->ib_dev);
  1267. }
  1268. static DEFINE_PCI_DEVICE_TABLE(mlx5_ib_pci_table) = {
  1269. { PCI_VDEVICE(MELLANOX, 4113) }, /* MT4113 Connect-IB */
  1270. { 0, }
  1271. };
  1272. MODULE_DEVICE_TABLE(pci, mlx5_ib_pci_table);
  1273. static struct pci_driver mlx5_ib_driver = {
  1274. .name = DRIVER_NAME,
  1275. .id_table = mlx5_ib_pci_table,
  1276. .probe = init_one,
  1277. .remove = remove_one
  1278. };
  1279. static int __init mlx5_ib_init(void)
  1280. {
  1281. return pci_register_driver(&mlx5_ib_driver);
  1282. }
  1283. static void __exit mlx5_ib_cleanup(void)
  1284. {
  1285. pci_unregister_driver(&mlx5_ib_driver);
  1286. }
  1287. module_init(mlx5_ib_init);
  1288. module_exit(mlx5_ib_cleanup);