vmwgfx_execbuf.c 78 KB

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  1. /**************************************************************************
  2. *
  3. * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
  4. * All Rights Reserved.
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the
  8. * "Software"), to deal in the Software without restriction, including
  9. * without limitation the rights to use, copy, modify, merge, publish,
  10. * distribute, sub license, and/or sell copies of the Software, and to
  11. * permit persons to whom the Software is furnished to do so, subject to
  12. * the following conditions:
  13. *
  14. * The above copyright notice and this permission notice (including the
  15. * next paragraph) shall be included in all copies or substantial portions
  16. * of the Software.
  17. *
  18. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20. * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  21. * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  22. * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  23. * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  24. * USE OR OTHER DEALINGS IN THE SOFTWARE.
  25. *
  26. **************************************************************************/
  27. #include "vmwgfx_drv.h"
  28. #include "vmwgfx_reg.h"
  29. #include <drm/ttm/ttm_bo_api.h>
  30. #include <drm/ttm/ttm_placement.h>
  31. #define VMW_RES_HT_ORDER 12
  32. /**
  33. * struct vmw_resource_relocation - Relocation info for resources
  34. *
  35. * @head: List head for the software context's relocation list.
  36. * @res: Non-ref-counted pointer to the resource.
  37. * @offset: Offset of 4 byte entries into the command buffer where the
  38. * id that needs fixup is located.
  39. */
  40. struct vmw_resource_relocation {
  41. struct list_head head;
  42. const struct vmw_resource *res;
  43. unsigned long offset;
  44. };
  45. /**
  46. * struct vmw_resource_val_node - Validation info for resources
  47. *
  48. * @head: List head for the software context's resource list.
  49. * @hash: Hash entry for quick resouce to val_node lookup.
  50. * @res: Ref-counted pointer to the resource.
  51. * @switch_backup: Boolean whether to switch backup buffer on unreserve.
  52. * @new_backup: Refcounted pointer to the new backup buffer.
  53. * @staged_bindings: If @res is a context, tracks bindings set up during
  54. * the command batch. Otherwise NULL.
  55. * @new_backup_offset: New backup buffer offset if @new_backup is non-NUll.
  56. * @first_usage: Set to true the first time the resource is referenced in
  57. * the command stream.
  58. * @no_buffer_needed: Resources do not need to allocate buffer backup on
  59. * reservation. The command stream will provide one.
  60. */
  61. struct vmw_resource_val_node {
  62. struct list_head head;
  63. struct drm_hash_item hash;
  64. struct vmw_resource *res;
  65. struct vmw_dma_buffer *new_backup;
  66. struct vmw_ctx_binding_state *staged_bindings;
  67. unsigned long new_backup_offset;
  68. bool first_usage;
  69. bool no_buffer_needed;
  70. };
  71. /**
  72. * struct vmw_cmd_entry - Describe a command for the verifier
  73. *
  74. * @user_allow: Whether allowed from the execbuf ioctl.
  75. * @gb_disable: Whether disabled if guest-backed objects are available.
  76. * @gb_enable: Whether enabled iff guest-backed objects are available.
  77. */
  78. struct vmw_cmd_entry {
  79. int (*func) (struct vmw_private *, struct vmw_sw_context *,
  80. SVGA3dCmdHeader *);
  81. bool user_allow;
  82. bool gb_disable;
  83. bool gb_enable;
  84. };
  85. #define VMW_CMD_DEF(_cmd, _func, _user_allow, _gb_disable, _gb_enable) \
  86. [(_cmd) - SVGA_3D_CMD_BASE] = {(_func), (_user_allow),\
  87. (_gb_disable), (_gb_enable)}
  88. /**
  89. * vmw_resource_unreserve - unreserve resources previously reserved for
  90. * command submission.
  91. *
  92. * @list_head: list of resources to unreserve.
  93. * @backoff: Whether command submission failed.
  94. */
  95. static void vmw_resource_list_unreserve(struct list_head *list,
  96. bool backoff)
  97. {
  98. struct vmw_resource_val_node *val;
  99. list_for_each_entry(val, list, head) {
  100. struct vmw_resource *res = val->res;
  101. struct vmw_dma_buffer *new_backup =
  102. backoff ? NULL : val->new_backup;
  103. /*
  104. * Transfer staged context bindings to the
  105. * persistent context binding tracker.
  106. */
  107. if (unlikely(val->staged_bindings)) {
  108. if (!backoff) {
  109. vmw_context_binding_state_transfer
  110. (val->res, val->staged_bindings);
  111. }
  112. kfree(val->staged_bindings);
  113. val->staged_bindings = NULL;
  114. }
  115. vmw_resource_unreserve(res, new_backup,
  116. val->new_backup_offset);
  117. vmw_dmabuf_unreference(&val->new_backup);
  118. }
  119. }
  120. /**
  121. * vmw_resource_val_add - Add a resource to the software context's
  122. * resource list if it's not already on it.
  123. *
  124. * @sw_context: Pointer to the software context.
  125. * @res: Pointer to the resource.
  126. * @p_node On successful return points to a valid pointer to a
  127. * struct vmw_resource_val_node, if non-NULL on entry.
  128. */
  129. static int vmw_resource_val_add(struct vmw_sw_context *sw_context,
  130. struct vmw_resource *res,
  131. struct vmw_resource_val_node **p_node)
  132. {
  133. struct vmw_resource_val_node *node;
  134. struct drm_hash_item *hash;
  135. int ret;
  136. if (likely(drm_ht_find_item(&sw_context->res_ht, (unsigned long) res,
  137. &hash) == 0)) {
  138. node = container_of(hash, struct vmw_resource_val_node, hash);
  139. node->first_usage = false;
  140. if (unlikely(p_node != NULL))
  141. *p_node = node;
  142. return 0;
  143. }
  144. node = kzalloc(sizeof(*node), GFP_KERNEL);
  145. if (unlikely(node == NULL)) {
  146. DRM_ERROR("Failed to allocate a resource validation "
  147. "entry.\n");
  148. return -ENOMEM;
  149. }
  150. node->hash.key = (unsigned long) res;
  151. ret = drm_ht_insert_item(&sw_context->res_ht, &node->hash);
  152. if (unlikely(ret != 0)) {
  153. DRM_ERROR("Failed to initialize a resource validation "
  154. "entry.\n");
  155. kfree(node);
  156. return ret;
  157. }
  158. list_add_tail(&node->head, &sw_context->resource_list);
  159. node->res = vmw_resource_reference(res);
  160. node->first_usage = true;
  161. if (unlikely(p_node != NULL))
  162. *p_node = node;
  163. return 0;
  164. }
  165. /**
  166. * vmw_resource_context_res_add - Put resources previously bound to a context on
  167. * the validation list
  168. *
  169. * @dev_priv: Pointer to a device private structure
  170. * @sw_context: Pointer to a software context used for this command submission
  171. * @ctx: Pointer to the context resource
  172. *
  173. * This function puts all resources that were previously bound to @ctx on
  174. * the resource validation list. This is part of the context state reemission
  175. */
  176. static int vmw_resource_context_res_add(struct vmw_private *dev_priv,
  177. struct vmw_sw_context *sw_context,
  178. struct vmw_resource *ctx)
  179. {
  180. struct list_head *binding_list;
  181. struct vmw_ctx_binding *entry;
  182. int ret = 0;
  183. struct vmw_resource *res;
  184. mutex_lock(&dev_priv->binding_mutex);
  185. binding_list = vmw_context_binding_list(ctx);
  186. list_for_each_entry(entry, binding_list, ctx_list) {
  187. res = vmw_resource_reference_unless_doomed(entry->bi.res);
  188. if (unlikely(res == NULL))
  189. continue;
  190. ret = vmw_resource_val_add(sw_context, entry->bi.res, NULL);
  191. vmw_resource_unreference(&res);
  192. if (unlikely(ret != 0))
  193. break;
  194. }
  195. mutex_unlock(&dev_priv->binding_mutex);
  196. return ret;
  197. }
  198. /**
  199. * vmw_resource_relocation_add - Add a relocation to the relocation list
  200. *
  201. * @list: Pointer to head of relocation list.
  202. * @res: The resource.
  203. * @offset: Offset into the command buffer currently being parsed where the
  204. * id that needs fixup is located. Granularity is 4 bytes.
  205. */
  206. static int vmw_resource_relocation_add(struct list_head *list,
  207. const struct vmw_resource *res,
  208. unsigned long offset)
  209. {
  210. struct vmw_resource_relocation *rel;
  211. rel = kmalloc(sizeof(*rel), GFP_KERNEL);
  212. if (unlikely(rel == NULL)) {
  213. DRM_ERROR("Failed to allocate a resource relocation.\n");
  214. return -ENOMEM;
  215. }
  216. rel->res = res;
  217. rel->offset = offset;
  218. list_add_tail(&rel->head, list);
  219. return 0;
  220. }
  221. /**
  222. * vmw_resource_relocations_free - Free all relocations on a list
  223. *
  224. * @list: Pointer to the head of the relocation list.
  225. */
  226. static void vmw_resource_relocations_free(struct list_head *list)
  227. {
  228. struct vmw_resource_relocation *rel, *n;
  229. list_for_each_entry_safe(rel, n, list, head) {
  230. list_del(&rel->head);
  231. kfree(rel);
  232. }
  233. }
  234. /**
  235. * vmw_resource_relocations_apply - Apply all relocations on a list
  236. *
  237. * @cb: Pointer to the start of the command buffer bein patch. This need
  238. * not be the same buffer as the one being parsed when the relocation
  239. * list was built, but the contents must be the same modulo the
  240. * resource ids.
  241. * @list: Pointer to the head of the relocation list.
  242. */
  243. static void vmw_resource_relocations_apply(uint32_t *cb,
  244. struct list_head *list)
  245. {
  246. struct vmw_resource_relocation *rel;
  247. list_for_each_entry(rel, list, head) {
  248. if (likely(rel->res != NULL))
  249. cb[rel->offset] = rel->res->id;
  250. else
  251. cb[rel->offset] = SVGA_3D_CMD_NOP;
  252. }
  253. }
  254. static int vmw_cmd_invalid(struct vmw_private *dev_priv,
  255. struct vmw_sw_context *sw_context,
  256. SVGA3dCmdHeader *header)
  257. {
  258. return capable(CAP_SYS_ADMIN) ? : -EINVAL;
  259. }
  260. static int vmw_cmd_ok(struct vmw_private *dev_priv,
  261. struct vmw_sw_context *sw_context,
  262. SVGA3dCmdHeader *header)
  263. {
  264. return 0;
  265. }
  266. /**
  267. * vmw_bo_to_validate_list - add a bo to a validate list
  268. *
  269. * @sw_context: The software context used for this command submission batch.
  270. * @bo: The buffer object to add.
  271. * @validate_as_mob: Validate this buffer as a MOB.
  272. * @p_val_node: If non-NULL Will be updated with the validate node number
  273. * on return.
  274. *
  275. * Returns -EINVAL if the limit of number of buffer objects per command
  276. * submission is reached.
  277. */
  278. static int vmw_bo_to_validate_list(struct vmw_sw_context *sw_context,
  279. struct ttm_buffer_object *bo,
  280. bool validate_as_mob,
  281. uint32_t *p_val_node)
  282. {
  283. uint32_t val_node;
  284. struct vmw_validate_buffer *vval_buf;
  285. struct ttm_validate_buffer *val_buf;
  286. struct drm_hash_item *hash;
  287. int ret;
  288. if (likely(drm_ht_find_item(&sw_context->res_ht, (unsigned long) bo,
  289. &hash) == 0)) {
  290. vval_buf = container_of(hash, struct vmw_validate_buffer,
  291. hash);
  292. if (unlikely(vval_buf->validate_as_mob != validate_as_mob)) {
  293. DRM_ERROR("Inconsistent buffer usage.\n");
  294. return -EINVAL;
  295. }
  296. val_buf = &vval_buf->base;
  297. val_node = vval_buf - sw_context->val_bufs;
  298. } else {
  299. val_node = sw_context->cur_val_buf;
  300. if (unlikely(val_node >= VMWGFX_MAX_VALIDATIONS)) {
  301. DRM_ERROR("Max number of DMA buffers per submission "
  302. "exceeded.\n");
  303. return -EINVAL;
  304. }
  305. vval_buf = &sw_context->val_bufs[val_node];
  306. vval_buf->hash.key = (unsigned long) bo;
  307. ret = drm_ht_insert_item(&sw_context->res_ht, &vval_buf->hash);
  308. if (unlikely(ret != 0)) {
  309. DRM_ERROR("Failed to initialize a buffer validation "
  310. "entry.\n");
  311. return ret;
  312. }
  313. ++sw_context->cur_val_buf;
  314. val_buf = &vval_buf->base;
  315. val_buf->bo = ttm_bo_reference(bo);
  316. val_buf->reserved = false;
  317. list_add_tail(&val_buf->head, &sw_context->validate_nodes);
  318. vval_buf->validate_as_mob = validate_as_mob;
  319. }
  320. sw_context->fence_flags |= DRM_VMW_FENCE_FLAG_EXEC;
  321. if (p_val_node)
  322. *p_val_node = val_node;
  323. return 0;
  324. }
  325. /**
  326. * vmw_resources_reserve - Reserve all resources on the sw_context's
  327. * resource list.
  328. *
  329. * @sw_context: Pointer to the software context.
  330. *
  331. * Note that since vmware's command submission currently is protected by
  332. * the cmdbuf mutex, no fancy deadlock avoidance is required for resources,
  333. * since only a single thread at once will attempt this.
  334. */
  335. static int vmw_resources_reserve(struct vmw_sw_context *sw_context)
  336. {
  337. struct vmw_resource_val_node *val;
  338. int ret;
  339. list_for_each_entry(val, &sw_context->resource_list, head) {
  340. struct vmw_resource *res = val->res;
  341. ret = vmw_resource_reserve(res, val->no_buffer_needed);
  342. if (unlikely(ret != 0))
  343. return ret;
  344. if (res->backup) {
  345. struct ttm_buffer_object *bo = &res->backup->base;
  346. ret = vmw_bo_to_validate_list
  347. (sw_context, bo,
  348. vmw_resource_needs_backup(res), NULL);
  349. if (unlikely(ret != 0))
  350. return ret;
  351. }
  352. }
  353. return 0;
  354. }
  355. /**
  356. * vmw_resources_validate - Validate all resources on the sw_context's
  357. * resource list.
  358. *
  359. * @sw_context: Pointer to the software context.
  360. *
  361. * Before this function is called, all resource backup buffers must have
  362. * been validated.
  363. */
  364. static int vmw_resources_validate(struct vmw_sw_context *sw_context)
  365. {
  366. struct vmw_resource_val_node *val;
  367. int ret;
  368. list_for_each_entry(val, &sw_context->resource_list, head) {
  369. struct vmw_resource *res = val->res;
  370. ret = vmw_resource_validate(res);
  371. if (unlikely(ret != 0)) {
  372. if (ret != -ERESTARTSYS)
  373. DRM_ERROR("Failed to validate resource.\n");
  374. return ret;
  375. }
  376. }
  377. return 0;
  378. }
  379. /**
  380. * vmw_cmd_compat_res_check - Check that a resource is present and if so, put it
  381. * on the resource validate list unless it's already there.
  382. *
  383. * @dev_priv: Pointer to a device private structure.
  384. * @sw_context: Pointer to the software context.
  385. * @res_type: Resource type.
  386. * @converter: User-space visisble type specific information.
  387. * @id: user-space resource id handle.
  388. * @id_loc: Pointer to the location in the command buffer currently being
  389. * parsed from where the user-space resource id handle is located.
  390. * @p_val: Pointer to pointer to resource validalidation node. Populated
  391. * on exit.
  392. */
  393. static int
  394. vmw_cmd_compat_res_check(struct vmw_private *dev_priv,
  395. struct vmw_sw_context *sw_context,
  396. enum vmw_res_type res_type,
  397. const struct vmw_user_resource_conv *converter,
  398. uint32_t id,
  399. uint32_t *id_loc,
  400. struct vmw_resource_val_node **p_val)
  401. {
  402. struct vmw_res_cache_entry *rcache =
  403. &sw_context->res_cache[res_type];
  404. struct vmw_resource *res;
  405. struct vmw_resource_val_node *node;
  406. int ret;
  407. if (id == SVGA3D_INVALID_ID) {
  408. if (p_val)
  409. *p_val = NULL;
  410. if (res_type == vmw_res_context) {
  411. DRM_ERROR("Illegal context invalid id.\n");
  412. return -EINVAL;
  413. }
  414. return 0;
  415. }
  416. /*
  417. * Fastpath in case of repeated commands referencing the same
  418. * resource
  419. */
  420. if (likely(rcache->valid && id == rcache->handle)) {
  421. const struct vmw_resource *res = rcache->res;
  422. rcache->node->first_usage = false;
  423. if (p_val)
  424. *p_val = rcache->node;
  425. return vmw_resource_relocation_add
  426. (&sw_context->res_relocations, res,
  427. id_loc - sw_context->buf_start);
  428. }
  429. ret = vmw_user_resource_lookup_handle(dev_priv,
  430. sw_context->fp->tfile,
  431. id,
  432. converter,
  433. &res);
  434. if (unlikely(ret != 0)) {
  435. DRM_ERROR("Could not find or use resource 0x%08x.\n",
  436. (unsigned) id);
  437. dump_stack();
  438. return ret;
  439. }
  440. rcache->valid = true;
  441. rcache->res = res;
  442. rcache->handle = id;
  443. ret = vmw_resource_relocation_add(&sw_context->res_relocations,
  444. res,
  445. id_loc - sw_context->buf_start);
  446. if (unlikely(ret != 0))
  447. goto out_no_reloc;
  448. ret = vmw_resource_val_add(sw_context, res, &node);
  449. if (unlikely(ret != 0))
  450. goto out_no_reloc;
  451. rcache->node = node;
  452. if (p_val)
  453. *p_val = node;
  454. if (dev_priv->has_mob && node->first_usage &&
  455. res_type == vmw_res_context) {
  456. ret = vmw_resource_context_res_add(dev_priv, sw_context, res);
  457. if (unlikely(ret != 0))
  458. goto out_no_reloc;
  459. node->staged_bindings =
  460. kzalloc(sizeof(*node->staged_bindings), GFP_KERNEL);
  461. if (node->staged_bindings == NULL) {
  462. DRM_ERROR("Failed to allocate context binding "
  463. "information.\n");
  464. goto out_no_reloc;
  465. }
  466. INIT_LIST_HEAD(&node->staged_bindings->list);
  467. }
  468. vmw_resource_unreference(&res);
  469. return 0;
  470. out_no_reloc:
  471. BUG_ON(sw_context->error_resource != NULL);
  472. sw_context->error_resource = res;
  473. return ret;
  474. }
  475. /**
  476. * vmw_cmd_res_check - Check that a resource is present and if so, put it
  477. * on the resource validate list unless it's already there.
  478. *
  479. * @dev_priv: Pointer to a device private structure.
  480. * @sw_context: Pointer to the software context.
  481. * @res_type: Resource type.
  482. * @converter: User-space visisble type specific information.
  483. * @id_loc: Pointer to the location in the command buffer currently being
  484. * parsed from where the user-space resource id handle is located.
  485. * @p_val: Pointer to pointer to resource validalidation node. Populated
  486. * on exit.
  487. */
  488. static int
  489. vmw_cmd_res_check(struct vmw_private *dev_priv,
  490. struct vmw_sw_context *sw_context,
  491. enum vmw_res_type res_type,
  492. const struct vmw_user_resource_conv *converter,
  493. uint32_t *id_loc,
  494. struct vmw_resource_val_node **p_val)
  495. {
  496. return vmw_cmd_compat_res_check(dev_priv, sw_context, res_type,
  497. converter, *id_loc, id_loc, p_val);
  498. }
  499. /**
  500. * vmw_rebind_contexts - Rebind all resources previously bound to
  501. * referenced contexts.
  502. *
  503. * @sw_context: Pointer to the software context.
  504. *
  505. * Rebind context binding points that have been scrubbed because of eviction.
  506. */
  507. static int vmw_rebind_contexts(struct vmw_sw_context *sw_context)
  508. {
  509. struct vmw_resource_val_node *val;
  510. int ret;
  511. list_for_each_entry(val, &sw_context->resource_list, head) {
  512. if (likely(!val->staged_bindings))
  513. continue;
  514. ret = vmw_context_rebind_all(val->res);
  515. if (unlikely(ret != 0)) {
  516. if (ret != -ERESTARTSYS)
  517. DRM_ERROR("Failed to rebind context.\n");
  518. return ret;
  519. }
  520. }
  521. return 0;
  522. }
  523. /**
  524. * vmw_cmd_cid_check - Check a command header for valid context information.
  525. *
  526. * @dev_priv: Pointer to a device private structure.
  527. * @sw_context: Pointer to the software context.
  528. * @header: A command header with an embedded user-space context handle.
  529. *
  530. * Convenience function: Call vmw_cmd_res_check with the user-space context
  531. * handle embedded in @header.
  532. */
  533. static int vmw_cmd_cid_check(struct vmw_private *dev_priv,
  534. struct vmw_sw_context *sw_context,
  535. SVGA3dCmdHeader *header)
  536. {
  537. struct vmw_cid_cmd {
  538. SVGA3dCmdHeader header;
  539. uint32_t cid;
  540. } *cmd;
  541. cmd = container_of(header, struct vmw_cid_cmd, header);
  542. return vmw_cmd_res_check(dev_priv, sw_context, vmw_res_context,
  543. user_context_converter, &cmd->cid, NULL);
  544. }
  545. static int vmw_cmd_set_render_target_check(struct vmw_private *dev_priv,
  546. struct vmw_sw_context *sw_context,
  547. SVGA3dCmdHeader *header)
  548. {
  549. struct vmw_sid_cmd {
  550. SVGA3dCmdHeader header;
  551. SVGA3dCmdSetRenderTarget body;
  552. } *cmd;
  553. struct vmw_resource_val_node *ctx_node;
  554. struct vmw_resource_val_node *res_node;
  555. int ret;
  556. cmd = container_of(header, struct vmw_sid_cmd, header);
  557. ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_context,
  558. user_context_converter, &cmd->body.cid,
  559. &ctx_node);
  560. if (unlikely(ret != 0))
  561. return ret;
  562. ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface,
  563. user_surface_converter,
  564. &cmd->body.target.sid, &res_node);
  565. if (unlikely(ret != 0))
  566. return ret;
  567. if (dev_priv->has_mob) {
  568. struct vmw_ctx_bindinfo bi;
  569. bi.ctx = ctx_node->res;
  570. bi.res = res_node ? res_node->res : NULL;
  571. bi.bt = vmw_ctx_binding_rt;
  572. bi.i1.rt_type = cmd->body.type;
  573. return vmw_context_binding_add(ctx_node->staged_bindings, &bi);
  574. }
  575. return 0;
  576. }
  577. static int vmw_cmd_surface_copy_check(struct vmw_private *dev_priv,
  578. struct vmw_sw_context *sw_context,
  579. SVGA3dCmdHeader *header)
  580. {
  581. struct vmw_sid_cmd {
  582. SVGA3dCmdHeader header;
  583. SVGA3dCmdSurfaceCopy body;
  584. } *cmd;
  585. int ret;
  586. cmd = container_of(header, struct vmw_sid_cmd, header);
  587. ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface,
  588. user_surface_converter,
  589. &cmd->body.src.sid, NULL);
  590. if (unlikely(ret != 0))
  591. return ret;
  592. return vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface,
  593. user_surface_converter,
  594. &cmd->body.dest.sid, NULL);
  595. }
  596. static int vmw_cmd_stretch_blt_check(struct vmw_private *dev_priv,
  597. struct vmw_sw_context *sw_context,
  598. SVGA3dCmdHeader *header)
  599. {
  600. struct vmw_sid_cmd {
  601. SVGA3dCmdHeader header;
  602. SVGA3dCmdSurfaceStretchBlt body;
  603. } *cmd;
  604. int ret;
  605. cmd = container_of(header, struct vmw_sid_cmd, header);
  606. ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface,
  607. user_surface_converter,
  608. &cmd->body.src.sid, NULL);
  609. if (unlikely(ret != 0))
  610. return ret;
  611. return vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface,
  612. user_surface_converter,
  613. &cmd->body.dest.sid, NULL);
  614. }
  615. static int vmw_cmd_blt_surf_screen_check(struct vmw_private *dev_priv,
  616. struct vmw_sw_context *sw_context,
  617. SVGA3dCmdHeader *header)
  618. {
  619. struct vmw_sid_cmd {
  620. SVGA3dCmdHeader header;
  621. SVGA3dCmdBlitSurfaceToScreen body;
  622. } *cmd;
  623. cmd = container_of(header, struct vmw_sid_cmd, header);
  624. return vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface,
  625. user_surface_converter,
  626. &cmd->body.srcImage.sid, NULL);
  627. }
  628. static int vmw_cmd_present_check(struct vmw_private *dev_priv,
  629. struct vmw_sw_context *sw_context,
  630. SVGA3dCmdHeader *header)
  631. {
  632. struct vmw_sid_cmd {
  633. SVGA3dCmdHeader header;
  634. SVGA3dCmdPresent body;
  635. } *cmd;
  636. cmd = container_of(header, struct vmw_sid_cmd, header);
  637. return vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface,
  638. user_surface_converter, &cmd->body.sid,
  639. NULL);
  640. }
  641. /**
  642. * vmw_query_bo_switch_prepare - Prepare to switch pinned buffer for queries.
  643. *
  644. * @dev_priv: The device private structure.
  645. * @new_query_bo: The new buffer holding query results.
  646. * @sw_context: The software context used for this command submission.
  647. *
  648. * This function checks whether @new_query_bo is suitable for holding
  649. * query results, and if another buffer currently is pinned for query
  650. * results. If so, the function prepares the state of @sw_context for
  651. * switching pinned buffers after successful submission of the current
  652. * command batch.
  653. */
  654. static int vmw_query_bo_switch_prepare(struct vmw_private *dev_priv,
  655. struct ttm_buffer_object *new_query_bo,
  656. struct vmw_sw_context *sw_context)
  657. {
  658. struct vmw_res_cache_entry *ctx_entry =
  659. &sw_context->res_cache[vmw_res_context];
  660. int ret;
  661. BUG_ON(!ctx_entry->valid);
  662. sw_context->last_query_ctx = ctx_entry->res;
  663. if (unlikely(new_query_bo != sw_context->cur_query_bo)) {
  664. if (unlikely(new_query_bo->num_pages > 4)) {
  665. DRM_ERROR("Query buffer too large.\n");
  666. return -EINVAL;
  667. }
  668. if (unlikely(sw_context->cur_query_bo != NULL)) {
  669. sw_context->needs_post_query_barrier = true;
  670. ret = vmw_bo_to_validate_list(sw_context,
  671. sw_context->cur_query_bo,
  672. dev_priv->has_mob, NULL);
  673. if (unlikely(ret != 0))
  674. return ret;
  675. }
  676. sw_context->cur_query_bo = new_query_bo;
  677. ret = vmw_bo_to_validate_list(sw_context,
  678. dev_priv->dummy_query_bo,
  679. dev_priv->has_mob, NULL);
  680. if (unlikely(ret != 0))
  681. return ret;
  682. }
  683. return 0;
  684. }
  685. /**
  686. * vmw_query_bo_switch_commit - Finalize switching pinned query buffer
  687. *
  688. * @dev_priv: The device private structure.
  689. * @sw_context: The software context used for this command submission batch.
  690. *
  691. * This function will check if we're switching query buffers, and will then,
  692. * issue a dummy occlusion query wait used as a query barrier. When the fence
  693. * object following that query wait has signaled, we are sure that all
  694. * preceding queries have finished, and the old query buffer can be unpinned.
  695. * However, since both the new query buffer and the old one are fenced with
  696. * that fence, we can do an asynchronus unpin now, and be sure that the
  697. * old query buffer won't be moved until the fence has signaled.
  698. *
  699. * As mentioned above, both the new - and old query buffers need to be fenced
  700. * using a sequence emitted *after* calling this function.
  701. */
  702. static void vmw_query_bo_switch_commit(struct vmw_private *dev_priv,
  703. struct vmw_sw_context *sw_context)
  704. {
  705. /*
  706. * The validate list should still hold references to all
  707. * contexts here.
  708. */
  709. if (sw_context->needs_post_query_barrier) {
  710. struct vmw_res_cache_entry *ctx_entry =
  711. &sw_context->res_cache[vmw_res_context];
  712. struct vmw_resource *ctx;
  713. int ret;
  714. BUG_ON(!ctx_entry->valid);
  715. ctx = ctx_entry->res;
  716. ret = vmw_fifo_emit_dummy_query(dev_priv, ctx->id);
  717. if (unlikely(ret != 0))
  718. DRM_ERROR("Out of fifo space for dummy query.\n");
  719. }
  720. if (dev_priv->pinned_bo != sw_context->cur_query_bo) {
  721. if (dev_priv->pinned_bo) {
  722. vmw_bo_pin(dev_priv->pinned_bo, false);
  723. ttm_bo_unref(&dev_priv->pinned_bo);
  724. }
  725. if (!sw_context->needs_post_query_barrier) {
  726. vmw_bo_pin(sw_context->cur_query_bo, true);
  727. /*
  728. * We pin also the dummy_query_bo buffer so that we
  729. * don't need to validate it when emitting
  730. * dummy queries in context destroy paths.
  731. */
  732. vmw_bo_pin(dev_priv->dummy_query_bo, true);
  733. dev_priv->dummy_query_bo_pinned = true;
  734. BUG_ON(sw_context->last_query_ctx == NULL);
  735. dev_priv->query_cid = sw_context->last_query_ctx->id;
  736. dev_priv->query_cid_valid = true;
  737. dev_priv->pinned_bo =
  738. ttm_bo_reference(sw_context->cur_query_bo);
  739. }
  740. }
  741. }
  742. /**
  743. * vmw_translate_mob_pointer - Prepare to translate a user-space buffer
  744. * handle to a MOB id.
  745. *
  746. * @dev_priv: Pointer to a device private structure.
  747. * @sw_context: The software context used for this command batch validation.
  748. * @id: Pointer to the user-space handle to be translated.
  749. * @vmw_bo_p: Points to a location that, on successful return will carry
  750. * a reference-counted pointer to the DMA buffer identified by the
  751. * user-space handle in @id.
  752. *
  753. * This function saves information needed to translate a user-space buffer
  754. * handle to a MOB id. The translation does not take place immediately, but
  755. * during a call to vmw_apply_relocations(). This function builds a relocation
  756. * list and a list of buffers to validate. The former needs to be freed using
  757. * either vmw_apply_relocations() or vmw_free_relocations(). The latter
  758. * needs to be freed using vmw_clear_validations.
  759. */
  760. static int vmw_translate_mob_ptr(struct vmw_private *dev_priv,
  761. struct vmw_sw_context *sw_context,
  762. SVGAMobId *id,
  763. struct vmw_dma_buffer **vmw_bo_p)
  764. {
  765. struct vmw_dma_buffer *vmw_bo = NULL;
  766. struct ttm_buffer_object *bo;
  767. uint32_t handle = *id;
  768. struct vmw_relocation *reloc;
  769. int ret;
  770. ret = vmw_user_dmabuf_lookup(sw_context->fp->tfile, handle, &vmw_bo);
  771. if (unlikely(ret != 0)) {
  772. DRM_ERROR("Could not find or use MOB buffer.\n");
  773. return -EINVAL;
  774. }
  775. bo = &vmw_bo->base;
  776. if (unlikely(sw_context->cur_reloc >= VMWGFX_MAX_RELOCATIONS)) {
  777. DRM_ERROR("Max number relocations per submission"
  778. " exceeded\n");
  779. ret = -EINVAL;
  780. goto out_no_reloc;
  781. }
  782. reloc = &sw_context->relocs[sw_context->cur_reloc++];
  783. reloc->mob_loc = id;
  784. reloc->location = NULL;
  785. ret = vmw_bo_to_validate_list(sw_context, bo, true, &reloc->index);
  786. if (unlikely(ret != 0))
  787. goto out_no_reloc;
  788. *vmw_bo_p = vmw_bo;
  789. return 0;
  790. out_no_reloc:
  791. vmw_dmabuf_unreference(&vmw_bo);
  792. vmw_bo_p = NULL;
  793. return ret;
  794. }
  795. /**
  796. * vmw_translate_guest_pointer - Prepare to translate a user-space buffer
  797. * handle to a valid SVGAGuestPtr
  798. *
  799. * @dev_priv: Pointer to a device private structure.
  800. * @sw_context: The software context used for this command batch validation.
  801. * @ptr: Pointer to the user-space handle to be translated.
  802. * @vmw_bo_p: Points to a location that, on successful return will carry
  803. * a reference-counted pointer to the DMA buffer identified by the
  804. * user-space handle in @id.
  805. *
  806. * This function saves information needed to translate a user-space buffer
  807. * handle to a valid SVGAGuestPtr. The translation does not take place
  808. * immediately, but during a call to vmw_apply_relocations().
  809. * This function builds a relocation list and a list of buffers to validate.
  810. * The former needs to be freed using either vmw_apply_relocations() or
  811. * vmw_free_relocations(). The latter needs to be freed using
  812. * vmw_clear_validations.
  813. */
  814. static int vmw_translate_guest_ptr(struct vmw_private *dev_priv,
  815. struct vmw_sw_context *sw_context,
  816. SVGAGuestPtr *ptr,
  817. struct vmw_dma_buffer **vmw_bo_p)
  818. {
  819. struct vmw_dma_buffer *vmw_bo = NULL;
  820. struct ttm_buffer_object *bo;
  821. uint32_t handle = ptr->gmrId;
  822. struct vmw_relocation *reloc;
  823. int ret;
  824. ret = vmw_user_dmabuf_lookup(sw_context->fp->tfile, handle, &vmw_bo);
  825. if (unlikely(ret != 0)) {
  826. DRM_ERROR("Could not find or use GMR region.\n");
  827. return -EINVAL;
  828. }
  829. bo = &vmw_bo->base;
  830. if (unlikely(sw_context->cur_reloc >= VMWGFX_MAX_RELOCATIONS)) {
  831. DRM_ERROR("Max number relocations per submission"
  832. " exceeded\n");
  833. ret = -EINVAL;
  834. goto out_no_reloc;
  835. }
  836. reloc = &sw_context->relocs[sw_context->cur_reloc++];
  837. reloc->location = ptr;
  838. ret = vmw_bo_to_validate_list(sw_context, bo, false, &reloc->index);
  839. if (unlikely(ret != 0))
  840. goto out_no_reloc;
  841. *vmw_bo_p = vmw_bo;
  842. return 0;
  843. out_no_reloc:
  844. vmw_dmabuf_unreference(&vmw_bo);
  845. vmw_bo_p = NULL;
  846. return ret;
  847. }
  848. /**
  849. * vmw_cmd_begin_gb_query - validate a SVGA_3D_CMD_BEGIN_GB_QUERY command.
  850. *
  851. * @dev_priv: Pointer to a device private struct.
  852. * @sw_context: The software context used for this command submission.
  853. * @header: Pointer to the command header in the command stream.
  854. */
  855. static int vmw_cmd_begin_gb_query(struct vmw_private *dev_priv,
  856. struct vmw_sw_context *sw_context,
  857. SVGA3dCmdHeader *header)
  858. {
  859. struct vmw_begin_gb_query_cmd {
  860. SVGA3dCmdHeader header;
  861. SVGA3dCmdBeginGBQuery q;
  862. } *cmd;
  863. cmd = container_of(header, struct vmw_begin_gb_query_cmd,
  864. header);
  865. return vmw_cmd_res_check(dev_priv, sw_context, vmw_res_context,
  866. user_context_converter, &cmd->q.cid,
  867. NULL);
  868. }
  869. /**
  870. * vmw_cmd_begin_query - validate a SVGA_3D_CMD_BEGIN_QUERY command.
  871. *
  872. * @dev_priv: Pointer to a device private struct.
  873. * @sw_context: The software context used for this command submission.
  874. * @header: Pointer to the command header in the command stream.
  875. */
  876. static int vmw_cmd_begin_query(struct vmw_private *dev_priv,
  877. struct vmw_sw_context *sw_context,
  878. SVGA3dCmdHeader *header)
  879. {
  880. struct vmw_begin_query_cmd {
  881. SVGA3dCmdHeader header;
  882. SVGA3dCmdBeginQuery q;
  883. } *cmd;
  884. cmd = container_of(header, struct vmw_begin_query_cmd,
  885. header);
  886. if (unlikely(dev_priv->has_mob)) {
  887. struct {
  888. SVGA3dCmdHeader header;
  889. SVGA3dCmdBeginGBQuery q;
  890. } gb_cmd;
  891. BUG_ON(sizeof(gb_cmd) != sizeof(*cmd));
  892. gb_cmd.header.id = SVGA_3D_CMD_BEGIN_GB_QUERY;
  893. gb_cmd.header.size = cmd->header.size;
  894. gb_cmd.q.cid = cmd->q.cid;
  895. gb_cmd.q.type = cmd->q.type;
  896. memcpy(cmd, &gb_cmd, sizeof(*cmd));
  897. return vmw_cmd_begin_gb_query(dev_priv, sw_context, header);
  898. }
  899. return vmw_cmd_res_check(dev_priv, sw_context, vmw_res_context,
  900. user_context_converter, &cmd->q.cid,
  901. NULL);
  902. }
  903. /**
  904. * vmw_cmd_end_gb_query - validate a SVGA_3D_CMD_END_GB_QUERY command.
  905. *
  906. * @dev_priv: Pointer to a device private struct.
  907. * @sw_context: The software context used for this command submission.
  908. * @header: Pointer to the command header in the command stream.
  909. */
  910. static int vmw_cmd_end_gb_query(struct vmw_private *dev_priv,
  911. struct vmw_sw_context *sw_context,
  912. SVGA3dCmdHeader *header)
  913. {
  914. struct vmw_dma_buffer *vmw_bo;
  915. struct vmw_query_cmd {
  916. SVGA3dCmdHeader header;
  917. SVGA3dCmdEndGBQuery q;
  918. } *cmd;
  919. int ret;
  920. cmd = container_of(header, struct vmw_query_cmd, header);
  921. ret = vmw_cmd_cid_check(dev_priv, sw_context, header);
  922. if (unlikely(ret != 0))
  923. return ret;
  924. ret = vmw_translate_mob_ptr(dev_priv, sw_context,
  925. &cmd->q.mobid,
  926. &vmw_bo);
  927. if (unlikely(ret != 0))
  928. return ret;
  929. ret = vmw_query_bo_switch_prepare(dev_priv, &vmw_bo->base, sw_context);
  930. vmw_dmabuf_unreference(&vmw_bo);
  931. return ret;
  932. }
  933. /**
  934. * vmw_cmd_end_query - validate a SVGA_3D_CMD_END_QUERY command.
  935. *
  936. * @dev_priv: Pointer to a device private struct.
  937. * @sw_context: The software context used for this command submission.
  938. * @header: Pointer to the command header in the command stream.
  939. */
  940. static int vmw_cmd_end_query(struct vmw_private *dev_priv,
  941. struct vmw_sw_context *sw_context,
  942. SVGA3dCmdHeader *header)
  943. {
  944. struct vmw_dma_buffer *vmw_bo;
  945. struct vmw_query_cmd {
  946. SVGA3dCmdHeader header;
  947. SVGA3dCmdEndQuery q;
  948. } *cmd;
  949. int ret;
  950. cmd = container_of(header, struct vmw_query_cmd, header);
  951. if (dev_priv->has_mob) {
  952. struct {
  953. SVGA3dCmdHeader header;
  954. SVGA3dCmdEndGBQuery q;
  955. } gb_cmd;
  956. BUG_ON(sizeof(gb_cmd) != sizeof(*cmd));
  957. gb_cmd.header.id = SVGA_3D_CMD_END_GB_QUERY;
  958. gb_cmd.header.size = cmd->header.size;
  959. gb_cmd.q.cid = cmd->q.cid;
  960. gb_cmd.q.type = cmd->q.type;
  961. gb_cmd.q.mobid = cmd->q.guestResult.gmrId;
  962. gb_cmd.q.offset = cmd->q.guestResult.offset;
  963. memcpy(cmd, &gb_cmd, sizeof(*cmd));
  964. return vmw_cmd_end_gb_query(dev_priv, sw_context, header);
  965. }
  966. ret = vmw_cmd_cid_check(dev_priv, sw_context, header);
  967. if (unlikely(ret != 0))
  968. return ret;
  969. ret = vmw_translate_guest_ptr(dev_priv, sw_context,
  970. &cmd->q.guestResult,
  971. &vmw_bo);
  972. if (unlikely(ret != 0))
  973. return ret;
  974. ret = vmw_query_bo_switch_prepare(dev_priv, &vmw_bo->base, sw_context);
  975. vmw_dmabuf_unreference(&vmw_bo);
  976. return ret;
  977. }
  978. /**
  979. * vmw_cmd_wait_gb_query - validate a SVGA_3D_CMD_WAIT_GB_QUERY command.
  980. *
  981. * @dev_priv: Pointer to a device private struct.
  982. * @sw_context: The software context used for this command submission.
  983. * @header: Pointer to the command header in the command stream.
  984. */
  985. static int vmw_cmd_wait_gb_query(struct vmw_private *dev_priv,
  986. struct vmw_sw_context *sw_context,
  987. SVGA3dCmdHeader *header)
  988. {
  989. struct vmw_dma_buffer *vmw_bo;
  990. struct vmw_query_cmd {
  991. SVGA3dCmdHeader header;
  992. SVGA3dCmdWaitForGBQuery q;
  993. } *cmd;
  994. int ret;
  995. cmd = container_of(header, struct vmw_query_cmd, header);
  996. ret = vmw_cmd_cid_check(dev_priv, sw_context, header);
  997. if (unlikely(ret != 0))
  998. return ret;
  999. ret = vmw_translate_mob_ptr(dev_priv, sw_context,
  1000. &cmd->q.mobid,
  1001. &vmw_bo);
  1002. if (unlikely(ret != 0))
  1003. return ret;
  1004. vmw_dmabuf_unreference(&vmw_bo);
  1005. return 0;
  1006. }
  1007. /**
  1008. * vmw_cmd_wait_query - validate a SVGA_3D_CMD_WAIT_QUERY command.
  1009. *
  1010. * @dev_priv: Pointer to a device private struct.
  1011. * @sw_context: The software context used for this command submission.
  1012. * @header: Pointer to the command header in the command stream.
  1013. */
  1014. static int vmw_cmd_wait_query(struct vmw_private *dev_priv,
  1015. struct vmw_sw_context *sw_context,
  1016. SVGA3dCmdHeader *header)
  1017. {
  1018. struct vmw_dma_buffer *vmw_bo;
  1019. struct vmw_query_cmd {
  1020. SVGA3dCmdHeader header;
  1021. SVGA3dCmdWaitForQuery q;
  1022. } *cmd;
  1023. int ret;
  1024. cmd = container_of(header, struct vmw_query_cmd, header);
  1025. if (dev_priv->has_mob) {
  1026. struct {
  1027. SVGA3dCmdHeader header;
  1028. SVGA3dCmdWaitForGBQuery q;
  1029. } gb_cmd;
  1030. BUG_ON(sizeof(gb_cmd) != sizeof(*cmd));
  1031. gb_cmd.header.id = SVGA_3D_CMD_WAIT_FOR_GB_QUERY;
  1032. gb_cmd.header.size = cmd->header.size;
  1033. gb_cmd.q.cid = cmd->q.cid;
  1034. gb_cmd.q.type = cmd->q.type;
  1035. gb_cmd.q.mobid = cmd->q.guestResult.gmrId;
  1036. gb_cmd.q.offset = cmd->q.guestResult.offset;
  1037. memcpy(cmd, &gb_cmd, sizeof(*cmd));
  1038. return vmw_cmd_wait_gb_query(dev_priv, sw_context, header);
  1039. }
  1040. ret = vmw_cmd_cid_check(dev_priv, sw_context, header);
  1041. if (unlikely(ret != 0))
  1042. return ret;
  1043. ret = vmw_translate_guest_ptr(dev_priv, sw_context,
  1044. &cmd->q.guestResult,
  1045. &vmw_bo);
  1046. if (unlikely(ret != 0))
  1047. return ret;
  1048. vmw_dmabuf_unreference(&vmw_bo);
  1049. return 0;
  1050. }
  1051. static int vmw_cmd_dma(struct vmw_private *dev_priv,
  1052. struct vmw_sw_context *sw_context,
  1053. SVGA3dCmdHeader *header)
  1054. {
  1055. struct vmw_dma_buffer *vmw_bo = NULL;
  1056. struct vmw_surface *srf = NULL;
  1057. struct vmw_dma_cmd {
  1058. SVGA3dCmdHeader header;
  1059. SVGA3dCmdSurfaceDMA dma;
  1060. } *cmd;
  1061. int ret;
  1062. cmd = container_of(header, struct vmw_dma_cmd, header);
  1063. ret = vmw_translate_guest_ptr(dev_priv, sw_context,
  1064. &cmd->dma.guest.ptr,
  1065. &vmw_bo);
  1066. if (unlikely(ret != 0))
  1067. return ret;
  1068. ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface,
  1069. user_surface_converter, &cmd->dma.host.sid,
  1070. NULL);
  1071. if (unlikely(ret != 0)) {
  1072. if (unlikely(ret != -ERESTARTSYS))
  1073. DRM_ERROR("could not find surface for DMA.\n");
  1074. goto out_no_surface;
  1075. }
  1076. srf = vmw_res_to_srf(sw_context->res_cache[vmw_res_surface].res);
  1077. vmw_kms_cursor_snoop(srf, sw_context->fp->tfile, &vmw_bo->base,
  1078. header);
  1079. out_no_surface:
  1080. vmw_dmabuf_unreference(&vmw_bo);
  1081. return ret;
  1082. }
  1083. static int vmw_cmd_draw(struct vmw_private *dev_priv,
  1084. struct vmw_sw_context *sw_context,
  1085. SVGA3dCmdHeader *header)
  1086. {
  1087. struct vmw_draw_cmd {
  1088. SVGA3dCmdHeader header;
  1089. SVGA3dCmdDrawPrimitives body;
  1090. } *cmd;
  1091. SVGA3dVertexDecl *decl = (SVGA3dVertexDecl *)(
  1092. (unsigned long)header + sizeof(*cmd));
  1093. SVGA3dPrimitiveRange *range;
  1094. uint32_t i;
  1095. uint32_t maxnum;
  1096. int ret;
  1097. ret = vmw_cmd_cid_check(dev_priv, sw_context, header);
  1098. if (unlikely(ret != 0))
  1099. return ret;
  1100. cmd = container_of(header, struct vmw_draw_cmd, header);
  1101. maxnum = (header->size - sizeof(cmd->body)) / sizeof(*decl);
  1102. if (unlikely(cmd->body.numVertexDecls > maxnum)) {
  1103. DRM_ERROR("Illegal number of vertex declarations.\n");
  1104. return -EINVAL;
  1105. }
  1106. for (i = 0; i < cmd->body.numVertexDecls; ++i, ++decl) {
  1107. ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface,
  1108. user_surface_converter,
  1109. &decl->array.surfaceId, NULL);
  1110. if (unlikely(ret != 0))
  1111. return ret;
  1112. }
  1113. maxnum = (header->size - sizeof(cmd->body) -
  1114. cmd->body.numVertexDecls * sizeof(*decl)) / sizeof(*range);
  1115. if (unlikely(cmd->body.numRanges > maxnum)) {
  1116. DRM_ERROR("Illegal number of index ranges.\n");
  1117. return -EINVAL;
  1118. }
  1119. range = (SVGA3dPrimitiveRange *) decl;
  1120. for (i = 0; i < cmd->body.numRanges; ++i, ++range) {
  1121. ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface,
  1122. user_surface_converter,
  1123. &range->indexArray.surfaceId, NULL);
  1124. if (unlikely(ret != 0))
  1125. return ret;
  1126. }
  1127. return 0;
  1128. }
  1129. static int vmw_cmd_tex_state(struct vmw_private *dev_priv,
  1130. struct vmw_sw_context *sw_context,
  1131. SVGA3dCmdHeader *header)
  1132. {
  1133. struct vmw_tex_state_cmd {
  1134. SVGA3dCmdHeader header;
  1135. SVGA3dCmdSetTextureState state;
  1136. } *cmd;
  1137. SVGA3dTextureState *last_state = (SVGA3dTextureState *)
  1138. ((unsigned long) header + header->size + sizeof(header));
  1139. SVGA3dTextureState *cur_state = (SVGA3dTextureState *)
  1140. ((unsigned long) header + sizeof(struct vmw_tex_state_cmd));
  1141. struct vmw_resource_val_node *ctx_node;
  1142. struct vmw_resource_val_node *res_node;
  1143. int ret;
  1144. cmd = container_of(header, struct vmw_tex_state_cmd,
  1145. header);
  1146. ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_context,
  1147. user_context_converter, &cmd->state.cid,
  1148. &ctx_node);
  1149. if (unlikely(ret != 0))
  1150. return ret;
  1151. for (; cur_state < last_state; ++cur_state) {
  1152. if (likely(cur_state->name != SVGA3D_TS_BIND_TEXTURE))
  1153. continue;
  1154. ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface,
  1155. user_surface_converter,
  1156. &cur_state->value, &res_node);
  1157. if (unlikely(ret != 0))
  1158. return ret;
  1159. if (dev_priv->has_mob) {
  1160. struct vmw_ctx_bindinfo bi;
  1161. bi.ctx = ctx_node->res;
  1162. bi.res = res_node ? res_node->res : NULL;
  1163. bi.bt = vmw_ctx_binding_tex;
  1164. bi.i1.texture_stage = cur_state->stage;
  1165. vmw_context_binding_add(ctx_node->staged_bindings,
  1166. &bi);
  1167. }
  1168. }
  1169. return 0;
  1170. }
  1171. static int vmw_cmd_check_define_gmrfb(struct vmw_private *dev_priv,
  1172. struct vmw_sw_context *sw_context,
  1173. void *buf)
  1174. {
  1175. struct vmw_dma_buffer *vmw_bo;
  1176. int ret;
  1177. struct {
  1178. uint32_t header;
  1179. SVGAFifoCmdDefineGMRFB body;
  1180. } *cmd = buf;
  1181. ret = vmw_translate_guest_ptr(dev_priv, sw_context,
  1182. &cmd->body.ptr,
  1183. &vmw_bo);
  1184. if (unlikely(ret != 0))
  1185. return ret;
  1186. vmw_dmabuf_unreference(&vmw_bo);
  1187. return ret;
  1188. }
  1189. /**
  1190. * vmw_cmd_switch_backup - Utility function to handle backup buffer switching
  1191. *
  1192. * @dev_priv: Pointer to a device private struct.
  1193. * @sw_context: The software context being used for this batch.
  1194. * @res_type: The resource type.
  1195. * @converter: Information about user-space binding for this resource type.
  1196. * @res_id: Pointer to the user-space resource handle in the command stream.
  1197. * @buf_id: Pointer to the user-space backup buffer handle in the command
  1198. * stream.
  1199. * @backup_offset: Offset of backup into MOB.
  1200. *
  1201. * This function prepares for registering a switch of backup buffers
  1202. * in the resource metadata just prior to unreserving.
  1203. */
  1204. static int vmw_cmd_switch_backup(struct vmw_private *dev_priv,
  1205. struct vmw_sw_context *sw_context,
  1206. enum vmw_res_type res_type,
  1207. const struct vmw_user_resource_conv
  1208. *converter,
  1209. uint32_t *res_id,
  1210. uint32_t *buf_id,
  1211. unsigned long backup_offset)
  1212. {
  1213. int ret;
  1214. struct vmw_dma_buffer *dma_buf;
  1215. struct vmw_resource_val_node *val_node;
  1216. ret = vmw_cmd_res_check(dev_priv, sw_context, res_type,
  1217. converter, res_id, &val_node);
  1218. if (unlikely(ret != 0))
  1219. return ret;
  1220. ret = vmw_translate_mob_ptr(dev_priv, sw_context, buf_id, &dma_buf);
  1221. if (unlikely(ret != 0))
  1222. return ret;
  1223. if (val_node->first_usage)
  1224. val_node->no_buffer_needed = true;
  1225. vmw_dmabuf_unreference(&val_node->new_backup);
  1226. val_node->new_backup = dma_buf;
  1227. val_node->new_backup_offset = backup_offset;
  1228. return 0;
  1229. }
  1230. /**
  1231. * vmw_cmd_bind_gb_surface - Validate an SVGA_3D_CMD_BIND_GB_SURFACE
  1232. * command
  1233. *
  1234. * @dev_priv: Pointer to a device private struct.
  1235. * @sw_context: The software context being used for this batch.
  1236. * @header: Pointer to the command header in the command stream.
  1237. */
  1238. static int vmw_cmd_bind_gb_surface(struct vmw_private *dev_priv,
  1239. struct vmw_sw_context *sw_context,
  1240. SVGA3dCmdHeader *header)
  1241. {
  1242. struct vmw_bind_gb_surface_cmd {
  1243. SVGA3dCmdHeader header;
  1244. SVGA3dCmdBindGBSurface body;
  1245. } *cmd;
  1246. cmd = container_of(header, struct vmw_bind_gb_surface_cmd, header);
  1247. return vmw_cmd_switch_backup(dev_priv, sw_context, vmw_res_surface,
  1248. user_surface_converter,
  1249. &cmd->body.sid, &cmd->body.mobid,
  1250. 0);
  1251. }
  1252. /**
  1253. * vmw_cmd_update_gb_image - Validate an SVGA_3D_CMD_UPDATE_GB_IMAGE
  1254. * command
  1255. *
  1256. * @dev_priv: Pointer to a device private struct.
  1257. * @sw_context: The software context being used for this batch.
  1258. * @header: Pointer to the command header in the command stream.
  1259. */
  1260. static int vmw_cmd_update_gb_image(struct vmw_private *dev_priv,
  1261. struct vmw_sw_context *sw_context,
  1262. SVGA3dCmdHeader *header)
  1263. {
  1264. struct vmw_gb_surface_cmd {
  1265. SVGA3dCmdHeader header;
  1266. SVGA3dCmdUpdateGBImage body;
  1267. } *cmd;
  1268. cmd = container_of(header, struct vmw_gb_surface_cmd, header);
  1269. return vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface,
  1270. user_surface_converter,
  1271. &cmd->body.image.sid, NULL);
  1272. }
  1273. /**
  1274. * vmw_cmd_update_gb_surface - Validate an SVGA_3D_CMD_UPDATE_GB_SURFACE
  1275. * command
  1276. *
  1277. * @dev_priv: Pointer to a device private struct.
  1278. * @sw_context: The software context being used for this batch.
  1279. * @header: Pointer to the command header in the command stream.
  1280. */
  1281. static int vmw_cmd_update_gb_surface(struct vmw_private *dev_priv,
  1282. struct vmw_sw_context *sw_context,
  1283. SVGA3dCmdHeader *header)
  1284. {
  1285. struct vmw_gb_surface_cmd {
  1286. SVGA3dCmdHeader header;
  1287. SVGA3dCmdUpdateGBSurface body;
  1288. } *cmd;
  1289. cmd = container_of(header, struct vmw_gb_surface_cmd, header);
  1290. return vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface,
  1291. user_surface_converter,
  1292. &cmd->body.sid, NULL);
  1293. }
  1294. /**
  1295. * vmw_cmd_readback_gb_image - Validate an SVGA_3D_CMD_READBACK_GB_IMAGE
  1296. * command
  1297. *
  1298. * @dev_priv: Pointer to a device private struct.
  1299. * @sw_context: The software context being used for this batch.
  1300. * @header: Pointer to the command header in the command stream.
  1301. */
  1302. static int vmw_cmd_readback_gb_image(struct vmw_private *dev_priv,
  1303. struct vmw_sw_context *sw_context,
  1304. SVGA3dCmdHeader *header)
  1305. {
  1306. struct vmw_gb_surface_cmd {
  1307. SVGA3dCmdHeader header;
  1308. SVGA3dCmdReadbackGBImage body;
  1309. } *cmd;
  1310. cmd = container_of(header, struct vmw_gb_surface_cmd, header);
  1311. return vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface,
  1312. user_surface_converter,
  1313. &cmd->body.image.sid, NULL);
  1314. }
  1315. /**
  1316. * vmw_cmd_readback_gb_surface - Validate an SVGA_3D_CMD_READBACK_GB_SURFACE
  1317. * command
  1318. *
  1319. * @dev_priv: Pointer to a device private struct.
  1320. * @sw_context: The software context being used for this batch.
  1321. * @header: Pointer to the command header in the command stream.
  1322. */
  1323. static int vmw_cmd_readback_gb_surface(struct vmw_private *dev_priv,
  1324. struct vmw_sw_context *sw_context,
  1325. SVGA3dCmdHeader *header)
  1326. {
  1327. struct vmw_gb_surface_cmd {
  1328. SVGA3dCmdHeader header;
  1329. SVGA3dCmdReadbackGBSurface body;
  1330. } *cmd;
  1331. cmd = container_of(header, struct vmw_gb_surface_cmd, header);
  1332. return vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface,
  1333. user_surface_converter,
  1334. &cmd->body.sid, NULL);
  1335. }
  1336. /**
  1337. * vmw_cmd_invalidate_gb_image - Validate an SVGA_3D_CMD_INVALIDATE_GB_IMAGE
  1338. * command
  1339. *
  1340. * @dev_priv: Pointer to a device private struct.
  1341. * @sw_context: The software context being used for this batch.
  1342. * @header: Pointer to the command header in the command stream.
  1343. */
  1344. static int vmw_cmd_invalidate_gb_image(struct vmw_private *dev_priv,
  1345. struct vmw_sw_context *sw_context,
  1346. SVGA3dCmdHeader *header)
  1347. {
  1348. struct vmw_gb_surface_cmd {
  1349. SVGA3dCmdHeader header;
  1350. SVGA3dCmdInvalidateGBImage body;
  1351. } *cmd;
  1352. cmd = container_of(header, struct vmw_gb_surface_cmd, header);
  1353. return vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface,
  1354. user_surface_converter,
  1355. &cmd->body.image.sid, NULL);
  1356. }
  1357. /**
  1358. * vmw_cmd_invalidate_gb_surface - Validate an
  1359. * SVGA_3D_CMD_INVALIDATE_GB_SURFACE command
  1360. *
  1361. * @dev_priv: Pointer to a device private struct.
  1362. * @sw_context: The software context being used for this batch.
  1363. * @header: Pointer to the command header in the command stream.
  1364. */
  1365. static int vmw_cmd_invalidate_gb_surface(struct vmw_private *dev_priv,
  1366. struct vmw_sw_context *sw_context,
  1367. SVGA3dCmdHeader *header)
  1368. {
  1369. struct vmw_gb_surface_cmd {
  1370. SVGA3dCmdHeader header;
  1371. SVGA3dCmdInvalidateGBSurface body;
  1372. } *cmd;
  1373. cmd = container_of(header, struct vmw_gb_surface_cmd, header);
  1374. return vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface,
  1375. user_surface_converter,
  1376. &cmd->body.sid, NULL);
  1377. }
  1378. /**
  1379. * vmw_cmd_shader_define - Validate an SVGA_3D_CMD_SHADER_DEFINE
  1380. * command
  1381. *
  1382. * @dev_priv: Pointer to a device private struct.
  1383. * @sw_context: The software context being used for this batch.
  1384. * @header: Pointer to the command header in the command stream.
  1385. */
  1386. static int vmw_cmd_shader_define(struct vmw_private *dev_priv,
  1387. struct vmw_sw_context *sw_context,
  1388. SVGA3dCmdHeader *header)
  1389. {
  1390. struct vmw_shader_define_cmd {
  1391. SVGA3dCmdHeader header;
  1392. SVGA3dCmdDefineShader body;
  1393. } *cmd;
  1394. int ret;
  1395. size_t size;
  1396. cmd = container_of(header, struct vmw_shader_define_cmd,
  1397. header);
  1398. ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_context,
  1399. user_context_converter, &cmd->body.cid,
  1400. NULL);
  1401. if (unlikely(ret != 0))
  1402. return ret;
  1403. if (unlikely(!dev_priv->has_mob))
  1404. return 0;
  1405. size = cmd->header.size - sizeof(cmd->body);
  1406. ret = vmw_compat_shader_add(sw_context->fp->shman,
  1407. cmd->body.shid, cmd + 1,
  1408. cmd->body.type, size,
  1409. sw_context->fp->tfile,
  1410. &sw_context->staged_shaders);
  1411. if (unlikely(ret != 0))
  1412. return ret;
  1413. return vmw_resource_relocation_add(&sw_context->res_relocations,
  1414. NULL, &cmd->header.id -
  1415. sw_context->buf_start);
  1416. return 0;
  1417. }
  1418. /**
  1419. * vmw_cmd_shader_destroy - Validate an SVGA_3D_CMD_SHADER_DESTROY
  1420. * command
  1421. *
  1422. * @dev_priv: Pointer to a device private struct.
  1423. * @sw_context: The software context being used for this batch.
  1424. * @header: Pointer to the command header in the command stream.
  1425. */
  1426. static int vmw_cmd_shader_destroy(struct vmw_private *dev_priv,
  1427. struct vmw_sw_context *sw_context,
  1428. SVGA3dCmdHeader *header)
  1429. {
  1430. struct vmw_shader_destroy_cmd {
  1431. SVGA3dCmdHeader header;
  1432. SVGA3dCmdDestroyShader body;
  1433. } *cmd;
  1434. int ret;
  1435. cmd = container_of(header, struct vmw_shader_destroy_cmd,
  1436. header);
  1437. ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_context,
  1438. user_context_converter, &cmd->body.cid,
  1439. NULL);
  1440. if (unlikely(ret != 0))
  1441. return ret;
  1442. if (unlikely(!dev_priv->has_mob))
  1443. return 0;
  1444. ret = vmw_compat_shader_remove(sw_context->fp->shman,
  1445. cmd->body.shid,
  1446. cmd->body.type,
  1447. &sw_context->staged_shaders);
  1448. if (unlikely(ret != 0))
  1449. return ret;
  1450. return vmw_resource_relocation_add(&sw_context->res_relocations,
  1451. NULL, &cmd->header.id -
  1452. sw_context->buf_start);
  1453. return 0;
  1454. }
  1455. /**
  1456. * vmw_cmd_set_shader - Validate an SVGA_3D_CMD_SET_SHADER
  1457. * command
  1458. *
  1459. * @dev_priv: Pointer to a device private struct.
  1460. * @sw_context: The software context being used for this batch.
  1461. * @header: Pointer to the command header in the command stream.
  1462. */
  1463. static int vmw_cmd_set_shader(struct vmw_private *dev_priv,
  1464. struct vmw_sw_context *sw_context,
  1465. SVGA3dCmdHeader *header)
  1466. {
  1467. struct vmw_set_shader_cmd {
  1468. SVGA3dCmdHeader header;
  1469. SVGA3dCmdSetShader body;
  1470. } *cmd;
  1471. struct vmw_resource_val_node *ctx_node;
  1472. int ret;
  1473. cmd = container_of(header, struct vmw_set_shader_cmd,
  1474. header);
  1475. ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_context,
  1476. user_context_converter, &cmd->body.cid,
  1477. &ctx_node);
  1478. if (unlikely(ret != 0))
  1479. return ret;
  1480. if (dev_priv->has_mob) {
  1481. struct vmw_ctx_bindinfo bi;
  1482. struct vmw_resource_val_node *res_node;
  1483. u32 shid = cmd->body.shid;
  1484. if (shid != SVGA3D_INVALID_ID)
  1485. (void) vmw_compat_shader_lookup(sw_context->fp->shman,
  1486. cmd->body.type,
  1487. &shid);
  1488. ret = vmw_cmd_compat_res_check(dev_priv, sw_context,
  1489. vmw_res_shader,
  1490. user_shader_converter,
  1491. shid,
  1492. &cmd->body.shid, &res_node);
  1493. if (unlikely(ret != 0))
  1494. return ret;
  1495. bi.ctx = ctx_node->res;
  1496. bi.res = res_node ? res_node->res : NULL;
  1497. bi.bt = vmw_ctx_binding_shader;
  1498. bi.i1.shader_type = cmd->body.type;
  1499. return vmw_context_binding_add(ctx_node->staged_bindings, &bi);
  1500. }
  1501. return 0;
  1502. }
  1503. /**
  1504. * vmw_cmd_set_shader_const - Validate an SVGA_3D_CMD_SET_SHADER_CONST
  1505. * command
  1506. *
  1507. * @dev_priv: Pointer to a device private struct.
  1508. * @sw_context: The software context being used for this batch.
  1509. * @header: Pointer to the command header in the command stream.
  1510. */
  1511. static int vmw_cmd_set_shader_const(struct vmw_private *dev_priv,
  1512. struct vmw_sw_context *sw_context,
  1513. SVGA3dCmdHeader *header)
  1514. {
  1515. struct vmw_set_shader_const_cmd {
  1516. SVGA3dCmdHeader header;
  1517. SVGA3dCmdSetShaderConst body;
  1518. } *cmd;
  1519. int ret;
  1520. cmd = container_of(header, struct vmw_set_shader_const_cmd,
  1521. header);
  1522. ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_context,
  1523. user_context_converter, &cmd->body.cid,
  1524. NULL);
  1525. if (unlikely(ret != 0))
  1526. return ret;
  1527. if (dev_priv->has_mob)
  1528. header->id = SVGA_3D_CMD_SET_GB_SHADERCONSTS_INLINE;
  1529. return 0;
  1530. }
  1531. /**
  1532. * vmw_cmd_bind_gb_shader - Validate an SVGA_3D_CMD_BIND_GB_SHADER
  1533. * command
  1534. *
  1535. * @dev_priv: Pointer to a device private struct.
  1536. * @sw_context: The software context being used for this batch.
  1537. * @header: Pointer to the command header in the command stream.
  1538. */
  1539. static int vmw_cmd_bind_gb_shader(struct vmw_private *dev_priv,
  1540. struct vmw_sw_context *sw_context,
  1541. SVGA3dCmdHeader *header)
  1542. {
  1543. struct vmw_bind_gb_shader_cmd {
  1544. SVGA3dCmdHeader header;
  1545. SVGA3dCmdBindGBShader body;
  1546. } *cmd;
  1547. cmd = container_of(header, struct vmw_bind_gb_shader_cmd,
  1548. header);
  1549. return vmw_cmd_switch_backup(dev_priv, sw_context, vmw_res_shader,
  1550. user_shader_converter,
  1551. &cmd->body.shid, &cmd->body.mobid,
  1552. cmd->body.offsetInBytes);
  1553. }
  1554. static int vmw_cmd_check_not_3d(struct vmw_private *dev_priv,
  1555. struct vmw_sw_context *sw_context,
  1556. void *buf, uint32_t *size)
  1557. {
  1558. uint32_t size_remaining = *size;
  1559. uint32_t cmd_id;
  1560. cmd_id = le32_to_cpu(((uint32_t *)buf)[0]);
  1561. switch (cmd_id) {
  1562. case SVGA_CMD_UPDATE:
  1563. *size = sizeof(uint32_t) + sizeof(SVGAFifoCmdUpdate);
  1564. break;
  1565. case SVGA_CMD_DEFINE_GMRFB:
  1566. *size = sizeof(uint32_t) + sizeof(SVGAFifoCmdDefineGMRFB);
  1567. break;
  1568. case SVGA_CMD_BLIT_GMRFB_TO_SCREEN:
  1569. *size = sizeof(uint32_t) + sizeof(SVGAFifoCmdBlitGMRFBToScreen);
  1570. break;
  1571. case SVGA_CMD_BLIT_SCREEN_TO_GMRFB:
  1572. *size = sizeof(uint32_t) + sizeof(SVGAFifoCmdBlitGMRFBToScreen);
  1573. break;
  1574. default:
  1575. DRM_ERROR("Unsupported SVGA command: %u.\n", cmd_id);
  1576. return -EINVAL;
  1577. }
  1578. if (*size > size_remaining) {
  1579. DRM_ERROR("Invalid SVGA command (size mismatch):"
  1580. " %u.\n", cmd_id);
  1581. return -EINVAL;
  1582. }
  1583. if (unlikely(!sw_context->kernel)) {
  1584. DRM_ERROR("Kernel only SVGA command: %u.\n", cmd_id);
  1585. return -EPERM;
  1586. }
  1587. if (cmd_id == SVGA_CMD_DEFINE_GMRFB)
  1588. return vmw_cmd_check_define_gmrfb(dev_priv, sw_context, buf);
  1589. return 0;
  1590. }
  1591. static const struct vmw_cmd_entry vmw_cmd_entries[SVGA_3D_CMD_MAX] = {
  1592. VMW_CMD_DEF(SVGA_3D_CMD_SURFACE_DEFINE, &vmw_cmd_invalid,
  1593. false, false, false),
  1594. VMW_CMD_DEF(SVGA_3D_CMD_SURFACE_DESTROY, &vmw_cmd_invalid,
  1595. false, false, false),
  1596. VMW_CMD_DEF(SVGA_3D_CMD_SURFACE_COPY, &vmw_cmd_surface_copy_check,
  1597. true, false, false),
  1598. VMW_CMD_DEF(SVGA_3D_CMD_SURFACE_STRETCHBLT, &vmw_cmd_stretch_blt_check,
  1599. true, false, false),
  1600. VMW_CMD_DEF(SVGA_3D_CMD_SURFACE_DMA, &vmw_cmd_dma,
  1601. true, false, false),
  1602. VMW_CMD_DEF(SVGA_3D_CMD_CONTEXT_DEFINE, &vmw_cmd_invalid,
  1603. false, false, false),
  1604. VMW_CMD_DEF(SVGA_3D_CMD_CONTEXT_DESTROY, &vmw_cmd_invalid,
  1605. false, false, false),
  1606. VMW_CMD_DEF(SVGA_3D_CMD_SETTRANSFORM, &vmw_cmd_cid_check,
  1607. true, false, false),
  1608. VMW_CMD_DEF(SVGA_3D_CMD_SETZRANGE, &vmw_cmd_cid_check,
  1609. true, false, false),
  1610. VMW_CMD_DEF(SVGA_3D_CMD_SETRENDERSTATE, &vmw_cmd_cid_check,
  1611. true, false, false),
  1612. VMW_CMD_DEF(SVGA_3D_CMD_SETRENDERTARGET,
  1613. &vmw_cmd_set_render_target_check, true, false, false),
  1614. VMW_CMD_DEF(SVGA_3D_CMD_SETTEXTURESTATE, &vmw_cmd_tex_state,
  1615. true, false, false),
  1616. VMW_CMD_DEF(SVGA_3D_CMD_SETMATERIAL, &vmw_cmd_cid_check,
  1617. true, false, false),
  1618. VMW_CMD_DEF(SVGA_3D_CMD_SETLIGHTDATA, &vmw_cmd_cid_check,
  1619. true, false, false),
  1620. VMW_CMD_DEF(SVGA_3D_CMD_SETLIGHTENABLED, &vmw_cmd_cid_check,
  1621. true, false, false),
  1622. VMW_CMD_DEF(SVGA_3D_CMD_SETVIEWPORT, &vmw_cmd_cid_check,
  1623. true, false, false),
  1624. VMW_CMD_DEF(SVGA_3D_CMD_SETCLIPPLANE, &vmw_cmd_cid_check,
  1625. true, false, false),
  1626. VMW_CMD_DEF(SVGA_3D_CMD_CLEAR, &vmw_cmd_cid_check,
  1627. true, false, false),
  1628. VMW_CMD_DEF(SVGA_3D_CMD_PRESENT, &vmw_cmd_present_check,
  1629. false, false, false),
  1630. VMW_CMD_DEF(SVGA_3D_CMD_SHADER_DEFINE, &vmw_cmd_shader_define,
  1631. true, false, false),
  1632. VMW_CMD_DEF(SVGA_3D_CMD_SHADER_DESTROY, &vmw_cmd_shader_destroy,
  1633. true, false, false),
  1634. VMW_CMD_DEF(SVGA_3D_CMD_SET_SHADER, &vmw_cmd_set_shader,
  1635. true, false, false),
  1636. VMW_CMD_DEF(SVGA_3D_CMD_SET_SHADER_CONST, &vmw_cmd_set_shader_const,
  1637. true, false, false),
  1638. VMW_CMD_DEF(SVGA_3D_CMD_DRAW_PRIMITIVES, &vmw_cmd_draw,
  1639. true, false, false),
  1640. VMW_CMD_DEF(SVGA_3D_CMD_SETSCISSORRECT, &vmw_cmd_cid_check,
  1641. true, false, false),
  1642. VMW_CMD_DEF(SVGA_3D_CMD_BEGIN_QUERY, &vmw_cmd_begin_query,
  1643. true, false, false),
  1644. VMW_CMD_DEF(SVGA_3D_CMD_END_QUERY, &vmw_cmd_end_query,
  1645. true, false, false),
  1646. VMW_CMD_DEF(SVGA_3D_CMD_WAIT_FOR_QUERY, &vmw_cmd_wait_query,
  1647. true, false, false),
  1648. VMW_CMD_DEF(SVGA_3D_CMD_PRESENT_READBACK, &vmw_cmd_ok,
  1649. true, false, false),
  1650. VMW_CMD_DEF(SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN,
  1651. &vmw_cmd_blt_surf_screen_check, false, false, false),
  1652. VMW_CMD_DEF(SVGA_3D_CMD_SURFACE_DEFINE_V2, &vmw_cmd_invalid,
  1653. false, false, false),
  1654. VMW_CMD_DEF(SVGA_3D_CMD_GENERATE_MIPMAPS, &vmw_cmd_invalid,
  1655. false, false, false),
  1656. VMW_CMD_DEF(SVGA_3D_CMD_ACTIVATE_SURFACE, &vmw_cmd_invalid,
  1657. false, false, false),
  1658. VMW_CMD_DEF(SVGA_3D_CMD_DEACTIVATE_SURFACE, &vmw_cmd_invalid,
  1659. false, false, false),
  1660. VMW_CMD_DEF(SVGA_3D_CMD_SCREEN_DMA, &vmw_cmd_invalid,
  1661. false, false, false),
  1662. VMW_CMD_DEF(SVGA_3D_CMD_SET_UNITY_SURFACE_COOKIE, &vmw_cmd_invalid,
  1663. false, false, false),
  1664. VMW_CMD_DEF(SVGA_3D_CMD_OPEN_CONTEXT_SURFACE, &vmw_cmd_invalid,
  1665. false, false, false),
  1666. VMW_CMD_DEF(SVGA_3D_CMD_LOGICOPS_BITBLT, &vmw_cmd_invalid,
  1667. false, false, false),
  1668. VMW_CMD_DEF(SVGA_3D_CMD_LOGICOPS_TRANSBLT, &vmw_cmd_invalid,
  1669. false, false, false),
  1670. VMW_CMD_DEF(SVGA_3D_CMD_LOGICOPS_STRETCHBLT, &vmw_cmd_invalid,
  1671. false, false, false),
  1672. VMW_CMD_DEF(SVGA_3D_CMD_LOGICOPS_COLORFILL, &vmw_cmd_invalid,
  1673. false, false, false),
  1674. VMW_CMD_DEF(SVGA_3D_CMD_LOGICOPS_ALPHABLEND, &vmw_cmd_invalid,
  1675. false, false, false),
  1676. VMW_CMD_DEF(SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND, &vmw_cmd_invalid,
  1677. false, false, false),
  1678. VMW_CMD_DEF(SVGA_3D_CMD_SET_OTABLE_BASE, &vmw_cmd_invalid,
  1679. false, false, true),
  1680. VMW_CMD_DEF(SVGA_3D_CMD_READBACK_OTABLE, &vmw_cmd_invalid,
  1681. false, false, true),
  1682. VMW_CMD_DEF(SVGA_3D_CMD_DEFINE_GB_MOB, &vmw_cmd_invalid,
  1683. false, false, true),
  1684. VMW_CMD_DEF(SVGA_3D_CMD_DESTROY_GB_MOB, &vmw_cmd_invalid,
  1685. false, false, true),
  1686. VMW_CMD_DEF(SVGA_3D_CMD_REDEFINE_GB_MOB, &vmw_cmd_invalid,
  1687. false, false, true),
  1688. VMW_CMD_DEF(SVGA_3D_CMD_UPDATE_GB_MOB_MAPPING, &vmw_cmd_invalid,
  1689. false, false, true),
  1690. VMW_CMD_DEF(SVGA_3D_CMD_DEFINE_GB_SURFACE, &vmw_cmd_invalid,
  1691. false, false, true),
  1692. VMW_CMD_DEF(SVGA_3D_CMD_DESTROY_GB_SURFACE, &vmw_cmd_invalid,
  1693. false, false, true),
  1694. VMW_CMD_DEF(SVGA_3D_CMD_BIND_GB_SURFACE, &vmw_cmd_bind_gb_surface,
  1695. true, false, true),
  1696. VMW_CMD_DEF(SVGA_3D_CMD_COND_BIND_GB_SURFACE, &vmw_cmd_invalid,
  1697. false, false, true),
  1698. VMW_CMD_DEF(SVGA_3D_CMD_UPDATE_GB_IMAGE, &vmw_cmd_update_gb_image,
  1699. true, false, true),
  1700. VMW_CMD_DEF(SVGA_3D_CMD_UPDATE_GB_SURFACE,
  1701. &vmw_cmd_update_gb_surface, true, false, true),
  1702. VMW_CMD_DEF(SVGA_3D_CMD_READBACK_GB_IMAGE,
  1703. &vmw_cmd_readback_gb_image, true, false, true),
  1704. VMW_CMD_DEF(SVGA_3D_CMD_READBACK_GB_SURFACE,
  1705. &vmw_cmd_readback_gb_surface, true, false, true),
  1706. VMW_CMD_DEF(SVGA_3D_CMD_INVALIDATE_GB_IMAGE,
  1707. &vmw_cmd_invalidate_gb_image, true, false, true),
  1708. VMW_CMD_DEF(SVGA_3D_CMD_INVALIDATE_GB_SURFACE,
  1709. &vmw_cmd_invalidate_gb_surface, true, false, true),
  1710. VMW_CMD_DEF(SVGA_3D_CMD_DEFINE_GB_CONTEXT, &vmw_cmd_invalid,
  1711. false, false, true),
  1712. VMW_CMD_DEF(SVGA_3D_CMD_DESTROY_GB_CONTEXT, &vmw_cmd_invalid,
  1713. false, false, true),
  1714. VMW_CMD_DEF(SVGA_3D_CMD_BIND_GB_CONTEXT, &vmw_cmd_invalid,
  1715. false, false, true),
  1716. VMW_CMD_DEF(SVGA_3D_CMD_READBACK_GB_CONTEXT, &vmw_cmd_invalid,
  1717. false, false, true),
  1718. VMW_CMD_DEF(SVGA_3D_CMD_INVALIDATE_GB_CONTEXT, &vmw_cmd_invalid,
  1719. false, false, true),
  1720. VMW_CMD_DEF(SVGA_3D_CMD_DEFINE_GB_SHADER, &vmw_cmd_invalid,
  1721. false, false, true),
  1722. VMW_CMD_DEF(SVGA_3D_CMD_BIND_GB_SHADER, &vmw_cmd_bind_gb_shader,
  1723. true, false, true),
  1724. VMW_CMD_DEF(SVGA_3D_CMD_DESTROY_GB_SHADER, &vmw_cmd_invalid,
  1725. false, false, true),
  1726. VMW_CMD_DEF(SVGA_3D_CMD_SET_OTABLE_BASE64, &vmw_cmd_invalid,
  1727. false, false, false),
  1728. VMW_CMD_DEF(SVGA_3D_CMD_BEGIN_GB_QUERY, &vmw_cmd_begin_gb_query,
  1729. true, false, true),
  1730. VMW_CMD_DEF(SVGA_3D_CMD_END_GB_QUERY, &vmw_cmd_end_gb_query,
  1731. true, false, true),
  1732. VMW_CMD_DEF(SVGA_3D_CMD_WAIT_FOR_GB_QUERY, &vmw_cmd_wait_gb_query,
  1733. true, false, true),
  1734. VMW_CMD_DEF(SVGA_3D_CMD_NOP, &vmw_cmd_ok,
  1735. true, false, true),
  1736. VMW_CMD_DEF(SVGA_3D_CMD_ENABLE_GART, &vmw_cmd_invalid,
  1737. false, false, true),
  1738. VMW_CMD_DEF(SVGA_3D_CMD_DISABLE_GART, &vmw_cmd_invalid,
  1739. false, false, true),
  1740. VMW_CMD_DEF(SVGA_3D_CMD_MAP_MOB_INTO_GART, &vmw_cmd_invalid,
  1741. false, false, true),
  1742. VMW_CMD_DEF(SVGA_3D_CMD_UNMAP_GART_RANGE, &vmw_cmd_invalid,
  1743. false, false, true),
  1744. VMW_CMD_DEF(SVGA_3D_CMD_DEFINE_GB_SCREENTARGET, &vmw_cmd_invalid,
  1745. false, false, true),
  1746. VMW_CMD_DEF(SVGA_3D_CMD_DESTROY_GB_SCREENTARGET, &vmw_cmd_invalid,
  1747. false, false, true),
  1748. VMW_CMD_DEF(SVGA_3D_CMD_BIND_GB_SCREENTARGET, &vmw_cmd_invalid,
  1749. false, false, true),
  1750. VMW_CMD_DEF(SVGA_3D_CMD_UPDATE_GB_SCREENTARGET, &vmw_cmd_invalid,
  1751. false, false, true),
  1752. VMW_CMD_DEF(SVGA_3D_CMD_READBACK_GB_IMAGE_PARTIAL, &vmw_cmd_invalid,
  1753. false, false, true),
  1754. VMW_CMD_DEF(SVGA_3D_CMD_INVALIDATE_GB_IMAGE_PARTIAL, &vmw_cmd_invalid,
  1755. false, false, true),
  1756. VMW_CMD_DEF(SVGA_3D_CMD_SET_GB_SHADERCONSTS_INLINE, &vmw_cmd_cid_check,
  1757. true, false, true)
  1758. };
  1759. static int vmw_cmd_check(struct vmw_private *dev_priv,
  1760. struct vmw_sw_context *sw_context,
  1761. void *buf, uint32_t *size)
  1762. {
  1763. uint32_t cmd_id;
  1764. uint32_t size_remaining = *size;
  1765. SVGA3dCmdHeader *header = (SVGA3dCmdHeader *) buf;
  1766. int ret;
  1767. const struct vmw_cmd_entry *entry;
  1768. bool gb = dev_priv->capabilities & SVGA_CAP_GBOBJECTS;
  1769. cmd_id = le32_to_cpu(((uint32_t *)buf)[0]);
  1770. /* Handle any none 3D commands */
  1771. if (unlikely(cmd_id < SVGA_CMD_MAX))
  1772. return vmw_cmd_check_not_3d(dev_priv, sw_context, buf, size);
  1773. cmd_id = le32_to_cpu(header->id);
  1774. *size = le32_to_cpu(header->size) + sizeof(SVGA3dCmdHeader);
  1775. cmd_id -= SVGA_3D_CMD_BASE;
  1776. if (unlikely(*size > size_remaining))
  1777. goto out_invalid;
  1778. if (unlikely(cmd_id >= SVGA_3D_CMD_MAX - SVGA_3D_CMD_BASE))
  1779. goto out_invalid;
  1780. entry = &vmw_cmd_entries[cmd_id];
  1781. if (unlikely(!entry->func))
  1782. goto out_invalid;
  1783. if (unlikely(!entry->user_allow && !sw_context->kernel))
  1784. goto out_privileged;
  1785. if (unlikely(entry->gb_disable && gb))
  1786. goto out_old;
  1787. if (unlikely(entry->gb_enable && !gb))
  1788. goto out_new;
  1789. ret = entry->func(dev_priv, sw_context, header);
  1790. if (unlikely(ret != 0))
  1791. goto out_invalid;
  1792. return 0;
  1793. out_invalid:
  1794. DRM_ERROR("Invalid SVGA3D command: %d\n",
  1795. cmd_id + SVGA_3D_CMD_BASE);
  1796. return -EINVAL;
  1797. out_privileged:
  1798. DRM_ERROR("Privileged SVGA3D command: %d\n",
  1799. cmd_id + SVGA_3D_CMD_BASE);
  1800. return -EPERM;
  1801. out_old:
  1802. DRM_ERROR("Deprecated (disallowed) SVGA3D command: %d\n",
  1803. cmd_id + SVGA_3D_CMD_BASE);
  1804. return -EINVAL;
  1805. out_new:
  1806. DRM_ERROR("SVGA3D command: %d not supported by virtual hardware.\n",
  1807. cmd_id + SVGA_3D_CMD_BASE);
  1808. return -EINVAL;
  1809. }
  1810. static int vmw_cmd_check_all(struct vmw_private *dev_priv,
  1811. struct vmw_sw_context *sw_context,
  1812. void *buf,
  1813. uint32_t size)
  1814. {
  1815. int32_t cur_size = size;
  1816. int ret;
  1817. sw_context->buf_start = buf;
  1818. while (cur_size > 0) {
  1819. size = cur_size;
  1820. ret = vmw_cmd_check(dev_priv, sw_context, buf, &size);
  1821. if (unlikely(ret != 0))
  1822. return ret;
  1823. buf = (void *)((unsigned long) buf + size);
  1824. cur_size -= size;
  1825. }
  1826. if (unlikely(cur_size != 0)) {
  1827. DRM_ERROR("Command verifier out of sync.\n");
  1828. return -EINVAL;
  1829. }
  1830. return 0;
  1831. }
  1832. static void vmw_free_relocations(struct vmw_sw_context *sw_context)
  1833. {
  1834. sw_context->cur_reloc = 0;
  1835. }
  1836. static void vmw_apply_relocations(struct vmw_sw_context *sw_context)
  1837. {
  1838. uint32_t i;
  1839. struct vmw_relocation *reloc;
  1840. struct ttm_validate_buffer *validate;
  1841. struct ttm_buffer_object *bo;
  1842. for (i = 0; i < sw_context->cur_reloc; ++i) {
  1843. reloc = &sw_context->relocs[i];
  1844. validate = &sw_context->val_bufs[reloc->index].base;
  1845. bo = validate->bo;
  1846. switch (bo->mem.mem_type) {
  1847. case TTM_PL_VRAM:
  1848. reloc->location->offset += bo->offset;
  1849. reloc->location->gmrId = SVGA_GMR_FRAMEBUFFER;
  1850. break;
  1851. case VMW_PL_GMR:
  1852. reloc->location->gmrId = bo->mem.start;
  1853. break;
  1854. case VMW_PL_MOB:
  1855. *reloc->mob_loc = bo->mem.start;
  1856. break;
  1857. default:
  1858. BUG();
  1859. }
  1860. }
  1861. vmw_free_relocations(sw_context);
  1862. }
  1863. /**
  1864. * vmw_resource_list_unrefererence - Free up a resource list and unreference
  1865. * all resources referenced by it.
  1866. *
  1867. * @list: The resource list.
  1868. */
  1869. static void vmw_resource_list_unreference(struct list_head *list)
  1870. {
  1871. struct vmw_resource_val_node *val, *val_next;
  1872. /*
  1873. * Drop references to resources held during command submission.
  1874. */
  1875. list_for_each_entry_safe(val, val_next, list, head) {
  1876. list_del_init(&val->head);
  1877. vmw_resource_unreference(&val->res);
  1878. if (unlikely(val->staged_bindings))
  1879. kfree(val->staged_bindings);
  1880. kfree(val);
  1881. }
  1882. }
  1883. static void vmw_clear_validations(struct vmw_sw_context *sw_context)
  1884. {
  1885. struct vmw_validate_buffer *entry, *next;
  1886. struct vmw_resource_val_node *val;
  1887. /*
  1888. * Drop references to DMA buffers held during command submission.
  1889. */
  1890. list_for_each_entry_safe(entry, next, &sw_context->validate_nodes,
  1891. base.head) {
  1892. list_del(&entry->base.head);
  1893. ttm_bo_unref(&entry->base.bo);
  1894. (void) drm_ht_remove_item(&sw_context->res_ht, &entry->hash);
  1895. sw_context->cur_val_buf--;
  1896. }
  1897. BUG_ON(sw_context->cur_val_buf != 0);
  1898. list_for_each_entry(val, &sw_context->resource_list, head)
  1899. (void) drm_ht_remove_item(&sw_context->res_ht, &val->hash);
  1900. }
  1901. static int vmw_validate_single_buffer(struct vmw_private *dev_priv,
  1902. struct ttm_buffer_object *bo,
  1903. bool validate_as_mob)
  1904. {
  1905. int ret;
  1906. /*
  1907. * Don't validate pinned buffers.
  1908. */
  1909. if (bo == dev_priv->pinned_bo ||
  1910. (bo == dev_priv->dummy_query_bo &&
  1911. dev_priv->dummy_query_bo_pinned))
  1912. return 0;
  1913. if (validate_as_mob)
  1914. return ttm_bo_validate(bo, &vmw_mob_placement, true, false);
  1915. /**
  1916. * Put BO in VRAM if there is space, otherwise as a GMR.
  1917. * If there is no space in VRAM and GMR ids are all used up,
  1918. * start evicting GMRs to make room. If the DMA buffer can't be
  1919. * used as a GMR, this will return -ENOMEM.
  1920. */
  1921. ret = ttm_bo_validate(bo, &vmw_vram_gmr_placement, true, false);
  1922. if (likely(ret == 0 || ret == -ERESTARTSYS))
  1923. return ret;
  1924. /**
  1925. * If that failed, try VRAM again, this time evicting
  1926. * previous contents.
  1927. */
  1928. DRM_INFO("Falling through to VRAM.\n");
  1929. ret = ttm_bo_validate(bo, &vmw_vram_placement, true, false);
  1930. return ret;
  1931. }
  1932. static int vmw_validate_buffers(struct vmw_private *dev_priv,
  1933. struct vmw_sw_context *sw_context)
  1934. {
  1935. struct vmw_validate_buffer *entry;
  1936. int ret;
  1937. list_for_each_entry(entry, &sw_context->validate_nodes, base.head) {
  1938. ret = vmw_validate_single_buffer(dev_priv, entry->base.bo,
  1939. entry->validate_as_mob);
  1940. if (unlikely(ret != 0))
  1941. return ret;
  1942. }
  1943. return 0;
  1944. }
  1945. static int vmw_resize_cmd_bounce(struct vmw_sw_context *sw_context,
  1946. uint32_t size)
  1947. {
  1948. if (likely(sw_context->cmd_bounce_size >= size))
  1949. return 0;
  1950. if (sw_context->cmd_bounce_size == 0)
  1951. sw_context->cmd_bounce_size = VMWGFX_CMD_BOUNCE_INIT_SIZE;
  1952. while (sw_context->cmd_bounce_size < size) {
  1953. sw_context->cmd_bounce_size =
  1954. PAGE_ALIGN(sw_context->cmd_bounce_size +
  1955. (sw_context->cmd_bounce_size >> 1));
  1956. }
  1957. if (sw_context->cmd_bounce != NULL)
  1958. vfree(sw_context->cmd_bounce);
  1959. sw_context->cmd_bounce = vmalloc(sw_context->cmd_bounce_size);
  1960. if (sw_context->cmd_bounce == NULL) {
  1961. DRM_ERROR("Failed to allocate command bounce buffer.\n");
  1962. sw_context->cmd_bounce_size = 0;
  1963. return -ENOMEM;
  1964. }
  1965. return 0;
  1966. }
  1967. /**
  1968. * vmw_execbuf_fence_commands - create and submit a command stream fence
  1969. *
  1970. * Creates a fence object and submits a command stream marker.
  1971. * If this fails for some reason, We sync the fifo and return NULL.
  1972. * It is then safe to fence buffers with a NULL pointer.
  1973. *
  1974. * If @p_handle is not NULL @file_priv must also not be NULL. Creates
  1975. * a userspace handle if @p_handle is not NULL, otherwise not.
  1976. */
  1977. int vmw_execbuf_fence_commands(struct drm_file *file_priv,
  1978. struct vmw_private *dev_priv,
  1979. struct vmw_fence_obj **p_fence,
  1980. uint32_t *p_handle)
  1981. {
  1982. uint32_t sequence;
  1983. int ret;
  1984. bool synced = false;
  1985. /* p_handle implies file_priv. */
  1986. BUG_ON(p_handle != NULL && file_priv == NULL);
  1987. ret = vmw_fifo_send_fence(dev_priv, &sequence);
  1988. if (unlikely(ret != 0)) {
  1989. DRM_ERROR("Fence submission error. Syncing.\n");
  1990. synced = true;
  1991. }
  1992. if (p_handle != NULL)
  1993. ret = vmw_user_fence_create(file_priv, dev_priv->fman,
  1994. sequence,
  1995. DRM_VMW_FENCE_FLAG_EXEC,
  1996. p_fence, p_handle);
  1997. else
  1998. ret = vmw_fence_create(dev_priv->fman, sequence,
  1999. DRM_VMW_FENCE_FLAG_EXEC,
  2000. p_fence);
  2001. if (unlikely(ret != 0 && !synced)) {
  2002. (void) vmw_fallback_wait(dev_priv, false, false,
  2003. sequence, false,
  2004. VMW_FENCE_WAIT_TIMEOUT);
  2005. *p_fence = NULL;
  2006. }
  2007. return 0;
  2008. }
  2009. /**
  2010. * vmw_execbuf_copy_fence_user - copy fence object information to
  2011. * user-space.
  2012. *
  2013. * @dev_priv: Pointer to a vmw_private struct.
  2014. * @vmw_fp: Pointer to the struct vmw_fpriv representing the calling file.
  2015. * @ret: Return value from fence object creation.
  2016. * @user_fence_rep: User space address of a struct drm_vmw_fence_rep to
  2017. * which the information should be copied.
  2018. * @fence: Pointer to the fenc object.
  2019. * @fence_handle: User-space fence handle.
  2020. *
  2021. * This function copies fence information to user-space. If copying fails,
  2022. * The user-space struct drm_vmw_fence_rep::error member is hopefully
  2023. * left untouched, and if it's preloaded with an -EFAULT by user-space,
  2024. * the error will hopefully be detected.
  2025. * Also if copying fails, user-space will be unable to signal the fence
  2026. * object so we wait for it immediately, and then unreference the
  2027. * user-space reference.
  2028. */
  2029. void
  2030. vmw_execbuf_copy_fence_user(struct vmw_private *dev_priv,
  2031. struct vmw_fpriv *vmw_fp,
  2032. int ret,
  2033. struct drm_vmw_fence_rep __user *user_fence_rep,
  2034. struct vmw_fence_obj *fence,
  2035. uint32_t fence_handle)
  2036. {
  2037. struct drm_vmw_fence_rep fence_rep;
  2038. if (user_fence_rep == NULL)
  2039. return;
  2040. memset(&fence_rep, 0, sizeof(fence_rep));
  2041. fence_rep.error = ret;
  2042. if (ret == 0) {
  2043. BUG_ON(fence == NULL);
  2044. fence_rep.handle = fence_handle;
  2045. fence_rep.seqno = fence->seqno;
  2046. vmw_update_seqno(dev_priv, &dev_priv->fifo);
  2047. fence_rep.passed_seqno = dev_priv->last_read_seqno;
  2048. }
  2049. /*
  2050. * copy_to_user errors will be detected by user space not
  2051. * seeing fence_rep::error filled in. Typically
  2052. * user-space would have pre-set that member to -EFAULT.
  2053. */
  2054. ret = copy_to_user(user_fence_rep, &fence_rep,
  2055. sizeof(fence_rep));
  2056. /*
  2057. * User-space lost the fence object. We need to sync
  2058. * and unreference the handle.
  2059. */
  2060. if (unlikely(ret != 0) && (fence_rep.error == 0)) {
  2061. ttm_ref_object_base_unref(vmw_fp->tfile,
  2062. fence_handle, TTM_REF_USAGE);
  2063. DRM_ERROR("Fence copy error. Syncing.\n");
  2064. (void) vmw_fence_obj_wait(fence, fence->signal_mask,
  2065. false, false,
  2066. VMW_FENCE_WAIT_TIMEOUT);
  2067. }
  2068. }
  2069. int vmw_execbuf_process(struct drm_file *file_priv,
  2070. struct vmw_private *dev_priv,
  2071. void __user *user_commands,
  2072. void *kernel_commands,
  2073. uint32_t command_size,
  2074. uint64_t throttle_us,
  2075. struct drm_vmw_fence_rep __user *user_fence_rep,
  2076. struct vmw_fence_obj **out_fence)
  2077. {
  2078. struct vmw_sw_context *sw_context = &dev_priv->ctx;
  2079. struct vmw_fence_obj *fence = NULL;
  2080. struct vmw_resource *error_resource;
  2081. struct list_head resource_list;
  2082. struct ww_acquire_ctx ticket;
  2083. uint32_t handle;
  2084. void *cmd;
  2085. int ret;
  2086. ret = mutex_lock_interruptible(&dev_priv->cmdbuf_mutex);
  2087. if (unlikely(ret != 0))
  2088. return -ERESTARTSYS;
  2089. if (kernel_commands == NULL) {
  2090. sw_context->kernel = false;
  2091. ret = vmw_resize_cmd_bounce(sw_context, command_size);
  2092. if (unlikely(ret != 0))
  2093. goto out_unlock;
  2094. ret = copy_from_user(sw_context->cmd_bounce,
  2095. user_commands, command_size);
  2096. if (unlikely(ret != 0)) {
  2097. ret = -EFAULT;
  2098. DRM_ERROR("Failed copying commands.\n");
  2099. goto out_unlock;
  2100. }
  2101. kernel_commands = sw_context->cmd_bounce;
  2102. } else
  2103. sw_context->kernel = true;
  2104. sw_context->fp = vmw_fpriv(file_priv);
  2105. sw_context->cur_reloc = 0;
  2106. sw_context->cur_val_buf = 0;
  2107. sw_context->fence_flags = 0;
  2108. INIT_LIST_HEAD(&sw_context->resource_list);
  2109. sw_context->cur_query_bo = dev_priv->pinned_bo;
  2110. sw_context->last_query_ctx = NULL;
  2111. sw_context->needs_post_query_barrier = false;
  2112. memset(sw_context->res_cache, 0, sizeof(sw_context->res_cache));
  2113. INIT_LIST_HEAD(&sw_context->validate_nodes);
  2114. INIT_LIST_HEAD(&sw_context->res_relocations);
  2115. if (!sw_context->res_ht_initialized) {
  2116. ret = drm_ht_create(&sw_context->res_ht, VMW_RES_HT_ORDER);
  2117. if (unlikely(ret != 0))
  2118. goto out_unlock;
  2119. sw_context->res_ht_initialized = true;
  2120. }
  2121. INIT_LIST_HEAD(&sw_context->staged_shaders);
  2122. INIT_LIST_HEAD(&resource_list);
  2123. ret = vmw_cmd_check_all(dev_priv, sw_context, kernel_commands,
  2124. command_size);
  2125. if (unlikely(ret != 0))
  2126. goto out_err_nores;
  2127. ret = vmw_resources_reserve(sw_context);
  2128. if (unlikely(ret != 0))
  2129. goto out_err_nores;
  2130. ret = ttm_eu_reserve_buffers(&ticket, &sw_context->validate_nodes);
  2131. if (unlikely(ret != 0))
  2132. goto out_err;
  2133. ret = vmw_validate_buffers(dev_priv, sw_context);
  2134. if (unlikely(ret != 0))
  2135. goto out_err;
  2136. ret = vmw_resources_validate(sw_context);
  2137. if (unlikely(ret != 0))
  2138. goto out_err;
  2139. if (throttle_us) {
  2140. ret = vmw_wait_lag(dev_priv, &dev_priv->fifo.marker_queue,
  2141. throttle_us);
  2142. if (unlikely(ret != 0))
  2143. goto out_err;
  2144. }
  2145. ret = mutex_lock_interruptible(&dev_priv->binding_mutex);
  2146. if (unlikely(ret != 0)) {
  2147. ret = -ERESTARTSYS;
  2148. goto out_err;
  2149. }
  2150. if (dev_priv->has_mob) {
  2151. ret = vmw_rebind_contexts(sw_context);
  2152. if (unlikely(ret != 0))
  2153. goto out_unlock_binding;
  2154. }
  2155. cmd = vmw_fifo_reserve(dev_priv, command_size);
  2156. if (unlikely(cmd == NULL)) {
  2157. DRM_ERROR("Failed reserving fifo space for commands.\n");
  2158. ret = -ENOMEM;
  2159. goto out_unlock_binding;
  2160. }
  2161. vmw_apply_relocations(sw_context);
  2162. memcpy(cmd, kernel_commands, command_size);
  2163. vmw_resource_relocations_apply(cmd, &sw_context->res_relocations);
  2164. vmw_resource_relocations_free(&sw_context->res_relocations);
  2165. vmw_fifo_commit(dev_priv, command_size);
  2166. vmw_query_bo_switch_commit(dev_priv, sw_context);
  2167. ret = vmw_execbuf_fence_commands(file_priv, dev_priv,
  2168. &fence,
  2169. (user_fence_rep) ? &handle : NULL);
  2170. /*
  2171. * This error is harmless, because if fence submission fails,
  2172. * vmw_fifo_send_fence will sync. The error will be propagated to
  2173. * user-space in @fence_rep
  2174. */
  2175. if (ret != 0)
  2176. DRM_ERROR("Fence submission error. Syncing.\n");
  2177. vmw_resource_list_unreserve(&sw_context->resource_list, false);
  2178. mutex_unlock(&dev_priv->binding_mutex);
  2179. ttm_eu_fence_buffer_objects(&ticket, &sw_context->validate_nodes,
  2180. (void *) fence);
  2181. if (unlikely(dev_priv->pinned_bo != NULL &&
  2182. !dev_priv->query_cid_valid))
  2183. __vmw_execbuf_release_pinned_bo(dev_priv, fence);
  2184. vmw_clear_validations(sw_context);
  2185. vmw_execbuf_copy_fence_user(dev_priv, vmw_fpriv(file_priv), ret,
  2186. user_fence_rep, fence, handle);
  2187. /* Don't unreference when handing fence out */
  2188. if (unlikely(out_fence != NULL)) {
  2189. *out_fence = fence;
  2190. fence = NULL;
  2191. } else if (likely(fence != NULL)) {
  2192. vmw_fence_obj_unreference(&fence);
  2193. }
  2194. list_splice_init(&sw_context->resource_list, &resource_list);
  2195. vmw_compat_shaders_commit(sw_context->fp->shman,
  2196. &sw_context->staged_shaders);
  2197. mutex_unlock(&dev_priv->cmdbuf_mutex);
  2198. /*
  2199. * Unreference resources outside of the cmdbuf_mutex to
  2200. * avoid deadlocks in resource destruction paths.
  2201. */
  2202. vmw_resource_list_unreference(&resource_list);
  2203. return 0;
  2204. out_unlock_binding:
  2205. mutex_unlock(&dev_priv->binding_mutex);
  2206. out_err:
  2207. ttm_eu_backoff_reservation(&ticket, &sw_context->validate_nodes);
  2208. out_err_nores:
  2209. vmw_resource_list_unreserve(&sw_context->resource_list, true);
  2210. vmw_resource_relocations_free(&sw_context->res_relocations);
  2211. vmw_free_relocations(sw_context);
  2212. vmw_clear_validations(sw_context);
  2213. if (unlikely(dev_priv->pinned_bo != NULL &&
  2214. !dev_priv->query_cid_valid))
  2215. __vmw_execbuf_release_pinned_bo(dev_priv, NULL);
  2216. out_unlock:
  2217. list_splice_init(&sw_context->resource_list, &resource_list);
  2218. error_resource = sw_context->error_resource;
  2219. sw_context->error_resource = NULL;
  2220. vmw_compat_shaders_revert(sw_context->fp->shman,
  2221. &sw_context->staged_shaders);
  2222. mutex_unlock(&dev_priv->cmdbuf_mutex);
  2223. /*
  2224. * Unreference resources outside of the cmdbuf_mutex to
  2225. * avoid deadlocks in resource destruction paths.
  2226. */
  2227. vmw_resource_list_unreference(&resource_list);
  2228. if (unlikely(error_resource != NULL))
  2229. vmw_resource_unreference(&error_resource);
  2230. return ret;
  2231. }
  2232. /**
  2233. * vmw_execbuf_unpin_panic - Idle the fifo and unpin the query buffer.
  2234. *
  2235. * @dev_priv: The device private structure.
  2236. *
  2237. * This function is called to idle the fifo and unpin the query buffer
  2238. * if the normal way to do this hits an error, which should typically be
  2239. * extremely rare.
  2240. */
  2241. static void vmw_execbuf_unpin_panic(struct vmw_private *dev_priv)
  2242. {
  2243. DRM_ERROR("Can't unpin query buffer. Trying to recover.\n");
  2244. (void) vmw_fallback_wait(dev_priv, false, true, 0, false, 10*HZ);
  2245. vmw_bo_pin(dev_priv->pinned_bo, false);
  2246. vmw_bo_pin(dev_priv->dummy_query_bo, false);
  2247. dev_priv->dummy_query_bo_pinned = false;
  2248. }
  2249. /**
  2250. * __vmw_execbuf_release_pinned_bo - Flush queries and unpin the pinned
  2251. * query bo.
  2252. *
  2253. * @dev_priv: The device private structure.
  2254. * @fence: If non-NULL should point to a struct vmw_fence_obj issued
  2255. * _after_ a query barrier that flushes all queries touching the current
  2256. * buffer pointed to by @dev_priv->pinned_bo
  2257. *
  2258. * This function should be used to unpin the pinned query bo, or
  2259. * as a query barrier when we need to make sure that all queries have
  2260. * finished before the next fifo command. (For example on hardware
  2261. * context destructions where the hardware may otherwise leak unfinished
  2262. * queries).
  2263. *
  2264. * This function does not return any failure codes, but make attempts
  2265. * to do safe unpinning in case of errors.
  2266. *
  2267. * The function will synchronize on the previous query barrier, and will
  2268. * thus not finish until that barrier has executed.
  2269. *
  2270. * the @dev_priv->cmdbuf_mutex needs to be held by the current thread
  2271. * before calling this function.
  2272. */
  2273. void __vmw_execbuf_release_pinned_bo(struct vmw_private *dev_priv,
  2274. struct vmw_fence_obj *fence)
  2275. {
  2276. int ret = 0;
  2277. struct list_head validate_list;
  2278. struct ttm_validate_buffer pinned_val, query_val;
  2279. struct vmw_fence_obj *lfence = NULL;
  2280. struct ww_acquire_ctx ticket;
  2281. if (dev_priv->pinned_bo == NULL)
  2282. goto out_unlock;
  2283. INIT_LIST_HEAD(&validate_list);
  2284. pinned_val.bo = ttm_bo_reference(dev_priv->pinned_bo);
  2285. list_add_tail(&pinned_val.head, &validate_list);
  2286. query_val.bo = ttm_bo_reference(dev_priv->dummy_query_bo);
  2287. list_add_tail(&query_val.head, &validate_list);
  2288. do {
  2289. ret = ttm_eu_reserve_buffers(&ticket, &validate_list);
  2290. } while (ret == -ERESTARTSYS);
  2291. if (unlikely(ret != 0)) {
  2292. vmw_execbuf_unpin_panic(dev_priv);
  2293. goto out_no_reserve;
  2294. }
  2295. if (dev_priv->query_cid_valid) {
  2296. BUG_ON(fence != NULL);
  2297. ret = vmw_fifo_emit_dummy_query(dev_priv, dev_priv->query_cid);
  2298. if (unlikely(ret != 0)) {
  2299. vmw_execbuf_unpin_panic(dev_priv);
  2300. goto out_no_emit;
  2301. }
  2302. dev_priv->query_cid_valid = false;
  2303. }
  2304. vmw_bo_pin(dev_priv->pinned_bo, false);
  2305. vmw_bo_pin(dev_priv->dummy_query_bo, false);
  2306. dev_priv->dummy_query_bo_pinned = false;
  2307. if (fence == NULL) {
  2308. (void) vmw_execbuf_fence_commands(NULL, dev_priv, &lfence,
  2309. NULL);
  2310. fence = lfence;
  2311. }
  2312. ttm_eu_fence_buffer_objects(&ticket, &validate_list, (void *) fence);
  2313. if (lfence != NULL)
  2314. vmw_fence_obj_unreference(&lfence);
  2315. ttm_bo_unref(&query_val.bo);
  2316. ttm_bo_unref(&pinned_val.bo);
  2317. ttm_bo_unref(&dev_priv->pinned_bo);
  2318. out_unlock:
  2319. return;
  2320. out_no_emit:
  2321. ttm_eu_backoff_reservation(&ticket, &validate_list);
  2322. out_no_reserve:
  2323. ttm_bo_unref(&query_val.bo);
  2324. ttm_bo_unref(&pinned_val.bo);
  2325. ttm_bo_unref(&dev_priv->pinned_bo);
  2326. }
  2327. /**
  2328. * vmw_execbuf_release_pinned_bo - Flush queries and unpin the pinned
  2329. * query bo.
  2330. *
  2331. * @dev_priv: The device private structure.
  2332. *
  2333. * This function should be used to unpin the pinned query bo, or
  2334. * as a query barrier when we need to make sure that all queries have
  2335. * finished before the next fifo command. (For example on hardware
  2336. * context destructions where the hardware may otherwise leak unfinished
  2337. * queries).
  2338. *
  2339. * This function does not return any failure codes, but make attempts
  2340. * to do safe unpinning in case of errors.
  2341. *
  2342. * The function will synchronize on the previous query barrier, and will
  2343. * thus not finish until that barrier has executed.
  2344. */
  2345. void vmw_execbuf_release_pinned_bo(struct vmw_private *dev_priv)
  2346. {
  2347. mutex_lock(&dev_priv->cmdbuf_mutex);
  2348. if (dev_priv->query_cid_valid)
  2349. __vmw_execbuf_release_pinned_bo(dev_priv, NULL);
  2350. mutex_unlock(&dev_priv->cmdbuf_mutex);
  2351. }
  2352. int vmw_execbuf_ioctl(struct drm_device *dev, void *data,
  2353. struct drm_file *file_priv)
  2354. {
  2355. struct vmw_private *dev_priv = vmw_priv(dev);
  2356. struct drm_vmw_execbuf_arg *arg = (struct drm_vmw_execbuf_arg *)data;
  2357. struct vmw_master *vmaster = vmw_master(file_priv->master);
  2358. int ret;
  2359. /*
  2360. * This will allow us to extend the ioctl argument while
  2361. * maintaining backwards compatibility:
  2362. * We take different code paths depending on the value of
  2363. * arg->version.
  2364. */
  2365. if (unlikely(arg->version != DRM_VMW_EXECBUF_VERSION)) {
  2366. DRM_ERROR("Incorrect execbuf version.\n");
  2367. DRM_ERROR("You're running outdated experimental "
  2368. "vmwgfx user-space drivers.");
  2369. return -EINVAL;
  2370. }
  2371. ret = ttm_read_lock(&vmaster->lock, true);
  2372. if (unlikely(ret != 0))
  2373. return ret;
  2374. ret = vmw_execbuf_process(file_priv, dev_priv,
  2375. (void __user *)(unsigned long)arg->commands,
  2376. NULL, arg->command_size, arg->throttle_us,
  2377. (void __user *)(unsigned long)arg->fence_rep,
  2378. NULL);
  2379. if (unlikely(ret != 0))
  2380. goto out_unlock;
  2381. vmw_kms_cursor_post_execbuf(dev_priv);
  2382. out_unlock:
  2383. ttm_read_unlock(&vmaster->lock);
  2384. return ret;
  2385. }