mdp4_kms.h 6.1 KB

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  1. /*
  2. * Copyright (C) 2013 Red Hat
  3. * Author: Rob Clark <robdclark@gmail.com>
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License version 2 as published by
  7. * the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program. If not, see <http://www.gnu.org/licenses/>.
  16. */
  17. #ifndef __MDP4_KMS_H__
  18. #define __MDP4_KMS_H__
  19. #include "msm_drv.h"
  20. #include "msm_kms.h"
  21. #include "mdp/mdp_kms.h"
  22. #include "mdp4.xml.h"
  23. struct mdp4_kms {
  24. struct mdp_kms base;
  25. struct drm_device *dev;
  26. int rev;
  27. /* mapper-id used to request GEM buffer mapped for scanout: */
  28. int id;
  29. void __iomem *mmio;
  30. struct regulator *dsi_pll_vdda;
  31. struct regulator *dsi_pll_vddio;
  32. struct regulator *vdd;
  33. struct clk *clk;
  34. struct clk *pclk;
  35. struct clk *lut_clk;
  36. struct mdp_irq error_handler;
  37. };
  38. #define to_mdp4_kms(x) container_of(x, struct mdp4_kms, base)
  39. /* platform config data (ie. from DT, or pdata) */
  40. struct mdp4_platform_config {
  41. struct iommu_domain *iommu;
  42. uint32_t max_clk;
  43. };
  44. static inline void mdp4_write(struct mdp4_kms *mdp4_kms, u32 reg, u32 data)
  45. {
  46. msm_writel(data, mdp4_kms->mmio + reg);
  47. }
  48. static inline u32 mdp4_read(struct mdp4_kms *mdp4_kms, u32 reg)
  49. {
  50. return msm_readl(mdp4_kms->mmio + reg);
  51. }
  52. static inline uint32_t pipe2flush(enum mdp4_pipe pipe)
  53. {
  54. switch (pipe) {
  55. case VG1: return MDP4_OVERLAY_FLUSH_VG1;
  56. case VG2: return MDP4_OVERLAY_FLUSH_VG2;
  57. case RGB1: return MDP4_OVERLAY_FLUSH_RGB1;
  58. case RGB2: return MDP4_OVERLAY_FLUSH_RGB1;
  59. default: return 0;
  60. }
  61. }
  62. static inline uint32_t ovlp2flush(int ovlp)
  63. {
  64. switch (ovlp) {
  65. case 0: return MDP4_OVERLAY_FLUSH_OVLP0;
  66. case 1: return MDP4_OVERLAY_FLUSH_OVLP1;
  67. default: return 0;
  68. }
  69. }
  70. static inline uint32_t dma2irq(enum mdp4_dma dma)
  71. {
  72. switch (dma) {
  73. case DMA_P: return MDP4_IRQ_DMA_P_DONE;
  74. case DMA_S: return MDP4_IRQ_DMA_S_DONE;
  75. case DMA_E: return MDP4_IRQ_DMA_E_DONE;
  76. default: return 0;
  77. }
  78. }
  79. static inline uint32_t dma2err(enum mdp4_dma dma)
  80. {
  81. switch (dma) {
  82. case DMA_P: return MDP4_IRQ_PRIMARY_INTF_UDERRUN;
  83. case DMA_S: return 0; // ???
  84. case DMA_E: return MDP4_IRQ_EXTERNAL_INTF_UDERRUN;
  85. default: return 0;
  86. }
  87. }
  88. static inline uint32_t mixercfg(int mixer, enum mdp4_pipe pipe,
  89. enum mdp_mixer_stage_id stage)
  90. {
  91. uint32_t mixer_cfg = 0;
  92. switch (pipe) {
  93. case VG1:
  94. mixer_cfg = MDP4_LAYERMIXER_IN_CFG_PIPE0(stage) |
  95. COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE0_MIXER1);
  96. break;
  97. case VG2:
  98. mixer_cfg = MDP4_LAYERMIXER_IN_CFG_PIPE1(stage) |
  99. COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE1_MIXER1);
  100. break;
  101. case RGB1:
  102. mixer_cfg = MDP4_LAYERMIXER_IN_CFG_PIPE2(stage) |
  103. COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE2_MIXER1);
  104. break;
  105. case RGB2:
  106. mixer_cfg = MDP4_LAYERMIXER_IN_CFG_PIPE3(stage) |
  107. COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE3_MIXER1);
  108. break;
  109. case RGB3:
  110. mixer_cfg = MDP4_LAYERMIXER_IN_CFG_PIPE4(stage) |
  111. COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE4_MIXER1);
  112. break;
  113. case VG3:
  114. mixer_cfg = MDP4_LAYERMIXER_IN_CFG_PIPE5(stage) |
  115. COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE5_MIXER1);
  116. break;
  117. case VG4:
  118. mixer_cfg = MDP4_LAYERMIXER_IN_CFG_PIPE6(stage) |
  119. COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE6_MIXER1);
  120. break;
  121. default:
  122. WARN_ON("invalid pipe");
  123. break;
  124. }
  125. return mixer_cfg;
  126. }
  127. int mdp4_disable(struct mdp4_kms *mdp4_kms);
  128. int mdp4_enable(struct mdp4_kms *mdp4_kms);
  129. void mdp4_set_irqmask(struct mdp_kms *mdp_kms, uint32_t irqmask);
  130. void mdp4_irq_preinstall(struct msm_kms *kms);
  131. int mdp4_irq_postinstall(struct msm_kms *kms);
  132. void mdp4_irq_uninstall(struct msm_kms *kms);
  133. irqreturn_t mdp4_irq(struct msm_kms *kms);
  134. int mdp4_enable_vblank(struct msm_kms *kms, struct drm_crtc *crtc);
  135. void mdp4_disable_vblank(struct msm_kms *kms, struct drm_crtc *crtc);
  136. static inline
  137. uint32_t mdp4_get_formats(enum mdp4_pipe pipe_id, uint32_t *pixel_formats,
  138. uint32_t max_formats)
  139. {
  140. /* TODO when we have YUV, we need to filter supported formats
  141. * based on pipe_id..
  142. */
  143. return mdp_get_formats(pixel_formats, max_formats);
  144. }
  145. void mdp4_plane_install_properties(struct drm_plane *plane,
  146. struct drm_mode_object *obj);
  147. void mdp4_plane_set_scanout(struct drm_plane *plane,
  148. struct drm_framebuffer *fb);
  149. int mdp4_plane_mode_set(struct drm_plane *plane,
  150. struct drm_crtc *crtc, struct drm_framebuffer *fb,
  151. int crtc_x, int crtc_y,
  152. unsigned int crtc_w, unsigned int crtc_h,
  153. uint32_t src_x, uint32_t src_y,
  154. uint32_t src_w, uint32_t src_h);
  155. enum mdp4_pipe mdp4_plane_pipe(struct drm_plane *plane);
  156. struct drm_plane *mdp4_plane_init(struct drm_device *dev,
  157. enum mdp4_pipe pipe_id, bool private_plane);
  158. uint32_t mdp4_crtc_vblank(struct drm_crtc *crtc);
  159. void mdp4_crtc_cancel_pending_flip(struct drm_crtc *crtc, struct drm_file *file);
  160. void mdp4_crtc_set_config(struct drm_crtc *crtc, uint32_t config);
  161. void mdp4_crtc_set_intf(struct drm_crtc *crtc, enum mdp4_intf intf);
  162. void mdp4_crtc_attach(struct drm_crtc *crtc, struct drm_plane *plane);
  163. void mdp4_crtc_detach(struct drm_crtc *crtc, struct drm_plane *plane);
  164. struct drm_crtc *mdp4_crtc_init(struct drm_device *dev,
  165. struct drm_plane *plane, int id, int ovlp_id,
  166. enum mdp4_dma dma_id);
  167. long mdp4_dtv_round_pixclk(struct drm_encoder *encoder, unsigned long rate);
  168. struct drm_encoder *mdp4_dtv_encoder_init(struct drm_device *dev);
  169. #ifdef CONFIG_MSM_BUS_SCALING
  170. static inline int match_dev_name(struct device *dev, void *data)
  171. {
  172. return !strcmp(dev_name(dev), data);
  173. }
  174. /* bus scaling data is associated with extra pointless platform devices,
  175. * "dtv", etc.. this is a bit of a hack, but we need a way for encoders
  176. * to find their pdata to make the bus-scaling stuff work.
  177. */
  178. static inline void *mdp4_find_pdata(const char *devname)
  179. {
  180. struct device *dev;
  181. dev = bus_find_device(&platform_bus_type, NULL,
  182. (void *)devname, match_dev_name);
  183. return dev ? dev->platform_data : NULL;
  184. }
  185. #endif
  186. #endif /* __MDP4_KMS_H__ */