hdmi_bridge.c 6.3 KB

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  1. /*
  2. * Copyright (C) 2013 Red Hat
  3. * Author: Rob Clark <robdclark@gmail.com>
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License version 2 as published by
  7. * the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program. If not, see <http://www.gnu.org/licenses/>.
  16. */
  17. #include "hdmi.h"
  18. struct hdmi_bridge {
  19. struct drm_bridge base;
  20. struct hdmi *hdmi;
  21. bool power_on;
  22. unsigned long int pixclock;
  23. };
  24. #define to_hdmi_bridge(x) container_of(x, struct hdmi_bridge, base)
  25. static void hdmi_bridge_destroy(struct drm_bridge *bridge)
  26. {
  27. struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge);
  28. hdmi_unreference(hdmi_bridge->hdmi);
  29. drm_bridge_cleanup(bridge);
  30. kfree(hdmi_bridge);
  31. }
  32. static void power_on(struct drm_bridge *bridge)
  33. {
  34. struct drm_device *dev = bridge->dev;
  35. struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge);
  36. struct hdmi *hdmi = hdmi_bridge->hdmi;
  37. const struct hdmi_platform_config *config = hdmi->config;
  38. int i, ret;
  39. for (i = 0; i < config->pwr_reg_cnt; i++) {
  40. ret = regulator_enable(hdmi->pwr_regs[i]);
  41. if (ret) {
  42. dev_err(dev->dev, "failed to enable pwr regulator: %s (%d)\n",
  43. config->pwr_reg_names[i], ret);
  44. }
  45. }
  46. if (config->pwr_clk_cnt > 0) {
  47. DBG("pixclock: %lu", hdmi_bridge->pixclock);
  48. ret = clk_set_rate(hdmi->pwr_clks[0], hdmi_bridge->pixclock);
  49. if (ret) {
  50. dev_err(dev->dev, "failed to set pixel clk: %s (%d)\n",
  51. config->pwr_clk_names[0], ret);
  52. }
  53. }
  54. for (i = 0; i < config->pwr_clk_cnt; i++) {
  55. ret = clk_prepare_enable(hdmi->pwr_clks[i]);
  56. if (ret) {
  57. dev_err(dev->dev, "failed to enable pwr clk: %s (%d)\n",
  58. config->pwr_clk_names[i], ret);
  59. }
  60. }
  61. }
  62. static void power_off(struct drm_bridge *bridge)
  63. {
  64. struct drm_device *dev = bridge->dev;
  65. struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge);
  66. struct hdmi *hdmi = hdmi_bridge->hdmi;
  67. const struct hdmi_platform_config *config = hdmi->config;
  68. int i, ret;
  69. /* TODO do we need to wait for final vblank somewhere before
  70. * cutting the clocks?
  71. */
  72. mdelay(16 + 4);
  73. for (i = 0; i < config->pwr_clk_cnt; i++)
  74. clk_disable_unprepare(hdmi->pwr_clks[i]);
  75. for (i = 0; i < config->pwr_reg_cnt; i++) {
  76. ret = regulator_disable(hdmi->pwr_regs[i]);
  77. if (ret) {
  78. dev_err(dev->dev, "failed to disable pwr regulator: %s (%d)\n",
  79. config->pwr_reg_names[i], ret);
  80. }
  81. }
  82. }
  83. static void hdmi_bridge_pre_enable(struct drm_bridge *bridge)
  84. {
  85. struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge);
  86. struct hdmi *hdmi = hdmi_bridge->hdmi;
  87. struct hdmi_phy *phy = hdmi->phy;
  88. DBG("power up");
  89. if (!hdmi_bridge->power_on) {
  90. power_on(bridge);
  91. hdmi_bridge->power_on = true;
  92. }
  93. phy->funcs->powerup(phy, hdmi_bridge->pixclock);
  94. hdmi_set_mode(hdmi, true);
  95. }
  96. static void hdmi_bridge_enable(struct drm_bridge *bridge)
  97. {
  98. }
  99. static void hdmi_bridge_disable(struct drm_bridge *bridge)
  100. {
  101. }
  102. static void hdmi_bridge_post_disable(struct drm_bridge *bridge)
  103. {
  104. struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge);
  105. struct hdmi *hdmi = hdmi_bridge->hdmi;
  106. struct hdmi_phy *phy = hdmi->phy;
  107. DBG("power down");
  108. hdmi_set_mode(hdmi, false);
  109. phy->funcs->powerdown(phy);
  110. if (hdmi_bridge->power_on) {
  111. power_off(bridge);
  112. hdmi_bridge->power_on = false;
  113. }
  114. }
  115. static void hdmi_bridge_mode_set(struct drm_bridge *bridge,
  116. struct drm_display_mode *mode,
  117. struct drm_display_mode *adjusted_mode)
  118. {
  119. struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge);
  120. struct hdmi *hdmi = hdmi_bridge->hdmi;
  121. int hstart, hend, vstart, vend;
  122. uint32_t frame_ctrl;
  123. mode = adjusted_mode;
  124. hdmi_bridge->pixclock = mode->clock * 1000;
  125. hdmi->hdmi_mode = drm_match_cea_mode(mode) > 1;
  126. hstart = mode->htotal - mode->hsync_start;
  127. hend = mode->htotal - mode->hsync_start + mode->hdisplay;
  128. vstart = mode->vtotal - mode->vsync_start - 1;
  129. vend = mode->vtotal - mode->vsync_start + mode->vdisplay - 1;
  130. DBG("htotal=%d, vtotal=%d, hstart=%d, hend=%d, vstart=%d, vend=%d",
  131. mode->htotal, mode->vtotal, hstart, hend, vstart, vend);
  132. hdmi_write(hdmi, REG_HDMI_TOTAL,
  133. HDMI_TOTAL_H_TOTAL(mode->htotal - 1) |
  134. HDMI_TOTAL_V_TOTAL(mode->vtotal - 1));
  135. hdmi_write(hdmi, REG_HDMI_ACTIVE_HSYNC,
  136. HDMI_ACTIVE_HSYNC_START(hstart) |
  137. HDMI_ACTIVE_HSYNC_END(hend));
  138. hdmi_write(hdmi, REG_HDMI_ACTIVE_VSYNC,
  139. HDMI_ACTIVE_VSYNC_START(vstart) |
  140. HDMI_ACTIVE_VSYNC_END(vend));
  141. if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
  142. hdmi_write(hdmi, REG_HDMI_VSYNC_TOTAL_F2,
  143. HDMI_VSYNC_TOTAL_F2_V_TOTAL(mode->vtotal));
  144. hdmi_write(hdmi, REG_HDMI_VSYNC_ACTIVE_F2,
  145. HDMI_VSYNC_ACTIVE_F2_START(vstart + 1) |
  146. HDMI_VSYNC_ACTIVE_F2_END(vend + 1));
  147. } else {
  148. hdmi_write(hdmi, REG_HDMI_VSYNC_TOTAL_F2,
  149. HDMI_VSYNC_TOTAL_F2_V_TOTAL(0));
  150. hdmi_write(hdmi, REG_HDMI_VSYNC_ACTIVE_F2,
  151. HDMI_VSYNC_ACTIVE_F2_START(0) |
  152. HDMI_VSYNC_ACTIVE_F2_END(0));
  153. }
  154. frame_ctrl = 0;
  155. if (mode->flags & DRM_MODE_FLAG_NHSYNC)
  156. frame_ctrl |= HDMI_FRAME_CTRL_HSYNC_LOW;
  157. if (mode->flags & DRM_MODE_FLAG_NVSYNC)
  158. frame_ctrl |= HDMI_FRAME_CTRL_VSYNC_LOW;
  159. if (mode->flags & DRM_MODE_FLAG_INTERLACE)
  160. frame_ctrl |= HDMI_FRAME_CTRL_INTERLACED_EN;
  161. DBG("frame_ctrl=%08x", frame_ctrl);
  162. hdmi_write(hdmi, REG_HDMI_FRAME_CTRL, frame_ctrl);
  163. // TODO until we have audio, this might be safest:
  164. if (hdmi->hdmi_mode)
  165. hdmi_write(hdmi, REG_HDMI_GC, HDMI_GC_MUTE);
  166. }
  167. static const struct drm_bridge_funcs hdmi_bridge_funcs = {
  168. .pre_enable = hdmi_bridge_pre_enable,
  169. .enable = hdmi_bridge_enable,
  170. .disable = hdmi_bridge_disable,
  171. .post_disable = hdmi_bridge_post_disable,
  172. .mode_set = hdmi_bridge_mode_set,
  173. .destroy = hdmi_bridge_destroy,
  174. };
  175. /* initialize bridge */
  176. struct drm_bridge *hdmi_bridge_init(struct hdmi *hdmi)
  177. {
  178. struct drm_bridge *bridge = NULL;
  179. struct hdmi_bridge *hdmi_bridge;
  180. int ret;
  181. hdmi_bridge = kzalloc(sizeof(*hdmi_bridge), GFP_KERNEL);
  182. if (!hdmi_bridge) {
  183. ret = -ENOMEM;
  184. goto fail;
  185. }
  186. hdmi_bridge->hdmi = hdmi_reference(hdmi);
  187. bridge = &hdmi_bridge->base;
  188. drm_bridge_init(hdmi->dev, bridge, &hdmi_bridge_funcs);
  189. return bridge;
  190. fail:
  191. if (bridge)
  192. hdmi_bridge_destroy(bridge);
  193. return ERR_PTR(ret);
  194. }