intel_dsi.c 19 KB

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  1. /*
  2. * Copyright © 2013 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21. * DEALINGS IN THE SOFTWARE.
  22. *
  23. * Author: Jani Nikula <jani.nikula@intel.com>
  24. */
  25. #include <drm/drmP.h>
  26. #include <drm/drm_crtc.h>
  27. #include <drm/drm_edid.h>
  28. #include <drm/i915_drm.h>
  29. #include <linux/slab.h>
  30. #include "i915_drv.h"
  31. #include "intel_drv.h"
  32. #include "intel_dsi.h"
  33. #include "intel_dsi_cmd.h"
  34. /* the sub-encoders aka panel drivers */
  35. static const struct intel_dsi_device intel_dsi_devices[] = {
  36. };
  37. static void band_gap_reset(struct drm_i915_private *dev_priv)
  38. {
  39. mutex_lock(&dev_priv->dpio_lock);
  40. vlv_flisdsi_write(dev_priv, 0x08, 0x0001);
  41. vlv_flisdsi_write(dev_priv, 0x0F, 0x0005);
  42. vlv_flisdsi_write(dev_priv, 0x0F, 0x0025);
  43. udelay(150);
  44. vlv_flisdsi_write(dev_priv, 0x0F, 0x0000);
  45. vlv_flisdsi_write(dev_priv, 0x08, 0x0000);
  46. mutex_unlock(&dev_priv->dpio_lock);
  47. }
  48. static struct intel_dsi *intel_attached_dsi(struct drm_connector *connector)
  49. {
  50. return container_of(intel_attached_encoder(connector),
  51. struct intel_dsi, base);
  52. }
  53. static inline bool is_vid_mode(struct intel_dsi *intel_dsi)
  54. {
  55. return intel_dsi->dev.type == INTEL_DSI_VIDEO_MODE;
  56. }
  57. static inline bool is_cmd_mode(struct intel_dsi *intel_dsi)
  58. {
  59. return intel_dsi->dev.type == INTEL_DSI_COMMAND_MODE;
  60. }
  61. static void intel_dsi_hot_plug(struct intel_encoder *encoder)
  62. {
  63. DRM_DEBUG_KMS("\n");
  64. }
  65. static bool intel_dsi_compute_config(struct intel_encoder *encoder,
  66. struct intel_crtc_config *config)
  67. {
  68. struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
  69. base);
  70. struct intel_connector *intel_connector = intel_dsi->attached_connector;
  71. struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
  72. struct drm_display_mode *adjusted_mode = &config->adjusted_mode;
  73. struct drm_display_mode *mode = &config->requested_mode;
  74. DRM_DEBUG_KMS("\n");
  75. if (fixed_mode)
  76. intel_fixed_panel_mode(fixed_mode, adjusted_mode);
  77. if (intel_dsi->dev.dev_ops->mode_fixup)
  78. return intel_dsi->dev.dev_ops->mode_fixup(&intel_dsi->dev,
  79. mode, adjusted_mode);
  80. return true;
  81. }
  82. static void intel_dsi_pre_pll_enable(struct intel_encoder *encoder)
  83. {
  84. DRM_DEBUG_KMS("\n");
  85. vlv_enable_dsi_pll(encoder);
  86. }
  87. static void intel_dsi_device_ready(struct intel_encoder *encoder)
  88. {
  89. struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
  90. struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
  91. int pipe = intel_crtc->pipe;
  92. u32 val;
  93. DRM_DEBUG_KMS("\n");
  94. val = I915_READ(MIPI_PORT_CTRL(pipe));
  95. I915_WRITE(MIPI_PORT_CTRL(pipe), val | LP_OUTPUT_HOLD);
  96. usleep_range(1000, 1500);
  97. I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY | ULPS_STATE_EXIT);
  98. usleep_range(2000, 2500);
  99. I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY);
  100. usleep_range(2000, 2500);
  101. I915_WRITE(MIPI_DEVICE_READY(pipe), 0x00);
  102. usleep_range(2000, 2500);
  103. I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY);
  104. usleep_range(2000, 2500);
  105. }
  106. static void intel_dsi_pre_enable(struct intel_encoder *encoder)
  107. {
  108. struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
  109. DRM_DEBUG_KMS("\n");
  110. if (intel_dsi->dev.dev_ops->panel_reset)
  111. intel_dsi->dev.dev_ops->panel_reset(&intel_dsi->dev);
  112. /* put device in ready state */
  113. intel_dsi_device_ready(encoder);
  114. if (intel_dsi->dev.dev_ops->send_otp_cmds)
  115. intel_dsi->dev.dev_ops->send_otp_cmds(&intel_dsi->dev);
  116. }
  117. static void intel_dsi_enable(struct intel_encoder *encoder)
  118. {
  119. struct drm_device *dev = encoder->base.dev;
  120. struct drm_i915_private *dev_priv = dev->dev_private;
  121. struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
  122. struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
  123. int pipe = intel_crtc->pipe;
  124. u32 temp;
  125. DRM_DEBUG_KMS("\n");
  126. if (is_cmd_mode(intel_dsi))
  127. I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(pipe), 8 * 4);
  128. else {
  129. msleep(20); /* XXX */
  130. dpi_send_cmd(intel_dsi, TURN_ON);
  131. msleep(100);
  132. /* assert ip_tg_enable signal */
  133. temp = I915_READ(MIPI_PORT_CTRL(pipe)) & ~LANE_CONFIGURATION_MASK;
  134. temp = temp | intel_dsi->port_bits;
  135. I915_WRITE(MIPI_PORT_CTRL(pipe), temp | DPI_ENABLE);
  136. POSTING_READ(MIPI_PORT_CTRL(pipe));
  137. }
  138. if (intel_dsi->dev.dev_ops->enable)
  139. intel_dsi->dev.dev_ops->enable(&intel_dsi->dev);
  140. }
  141. static void intel_dsi_disable(struct intel_encoder *encoder)
  142. {
  143. struct drm_device *dev = encoder->base.dev;
  144. struct drm_i915_private *dev_priv = dev->dev_private;
  145. struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
  146. struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
  147. int pipe = intel_crtc->pipe;
  148. u32 temp;
  149. DRM_DEBUG_KMS("\n");
  150. if (is_vid_mode(intel_dsi)) {
  151. dpi_send_cmd(intel_dsi, SHUTDOWN);
  152. msleep(10);
  153. /* de-assert ip_tg_enable signal */
  154. temp = I915_READ(MIPI_PORT_CTRL(pipe));
  155. I915_WRITE(MIPI_PORT_CTRL(pipe), temp & ~DPI_ENABLE);
  156. POSTING_READ(MIPI_PORT_CTRL(pipe));
  157. msleep(2);
  158. }
  159. /* if disable packets are sent before sending shutdown packet then in
  160. * some next enable sequence send turn on packet error is observed */
  161. if (intel_dsi->dev.dev_ops->disable)
  162. intel_dsi->dev.dev_ops->disable(&intel_dsi->dev);
  163. }
  164. static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
  165. {
  166. struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
  167. struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
  168. int pipe = intel_crtc->pipe;
  169. u32 val;
  170. DRM_DEBUG_KMS("\n");
  171. I915_WRITE(MIPI_DEVICE_READY(pipe), ULPS_STATE_ENTER);
  172. usleep_range(2000, 2500);
  173. I915_WRITE(MIPI_DEVICE_READY(pipe), ULPS_STATE_EXIT);
  174. usleep_range(2000, 2500);
  175. I915_WRITE(MIPI_DEVICE_READY(pipe), ULPS_STATE_ENTER);
  176. usleep_range(2000, 2500);
  177. val = I915_READ(MIPI_PORT_CTRL(pipe));
  178. I915_WRITE(MIPI_PORT_CTRL(pipe), val & ~LP_OUTPUT_HOLD);
  179. usleep_range(1000, 1500);
  180. if (wait_for(((I915_READ(MIPI_PORT_CTRL(pipe)) & AFE_LATCHOUT)
  181. == 0x00000), 30))
  182. DRM_ERROR("DSI LP not going Low\n");
  183. I915_WRITE(MIPI_DEVICE_READY(pipe), 0x00);
  184. usleep_range(2000, 2500);
  185. vlv_disable_dsi_pll(encoder);
  186. }
  187. static void intel_dsi_post_disable(struct intel_encoder *encoder)
  188. {
  189. struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
  190. DRM_DEBUG_KMS("\n");
  191. intel_dsi_clear_device_ready(encoder);
  192. if (intel_dsi->dev.dev_ops->disable_panel_power)
  193. intel_dsi->dev.dev_ops->disable_panel_power(&intel_dsi->dev);
  194. }
  195. static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
  196. enum pipe *pipe)
  197. {
  198. struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
  199. u32 port, func;
  200. enum pipe p;
  201. DRM_DEBUG_KMS("\n");
  202. /* XXX: this only works for one DSI output */
  203. for (p = PIPE_A; p <= PIPE_B; p++) {
  204. port = I915_READ(MIPI_PORT_CTRL(p));
  205. func = I915_READ(MIPI_DSI_FUNC_PRG(p));
  206. if ((port & DPI_ENABLE) || (func & CMD_MODE_DATA_WIDTH_MASK)) {
  207. if (I915_READ(MIPI_DEVICE_READY(p)) & DEVICE_READY) {
  208. *pipe = p;
  209. return true;
  210. }
  211. }
  212. }
  213. return false;
  214. }
  215. static void intel_dsi_get_config(struct intel_encoder *encoder,
  216. struct intel_crtc_config *pipe_config)
  217. {
  218. DRM_DEBUG_KMS("\n");
  219. /* XXX: read flags, set to adjusted_mode */
  220. }
  221. static enum drm_mode_status
  222. intel_dsi_mode_valid(struct drm_connector *connector,
  223. struct drm_display_mode *mode)
  224. {
  225. struct intel_connector *intel_connector = to_intel_connector(connector);
  226. struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
  227. struct intel_dsi *intel_dsi = intel_attached_dsi(connector);
  228. DRM_DEBUG_KMS("\n");
  229. if (mode->flags & DRM_MODE_FLAG_DBLSCAN) {
  230. DRM_DEBUG_KMS("MODE_NO_DBLESCAN\n");
  231. return MODE_NO_DBLESCAN;
  232. }
  233. if (fixed_mode) {
  234. if (mode->hdisplay > fixed_mode->hdisplay)
  235. return MODE_PANEL;
  236. if (mode->vdisplay > fixed_mode->vdisplay)
  237. return MODE_PANEL;
  238. }
  239. return intel_dsi->dev.dev_ops->mode_valid(&intel_dsi->dev, mode);
  240. }
  241. /* return txclkesc cycles in terms of divider and duration in us */
  242. static u16 txclkesc(u32 divider, unsigned int us)
  243. {
  244. switch (divider) {
  245. case ESCAPE_CLOCK_DIVIDER_1:
  246. default:
  247. return 20 * us;
  248. case ESCAPE_CLOCK_DIVIDER_2:
  249. return 10 * us;
  250. case ESCAPE_CLOCK_DIVIDER_4:
  251. return 5 * us;
  252. }
  253. }
  254. /* return pixels in terms of txbyteclkhs */
  255. static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count)
  256. {
  257. return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp, 8), lane_count);
  258. }
  259. static void set_dsi_timings(struct drm_encoder *encoder,
  260. const struct drm_display_mode *mode)
  261. {
  262. struct drm_device *dev = encoder->dev;
  263. struct drm_i915_private *dev_priv = dev->dev_private;
  264. struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
  265. struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
  266. int pipe = intel_crtc->pipe;
  267. unsigned int bpp = intel_crtc->config.pipe_bpp;
  268. unsigned int lane_count = intel_dsi->lane_count;
  269. u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
  270. hactive = mode->hdisplay;
  271. hfp = mode->hsync_start - mode->hdisplay;
  272. hsync = mode->hsync_end - mode->hsync_start;
  273. hbp = mode->htotal - mode->hsync_end;
  274. vfp = mode->vsync_start - mode->vdisplay;
  275. vsync = mode->vsync_end - mode->vsync_start;
  276. vbp = mode->vtotal - mode->vsync_end;
  277. /* horizontal values are in terms of high speed byte clock */
  278. hactive = txbyteclkhs(hactive, bpp, lane_count);
  279. hfp = txbyteclkhs(hfp, bpp, lane_count);
  280. hsync = txbyteclkhs(hsync, bpp, lane_count);
  281. hbp = txbyteclkhs(hbp, bpp, lane_count);
  282. I915_WRITE(MIPI_HACTIVE_AREA_COUNT(pipe), hactive);
  283. I915_WRITE(MIPI_HFP_COUNT(pipe), hfp);
  284. /* meaningful for video mode non-burst sync pulse mode only, can be zero
  285. * for non-burst sync events and burst modes */
  286. I915_WRITE(MIPI_HSYNC_PADDING_COUNT(pipe), hsync);
  287. I915_WRITE(MIPI_HBP_COUNT(pipe), hbp);
  288. /* vertical values are in terms of lines */
  289. I915_WRITE(MIPI_VFP_COUNT(pipe), vfp);
  290. I915_WRITE(MIPI_VSYNC_PADDING_COUNT(pipe), vsync);
  291. I915_WRITE(MIPI_VBP_COUNT(pipe), vbp);
  292. }
  293. static void intel_dsi_mode_set(struct intel_encoder *intel_encoder)
  294. {
  295. struct drm_encoder *encoder = &intel_encoder->base;
  296. struct drm_device *dev = encoder->dev;
  297. struct drm_i915_private *dev_priv = dev->dev_private;
  298. struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
  299. struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
  300. struct drm_display_mode *adjusted_mode =
  301. &intel_crtc->config.adjusted_mode;
  302. int pipe = intel_crtc->pipe;
  303. unsigned int bpp = intel_crtc->config.pipe_bpp;
  304. u32 val, tmp;
  305. DRM_DEBUG_KMS("pipe %c\n", pipe_name(pipe));
  306. /* XXX: Location of the call */
  307. band_gap_reset(dev_priv);
  308. /* escape clock divider, 20MHz, shared for A and C. device ready must be
  309. * off when doing this! txclkesc? */
  310. tmp = I915_READ(MIPI_CTRL(0));
  311. tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
  312. I915_WRITE(MIPI_CTRL(0), tmp | ESCAPE_CLOCK_DIVIDER_1);
  313. /* read request priority is per pipe */
  314. tmp = I915_READ(MIPI_CTRL(pipe));
  315. tmp &= ~READ_REQUEST_PRIORITY_MASK;
  316. I915_WRITE(MIPI_CTRL(pipe), tmp | READ_REQUEST_PRIORITY_HIGH);
  317. /* XXX: why here, why like this? handling in irq handler?! */
  318. I915_WRITE(MIPI_INTR_STAT(pipe), 0xffffffff);
  319. I915_WRITE(MIPI_INTR_EN(pipe), 0xffffffff);
  320. I915_WRITE(MIPI_DPHY_PARAM(pipe), intel_dsi->dphy_reg);
  321. I915_WRITE(MIPI_DPI_RESOLUTION(pipe),
  322. adjusted_mode->vdisplay << VERTICAL_ADDRESS_SHIFT |
  323. adjusted_mode->hdisplay << HORIZONTAL_ADDRESS_SHIFT);
  324. set_dsi_timings(encoder, adjusted_mode);
  325. val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT;
  326. if (is_cmd_mode(intel_dsi)) {
  327. val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT;
  328. val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */
  329. } else {
  330. val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT;
  331. /* XXX: cross-check bpp vs. pixel format? */
  332. val |= intel_dsi->pixel_format;
  333. }
  334. I915_WRITE(MIPI_DSI_FUNC_PRG(pipe), val);
  335. /* timeouts for recovery. one frame IIUC. if counter expires, EOT and
  336. * stop state. */
  337. /*
  338. * In burst mode, value greater than one DPI line Time in byte clock
  339. * (txbyteclkhs) To timeout this timer 1+ of the above said value is
  340. * recommended.
  341. *
  342. * In non-burst mode, Value greater than one DPI frame time in byte
  343. * clock(txbyteclkhs) To timeout this timer 1+ of the above said value
  344. * is recommended.
  345. *
  346. * In DBI only mode, value greater than one DBI frame time in byte
  347. * clock(txbyteclkhs) To timeout this timer 1+ of the above said value
  348. * is recommended.
  349. */
  350. if (is_vid_mode(intel_dsi) &&
  351. intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
  352. I915_WRITE(MIPI_HS_TX_TIMEOUT(pipe),
  353. txbyteclkhs(adjusted_mode->htotal, bpp,
  354. intel_dsi->lane_count) + 1);
  355. } else {
  356. I915_WRITE(MIPI_HS_TX_TIMEOUT(pipe),
  357. txbyteclkhs(adjusted_mode->vtotal *
  358. adjusted_mode->htotal,
  359. bpp, intel_dsi->lane_count) + 1);
  360. }
  361. I915_WRITE(MIPI_LP_RX_TIMEOUT(pipe), intel_dsi->lp_rx_timeout);
  362. I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(pipe), intel_dsi->turn_arnd_val);
  363. I915_WRITE(MIPI_DEVICE_RESET_TIMER(pipe), intel_dsi->rst_timer_val);
  364. /* dphy stuff */
  365. /* in terms of low power clock */
  366. I915_WRITE(MIPI_INIT_COUNT(pipe), txclkesc(ESCAPE_CLOCK_DIVIDER_1, 100));
  367. /* recovery disables */
  368. I915_WRITE(MIPI_EOT_DISABLE(pipe), intel_dsi->eot_disable);
  369. /* in terms of txbyteclkhs. actual high to low switch +
  370. * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK.
  371. *
  372. * XXX: write MIPI_STOP_STATE_STALL?
  373. */
  374. I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(pipe),
  375. intel_dsi->hs_to_lp_count);
  376. /* XXX: low power clock equivalence in terms of byte clock. the number
  377. * of byte clocks occupied in one low power clock. based on txbyteclkhs
  378. * and txclkesc. txclkesc time / txbyteclk time * (105 +
  379. * MIPI_STOP_STATE_STALL) / 105.???
  380. */
  381. I915_WRITE(MIPI_LP_BYTECLK(pipe), intel_dsi->lp_byte_clk);
  382. /* the bw essential for transmitting 16 long packets containing 252
  383. * bytes meant for dcs write memory command is programmed in this
  384. * register in terms of byte clocks. based on dsi transfer rate and the
  385. * number of lanes configured the time taken to transmit 16 long packets
  386. * in a dsi stream varies. */
  387. I915_WRITE(MIPI_DBI_BW_CTRL(pipe), intel_dsi->bw_timer);
  388. I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(pipe),
  389. intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT |
  390. intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT);
  391. if (is_vid_mode(intel_dsi))
  392. I915_WRITE(MIPI_VIDEO_MODE_FORMAT(pipe),
  393. intel_dsi->video_frmt_cfg_bits |
  394. intel_dsi->video_mode_format);
  395. }
  396. static enum drm_connector_status
  397. intel_dsi_detect(struct drm_connector *connector, bool force)
  398. {
  399. struct intel_dsi *intel_dsi = intel_attached_dsi(connector);
  400. DRM_DEBUG_KMS("\n");
  401. return intel_dsi->dev.dev_ops->detect(&intel_dsi->dev);
  402. }
  403. static int intel_dsi_get_modes(struct drm_connector *connector)
  404. {
  405. struct intel_connector *intel_connector = to_intel_connector(connector);
  406. struct drm_display_mode *mode;
  407. DRM_DEBUG_KMS("\n");
  408. if (!intel_connector->panel.fixed_mode) {
  409. DRM_DEBUG_KMS("no fixed mode\n");
  410. return 0;
  411. }
  412. mode = drm_mode_duplicate(connector->dev,
  413. intel_connector->panel.fixed_mode);
  414. if (!mode) {
  415. DRM_DEBUG_KMS("drm_mode_duplicate failed\n");
  416. return 0;
  417. }
  418. drm_mode_probed_add(connector, mode);
  419. return 1;
  420. }
  421. static void intel_dsi_destroy(struct drm_connector *connector)
  422. {
  423. struct intel_connector *intel_connector = to_intel_connector(connector);
  424. DRM_DEBUG_KMS("\n");
  425. intel_panel_fini(&intel_connector->panel);
  426. drm_connector_cleanup(connector);
  427. kfree(connector);
  428. }
  429. static const struct drm_encoder_funcs intel_dsi_funcs = {
  430. .destroy = intel_encoder_destroy,
  431. };
  432. static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = {
  433. .get_modes = intel_dsi_get_modes,
  434. .mode_valid = intel_dsi_mode_valid,
  435. .best_encoder = intel_best_encoder,
  436. };
  437. static const struct drm_connector_funcs intel_dsi_connector_funcs = {
  438. .dpms = intel_connector_dpms,
  439. .detect = intel_dsi_detect,
  440. .destroy = intel_dsi_destroy,
  441. .fill_modes = drm_helper_probe_single_connector_modes,
  442. };
  443. bool intel_dsi_init(struct drm_device *dev)
  444. {
  445. struct intel_dsi *intel_dsi;
  446. struct intel_encoder *intel_encoder;
  447. struct drm_encoder *encoder;
  448. struct intel_connector *intel_connector;
  449. struct drm_connector *connector;
  450. struct drm_display_mode *fixed_mode = NULL;
  451. const struct intel_dsi_device *dsi;
  452. unsigned int i;
  453. DRM_DEBUG_KMS("\n");
  454. intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
  455. if (!intel_dsi)
  456. return false;
  457. intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
  458. if (!intel_connector) {
  459. kfree(intel_dsi);
  460. return false;
  461. }
  462. intel_encoder = &intel_dsi->base;
  463. encoder = &intel_encoder->base;
  464. intel_dsi->attached_connector = intel_connector;
  465. connector = &intel_connector->base;
  466. drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI);
  467. /* XXX: very likely not all of these are needed */
  468. intel_encoder->hot_plug = intel_dsi_hot_plug;
  469. intel_encoder->compute_config = intel_dsi_compute_config;
  470. intel_encoder->pre_pll_enable = intel_dsi_pre_pll_enable;
  471. intel_encoder->pre_enable = intel_dsi_pre_enable;
  472. intel_encoder->enable = intel_dsi_enable;
  473. intel_encoder->mode_set = intel_dsi_mode_set;
  474. intel_encoder->disable = intel_dsi_disable;
  475. intel_encoder->post_disable = intel_dsi_post_disable;
  476. intel_encoder->get_hw_state = intel_dsi_get_hw_state;
  477. intel_encoder->get_config = intel_dsi_get_config;
  478. intel_connector->get_hw_state = intel_connector_get_hw_state;
  479. for (i = 0; i < ARRAY_SIZE(intel_dsi_devices); i++) {
  480. dsi = &intel_dsi_devices[i];
  481. intel_dsi->dev = *dsi;
  482. if (dsi->dev_ops->init(&intel_dsi->dev))
  483. break;
  484. }
  485. if (i == ARRAY_SIZE(intel_dsi_devices)) {
  486. DRM_DEBUG_KMS("no device found\n");
  487. goto err;
  488. }
  489. intel_encoder->type = INTEL_OUTPUT_DSI;
  490. intel_encoder->crtc_mask = (1 << 0); /* XXX */
  491. intel_encoder->cloneable = false;
  492. drm_connector_init(dev, connector, &intel_dsi_connector_funcs,
  493. DRM_MODE_CONNECTOR_DSI);
  494. drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs);
  495. connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/
  496. connector->interlace_allowed = false;
  497. connector->doublescan_allowed = false;
  498. intel_connector_attach_encoder(intel_connector, intel_encoder);
  499. drm_sysfs_connector_add(connector);
  500. fixed_mode = dsi->dev_ops->get_modes(&intel_dsi->dev);
  501. if (!fixed_mode) {
  502. DRM_DEBUG_KMS("no fixed mode\n");
  503. goto err;
  504. }
  505. fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
  506. intel_panel_init(&intel_connector->panel, fixed_mode);
  507. return true;
  508. err:
  509. drm_encoder_cleanup(&intel_encoder->base);
  510. kfree(intel_dsi);
  511. kfree(intel_connector);
  512. return false;
  513. }