i915_gpu_error.c 28 KB

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  1. /*
  2. * Copyright (c) 2008 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21. * IN THE SOFTWARE.
  22. *
  23. * Authors:
  24. * Eric Anholt <eric@anholt.net>
  25. * Keith Packard <keithp@keithp.com>
  26. * Mika Kuoppala <mika.kuoppala@intel.com>
  27. *
  28. */
  29. #include <generated/utsrelease.h>
  30. #include "i915_drv.h"
  31. static const char *yesno(int v)
  32. {
  33. return v ? "yes" : "no";
  34. }
  35. static const char *ring_str(int ring)
  36. {
  37. switch (ring) {
  38. case RCS: return "render";
  39. case VCS: return "bsd";
  40. case BCS: return "blt";
  41. case VECS: return "vebox";
  42. default: return "";
  43. }
  44. }
  45. static const char *pin_flag(int pinned)
  46. {
  47. if (pinned > 0)
  48. return " P";
  49. else if (pinned < 0)
  50. return " p";
  51. else
  52. return "";
  53. }
  54. static const char *tiling_flag(int tiling)
  55. {
  56. switch (tiling) {
  57. default:
  58. case I915_TILING_NONE: return "";
  59. case I915_TILING_X: return " X";
  60. case I915_TILING_Y: return " Y";
  61. }
  62. }
  63. static const char *dirty_flag(int dirty)
  64. {
  65. return dirty ? " dirty" : "";
  66. }
  67. static const char *purgeable_flag(int purgeable)
  68. {
  69. return purgeable ? " purgeable" : "";
  70. }
  71. static bool __i915_error_ok(struct drm_i915_error_state_buf *e)
  72. {
  73. if (!e->err && WARN(e->bytes > (e->size - 1), "overflow")) {
  74. e->err = -ENOSPC;
  75. return false;
  76. }
  77. if (e->bytes == e->size - 1 || e->err)
  78. return false;
  79. return true;
  80. }
  81. static bool __i915_error_seek(struct drm_i915_error_state_buf *e,
  82. unsigned len)
  83. {
  84. if (e->pos + len <= e->start) {
  85. e->pos += len;
  86. return false;
  87. }
  88. /* First vsnprintf needs to fit in its entirety for memmove */
  89. if (len >= e->size) {
  90. e->err = -EIO;
  91. return false;
  92. }
  93. return true;
  94. }
  95. static void __i915_error_advance(struct drm_i915_error_state_buf *e,
  96. unsigned len)
  97. {
  98. /* If this is first printf in this window, adjust it so that
  99. * start position matches start of the buffer
  100. */
  101. if (e->pos < e->start) {
  102. const size_t off = e->start - e->pos;
  103. /* Should not happen but be paranoid */
  104. if (off > len || e->bytes) {
  105. e->err = -EIO;
  106. return;
  107. }
  108. memmove(e->buf, e->buf + off, len - off);
  109. e->bytes = len - off;
  110. e->pos = e->start;
  111. return;
  112. }
  113. e->bytes += len;
  114. e->pos += len;
  115. }
  116. static void i915_error_vprintf(struct drm_i915_error_state_buf *e,
  117. const char *f, va_list args)
  118. {
  119. unsigned len;
  120. if (!__i915_error_ok(e))
  121. return;
  122. /* Seek the first printf which is hits start position */
  123. if (e->pos < e->start) {
  124. va_list tmp;
  125. va_copy(tmp, args);
  126. len = vsnprintf(NULL, 0, f, tmp);
  127. va_end(tmp);
  128. if (!__i915_error_seek(e, len))
  129. return;
  130. }
  131. len = vsnprintf(e->buf + e->bytes, e->size - e->bytes, f, args);
  132. if (len >= e->size - e->bytes)
  133. len = e->size - e->bytes - 1;
  134. __i915_error_advance(e, len);
  135. }
  136. static void i915_error_puts(struct drm_i915_error_state_buf *e,
  137. const char *str)
  138. {
  139. unsigned len;
  140. if (!__i915_error_ok(e))
  141. return;
  142. len = strlen(str);
  143. /* Seek the first printf which is hits start position */
  144. if (e->pos < e->start) {
  145. if (!__i915_error_seek(e, len))
  146. return;
  147. }
  148. if (len >= e->size - e->bytes)
  149. len = e->size - e->bytes - 1;
  150. memcpy(e->buf + e->bytes, str, len);
  151. __i915_error_advance(e, len);
  152. }
  153. #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
  154. #define err_puts(e, s) i915_error_puts(e, s)
  155. static void print_error_buffers(struct drm_i915_error_state_buf *m,
  156. const char *name,
  157. struct drm_i915_error_buffer *err,
  158. int count)
  159. {
  160. err_printf(m, "%s [%d]:\n", name, count);
  161. while (count--) {
  162. err_printf(m, " %08x %8u %02x %02x %x %x",
  163. err->gtt_offset,
  164. err->size,
  165. err->read_domains,
  166. err->write_domain,
  167. err->rseqno, err->wseqno);
  168. err_puts(m, pin_flag(err->pinned));
  169. err_puts(m, tiling_flag(err->tiling));
  170. err_puts(m, dirty_flag(err->dirty));
  171. err_puts(m, purgeable_flag(err->purgeable));
  172. err_puts(m, err->ring != -1 ? " " : "");
  173. err_puts(m, ring_str(err->ring));
  174. err_puts(m, i915_cache_level_str(err->cache_level));
  175. if (err->name)
  176. err_printf(m, " (name: %d)", err->name);
  177. if (err->fence_reg != I915_FENCE_REG_NONE)
  178. err_printf(m, " (fence: %d)", err->fence_reg);
  179. err_puts(m, "\n");
  180. err++;
  181. }
  182. }
  183. static const char *hangcheck_action_to_str(enum intel_ring_hangcheck_action a)
  184. {
  185. switch (a) {
  186. case HANGCHECK_IDLE:
  187. return "idle";
  188. case HANGCHECK_WAIT:
  189. return "wait";
  190. case HANGCHECK_ACTIVE:
  191. return "active";
  192. case HANGCHECK_KICK:
  193. return "kick";
  194. case HANGCHECK_HUNG:
  195. return "hung";
  196. }
  197. return "unknown";
  198. }
  199. static void i915_ring_error_state(struct drm_i915_error_state_buf *m,
  200. struct drm_device *dev,
  201. struct drm_i915_error_state *error,
  202. unsigned ring)
  203. {
  204. BUG_ON(ring >= I915_NUM_RINGS); /* shut up confused gcc */
  205. if (!error->ring[ring].valid)
  206. return;
  207. err_printf(m, "%s command stream:\n", ring_str(ring));
  208. err_printf(m, " HEAD: 0x%08x\n", error->head[ring]);
  209. err_printf(m, " TAIL: 0x%08x\n", error->tail[ring]);
  210. err_printf(m, " CTL: 0x%08x\n", error->ctl[ring]);
  211. err_printf(m, " ACTHD: 0x%08x\n", error->acthd[ring]);
  212. err_printf(m, " IPEIR: 0x%08x\n", error->ipeir[ring]);
  213. err_printf(m, " IPEHR: 0x%08x\n", error->ipehr[ring]);
  214. err_printf(m, " INSTDONE: 0x%08x\n", error->instdone[ring]);
  215. if (INTEL_INFO(dev)->gen >= 4) {
  216. err_printf(m, " BBADDR: 0x%08llx\n", error->bbaddr[ring]);
  217. err_printf(m, " BB_STATE: 0x%08x\n", error->bbstate[ring]);
  218. err_printf(m, " INSTPS: 0x%08x\n", error->instps[ring]);
  219. }
  220. err_printf(m, " INSTPM: 0x%08x\n", error->instpm[ring]);
  221. err_printf(m, " FADDR: 0x%08x\n", error->faddr[ring]);
  222. if (INTEL_INFO(dev)->gen >= 6) {
  223. err_printf(m, " RC PSMI: 0x%08x\n", error->rc_psmi[ring]);
  224. err_printf(m, " FAULT_REG: 0x%08x\n", error->fault_reg[ring]);
  225. err_printf(m, " SYNC_0: 0x%08x [last synced 0x%08x]\n",
  226. error->semaphore_mboxes[ring][0],
  227. error->semaphore_seqno[ring][0]);
  228. err_printf(m, " SYNC_1: 0x%08x [last synced 0x%08x]\n",
  229. error->semaphore_mboxes[ring][1],
  230. error->semaphore_seqno[ring][1]);
  231. if (HAS_VEBOX(dev)) {
  232. err_printf(m, " SYNC_2: 0x%08x [last synced 0x%08x]\n",
  233. error->semaphore_mboxes[ring][2],
  234. error->semaphore_seqno[ring][2]);
  235. }
  236. }
  237. err_printf(m, " seqno: 0x%08x\n", error->seqno[ring]);
  238. err_printf(m, " waiting: %s\n", yesno(error->waiting[ring]));
  239. err_printf(m, " ring->head: 0x%08x\n", error->cpu_ring_head[ring]);
  240. err_printf(m, " ring->tail: 0x%08x\n", error->cpu_ring_tail[ring]);
  241. err_printf(m, " hangcheck: %s [%d]\n",
  242. hangcheck_action_to_str(error->hangcheck_action[ring]),
  243. error->hangcheck_score[ring]);
  244. }
  245. void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...)
  246. {
  247. va_list args;
  248. va_start(args, f);
  249. i915_error_vprintf(e, f, args);
  250. va_end(args);
  251. }
  252. int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
  253. const struct i915_error_state_file_priv *error_priv)
  254. {
  255. struct drm_device *dev = error_priv->dev;
  256. drm_i915_private_t *dev_priv = dev->dev_private;
  257. struct drm_i915_error_state *error = error_priv->error;
  258. int i, j, page, offset, elt;
  259. if (!error) {
  260. err_printf(m, "no error state collected\n");
  261. goto out;
  262. }
  263. err_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec,
  264. error->time.tv_usec);
  265. err_printf(m, "Kernel: " UTS_RELEASE "\n");
  266. err_printf(m, "PCI ID: 0x%04x\n", dev->pdev->device);
  267. err_printf(m, "EIR: 0x%08x\n", error->eir);
  268. err_printf(m, "IER: 0x%08x\n", error->ier);
  269. err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
  270. err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake);
  271. err_printf(m, "DERRMR: 0x%08x\n", error->derrmr);
  272. err_printf(m, "CCID: 0x%08x\n", error->ccid);
  273. err_printf(m, "Missed interrupts: 0x%08lx\n", dev_priv->gpu_error.missed_irq_rings);
  274. for (i = 0; i < dev_priv->num_fence_regs; i++)
  275. err_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]);
  276. for (i = 0; i < ARRAY_SIZE(error->extra_instdone); i++)
  277. err_printf(m, " INSTDONE_%d: 0x%08x\n", i,
  278. error->extra_instdone[i]);
  279. if (INTEL_INFO(dev)->gen >= 6) {
  280. err_printf(m, "ERROR: 0x%08x\n", error->error);
  281. err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);
  282. }
  283. if (INTEL_INFO(dev)->gen == 7)
  284. err_printf(m, "ERR_INT: 0x%08x\n", error->err_int);
  285. for (i = 0; i < ARRAY_SIZE(error->ring); i++)
  286. i915_ring_error_state(m, dev, error, i);
  287. if (error->active_bo)
  288. print_error_buffers(m, "Active",
  289. error->active_bo[0],
  290. error->active_bo_count[0]);
  291. if (error->pinned_bo)
  292. print_error_buffers(m, "Pinned",
  293. error->pinned_bo[0],
  294. error->pinned_bo_count[0]);
  295. for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
  296. struct drm_i915_error_object *obj;
  297. if ((obj = error->ring[i].batchbuffer)) {
  298. err_printf(m, "%s --- gtt_offset = 0x%08x\n",
  299. dev_priv->ring[i].name,
  300. obj->gtt_offset);
  301. offset = 0;
  302. for (page = 0; page < obj->page_count; page++) {
  303. for (elt = 0; elt < PAGE_SIZE/4; elt++) {
  304. err_printf(m, "%08x : %08x\n", offset,
  305. obj->pages[page][elt]);
  306. offset += 4;
  307. }
  308. }
  309. }
  310. if (error->ring[i].num_requests) {
  311. err_printf(m, "%s --- %d requests\n",
  312. dev_priv->ring[i].name,
  313. error->ring[i].num_requests);
  314. for (j = 0; j < error->ring[i].num_requests; j++) {
  315. err_printf(m, " seqno 0x%08x, emitted %ld, tail 0x%08x\n",
  316. error->ring[i].requests[j].seqno,
  317. error->ring[i].requests[j].jiffies,
  318. error->ring[i].requests[j].tail);
  319. }
  320. }
  321. if ((obj = error->ring[i].ringbuffer)) {
  322. err_printf(m, "%s --- ringbuffer = 0x%08x\n",
  323. dev_priv->ring[i].name,
  324. obj->gtt_offset);
  325. offset = 0;
  326. for (page = 0; page < obj->page_count; page++) {
  327. for (elt = 0; elt < PAGE_SIZE/4; elt++) {
  328. err_printf(m, "%08x : %08x\n",
  329. offset,
  330. obj->pages[page][elt]);
  331. offset += 4;
  332. }
  333. }
  334. }
  335. if ((obj = error->ring[i].ctx)) {
  336. err_printf(m, "%s --- HW Context = 0x%08x\n",
  337. dev_priv->ring[i].name,
  338. obj->gtt_offset);
  339. offset = 0;
  340. for (elt = 0; elt < PAGE_SIZE/16; elt += 4) {
  341. err_printf(m, "[%04x] %08x %08x %08x %08x\n",
  342. offset,
  343. obj->pages[0][elt],
  344. obj->pages[0][elt+1],
  345. obj->pages[0][elt+2],
  346. obj->pages[0][elt+3]);
  347. offset += 16;
  348. }
  349. }
  350. }
  351. if (error->overlay)
  352. intel_overlay_print_error_state(m, error->overlay);
  353. if (error->display)
  354. intel_display_print_error_state(m, dev, error->display);
  355. out:
  356. if (m->bytes == 0 && m->err)
  357. return m->err;
  358. return 0;
  359. }
  360. int i915_error_state_buf_init(struct drm_i915_error_state_buf *ebuf,
  361. size_t count, loff_t pos)
  362. {
  363. memset(ebuf, 0, sizeof(*ebuf));
  364. /* We need to have enough room to store any i915_error_state printf
  365. * so that we can move it to start position.
  366. */
  367. ebuf->size = count + 1 > PAGE_SIZE ? count + 1 : PAGE_SIZE;
  368. ebuf->buf = kmalloc(ebuf->size,
  369. GFP_TEMPORARY | __GFP_NORETRY | __GFP_NOWARN);
  370. if (ebuf->buf == NULL) {
  371. ebuf->size = PAGE_SIZE;
  372. ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY);
  373. }
  374. if (ebuf->buf == NULL) {
  375. ebuf->size = 128;
  376. ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY);
  377. }
  378. if (ebuf->buf == NULL)
  379. return -ENOMEM;
  380. ebuf->start = pos;
  381. return 0;
  382. }
  383. static void i915_error_object_free(struct drm_i915_error_object *obj)
  384. {
  385. int page;
  386. if (obj == NULL)
  387. return;
  388. for (page = 0; page < obj->page_count; page++)
  389. kfree(obj->pages[page]);
  390. kfree(obj);
  391. }
  392. static void i915_error_state_free(struct kref *error_ref)
  393. {
  394. struct drm_i915_error_state *error = container_of(error_ref,
  395. typeof(*error), ref);
  396. int i;
  397. for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
  398. i915_error_object_free(error->ring[i].batchbuffer);
  399. i915_error_object_free(error->ring[i].ringbuffer);
  400. i915_error_object_free(error->ring[i].ctx);
  401. kfree(error->ring[i].requests);
  402. }
  403. kfree(error->active_bo);
  404. kfree(error->overlay);
  405. kfree(error->display);
  406. kfree(error);
  407. }
  408. static struct drm_i915_error_object *
  409. i915_error_object_create_sized(struct drm_i915_private *dev_priv,
  410. struct drm_i915_gem_object *src,
  411. const int num_pages)
  412. {
  413. struct drm_i915_error_object *dst;
  414. int i;
  415. u32 reloc_offset;
  416. if (src == NULL || src->pages == NULL)
  417. return NULL;
  418. dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), GFP_ATOMIC);
  419. if (dst == NULL)
  420. return NULL;
  421. reloc_offset = dst->gtt_offset = i915_gem_obj_ggtt_offset(src);
  422. for (i = 0; i < num_pages; i++) {
  423. unsigned long flags;
  424. void *d;
  425. d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
  426. if (d == NULL)
  427. goto unwind;
  428. local_irq_save(flags);
  429. if (reloc_offset < dev_priv->gtt.mappable_end &&
  430. src->has_global_gtt_mapping) {
  431. void __iomem *s;
  432. /* Simply ignore tiling or any overlapping fence.
  433. * It's part of the error state, and this hopefully
  434. * captures what the GPU read.
  435. */
  436. s = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
  437. reloc_offset);
  438. memcpy_fromio(d, s, PAGE_SIZE);
  439. io_mapping_unmap_atomic(s);
  440. } else if (src->stolen) {
  441. unsigned long offset;
  442. offset = dev_priv->mm.stolen_base;
  443. offset += src->stolen->start;
  444. offset += i << PAGE_SHIFT;
  445. memcpy_fromio(d, (void __iomem *) offset, PAGE_SIZE);
  446. } else {
  447. struct page *page;
  448. void *s;
  449. page = i915_gem_object_get_page(src, i);
  450. drm_clflush_pages(&page, 1);
  451. s = kmap_atomic(page);
  452. memcpy(d, s, PAGE_SIZE);
  453. kunmap_atomic(s);
  454. drm_clflush_pages(&page, 1);
  455. }
  456. local_irq_restore(flags);
  457. dst->pages[i] = d;
  458. reloc_offset += PAGE_SIZE;
  459. }
  460. dst->page_count = num_pages;
  461. return dst;
  462. unwind:
  463. while (i--)
  464. kfree(dst->pages[i]);
  465. kfree(dst);
  466. return NULL;
  467. }
  468. #define i915_error_object_create(dev_priv, src) \
  469. i915_error_object_create_sized((dev_priv), (src), \
  470. (src)->base.size>>PAGE_SHIFT)
  471. static void capture_bo(struct drm_i915_error_buffer *err,
  472. struct drm_i915_gem_object *obj)
  473. {
  474. err->size = obj->base.size;
  475. err->name = obj->base.name;
  476. err->rseqno = obj->last_read_seqno;
  477. err->wseqno = obj->last_write_seqno;
  478. err->gtt_offset = i915_gem_obj_ggtt_offset(obj);
  479. err->read_domains = obj->base.read_domains;
  480. err->write_domain = obj->base.write_domain;
  481. err->fence_reg = obj->fence_reg;
  482. err->pinned = 0;
  483. if (obj->pin_count > 0)
  484. err->pinned = 1;
  485. if (obj->user_pin_count > 0)
  486. err->pinned = -1;
  487. err->tiling = obj->tiling_mode;
  488. err->dirty = obj->dirty;
  489. err->purgeable = obj->madv != I915_MADV_WILLNEED;
  490. err->ring = obj->ring ? obj->ring->id : -1;
  491. err->cache_level = obj->cache_level;
  492. }
  493. static u32 capture_active_bo(struct drm_i915_error_buffer *err,
  494. int count, struct list_head *head)
  495. {
  496. struct i915_vma *vma;
  497. int i = 0;
  498. list_for_each_entry(vma, head, mm_list) {
  499. capture_bo(err++, vma->obj);
  500. if (++i == count)
  501. break;
  502. }
  503. return i;
  504. }
  505. static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
  506. int count, struct list_head *head)
  507. {
  508. struct drm_i915_gem_object *obj;
  509. int i = 0;
  510. list_for_each_entry(obj, head, global_list) {
  511. if (obj->pin_count == 0)
  512. continue;
  513. capture_bo(err++, obj);
  514. if (++i == count)
  515. break;
  516. }
  517. return i;
  518. }
  519. static void i915_gem_record_fences(struct drm_device *dev,
  520. struct drm_i915_error_state *error)
  521. {
  522. struct drm_i915_private *dev_priv = dev->dev_private;
  523. int i;
  524. /* Fences */
  525. switch (INTEL_INFO(dev)->gen) {
  526. case 8:
  527. case 7:
  528. case 6:
  529. for (i = 0; i < dev_priv->num_fence_regs; i++)
  530. error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
  531. break;
  532. case 5:
  533. case 4:
  534. for (i = 0; i < 16; i++)
  535. error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
  536. break;
  537. case 3:
  538. if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
  539. for (i = 0; i < 8; i++)
  540. error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
  541. case 2:
  542. for (i = 0; i < 8; i++)
  543. error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
  544. break;
  545. default:
  546. BUG();
  547. }
  548. }
  549. static struct drm_i915_error_object *
  550. i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
  551. struct intel_ring_buffer *ring)
  552. {
  553. struct i915_address_space *vm;
  554. struct i915_vma *vma;
  555. struct drm_i915_gem_object *obj;
  556. u32 seqno;
  557. if (!ring->get_seqno)
  558. return NULL;
  559. if (HAS_BROKEN_CS_TLB(dev_priv->dev)) {
  560. u32 acthd = I915_READ(ACTHD);
  561. if (WARN_ON(ring->id != RCS))
  562. return NULL;
  563. obj = ring->scratch.obj;
  564. if (obj != NULL &&
  565. acthd >= i915_gem_obj_ggtt_offset(obj) &&
  566. acthd < i915_gem_obj_ggtt_offset(obj) + obj->base.size)
  567. return i915_error_object_create(dev_priv, obj);
  568. }
  569. seqno = ring->get_seqno(ring, false);
  570. list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
  571. list_for_each_entry(vma, &vm->active_list, mm_list) {
  572. obj = vma->obj;
  573. if (obj->ring != ring)
  574. continue;
  575. if (i915_seqno_passed(seqno, obj->last_read_seqno))
  576. continue;
  577. if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
  578. continue;
  579. /* We need to copy these to an anonymous buffer as the simplest
  580. * method to avoid being overwritten by userspace.
  581. */
  582. return i915_error_object_create(dev_priv, obj);
  583. }
  584. }
  585. return NULL;
  586. }
  587. static void i915_record_ring_state(struct drm_device *dev,
  588. struct drm_i915_error_state *error,
  589. struct intel_ring_buffer *ring)
  590. {
  591. struct drm_i915_private *dev_priv = dev->dev_private;
  592. if (INTEL_INFO(dev)->gen >= 6) {
  593. error->rc_psmi[ring->id] = I915_READ(ring->mmio_base + 0x50);
  594. error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
  595. error->semaphore_mboxes[ring->id][0]
  596. = I915_READ(RING_SYNC_0(ring->mmio_base));
  597. error->semaphore_mboxes[ring->id][1]
  598. = I915_READ(RING_SYNC_1(ring->mmio_base));
  599. error->semaphore_seqno[ring->id][0] = ring->sync_seqno[0];
  600. error->semaphore_seqno[ring->id][1] = ring->sync_seqno[1];
  601. }
  602. if (HAS_VEBOX(dev)) {
  603. error->semaphore_mboxes[ring->id][2] =
  604. I915_READ(RING_SYNC_2(ring->mmio_base));
  605. error->semaphore_seqno[ring->id][2] = ring->sync_seqno[2];
  606. }
  607. if (INTEL_INFO(dev)->gen >= 4) {
  608. error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
  609. error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
  610. error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
  611. error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
  612. error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
  613. error->bbaddr[ring->id] = I915_READ(RING_BBADDR(ring->mmio_base));
  614. if (INTEL_INFO(dev)->gen >= 8)
  615. error->bbaddr[ring->id] |= (u64) I915_READ(RING_BBADDR_UDW(ring->mmio_base)) << 32;
  616. error->bbstate[ring->id] = I915_READ(RING_BBSTATE(ring->mmio_base));
  617. } else {
  618. error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX);
  619. error->ipeir[ring->id] = I915_READ(IPEIR);
  620. error->ipehr[ring->id] = I915_READ(IPEHR);
  621. error->instdone[ring->id] = I915_READ(INSTDONE);
  622. }
  623. error->waiting[ring->id] = waitqueue_active(&ring->irq_queue);
  624. error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
  625. error->seqno[ring->id] = ring->get_seqno(ring, false);
  626. error->acthd[ring->id] = intel_ring_get_active_head(ring);
  627. error->head[ring->id] = I915_READ_HEAD(ring);
  628. error->tail[ring->id] = I915_READ_TAIL(ring);
  629. error->ctl[ring->id] = I915_READ_CTL(ring);
  630. error->cpu_ring_head[ring->id] = ring->head;
  631. error->cpu_ring_tail[ring->id] = ring->tail;
  632. error->hangcheck_score[ring->id] = ring->hangcheck.score;
  633. error->hangcheck_action[ring->id] = ring->hangcheck.action;
  634. }
  635. static void i915_gem_record_active_context(struct intel_ring_buffer *ring,
  636. struct drm_i915_error_state *error,
  637. struct drm_i915_error_ring *ering)
  638. {
  639. struct drm_i915_private *dev_priv = ring->dev->dev_private;
  640. struct drm_i915_gem_object *obj;
  641. /* Currently render ring is the only HW context user */
  642. if (ring->id != RCS || !error->ccid)
  643. return;
  644. list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
  645. if ((error->ccid & PAGE_MASK) == i915_gem_obj_ggtt_offset(obj)) {
  646. ering->ctx = i915_error_object_create_sized(dev_priv,
  647. obj, 1);
  648. break;
  649. }
  650. }
  651. }
  652. static void i915_gem_record_rings(struct drm_device *dev,
  653. struct drm_i915_error_state *error)
  654. {
  655. struct drm_i915_private *dev_priv = dev->dev_private;
  656. struct drm_i915_gem_request *request;
  657. int i, count;
  658. for (i = 0; i < I915_NUM_RINGS; i++) {
  659. struct intel_ring_buffer *ring = &dev_priv->ring[i];
  660. if (ring->dev == NULL)
  661. continue;
  662. error->ring[i].valid = true;
  663. i915_record_ring_state(dev, error, ring);
  664. error->ring[i].batchbuffer =
  665. i915_error_first_batchbuffer(dev_priv, ring);
  666. error->ring[i].ringbuffer =
  667. i915_error_object_create(dev_priv, ring->obj);
  668. i915_gem_record_active_context(ring, error, &error->ring[i]);
  669. count = 0;
  670. list_for_each_entry(request, &ring->request_list, list)
  671. count++;
  672. error->ring[i].num_requests = count;
  673. error->ring[i].requests =
  674. kcalloc(count, sizeof(*error->ring[i].requests),
  675. GFP_ATOMIC);
  676. if (error->ring[i].requests == NULL) {
  677. error->ring[i].num_requests = 0;
  678. continue;
  679. }
  680. count = 0;
  681. list_for_each_entry(request, &ring->request_list, list) {
  682. struct drm_i915_error_request *erq;
  683. erq = &error->ring[i].requests[count++];
  684. erq->seqno = request->seqno;
  685. erq->jiffies = request->emitted_jiffies;
  686. erq->tail = request->tail;
  687. }
  688. }
  689. }
  690. /* FIXME: Since pin count/bound list is global, we duplicate what we capture per
  691. * VM.
  692. */
  693. static void i915_gem_capture_vm(struct drm_i915_private *dev_priv,
  694. struct drm_i915_error_state *error,
  695. struct i915_address_space *vm,
  696. const int ndx)
  697. {
  698. struct drm_i915_error_buffer *active_bo = NULL, *pinned_bo = NULL;
  699. struct drm_i915_gem_object *obj;
  700. struct i915_vma *vma;
  701. int i;
  702. i = 0;
  703. list_for_each_entry(vma, &vm->active_list, mm_list)
  704. i++;
  705. error->active_bo_count[ndx] = i;
  706. list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
  707. if (obj->pin_count)
  708. i++;
  709. error->pinned_bo_count[ndx] = i - error->active_bo_count[ndx];
  710. if (i) {
  711. active_bo = kcalloc(i, sizeof(*active_bo), GFP_ATOMIC);
  712. if (active_bo)
  713. pinned_bo = active_bo + error->active_bo_count[ndx];
  714. }
  715. if (active_bo)
  716. error->active_bo_count[ndx] =
  717. capture_active_bo(active_bo,
  718. error->active_bo_count[ndx],
  719. &vm->active_list);
  720. if (pinned_bo)
  721. error->pinned_bo_count[ndx] =
  722. capture_pinned_bo(pinned_bo,
  723. error->pinned_bo_count[ndx],
  724. &dev_priv->mm.bound_list);
  725. error->active_bo[ndx] = active_bo;
  726. error->pinned_bo[ndx] = pinned_bo;
  727. }
  728. static void i915_gem_capture_buffers(struct drm_i915_private *dev_priv,
  729. struct drm_i915_error_state *error)
  730. {
  731. struct i915_address_space *vm;
  732. int cnt = 0, i = 0;
  733. list_for_each_entry(vm, &dev_priv->vm_list, global_link)
  734. cnt++;
  735. if (WARN(cnt > 1, "Multiple VMs not yet supported\n"))
  736. cnt = 1;
  737. vm = &dev_priv->gtt.base;
  738. error->active_bo = kcalloc(cnt, sizeof(*error->active_bo), GFP_ATOMIC);
  739. error->pinned_bo = kcalloc(cnt, sizeof(*error->pinned_bo), GFP_ATOMIC);
  740. error->active_bo_count = kcalloc(cnt, sizeof(*error->active_bo_count),
  741. GFP_ATOMIC);
  742. error->pinned_bo_count = kcalloc(cnt, sizeof(*error->pinned_bo_count),
  743. GFP_ATOMIC);
  744. list_for_each_entry(vm, &dev_priv->vm_list, global_link)
  745. i915_gem_capture_vm(dev_priv, error, vm, i++);
  746. }
  747. /**
  748. * i915_capture_error_state - capture an error record for later analysis
  749. * @dev: drm device
  750. *
  751. * Should be called when an error is detected (either a hang or an error
  752. * interrupt) to capture error state from the time of the error. Fills
  753. * out a structure which becomes available in debugfs for user level tools
  754. * to pick up.
  755. */
  756. void i915_capture_error_state(struct drm_device *dev)
  757. {
  758. struct drm_i915_private *dev_priv = dev->dev_private;
  759. struct drm_i915_error_state *error;
  760. unsigned long flags;
  761. int pipe;
  762. spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
  763. error = dev_priv->gpu_error.first_error;
  764. spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
  765. if (error)
  766. return;
  767. /* Account for pipe specific data like PIPE*STAT */
  768. error = kzalloc(sizeof(*error), GFP_ATOMIC);
  769. if (!error) {
  770. DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
  771. return;
  772. }
  773. DRM_INFO("GPU crash dump saved to /sys/class/drm/card%d/error\n",
  774. dev->primary->index);
  775. DRM_INFO("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n");
  776. DRM_INFO("Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel\n");
  777. DRM_INFO("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n");
  778. DRM_INFO("The gpu crash dump is required to analyze gpu hangs, so please always attach it.\n");
  779. kref_init(&error->ref);
  780. error->eir = I915_READ(EIR);
  781. error->pgtbl_er = I915_READ(PGTBL_ER);
  782. if (HAS_HW_CONTEXTS(dev))
  783. error->ccid = I915_READ(CCID);
  784. if (HAS_PCH_SPLIT(dev))
  785. error->ier = I915_READ(DEIER) | I915_READ(GTIER);
  786. else if (IS_VALLEYVIEW(dev))
  787. error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
  788. else if (IS_GEN2(dev))
  789. error->ier = I915_READ16(IER);
  790. else
  791. error->ier = I915_READ(IER);
  792. if (INTEL_INFO(dev)->gen >= 6)
  793. error->derrmr = I915_READ(DERRMR);
  794. if (IS_VALLEYVIEW(dev))
  795. error->forcewake = I915_READ(FORCEWAKE_VLV);
  796. else if (INTEL_INFO(dev)->gen >= 7)
  797. error->forcewake = I915_READ(FORCEWAKE_MT);
  798. else if (INTEL_INFO(dev)->gen == 6)
  799. error->forcewake = I915_READ(FORCEWAKE);
  800. if (!HAS_PCH_SPLIT(dev))
  801. for_each_pipe(pipe)
  802. error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
  803. if (INTEL_INFO(dev)->gen >= 6) {
  804. error->error = I915_READ(ERROR_GEN6);
  805. error->done_reg = I915_READ(DONE_REG);
  806. }
  807. if (INTEL_INFO(dev)->gen == 7)
  808. error->err_int = I915_READ(GEN7_ERR_INT);
  809. i915_get_extra_instdone(dev, error->extra_instdone);
  810. i915_gem_capture_buffers(dev_priv, error);
  811. i915_gem_record_fences(dev, error);
  812. i915_gem_record_rings(dev, error);
  813. do_gettimeofday(&error->time);
  814. error->overlay = intel_overlay_capture_error_state(dev);
  815. error->display = intel_display_capture_error_state(dev);
  816. spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
  817. if (dev_priv->gpu_error.first_error == NULL) {
  818. dev_priv->gpu_error.first_error = error;
  819. error = NULL;
  820. }
  821. spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
  822. if (error)
  823. i915_error_state_free(&error->ref);
  824. }
  825. void i915_error_state_get(struct drm_device *dev,
  826. struct i915_error_state_file_priv *error_priv)
  827. {
  828. struct drm_i915_private *dev_priv = dev->dev_private;
  829. unsigned long flags;
  830. spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
  831. error_priv->error = dev_priv->gpu_error.first_error;
  832. if (error_priv->error)
  833. kref_get(&error_priv->error->ref);
  834. spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
  835. }
  836. void i915_error_state_put(struct i915_error_state_file_priv *error_priv)
  837. {
  838. if (error_priv->error)
  839. kref_put(&error_priv->error->ref, i915_error_state_free);
  840. }
  841. void i915_destroy_error_state(struct drm_device *dev)
  842. {
  843. struct drm_i915_private *dev_priv = dev->dev_private;
  844. struct drm_i915_error_state *error;
  845. unsigned long flags;
  846. spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
  847. error = dev_priv->gpu_error.first_error;
  848. dev_priv->gpu_error.first_error = NULL;
  849. spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
  850. if (error)
  851. kref_put(&error->ref, i915_error_state_free);
  852. }
  853. const char *i915_cache_level_str(int type)
  854. {
  855. switch (type) {
  856. case I915_CACHE_NONE: return " uncached";
  857. case I915_CACHE_LLC: return " snooped or LLC";
  858. case I915_CACHE_L3_LLC: return " L3+LLC";
  859. case I915_CACHE_WT: return " WT";
  860. default: return "";
  861. }
  862. }
  863. /* NB: please notice the memset */
  864. void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone)
  865. {
  866. struct drm_i915_private *dev_priv = dev->dev_private;
  867. memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG);
  868. switch (INTEL_INFO(dev)->gen) {
  869. case 2:
  870. case 3:
  871. instdone[0] = I915_READ(INSTDONE);
  872. break;
  873. case 4:
  874. case 5:
  875. case 6:
  876. instdone[0] = I915_READ(INSTDONE_I965);
  877. instdone[1] = I915_READ(INSTDONE1);
  878. break;
  879. default:
  880. WARN_ONCE(1, "Unsupported platform\n");
  881. case 7:
  882. case 8:
  883. instdone[0] = I915_READ(GEN7_INSTDONE_1);
  884. instdone[1] = I915_READ(GEN7_SC_INSTDONE);
  885. instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE);
  886. instdone[3] = I915_READ(GEN7_ROW_INSTDONE);
  887. break;
  888. }
  889. }