i915_gem_execbuffer.c 37 KB

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  1. /*
  2. * Copyright © 2008,2010 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21. * IN THE SOFTWARE.
  22. *
  23. * Authors:
  24. * Eric Anholt <eric@anholt.net>
  25. * Chris Wilson <chris@chris-wilson.co.uk>
  26. *
  27. */
  28. #include <drm/drmP.h>
  29. #include <drm/i915_drm.h>
  30. #include "i915_drv.h"
  31. #include "i915_trace.h"
  32. #include "intel_drv.h"
  33. #include <linux/dma_remapping.h>
  34. #define __EXEC_OBJECT_HAS_PIN (1<<31)
  35. #define __EXEC_OBJECT_HAS_FENCE (1<<30)
  36. struct eb_vmas {
  37. struct list_head vmas;
  38. int and;
  39. union {
  40. struct i915_vma *lut[0];
  41. struct hlist_head buckets[0];
  42. };
  43. };
  44. static struct eb_vmas *
  45. eb_create(struct drm_i915_gem_execbuffer2 *args)
  46. {
  47. struct eb_vmas *eb = NULL;
  48. if (args->flags & I915_EXEC_HANDLE_LUT) {
  49. unsigned size = args->buffer_count;
  50. size *= sizeof(struct i915_vma *);
  51. size += sizeof(struct eb_vmas);
  52. eb = kmalloc(size, GFP_TEMPORARY | __GFP_NOWARN | __GFP_NORETRY);
  53. }
  54. if (eb == NULL) {
  55. unsigned size = args->buffer_count;
  56. unsigned count = PAGE_SIZE / sizeof(struct hlist_head) / 2;
  57. BUILD_BUG_ON_NOT_POWER_OF_2(PAGE_SIZE / sizeof(struct hlist_head));
  58. while (count > 2*size)
  59. count >>= 1;
  60. eb = kzalloc(count*sizeof(struct hlist_head) +
  61. sizeof(struct eb_vmas),
  62. GFP_TEMPORARY);
  63. if (eb == NULL)
  64. return eb;
  65. eb->and = count - 1;
  66. } else
  67. eb->and = -args->buffer_count;
  68. INIT_LIST_HEAD(&eb->vmas);
  69. return eb;
  70. }
  71. static void
  72. eb_reset(struct eb_vmas *eb)
  73. {
  74. if (eb->and >= 0)
  75. memset(eb->buckets, 0, (eb->and+1)*sizeof(struct hlist_head));
  76. }
  77. static int
  78. eb_lookup_vmas(struct eb_vmas *eb,
  79. struct drm_i915_gem_exec_object2 *exec,
  80. const struct drm_i915_gem_execbuffer2 *args,
  81. struct i915_address_space *vm,
  82. struct drm_file *file)
  83. {
  84. struct drm_i915_gem_object *obj;
  85. struct list_head objects;
  86. int i, ret;
  87. INIT_LIST_HEAD(&objects);
  88. spin_lock(&file->table_lock);
  89. /* Grab a reference to the object and release the lock so we can lookup
  90. * or create the VMA without using GFP_ATOMIC */
  91. for (i = 0; i < args->buffer_count; i++) {
  92. obj = to_intel_bo(idr_find(&file->object_idr, exec[i].handle));
  93. if (obj == NULL) {
  94. spin_unlock(&file->table_lock);
  95. DRM_DEBUG("Invalid object handle %d at index %d\n",
  96. exec[i].handle, i);
  97. ret = -ENOENT;
  98. goto err;
  99. }
  100. if (!list_empty(&obj->obj_exec_link)) {
  101. spin_unlock(&file->table_lock);
  102. DRM_DEBUG("Object %p [handle %d, index %d] appears more than once in object list\n",
  103. obj, exec[i].handle, i);
  104. ret = -EINVAL;
  105. goto err;
  106. }
  107. drm_gem_object_reference(&obj->base);
  108. list_add_tail(&obj->obj_exec_link, &objects);
  109. }
  110. spin_unlock(&file->table_lock);
  111. i = 0;
  112. while (!list_empty(&objects)) {
  113. struct i915_vma *vma;
  114. obj = list_first_entry(&objects,
  115. struct drm_i915_gem_object,
  116. obj_exec_link);
  117. /*
  118. * NOTE: We can leak any vmas created here when something fails
  119. * later on. But that's no issue since vma_unbind can deal with
  120. * vmas which are not actually bound. And since only
  121. * lookup_or_create exists as an interface to get at the vma
  122. * from the (obj, vm) we don't run the risk of creating
  123. * duplicated vmas for the same vm.
  124. */
  125. vma = i915_gem_obj_lookup_or_create_vma(obj, vm);
  126. if (IS_ERR(vma)) {
  127. DRM_DEBUG("Failed to lookup VMA\n");
  128. ret = PTR_ERR(vma);
  129. goto err;
  130. }
  131. /* Transfer ownership from the objects list to the vmas list. */
  132. list_add_tail(&vma->exec_list, &eb->vmas);
  133. list_del_init(&obj->obj_exec_link);
  134. vma->exec_entry = &exec[i];
  135. if (eb->and < 0) {
  136. eb->lut[i] = vma;
  137. } else {
  138. uint32_t handle = args->flags & I915_EXEC_HANDLE_LUT ? i : exec[i].handle;
  139. vma->exec_handle = handle;
  140. hlist_add_head(&vma->exec_node,
  141. &eb->buckets[handle & eb->and]);
  142. }
  143. ++i;
  144. }
  145. return 0;
  146. err:
  147. while (!list_empty(&objects)) {
  148. obj = list_first_entry(&objects,
  149. struct drm_i915_gem_object,
  150. obj_exec_link);
  151. list_del_init(&obj->obj_exec_link);
  152. drm_gem_object_unreference(&obj->base);
  153. }
  154. /*
  155. * Objects already transfered to the vmas list will be unreferenced by
  156. * eb_destroy.
  157. */
  158. return ret;
  159. }
  160. static struct i915_vma *eb_get_vma(struct eb_vmas *eb, unsigned long handle)
  161. {
  162. if (eb->and < 0) {
  163. if (handle >= -eb->and)
  164. return NULL;
  165. return eb->lut[handle];
  166. } else {
  167. struct hlist_head *head;
  168. struct hlist_node *node;
  169. head = &eb->buckets[handle & eb->and];
  170. hlist_for_each(node, head) {
  171. struct i915_vma *vma;
  172. vma = hlist_entry(node, struct i915_vma, exec_node);
  173. if (vma->exec_handle == handle)
  174. return vma;
  175. }
  176. return NULL;
  177. }
  178. }
  179. static void
  180. i915_gem_execbuffer_unreserve_vma(struct i915_vma *vma)
  181. {
  182. struct drm_i915_gem_exec_object2 *entry;
  183. struct drm_i915_gem_object *obj = vma->obj;
  184. if (!drm_mm_node_allocated(&vma->node))
  185. return;
  186. entry = vma->exec_entry;
  187. if (entry->flags & __EXEC_OBJECT_HAS_FENCE)
  188. i915_gem_object_unpin_fence(obj);
  189. if (entry->flags & __EXEC_OBJECT_HAS_PIN)
  190. i915_gem_object_unpin(obj);
  191. entry->flags &= ~(__EXEC_OBJECT_HAS_FENCE | __EXEC_OBJECT_HAS_PIN);
  192. }
  193. static void eb_destroy(struct eb_vmas *eb)
  194. {
  195. while (!list_empty(&eb->vmas)) {
  196. struct i915_vma *vma;
  197. vma = list_first_entry(&eb->vmas,
  198. struct i915_vma,
  199. exec_list);
  200. list_del_init(&vma->exec_list);
  201. i915_gem_execbuffer_unreserve_vma(vma);
  202. drm_gem_object_unreference(&vma->obj->base);
  203. }
  204. kfree(eb);
  205. }
  206. static inline int use_cpu_reloc(struct drm_i915_gem_object *obj)
  207. {
  208. return (HAS_LLC(obj->base.dev) ||
  209. obj->base.write_domain == I915_GEM_DOMAIN_CPU ||
  210. !obj->map_and_fenceable ||
  211. obj->cache_level != I915_CACHE_NONE);
  212. }
  213. static int
  214. relocate_entry_cpu(struct drm_i915_gem_object *obj,
  215. struct drm_i915_gem_relocation_entry *reloc)
  216. {
  217. struct drm_device *dev = obj->base.dev;
  218. uint32_t page_offset = offset_in_page(reloc->offset);
  219. char *vaddr;
  220. int ret;
  221. ret = i915_gem_object_set_to_cpu_domain(obj, true);
  222. if (ret)
  223. return ret;
  224. vaddr = kmap_atomic(i915_gem_object_get_page(obj,
  225. reloc->offset >> PAGE_SHIFT));
  226. *(uint32_t *)(vaddr + page_offset) = reloc->delta;
  227. if (INTEL_INFO(dev)->gen >= 8) {
  228. page_offset = offset_in_page(page_offset + sizeof(uint32_t));
  229. if (page_offset == 0) {
  230. kunmap_atomic(vaddr);
  231. vaddr = kmap_atomic(i915_gem_object_get_page(obj,
  232. (reloc->offset + sizeof(uint32_t)) >> PAGE_SHIFT));
  233. }
  234. *(uint32_t *)(vaddr + page_offset) = 0;
  235. }
  236. kunmap_atomic(vaddr);
  237. return 0;
  238. }
  239. static int
  240. relocate_entry_gtt(struct drm_i915_gem_object *obj,
  241. struct drm_i915_gem_relocation_entry *reloc)
  242. {
  243. struct drm_device *dev = obj->base.dev;
  244. struct drm_i915_private *dev_priv = dev->dev_private;
  245. uint32_t __iomem *reloc_entry;
  246. void __iomem *reloc_page;
  247. int ret;
  248. ret = i915_gem_object_set_to_gtt_domain(obj, true);
  249. if (ret)
  250. return ret;
  251. ret = i915_gem_object_put_fence(obj);
  252. if (ret)
  253. return ret;
  254. /* Map the page containing the relocation we're going to perform. */
  255. reloc->offset += i915_gem_obj_ggtt_offset(obj);
  256. reloc_page = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
  257. reloc->offset & PAGE_MASK);
  258. reloc_entry = (uint32_t __iomem *)
  259. (reloc_page + offset_in_page(reloc->offset));
  260. iowrite32(reloc->delta, reloc_entry);
  261. if (INTEL_INFO(dev)->gen >= 8) {
  262. reloc_entry += 1;
  263. if (offset_in_page(reloc->offset + sizeof(uint32_t)) == 0) {
  264. io_mapping_unmap_atomic(reloc_page);
  265. reloc_page = io_mapping_map_atomic_wc(
  266. dev_priv->gtt.mappable,
  267. reloc->offset + sizeof(uint32_t));
  268. reloc_entry = reloc_page;
  269. }
  270. iowrite32(0, reloc_entry);
  271. }
  272. io_mapping_unmap_atomic(reloc_page);
  273. return 0;
  274. }
  275. static int
  276. i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
  277. struct eb_vmas *eb,
  278. struct drm_i915_gem_relocation_entry *reloc,
  279. struct i915_address_space *vm)
  280. {
  281. struct drm_device *dev = obj->base.dev;
  282. struct drm_gem_object *target_obj;
  283. struct drm_i915_gem_object *target_i915_obj;
  284. struct i915_vma *target_vma;
  285. uint32_t target_offset;
  286. int ret;
  287. /* we've already hold a reference to all valid objects */
  288. target_vma = eb_get_vma(eb, reloc->target_handle);
  289. if (unlikely(target_vma == NULL))
  290. return -ENOENT;
  291. target_i915_obj = target_vma->obj;
  292. target_obj = &target_vma->obj->base;
  293. target_offset = target_vma->node.start;
  294. /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and
  295. * pipe_control writes because the gpu doesn't properly redirect them
  296. * through the ppgtt for non_secure batchbuffers. */
  297. if (unlikely(IS_GEN6(dev) &&
  298. reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION &&
  299. !target_i915_obj->has_global_gtt_mapping)) {
  300. i915_gem_gtt_bind_object(target_i915_obj,
  301. target_i915_obj->cache_level);
  302. }
  303. /* Validate that the target is in a valid r/w GPU domain */
  304. if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) {
  305. DRM_DEBUG("reloc with multiple write domains: "
  306. "obj %p target %d offset %d "
  307. "read %08x write %08x",
  308. obj, reloc->target_handle,
  309. (int) reloc->offset,
  310. reloc->read_domains,
  311. reloc->write_domain);
  312. return -EINVAL;
  313. }
  314. if (unlikely((reloc->write_domain | reloc->read_domains)
  315. & ~I915_GEM_GPU_DOMAINS)) {
  316. DRM_DEBUG("reloc with read/write non-GPU domains: "
  317. "obj %p target %d offset %d "
  318. "read %08x write %08x",
  319. obj, reloc->target_handle,
  320. (int) reloc->offset,
  321. reloc->read_domains,
  322. reloc->write_domain);
  323. return -EINVAL;
  324. }
  325. target_obj->pending_read_domains |= reloc->read_domains;
  326. target_obj->pending_write_domain |= reloc->write_domain;
  327. /* If the relocation already has the right value in it, no
  328. * more work needs to be done.
  329. */
  330. if (target_offset == reloc->presumed_offset)
  331. return 0;
  332. /* Check that the relocation address is valid... */
  333. if (unlikely(reloc->offset >
  334. obj->base.size - (INTEL_INFO(dev)->gen >= 8 ? 8 : 4))) {
  335. DRM_DEBUG("Relocation beyond object bounds: "
  336. "obj %p target %d offset %d size %d.\n",
  337. obj, reloc->target_handle,
  338. (int) reloc->offset,
  339. (int) obj->base.size);
  340. return -EINVAL;
  341. }
  342. if (unlikely(reloc->offset & 3)) {
  343. DRM_DEBUG("Relocation not 4-byte aligned: "
  344. "obj %p target %d offset %d.\n",
  345. obj, reloc->target_handle,
  346. (int) reloc->offset);
  347. return -EINVAL;
  348. }
  349. /* We can't wait for rendering with pagefaults disabled */
  350. if (obj->active && in_atomic())
  351. return -EFAULT;
  352. reloc->delta += target_offset;
  353. if (use_cpu_reloc(obj))
  354. ret = relocate_entry_cpu(obj, reloc);
  355. else
  356. ret = relocate_entry_gtt(obj, reloc);
  357. if (ret)
  358. return ret;
  359. /* and update the user's relocation entry */
  360. reloc->presumed_offset = target_offset;
  361. return 0;
  362. }
  363. static int
  364. i915_gem_execbuffer_relocate_vma(struct i915_vma *vma,
  365. struct eb_vmas *eb)
  366. {
  367. #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry))
  368. struct drm_i915_gem_relocation_entry stack_reloc[N_RELOC(512)];
  369. struct drm_i915_gem_relocation_entry __user *user_relocs;
  370. struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
  371. int remain, ret;
  372. user_relocs = to_user_ptr(entry->relocs_ptr);
  373. remain = entry->relocation_count;
  374. while (remain) {
  375. struct drm_i915_gem_relocation_entry *r = stack_reloc;
  376. int count = remain;
  377. if (count > ARRAY_SIZE(stack_reloc))
  378. count = ARRAY_SIZE(stack_reloc);
  379. remain -= count;
  380. if (__copy_from_user_inatomic(r, user_relocs, count*sizeof(r[0])))
  381. return -EFAULT;
  382. do {
  383. u64 offset = r->presumed_offset;
  384. ret = i915_gem_execbuffer_relocate_entry(vma->obj, eb, r,
  385. vma->vm);
  386. if (ret)
  387. return ret;
  388. if (r->presumed_offset != offset &&
  389. __copy_to_user_inatomic(&user_relocs->presumed_offset,
  390. &r->presumed_offset,
  391. sizeof(r->presumed_offset))) {
  392. return -EFAULT;
  393. }
  394. user_relocs++;
  395. r++;
  396. } while (--count);
  397. }
  398. return 0;
  399. #undef N_RELOC
  400. }
  401. static int
  402. i915_gem_execbuffer_relocate_vma_slow(struct i915_vma *vma,
  403. struct eb_vmas *eb,
  404. struct drm_i915_gem_relocation_entry *relocs)
  405. {
  406. const struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
  407. int i, ret;
  408. for (i = 0; i < entry->relocation_count; i++) {
  409. ret = i915_gem_execbuffer_relocate_entry(vma->obj, eb, &relocs[i],
  410. vma->vm);
  411. if (ret)
  412. return ret;
  413. }
  414. return 0;
  415. }
  416. static int
  417. i915_gem_execbuffer_relocate(struct eb_vmas *eb)
  418. {
  419. struct i915_vma *vma;
  420. int ret = 0;
  421. /* This is the fast path and we cannot handle a pagefault whilst
  422. * holding the struct mutex lest the user pass in the relocations
  423. * contained within a mmaped bo. For in such a case we, the page
  424. * fault handler would call i915_gem_fault() and we would try to
  425. * acquire the struct mutex again. Obviously this is bad and so
  426. * lockdep complains vehemently.
  427. */
  428. pagefault_disable();
  429. list_for_each_entry(vma, &eb->vmas, exec_list) {
  430. ret = i915_gem_execbuffer_relocate_vma(vma, eb);
  431. if (ret)
  432. break;
  433. }
  434. pagefault_enable();
  435. return ret;
  436. }
  437. static int
  438. need_reloc_mappable(struct i915_vma *vma)
  439. {
  440. struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
  441. return entry->relocation_count && !use_cpu_reloc(vma->obj) &&
  442. i915_is_ggtt(vma->vm);
  443. }
  444. static int
  445. i915_gem_execbuffer_reserve_vma(struct i915_vma *vma,
  446. struct intel_ring_buffer *ring,
  447. bool *need_reloc)
  448. {
  449. struct drm_i915_private *dev_priv = ring->dev->dev_private;
  450. struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
  451. bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4;
  452. bool need_fence, need_mappable;
  453. struct drm_i915_gem_object *obj = vma->obj;
  454. int ret;
  455. need_fence =
  456. has_fenced_gpu_access &&
  457. entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
  458. obj->tiling_mode != I915_TILING_NONE;
  459. need_mappable = need_fence || need_reloc_mappable(vma);
  460. ret = i915_gem_object_pin(obj, vma->vm, entry->alignment, need_mappable,
  461. false);
  462. if (ret)
  463. return ret;
  464. entry->flags |= __EXEC_OBJECT_HAS_PIN;
  465. if (has_fenced_gpu_access) {
  466. if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) {
  467. ret = i915_gem_object_get_fence(obj);
  468. if (ret)
  469. return ret;
  470. if (i915_gem_object_pin_fence(obj))
  471. entry->flags |= __EXEC_OBJECT_HAS_FENCE;
  472. obj->pending_fenced_gpu_access = true;
  473. }
  474. }
  475. /* Ensure ppgtt mapping exists if needed */
  476. if (dev_priv->mm.aliasing_ppgtt && !obj->has_aliasing_ppgtt_mapping) {
  477. i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
  478. obj, obj->cache_level);
  479. obj->has_aliasing_ppgtt_mapping = 1;
  480. }
  481. if (entry->offset != vma->node.start) {
  482. entry->offset = vma->node.start;
  483. *need_reloc = true;
  484. }
  485. if (entry->flags & EXEC_OBJECT_WRITE) {
  486. obj->base.pending_read_domains = I915_GEM_DOMAIN_RENDER;
  487. obj->base.pending_write_domain = I915_GEM_DOMAIN_RENDER;
  488. }
  489. if (entry->flags & EXEC_OBJECT_NEEDS_GTT &&
  490. !obj->has_global_gtt_mapping)
  491. i915_gem_gtt_bind_object(obj, obj->cache_level);
  492. return 0;
  493. }
  494. static int
  495. i915_gem_execbuffer_reserve(struct intel_ring_buffer *ring,
  496. struct list_head *vmas,
  497. bool *need_relocs)
  498. {
  499. struct drm_i915_gem_object *obj;
  500. struct i915_vma *vma;
  501. struct i915_address_space *vm;
  502. struct list_head ordered_vmas;
  503. bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4;
  504. int retry;
  505. if (list_empty(vmas))
  506. return 0;
  507. vm = list_first_entry(vmas, struct i915_vma, exec_list)->vm;
  508. INIT_LIST_HEAD(&ordered_vmas);
  509. while (!list_empty(vmas)) {
  510. struct drm_i915_gem_exec_object2 *entry;
  511. bool need_fence, need_mappable;
  512. vma = list_first_entry(vmas, struct i915_vma, exec_list);
  513. obj = vma->obj;
  514. entry = vma->exec_entry;
  515. need_fence =
  516. has_fenced_gpu_access &&
  517. entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
  518. obj->tiling_mode != I915_TILING_NONE;
  519. need_mappable = need_fence || need_reloc_mappable(vma);
  520. if (need_mappable)
  521. list_move(&vma->exec_list, &ordered_vmas);
  522. else
  523. list_move_tail(&vma->exec_list, &ordered_vmas);
  524. obj->base.pending_read_domains = I915_GEM_GPU_DOMAINS & ~I915_GEM_DOMAIN_COMMAND;
  525. obj->base.pending_write_domain = 0;
  526. obj->pending_fenced_gpu_access = false;
  527. }
  528. list_splice(&ordered_vmas, vmas);
  529. /* Attempt to pin all of the buffers into the GTT.
  530. * This is done in 3 phases:
  531. *
  532. * 1a. Unbind all objects that do not match the GTT constraints for
  533. * the execbuffer (fenceable, mappable, alignment etc).
  534. * 1b. Increment pin count for already bound objects.
  535. * 2. Bind new objects.
  536. * 3. Decrement pin count.
  537. *
  538. * This avoid unnecessary unbinding of later objects in order to make
  539. * room for the earlier objects *unless* we need to defragment.
  540. */
  541. retry = 0;
  542. do {
  543. int ret = 0;
  544. /* Unbind any ill-fitting objects or pin. */
  545. list_for_each_entry(vma, vmas, exec_list) {
  546. struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
  547. bool need_fence, need_mappable;
  548. obj = vma->obj;
  549. if (!drm_mm_node_allocated(&vma->node))
  550. continue;
  551. need_fence =
  552. has_fenced_gpu_access &&
  553. entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
  554. obj->tiling_mode != I915_TILING_NONE;
  555. need_mappable = need_fence || need_reloc_mappable(vma);
  556. WARN_ON((need_mappable || need_fence) &&
  557. !i915_is_ggtt(vma->vm));
  558. if ((entry->alignment &&
  559. vma->node.start & (entry->alignment - 1)) ||
  560. (need_mappable && !obj->map_and_fenceable))
  561. ret = i915_vma_unbind(vma);
  562. else
  563. ret = i915_gem_execbuffer_reserve_vma(vma, ring, need_relocs);
  564. if (ret)
  565. goto err;
  566. }
  567. /* Bind fresh objects */
  568. list_for_each_entry(vma, vmas, exec_list) {
  569. if (drm_mm_node_allocated(&vma->node))
  570. continue;
  571. ret = i915_gem_execbuffer_reserve_vma(vma, ring, need_relocs);
  572. if (ret)
  573. goto err;
  574. }
  575. err:
  576. if (ret != -ENOSPC || retry++)
  577. return ret;
  578. /* Decrement pin count for bound objects */
  579. list_for_each_entry(vma, vmas, exec_list)
  580. i915_gem_execbuffer_unreserve_vma(vma);
  581. ret = i915_gem_evict_vm(vm, true);
  582. if (ret)
  583. return ret;
  584. } while (1);
  585. }
  586. static int
  587. i915_gem_execbuffer_relocate_slow(struct drm_device *dev,
  588. struct drm_i915_gem_execbuffer2 *args,
  589. struct drm_file *file,
  590. struct intel_ring_buffer *ring,
  591. struct eb_vmas *eb,
  592. struct drm_i915_gem_exec_object2 *exec)
  593. {
  594. struct drm_i915_gem_relocation_entry *reloc;
  595. struct i915_address_space *vm;
  596. struct i915_vma *vma;
  597. bool need_relocs;
  598. int *reloc_offset;
  599. int i, total, ret;
  600. unsigned count = args->buffer_count;
  601. if (WARN_ON(list_empty(&eb->vmas)))
  602. return 0;
  603. vm = list_first_entry(&eb->vmas, struct i915_vma, exec_list)->vm;
  604. /* We may process another execbuffer during the unlock... */
  605. while (!list_empty(&eb->vmas)) {
  606. vma = list_first_entry(&eb->vmas, struct i915_vma, exec_list);
  607. list_del_init(&vma->exec_list);
  608. i915_gem_execbuffer_unreserve_vma(vma);
  609. drm_gem_object_unreference(&vma->obj->base);
  610. }
  611. mutex_unlock(&dev->struct_mutex);
  612. total = 0;
  613. for (i = 0; i < count; i++)
  614. total += exec[i].relocation_count;
  615. reloc_offset = drm_malloc_ab(count, sizeof(*reloc_offset));
  616. reloc = drm_malloc_ab(total, sizeof(*reloc));
  617. if (reloc == NULL || reloc_offset == NULL) {
  618. drm_free_large(reloc);
  619. drm_free_large(reloc_offset);
  620. mutex_lock(&dev->struct_mutex);
  621. return -ENOMEM;
  622. }
  623. total = 0;
  624. for (i = 0; i < count; i++) {
  625. struct drm_i915_gem_relocation_entry __user *user_relocs;
  626. u64 invalid_offset = (u64)-1;
  627. int j;
  628. user_relocs = to_user_ptr(exec[i].relocs_ptr);
  629. if (copy_from_user(reloc+total, user_relocs,
  630. exec[i].relocation_count * sizeof(*reloc))) {
  631. ret = -EFAULT;
  632. mutex_lock(&dev->struct_mutex);
  633. goto err;
  634. }
  635. /* As we do not update the known relocation offsets after
  636. * relocating (due to the complexities in lock handling),
  637. * we need to mark them as invalid now so that we force the
  638. * relocation processing next time. Just in case the target
  639. * object is evicted and then rebound into its old
  640. * presumed_offset before the next execbuffer - if that
  641. * happened we would make the mistake of assuming that the
  642. * relocations were valid.
  643. */
  644. for (j = 0; j < exec[i].relocation_count; j++) {
  645. if (copy_to_user(&user_relocs[j].presumed_offset,
  646. &invalid_offset,
  647. sizeof(invalid_offset))) {
  648. ret = -EFAULT;
  649. mutex_lock(&dev->struct_mutex);
  650. goto err;
  651. }
  652. }
  653. reloc_offset[i] = total;
  654. total += exec[i].relocation_count;
  655. }
  656. ret = i915_mutex_lock_interruptible(dev);
  657. if (ret) {
  658. mutex_lock(&dev->struct_mutex);
  659. goto err;
  660. }
  661. /* reacquire the objects */
  662. eb_reset(eb);
  663. ret = eb_lookup_vmas(eb, exec, args, vm, file);
  664. if (ret)
  665. goto err;
  666. need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0;
  667. ret = i915_gem_execbuffer_reserve(ring, &eb->vmas, &need_relocs);
  668. if (ret)
  669. goto err;
  670. list_for_each_entry(vma, &eb->vmas, exec_list) {
  671. int offset = vma->exec_entry - exec;
  672. ret = i915_gem_execbuffer_relocate_vma_slow(vma, eb,
  673. reloc + reloc_offset[offset]);
  674. if (ret)
  675. goto err;
  676. }
  677. /* Leave the user relocations as are, this is the painfully slow path,
  678. * and we want to avoid the complication of dropping the lock whilst
  679. * having buffers reserved in the aperture and so causing spurious
  680. * ENOSPC for random operations.
  681. */
  682. err:
  683. drm_free_large(reloc);
  684. drm_free_large(reloc_offset);
  685. return ret;
  686. }
  687. static int
  688. i915_gem_execbuffer_move_to_gpu(struct intel_ring_buffer *ring,
  689. struct list_head *vmas)
  690. {
  691. struct i915_vma *vma;
  692. uint32_t flush_domains = 0;
  693. bool flush_chipset = false;
  694. int ret;
  695. list_for_each_entry(vma, vmas, exec_list) {
  696. struct drm_i915_gem_object *obj = vma->obj;
  697. ret = i915_gem_object_sync(obj, ring);
  698. if (ret)
  699. return ret;
  700. if (obj->base.write_domain & I915_GEM_DOMAIN_CPU)
  701. flush_chipset |= i915_gem_clflush_object(obj, false);
  702. flush_domains |= obj->base.write_domain;
  703. }
  704. if (flush_chipset)
  705. i915_gem_chipset_flush(ring->dev);
  706. if (flush_domains & I915_GEM_DOMAIN_GTT)
  707. wmb();
  708. /* Unconditionally invalidate gpu caches and ensure that we do flush
  709. * any residual writes from the previous batch.
  710. */
  711. return intel_ring_invalidate_all_caches(ring);
  712. }
  713. static bool
  714. i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec)
  715. {
  716. if (exec->flags & __I915_EXEC_UNKNOWN_FLAGS)
  717. return false;
  718. return ((exec->batch_start_offset | exec->batch_len) & 0x7) == 0;
  719. }
  720. static int
  721. validate_exec_list(struct drm_i915_gem_exec_object2 *exec,
  722. int count)
  723. {
  724. int i;
  725. unsigned relocs_total = 0;
  726. unsigned relocs_max = UINT_MAX / sizeof(struct drm_i915_gem_relocation_entry);
  727. for (i = 0; i < count; i++) {
  728. char __user *ptr = to_user_ptr(exec[i].relocs_ptr);
  729. int length; /* limited by fault_in_pages_readable() */
  730. if (exec[i].flags & __EXEC_OBJECT_UNKNOWN_FLAGS)
  731. return -EINVAL;
  732. /* First check for malicious input causing overflow in
  733. * the worst case where we need to allocate the entire
  734. * relocation tree as a single array.
  735. */
  736. if (exec[i].relocation_count > relocs_max - relocs_total)
  737. return -EINVAL;
  738. relocs_total += exec[i].relocation_count;
  739. length = exec[i].relocation_count *
  740. sizeof(struct drm_i915_gem_relocation_entry);
  741. /*
  742. * We must check that the entire relocation array is safe
  743. * to read, but since we may need to update the presumed
  744. * offsets during execution, check for full write access.
  745. */
  746. if (!access_ok(VERIFY_WRITE, ptr, length))
  747. return -EFAULT;
  748. if (likely(!i915_prefault_disable)) {
  749. if (fault_in_multipages_readable(ptr, length))
  750. return -EFAULT;
  751. }
  752. }
  753. return 0;
  754. }
  755. static int
  756. i915_gem_validate_context(struct drm_device *dev, struct drm_file *file,
  757. const u32 ctx_id)
  758. {
  759. struct i915_ctx_hang_stats *hs;
  760. hs = i915_gem_context_get_hang_stats(dev, file, ctx_id);
  761. if (IS_ERR(hs))
  762. return PTR_ERR(hs);
  763. if (hs->banned) {
  764. DRM_DEBUG("Context %u tried to submit while banned\n", ctx_id);
  765. return -EIO;
  766. }
  767. return 0;
  768. }
  769. static void
  770. i915_gem_execbuffer_move_to_active(struct list_head *vmas,
  771. struct intel_ring_buffer *ring)
  772. {
  773. struct i915_vma *vma;
  774. list_for_each_entry(vma, vmas, exec_list) {
  775. struct drm_i915_gem_object *obj = vma->obj;
  776. u32 old_read = obj->base.read_domains;
  777. u32 old_write = obj->base.write_domain;
  778. obj->base.write_domain = obj->base.pending_write_domain;
  779. if (obj->base.write_domain == 0)
  780. obj->base.pending_read_domains |= obj->base.read_domains;
  781. obj->base.read_domains = obj->base.pending_read_domains;
  782. obj->fenced_gpu_access = obj->pending_fenced_gpu_access;
  783. i915_vma_move_to_active(vma, ring);
  784. if (obj->base.write_domain) {
  785. obj->dirty = 1;
  786. obj->last_write_seqno = intel_ring_get_seqno(ring);
  787. if (obj->pin_count) /* check for potential scanout */
  788. intel_mark_fb_busy(obj, ring);
  789. }
  790. trace_i915_gem_object_change_domain(obj, old_read, old_write);
  791. }
  792. }
  793. static void
  794. i915_gem_execbuffer_retire_commands(struct drm_device *dev,
  795. struct drm_file *file,
  796. struct intel_ring_buffer *ring,
  797. struct drm_i915_gem_object *obj)
  798. {
  799. /* Unconditionally force add_request to emit a full flush. */
  800. ring->gpu_caches_dirty = true;
  801. /* Add a breadcrumb for the completion of the batch buffer */
  802. (void)__i915_add_request(ring, file, obj, NULL);
  803. }
  804. static int
  805. i915_reset_gen7_sol_offsets(struct drm_device *dev,
  806. struct intel_ring_buffer *ring)
  807. {
  808. drm_i915_private_t *dev_priv = dev->dev_private;
  809. int ret, i;
  810. if (!IS_GEN7(dev) || ring != &dev_priv->ring[RCS])
  811. return 0;
  812. ret = intel_ring_begin(ring, 4 * 3);
  813. if (ret)
  814. return ret;
  815. for (i = 0; i < 4; i++) {
  816. intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
  817. intel_ring_emit(ring, GEN7_SO_WRITE_OFFSET(i));
  818. intel_ring_emit(ring, 0);
  819. }
  820. intel_ring_advance(ring);
  821. return 0;
  822. }
  823. static int
  824. i915_gem_do_execbuffer(struct drm_device *dev, void *data,
  825. struct drm_file *file,
  826. struct drm_i915_gem_execbuffer2 *args,
  827. struct drm_i915_gem_exec_object2 *exec,
  828. struct i915_address_space *vm)
  829. {
  830. drm_i915_private_t *dev_priv = dev->dev_private;
  831. struct eb_vmas *eb;
  832. struct drm_i915_gem_object *batch_obj;
  833. struct drm_clip_rect *cliprects = NULL;
  834. struct intel_ring_buffer *ring;
  835. const u32 ctx_id = i915_execbuffer2_get_context_id(*args);
  836. u32 exec_start, exec_len;
  837. u32 mask, flags;
  838. int ret, mode, i;
  839. bool need_relocs;
  840. if (!i915_gem_check_execbuffer(args))
  841. return -EINVAL;
  842. ret = validate_exec_list(exec, args->buffer_count);
  843. if (ret)
  844. return ret;
  845. flags = 0;
  846. if (args->flags & I915_EXEC_SECURE) {
  847. if (!file->is_master || !capable(CAP_SYS_ADMIN))
  848. return -EPERM;
  849. flags |= I915_DISPATCH_SECURE;
  850. }
  851. if (args->flags & I915_EXEC_IS_PINNED)
  852. flags |= I915_DISPATCH_PINNED;
  853. switch (args->flags & I915_EXEC_RING_MASK) {
  854. case I915_EXEC_DEFAULT:
  855. case I915_EXEC_RENDER:
  856. ring = &dev_priv->ring[RCS];
  857. break;
  858. case I915_EXEC_BSD:
  859. ring = &dev_priv->ring[VCS];
  860. if (ctx_id != DEFAULT_CONTEXT_ID) {
  861. DRM_DEBUG("Ring %s doesn't support contexts\n",
  862. ring->name);
  863. return -EPERM;
  864. }
  865. break;
  866. case I915_EXEC_BLT:
  867. ring = &dev_priv->ring[BCS];
  868. if (ctx_id != DEFAULT_CONTEXT_ID) {
  869. DRM_DEBUG("Ring %s doesn't support contexts\n",
  870. ring->name);
  871. return -EPERM;
  872. }
  873. break;
  874. case I915_EXEC_VEBOX:
  875. ring = &dev_priv->ring[VECS];
  876. if (ctx_id != DEFAULT_CONTEXT_ID) {
  877. DRM_DEBUG("Ring %s doesn't support contexts\n",
  878. ring->name);
  879. return -EPERM;
  880. }
  881. break;
  882. default:
  883. DRM_DEBUG("execbuf with unknown ring: %d\n",
  884. (int)(args->flags & I915_EXEC_RING_MASK));
  885. return -EINVAL;
  886. }
  887. if (!intel_ring_initialized(ring)) {
  888. DRM_DEBUG("execbuf with invalid ring: %d\n",
  889. (int)(args->flags & I915_EXEC_RING_MASK));
  890. return -EINVAL;
  891. }
  892. mode = args->flags & I915_EXEC_CONSTANTS_MASK;
  893. mask = I915_EXEC_CONSTANTS_MASK;
  894. switch (mode) {
  895. case I915_EXEC_CONSTANTS_REL_GENERAL:
  896. case I915_EXEC_CONSTANTS_ABSOLUTE:
  897. case I915_EXEC_CONSTANTS_REL_SURFACE:
  898. if (ring == &dev_priv->ring[RCS] &&
  899. mode != dev_priv->relative_constants_mode) {
  900. if (INTEL_INFO(dev)->gen < 4)
  901. return -EINVAL;
  902. if (INTEL_INFO(dev)->gen > 5 &&
  903. mode == I915_EXEC_CONSTANTS_REL_SURFACE)
  904. return -EINVAL;
  905. /* The HW changed the meaning on this bit on gen6 */
  906. if (INTEL_INFO(dev)->gen >= 6)
  907. mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE;
  908. }
  909. break;
  910. default:
  911. DRM_DEBUG("execbuf with unknown constants: %d\n", mode);
  912. return -EINVAL;
  913. }
  914. if (args->buffer_count < 1) {
  915. DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count);
  916. return -EINVAL;
  917. }
  918. if (args->num_cliprects != 0) {
  919. if (ring != &dev_priv->ring[RCS]) {
  920. DRM_DEBUG("clip rectangles are only valid with the render ring\n");
  921. return -EINVAL;
  922. }
  923. if (INTEL_INFO(dev)->gen >= 5) {
  924. DRM_DEBUG("clip rectangles are only valid on pre-gen5\n");
  925. return -EINVAL;
  926. }
  927. if (args->num_cliprects > UINT_MAX / sizeof(*cliprects)) {
  928. DRM_DEBUG("execbuf with %u cliprects\n",
  929. args->num_cliprects);
  930. return -EINVAL;
  931. }
  932. cliprects = kcalloc(args->num_cliprects,
  933. sizeof(*cliprects),
  934. GFP_KERNEL);
  935. if (cliprects == NULL) {
  936. ret = -ENOMEM;
  937. goto pre_mutex_err;
  938. }
  939. if (copy_from_user(cliprects,
  940. to_user_ptr(args->cliprects_ptr),
  941. sizeof(*cliprects)*args->num_cliprects)) {
  942. ret = -EFAULT;
  943. goto pre_mutex_err;
  944. }
  945. }
  946. intel_runtime_pm_get(dev_priv);
  947. ret = i915_mutex_lock_interruptible(dev);
  948. if (ret)
  949. goto pre_mutex_err;
  950. if (dev_priv->ums.mm_suspended) {
  951. mutex_unlock(&dev->struct_mutex);
  952. ret = -EBUSY;
  953. goto pre_mutex_err;
  954. }
  955. ret = i915_gem_validate_context(dev, file, ctx_id);
  956. if (ret) {
  957. mutex_unlock(&dev->struct_mutex);
  958. goto pre_mutex_err;
  959. }
  960. eb = eb_create(args);
  961. if (eb == NULL) {
  962. mutex_unlock(&dev->struct_mutex);
  963. ret = -ENOMEM;
  964. goto pre_mutex_err;
  965. }
  966. /* Look up object handles */
  967. ret = eb_lookup_vmas(eb, exec, args, vm, file);
  968. if (ret)
  969. goto err;
  970. /* take note of the batch buffer before we might reorder the lists */
  971. batch_obj = list_entry(eb->vmas.prev, struct i915_vma, exec_list)->obj;
  972. /* Move the objects en-masse into the GTT, evicting if necessary. */
  973. need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0;
  974. ret = i915_gem_execbuffer_reserve(ring, &eb->vmas, &need_relocs);
  975. if (ret)
  976. goto err;
  977. /* The objects are in their final locations, apply the relocations. */
  978. if (need_relocs)
  979. ret = i915_gem_execbuffer_relocate(eb);
  980. if (ret) {
  981. if (ret == -EFAULT) {
  982. ret = i915_gem_execbuffer_relocate_slow(dev, args, file, ring,
  983. eb, exec);
  984. BUG_ON(!mutex_is_locked(&dev->struct_mutex));
  985. }
  986. if (ret)
  987. goto err;
  988. }
  989. /* Set the pending read domains for the batch buffer to COMMAND */
  990. if (batch_obj->base.pending_write_domain) {
  991. DRM_DEBUG("Attempting to use self-modifying batch buffer\n");
  992. ret = -EINVAL;
  993. goto err;
  994. }
  995. batch_obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
  996. /* snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure
  997. * batch" bit. Hence we need to pin secure batches into the global gtt.
  998. * hsw should have this fixed, but bdw mucks it up again. */
  999. if (flags & I915_DISPATCH_SECURE && !batch_obj->has_global_gtt_mapping)
  1000. i915_gem_gtt_bind_object(batch_obj, batch_obj->cache_level);
  1001. ret = i915_gem_execbuffer_move_to_gpu(ring, &eb->vmas);
  1002. if (ret)
  1003. goto err;
  1004. ret = i915_switch_context(ring, file, ctx_id);
  1005. if (ret)
  1006. goto err;
  1007. if (ring == &dev_priv->ring[RCS] &&
  1008. mode != dev_priv->relative_constants_mode) {
  1009. ret = intel_ring_begin(ring, 4);
  1010. if (ret)
  1011. goto err;
  1012. intel_ring_emit(ring, MI_NOOP);
  1013. intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
  1014. intel_ring_emit(ring, INSTPM);
  1015. intel_ring_emit(ring, mask << 16 | mode);
  1016. intel_ring_advance(ring);
  1017. dev_priv->relative_constants_mode = mode;
  1018. }
  1019. if (args->flags & I915_EXEC_GEN7_SOL_RESET) {
  1020. ret = i915_reset_gen7_sol_offsets(dev, ring);
  1021. if (ret)
  1022. goto err;
  1023. }
  1024. exec_start = i915_gem_obj_offset(batch_obj, vm) +
  1025. args->batch_start_offset;
  1026. exec_len = args->batch_len;
  1027. if (cliprects) {
  1028. for (i = 0; i < args->num_cliprects; i++) {
  1029. ret = i915_emit_box(dev, &cliprects[i],
  1030. args->DR1, args->DR4);
  1031. if (ret)
  1032. goto err;
  1033. ret = ring->dispatch_execbuffer(ring,
  1034. exec_start, exec_len,
  1035. flags);
  1036. if (ret)
  1037. goto err;
  1038. }
  1039. } else {
  1040. ret = ring->dispatch_execbuffer(ring,
  1041. exec_start, exec_len,
  1042. flags);
  1043. if (ret)
  1044. goto err;
  1045. }
  1046. trace_i915_gem_ring_dispatch(ring, intel_ring_get_seqno(ring), flags);
  1047. i915_gem_execbuffer_move_to_active(&eb->vmas, ring);
  1048. i915_gem_execbuffer_retire_commands(dev, file, ring, batch_obj);
  1049. err:
  1050. eb_destroy(eb);
  1051. mutex_unlock(&dev->struct_mutex);
  1052. pre_mutex_err:
  1053. kfree(cliprects);
  1054. /* intel_gpu_busy should also get a ref, so it will free when the device
  1055. * is really idle. */
  1056. intel_runtime_pm_put(dev_priv);
  1057. return ret;
  1058. }
  1059. /*
  1060. * Legacy execbuffer just creates an exec2 list from the original exec object
  1061. * list array and passes it to the real function.
  1062. */
  1063. int
  1064. i915_gem_execbuffer(struct drm_device *dev, void *data,
  1065. struct drm_file *file)
  1066. {
  1067. struct drm_i915_private *dev_priv = dev->dev_private;
  1068. struct drm_i915_gem_execbuffer *args = data;
  1069. struct drm_i915_gem_execbuffer2 exec2;
  1070. struct drm_i915_gem_exec_object *exec_list = NULL;
  1071. struct drm_i915_gem_exec_object2 *exec2_list = NULL;
  1072. int ret, i;
  1073. if (args->buffer_count < 1) {
  1074. DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count);
  1075. return -EINVAL;
  1076. }
  1077. /* Copy in the exec list from userland */
  1078. exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
  1079. exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
  1080. if (exec_list == NULL || exec2_list == NULL) {
  1081. DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
  1082. args->buffer_count);
  1083. drm_free_large(exec_list);
  1084. drm_free_large(exec2_list);
  1085. return -ENOMEM;
  1086. }
  1087. ret = copy_from_user(exec_list,
  1088. to_user_ptr(args->buffers_ptr),
  1089. sizeof(*exec_list) * args->buffer_count);
  1090. if (ret != 0) {
  1091. DRM_DEBUG("copy %d exec entries failed %d\n",
  1092. args->buffer_count, ret);
  1093. drm_free_large(exec_list);
  1094. drm_free_large(exec2_list);
  1095. return -EFAULT;
  1096. }
  1097. for (i = 0; i < args->buffer_count; i++) {
  1098. exec2_list[i].handle = exec_list[i].handle;
  1099. exec2_list[i].relocation_count = exec_list[i].relocation_count;
  1100. exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
  1101. exec2_list[i].alignment = exec_list[i].alignment;
  1102. exec2_list[i].offset = exec_list[i].offset;
  1103. if (INTEL_INFO(dev)->gen < 4)
  1104. exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
  1105. else
  1106. exec2_list[i].flags = 0;
  1107. }
  1108. exec2.buffers_ptr = args->buffers_ptr;
  1109. exec2.buffer_count = args->buffer_count;
  1110. exec2.batch_start_offset = args->batch_start_offset;
  1111. exec2.batch_len = args->batch_len;
  1112. exec2.DR1 = args->DR1;
  1113. exec2.DR4 = args->DR4;
  1114. exec2.num_cliprects = args->num_cliprects;
  1115. exec2.cliprects_ptr = args->cliprects_ptr;
  1116. exec2.flags = I915_EXEC_RENDER;
  1117. i915_execbuffer2_set_context_id(exec2, 0);
  1118. ret = i915_gem_do_execbuffer(dev, data, file, &exec2, exec2_list,
  1119. &dev_priv->gtt.base);
  1120. if (!ret) {
  1121. /* Copy the new buffer offsets back to the user's exec list. */
  1122. for (i = 0; i < args->buffer_count; i++)
  1123. exec_list[i].offset = exec2_list[i].offset;
  1124. /* ... and back out to userspace */
  1125. ret = copy_to_user(to_user_ptr(args->buffers_ptr),
  1126. exec_list,
  1127. sizeof(*exec_list) * args->buffer_count);
  1128. if (ret) {
  1129. ret = -EFAULT;
  1130. DRM_DEBUG("failed to copy %d exec entries "
  1131. "back to user (%d)\n",
  1132. args->buffer_count, ret);
  1133. }
  1134. }
  1135. drm_free_large(exec_list);
  1136. drm_free_large(exec2_list);
  1137. return ret;
  1138. }
  1139. int
  1140. i915_gem_execbuffer2(struct drm_device *dev, void *data,
  1141. struct drm_file *file)
  1142. {
  1143. struct drm_i915_private *dev_priv = dev->dev_private;
  1144. struct drm_i915_gem_execbuffer2 *args = data;
  1145. struct drm_i915_gem_exec_object2 *exec2_list = NULL;
  1146. int ret;
  1147. if (args->buffer_count < 1 ||
  1148. args->buffer_count > UINT_MAX / sizeof(*exec2_list)) {
  1149. DRM_DEBUG("execbuf2 with %d buffers\n", args->buffer_count);
  1150. return -EINVAL;
  1151. }
  1152. exec2_list = kmalloc(sizeof(*exec2_list)*args->buffer_count,
  1153. GFP_TEMPORARY | __GFP_NOWARN | __GFP_NORETRY);
  1154. if (exec2_list == NULL)
  1155. exec2_list = drm_malloc_ab(sizeof(*exec2_list),
  1156. args->buffer_count);
  1157. if (exec2_list == NULL) {
  1158. DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
  1159. args->buffer_count);
  1160. return -ENOMEM;
  1161. }
  1162. ret = copy_from_user(exec2_list,
  1163. to_user_ptr(args->buffers_ptr),
  1164. sizeof(*exec2_list) * args->buffer_count);
  1165. if (ret != 0) {
  1166. DRM_DEBUG("copy %d exec entries failed %d\n",
  1167. args->buffer_count, ret);
  1168. drm_free_large(exec2_list);
  1169. return -EFAULT;
  1170. }
  1171. ret = i915_gem_do_execbuffer(dev, data, file, args, exec2_list,
  1172. &dev_priv->gtt.base);
  1173. if (!ret) {
  1174. /* Copy the new buffer offsets back to the user's exec list. */
  1175. ret = copy_to_user(to_user_ptr(args->buffers_ptr),
  1176. exec2_list,
  1177. sizeof(*exec2_list) * args->buffer_count);
  1178. if (ret) {
  1179. ret = -EFAULT;
  1180. DRM_DEBUG("failed to copy %d exec entries "
  1181. "back to user (%d)\n",
  1182. args->buffer_count, ret);
  1183. }
  1184. }
  1185. drm_free_large(exec2_list);
  1186. return ret;
  1187. }