cpufreq-cpu0.c 6.4 KB

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  1. /*
  2. * Copyright (C) 2012 Freescale Semiconductor, Inc.
  3. *
  4. * The OPP code in function cpu0_set_target() is reused from
  5. * drivers/cpufreq/omap-cpufreq.c
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. */
  11. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  12. #include <linux/clk.h>
  13. #include <linux/cpu.h>
  14. #include <linux/cpu_cooling.h>
  15. #include <linux/cpufreq.h>
  16. #include <linux/cpumask.h>
  17. #include <linux/err.h>
  18. #include <linux/module.h>
  19. #include <linux/of.h>
  20. #include <linux/pm_opp.h>
  21. #include <linux/platform_device.h>
  22. #include <linux/regulator/consumer.h>
  23. #include <linux/slab.h>
  24. #include <linux/thermal.h>
  25. static unsigned int transition_latency;
  26. static unsigned int voltage_tolerance; /* in percentage */
  27. static struct device *cpu_dev;
  28. static struct clk *cpu_clk;
  29. static struct regulator *cpu_reg;
  30. static struct cpufreq_frequency_table *freq_table;
  31. static struct thermal_cooling_device *cdev;
  32. static int cpu0_set_target(struct cpufreq_policy *policy, unsigned int index)
  33. {
  34. struct dev_pm_opp *opp;
  35. unsigned long volt = 0, volt_old = 0, tol = 0;
  36. unsigned int old_freq, new_freq;
  37. long freq_Hz, freq_exact;
  38. int ret;
  39. freq_Hz = clk_round_rate(cpu_clk, freq_table[index].frequency * 1000);
  40. if (freq_Hz <= 0)
  41. freq_Hz = freq_table[index].frequency * 1000;
  42. freq_exact = freq_Hz;
  43. new_freq = freq_Hz / 1000;
  44. old_freq = clk_get_rate(cpu_clk) / 1000;
  45. if (!IS_ERR(cpu_reg)) {
  46. rcu_read_lock();
  47. opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_Hz);
  48. if (IS_ERR(opp)) {
  49. rcu_read_unlock();
  50. pr_err("failed to find OPP for %ld\n", freq_Hz);
  51. return PTR_ERR(opp);
  52. }
  53. volt = dev_pm_opp_get_voltage(opp);
  54. rcu_read_unlock();
  55. tol = volt * voltage_tolerance / 100;
  56. volt_old = regulator_get_voltage(cpu_reg);
  57. }
  58. pr_debug("%u MHz, %ld mV --> %u MHz, %ld mV\n",
  59. old_freq / 1000, volt_old ? volt_old / 1000 : -1,
  60. new_freq / 1000, volt ? volt / 1000 : -1);
  61. /* scaling up? scale voltage before frequency */
  62. if (!IS_ERR(cpu_reg) && new_freq > old_freq) {
  63. ret = regulator_set_voltage_tol(cpu_reg, volt, tol);
  64. if (ret) {
  65. pr_err("failed to scale voltage up: %d\n", ret);
  66. return ret;
  67. }
  68. }
  69. ret = clk_set_rate(cpu_clk, freq_exact);
  70. if (ret) {
  71. pr_err("failed to set clock rate: %d\n", ret);
  72. if (!IS_ERR(cpu_reg))
  73. regulator_set_voltage_tol(cpu_reg, volt_old, tol);
  74. return ret;
  75. }
  76. /* scaling down? scale voltage after frequency */
  77. if (!IS_ERR(cpu_reg) && new_freq < old_freq) {
  78. ret = regulator_set_voltage_tol(cpu_reg, volt, tol);
  79. if (ret) {
  80. pr_err("failed to scale voltage down: %d\n", ret);
  81. clk_set_rate(cpu_clk, old_freq * 1000);
  82. }
  83. }
  84. return ret;
  85. }
  86. static int cpu0_cpufreq_init(struct cpufreq_policy *policy)
  87. {
  88. policy->clk = cpu_clk;
  89. return cpufreq_generic_init(policy, freq_table, transition_latency);
  90. }
  91. static struct cpufreq_driver cpu0_cpufreq_driver = {
  92. .flags = CPUFREQ_STICKY,
  93. .verify = cpufreq_generic_frequency_table_verify,
  94. .target_index = cpu0_set_target,
  95. .get = cpufreq_generic_get,
  96. .init = cpu0_cpufreq_init,
  97. .exit = cpufreq_generic_exit,
  98. .name = "generic_cpu0",
  99. .attr = cpufreq_generic_attr,
  100. };
  101. static int cpu0_cpufreq_probe(struct platform_device *pdev)
  102. {
  103. struct device_node *np;
  104. int ret;
  105. cpu_dev = get_cpu_device(0);
  106. if (!cpu_dev) {
  107. pr_err("failed to get cpu0 device\n");
  108. return -ENODEV;
  109. }
  110. np = of_node_get(cpu_dev->of_node);
  111. if (!np) {
  112. pr_err("failed to find cpu0 node\n");
  113. return -ENOENT;
  114. }
  115. cpu_reg = devm_regulator_get_optional(cpu_dev, "cpu0");
  116. if (IS_ERR(cpu_reg)) {
  117. /*
  118. * If cpu0 regulator supply node is present, but regulator is
  119. * not yet registered, we should try defering probe.
  120. */
  121. if (PTR_ERR(cpu_reg) == -EPROBE_DEFER) {
  122. dev_err(cpu_dev, "cpu0 regulator not ready, retry\n");
  123. ret = -EPROBE_DEFER;
  124. goto out_put_node;
  125. }
  126. pr_warn("failed to get cpu0 regulator: %ld\n",
  127. PTR_ERR(cpu_reg));
  128. }
  129. cpu_clk = devm_clk_get(cpu_dev, NULL);
  130. if (IS_ERR(cpu_clk)) {
  131. ret = PTR_ERR(cpu_clk);
  132. pr_err("failed to get cpu0 clock: %d\n", ret);
  133. goto out_put_node;
  134. }
  135. ret = of_init_opp_table(cpu_dev);
  136. if (ret) {
  137. pr_err("failed to init OPP table: %d\n", ret);
  138. goto out_put_node;
  139. }
  140. ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table);
  141. if (ret) {
  142. pr_err("failed to init cpufreq table: %d\n", ret);
  143. goto out_put_node;
  144. }
  145. of_property_read_u32(np, "voltage-tolerance", &voltage_tolerance);
  146. if (of_property_read_u32(np, "clock-latency", &transition_latency))
  147. transition_latency = CPUFREQ_ETERNAL;
  148. if (!IS_ERR(cpu_reg)) {
  149. struct dev_pm_opp *opp;
  150. unsigned long min_uV, max_uV;
  151. int i;
  152. /*
  153. * OPP is maintained in order of increasing frequency, and
  154. * freq_table initialised from OPP is therefore sorted in the
  155. * same order.
  156. */
  157. for (i = 0; freq_table[i].frequency != CPUFREQ_TABLE_END; i++)
  158. ;
  159. rcu_read_lock();
  160. opp = dev_pm_opp_find_freq_exact(cpu_dev,
  161. freq_table[0].frequency * 1000, true);
  162. min_uV = dev_pm_opp_get_voltage(opp);
  163. opp = dev_pm_opp_find_freq_exact(cpu_dev,
  164. freq_table[i-1].frequency * 1000, true);
  165. max_uV = dev_pm_opp_get_voltage(opp);
  166. rcu_read_unlock();
  167. ret = regulator_set_voltage_time(cpu_reg, min_uV, max_uV);
  168. if (ret > 0)
  169. transition_latency += ret * 1000;
  170. }
  171. ret = cpufreq_register_driver(&cpu0_cpufreq_driver);
  172. if (ret) {
  173. pr_err("failed register driver: %d\n", ret);
  174. goto out_free_table;
  175. }
  176. /*
  177. * For now, just loading the cooling device;
  178. * thermal DT code takes care of matching them.
  179. */
  180. if (of_find_property(np, "#cooling-cells", NULL)) {
  181. cdev = of_cpufreq_cooling_register(np, cpu_present_mask);
  182. if (IS_ERR(cdev))
  183. pr_err("running cpufreq without cooling device: %ld\n",
  184. PTR_ERR(cdev));
  185. }
  186. of_node_put(np);
  187. return 0;
  188. out_free_table:
  189. dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
  190. out_put_node:
  191. of_node_put(np);
  192. return ret;
  193. }
  194. static int cpu0_cpufreq_remove(struct platform_device *pdev)
  195. {
  196. cpufreq_cooling_unregister(cdev);
  197. cpufreq_unregister_driver(&cpu0_cpufreq_driver);
  198. dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
  199. return 0;
  200. }
  201. static struct platform_driver cpu0_cpufreq_platdrv = {
  202. .driver = {
  203. .name = "cpufreq-cpu0",
  204. .owner = THIS_MODULE,
  205. },
  206. .probe = cpu0_cpufreq_probe,
  207. .remove = cpu0_cpufreq_remove,
  208. };
  209. module_platform_driver(cpu0_cpufreq_platdrv);
  210. MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
  211. MODULE_DESCRIPTION("Generic CPU0 cpufreq driver");
  212. MODULE_LICENSE("GPL");